Display substrate and display device
By employing a design in which the bias compensation sub-circuit and the data writing sub-circuit share a common control terminal in the OLED display panel, the problem of uneven brightness caused by the hysteresis effect of the driving transistor is solved, achieving a display effect with high pixel density and narrow bezel.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BOE TECHNOLOGY GROUP CO LTD
- Filing Date
- 2023-09-15
- Publication Date
- 2026-06-26
AI Technical Summary
Existing OLED display panels suffer from uneven brightness due to the hysteresis effect of the driving transistors when operating at low frequencies. Current technologies that add bias compensation transistors affect high pixel density and narrow bezel designs.
The bias compensation sub-circuit and the data writing sub-circuit share the same control terminal. By connecting them in series, the use of gate drive signal and bias voltage signal is reduced, and the characteristic curve of the drive transistor is corrected after data writing.
It achieves improved brightness uniformity of display panels during low-frequency operation without increasing bezels and pixel density, thus meeting the design requirements of narrow bezels and high pixel density.
Smart Images
Figure CN117059031B_ABST
Abstract
Description
Technical Field
[0001] This disclosure belongs to the field of display technology, specifically relating to a display substrate and a display device. Background Technology
[0002] With the development of display technology, people have higher and higher requirements for display devices. For example, organic electroluminescence display (OLED) devices are widely used due to their thinness, self-illumination, and fast response speed.
[0003] In existing OLED designs, the display panel includes multiple pixel units, each of which includes a pixel driving circuit to drive the sub-pixel to emit light. Typically, the pixel driving circuit operates directly into the light emission stage after the data writing and threshold compensation stages. As a result, when the display panel operates at low frequencies, brightness variations often occur due to the hysteresis effect of the driving transistors, leading to uneven display performance. Summary of the Invention
[0004] This disclosure aims to at least solve one of the technical problems existing in the prior art, and to provide a display substrate and a display device.
[0005] In a first aspect, the technical solution adopted to solve the technical problem of this disclosure is a display substrate, including M rows and N columns of pixel units; each pixel unit includes a pixel driving circuit, where M and N are both positive integers greater than 1; the pixel driving circuit includes a driving sub-circuit, a data writing sub-circuit, a bias compensation sub-circuit, and a first light emission control sub-circuit;
[0006] The first terminal of the driving sub-circuit and the second terminal of the data writing sub-circuit are electrically connected to the first node; the first terminal of the data writing sub-circuit and the second terminal of the bias compensation sub-circuit are electrically connected to the second node; the first terminal of the first light-emitting control sub-circuit is electrically connected to the first node;
[0007] For the pixel driving circuits located in the same column, the first node of the pixel driving circuit in the i-th row is electrically connected to the second node of the pixel driving circuit in the (i+1)-th row; i takes a positive integer from 1 to (M-1);
[0008] The bias compensation sub-circuit is configured to write a data signal to the second node in response to a first scan signal; and, for the pixel driving circuit in the (i+1)th row, the bias compensation sub-circuit is further configured to write the potential of the second node to the first node of the pixel driving circuit in the same column and the i-th row after writing the data signal to the second node in response to the first scan signal.
[0009] The data writing sub-circuit is configured to write the potential of the second node into the first node in response to the first scan signal;
[0010] The first light emission control sub-circuit is configured to drive the light emission device to be displayed to emit light through the drive current generated by the drive sub-circuit in response to the light emission control signal.
[0011] In some embodiments, the driving sub-circuit includes a third transistor;
[0012] The control electrode of the third transistor is electrically connected to the third node, the first electrode is electrically connected to the fourth node, and the second electrode is electrically connected to the first node.
[0013] In some embodiments, the bias compensation sub-circuit includes an eighth transistor;
[0014] The control electrode of the eighth transistor is electrically connected to the first scan signal line, the first electrode is electrically connected to the data signal line, and the second electrode is electrically connected to the second node.
[0015] In some embodiments, the data writing sub-circuit includes a second transistor;
[0016] The control electrode of the second transistor is electrically connected to the first scan signal line, the first electrode is electrically connected to the second node, and the second electrode is electrically connected to the first node.
[0017] In some embodiments, the pixel driving circuit further includes a threshold compensation sub-circuit;
[0018] The threshold compensation sub-circuit is configured to perform threshold voltage compensation on the driving sub-circuit in response to the first scan signal.
[0019] In some embodiments, the threshold compensation sub-circuit includes a fourth transistor;
[0020] The control electrode of the fourth transistor is electrically connected to the first scan signal line, the first electrode is electrically connected to the third node, and the second electrode is electrically connected to the fourth node.
[0021] In some embodiments, the first light-emitting control sub-circuit includes a first transistor;
[0022] The control electrode of the first transistor is electrically connected to the light-emitting control signal line, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the first electrode of the light-emitting device.
[0023] In some embodiments, the pixel driving circuit further includes a second light emission control sub-circuit;
[0024] The second light-emitting control sub-circuit is configured to transmit a first power supply voltage to the driving sub-circuit in response to the light-emitting control signal.
[0025] In some embodiments, the second light-emitting control sub-circuit includes a sixth transistor;
[0026] The control electrode of the sixth transistor is electrically connected to the light-emitting control signal line, the first electrode is electrically connected to the first power supply line, and the second electrode is electrically connected to the fourth node.
[0027] In some embodiments, the pixel driving circuit further includes a first reset sub-circuit;
[0028] The first reset sub-circuit is configured to transmit a first power supply voltage to the drive sub-circuit in response to a second scan signal;
[0029] For two adjacent pixel driving circuits located in the same column, the first scan signal of the pixel driving circuit in the i-th row is multiplexed as the second scan signal of the pixel driving circuit in the (i+1)-th row.
[0030] In some embodiments, the first reset sub-circuit includes a fifth transistor;
[0031] The control electrode of the fifth transistor is electrically connected to the second scan signal line, the first electrode is electrically connected to the first power supply line, and the second electrode is electrically connected to the third node.
[0032] In some embodiments, the pixel driving circuit further includes a second reset sub-circuit;
[0033] The second reset sub-circuit is configured to reset the first electrode of the light-emitting device in response to a reset control signal.
[0034] In some embodiments, the second reset sub-circuit includes a seventh transistor;
[0035] The control electrode of the seventh transistor is electrically connected to the reset control signal line, the first electrode is electrically connected to the initialization signal line, and the second electrode is electrically connected to the first electrode of the light-emitting device.
[0036] In some embodiments, the pixel driving circuit further includes a storage capacitor; the first plate of the storage capacitor is electrically connected to the driving sub-circuit, and the second plate is electrically connected to the first light-emitting control sub-circuit.
[0037] Secondly, embodiments of this disclosure also provide a display device, including the display substrate described in any one of the first aspects. Attached Figure Description
[0038] Figure 1 The circuit diagram is for an existing pixel driving circuit.
[0039] Figure 2 A schematic diagram showing the electrical connection between the pixel driving circuit in the i-th row and the pixel driving circuit in the (i+1)-th row of the same column, provided in an embodiment of this disclosure.
[0040] Figure 3 An equivalent circuit diagram showing the electrical connection between the pixel driving circuit in the i-th row and the pixel driving circuit in the (i+1)-th row of the same column, provided in an embodiment of this disclosure.
[0041] Figure 4 A timing diagram of a pixel driving circuit provided in an embodiment of this disclosure;
[0042] Figure 5a A schematic diagram illustrating the working principle of the driving circuits for two adjacent pixels in the same row in the first stage t1 provided in this embodiment of the disclosure;
[0043] Figure 5b This is a schematic diagram illustrating the working principle of the driving circuits for two adjacent pixels in the same row during the second stage t2, as provided in an embodiment of this disclosure.
[0044] Figure 5c A schematic diagram illustrating the working principle of the driving circuits for two adjacent pixels in the same row during the third stage t3, as provided in this embodiment of the disclosure.
[0045] Figure 5d This is a schematic diagram illustrating the working principle of the driving circuits for two adjacent pixels in the same row during the fourth stage t4, as provided in an embodiment of this disclosure.
[0046] The reference numerals in the attached diagram are as follows: 1. Driving sub-circuit; 2. Data writing sub-circuit; 3. Bias compensation sub-circuit; 4. First light emission control sub-circuit; 5. Second light emission control sub-circuit; 6. Threshold compensation sub-circuit; 7. First reset sub-circuit; 8. Second reset sub-circuit; Cst, storage capacitor; N1, first node; N2, second node; N3, third node; N4, fourth node; D, light emission device; T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; Data, data signal; Gate1, first scan signal; Gate2, second scan signal; EM, light emission control signal; Rst, reset control signal; Vinit, initialization signal; VDD, first power supply voltage; VSS, second power supply voltage. Detailed Implementation
[0047] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. The components of the embodiments of this disclosure described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this disclosure provided in the accompanying drawings is not intended to limit the scope of the claimed disclosure, but merely represents selected embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure.
[0048] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.
[0049] In this disclosure, "multiple or several" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.
[0050] In related technologies, Figure 1 For example, the circuit diagram of an existing pixel driving circuit, Figure 1As shown, the pixel driving circuit adds a bias compensation transistor T08 to apply a bias voltage signal Vbias to the source of the driving transistor T03. Before the light emission stage, by applying the bias voltage signal Vbias to the bias compensation transistor T08, the source of the driving transistor T03 (i.e., node N1) is reset. The characteristic curve of the driving transistor T03 can change with the bias voltage of node N1, thereby improving the brightness change caused by the hysteresis effect of the driving transistor T03. However, electrically connecting a bias compensation transistor T08 to the source of the driving transistor T03 (i.e., node N1) will simultaneously add a set of gate driving signals Gate0(i) and a set of bias voltage signals Vbias. The addition of the gate driving signal Gate0(i) increases the back panel bezel to some extent, and the addition of the bias voltage signal Vbias limits the pixel design of high pixel density (Pixels Per Inch, PPI) to some extent. Therefore, the above scheme is not conducive to the narrow bezel of the display panel and the development of high PPI.
[0051] In view of this, the present disclosure provides a display substrate that adds a bias compensation sub-circuit. This bias compensation sub-circuit and the data writing sub-circuit respond to the same first scan signal, meaning they share the same control terminal. Therefore, compared with the prior art, there is no need to add a gate drive signal Gate0(i), which can meet the design requirements of narrow bezels. At the same time, the bias compensation sub-circuit and the data writing sub-circuit are electrically connected to the second node, meaning they are connected in series. After the bias compensation sub-circuit and the data writing sub-circuit respond synchronously to the first scan signal, the bias compensation sub-circuit writes the data signal to the second node, and the data writing sub-circuit writes the data signal to the first node. Therefore, compared with the prior art, there is no need to add a bias voltage signal Vbias, which is beneficial for providing a high PPI. In addition, for the (i+1)th row pixel driving circuit, the bias compensation sub-circuit is also configured to write the potential of the second node to the first node of the i-th row pixel driving circuit in the same column after writing the data signal to the second node in response to the first scan signal. This is to correct the characteristic curve of the driving transistor (i.e., the third transistor below) in the driving sub-circuit, thereby effectively improving or preventing brightness changes caused by the hysteresis effect of the driving transistor when the display panel is operating at low frequency, and improving the uniformity of the display effect.
[0052] The specific details of the display substrate provided in the embodiments of this disclosure will be described in detail below. Figure 2 This is a schematic diagram showing the electrical connection between the pixel driving circuit in the i-th row and the pixel driving circuit in the (i+1)-th row, which are located in the same column, according to an embodiment of this disclosure.
[0053] The display substrate comprises M rows and N columns of pixel units; each pixel unit includes a pixel driving circuit, where M and N are both positive integers greater than 1. For example... Figure 2 As shown, the pixel driving circuit includes a driving sub-circuit 1, a data writing sub-circuit 2, a bias compensation sub-circuit 3, and a first light emission control sub-circuit 4.
[0054] like Figure 2 As shown, the first terminal of the driving sub-circuit 1 and the second terminal of the data writing sub-circuit 2 are electrically connected to the first node N1; the first terminal of the data writing sub-circuit 2 and the second terminal of the bias compensation sub-circuit 3 are electrically connected to the second node N2; the first terminal of the first light-emitting control sub-circuit 4 is electrically connected to the first node N1. The data writing sub-circuit 2 and the bias compensation sub-circuit 3 are connected in series.
[0055] like Figure 2 As shown, for pixel driving circuits located in the same column, the first node N1 of the pixel driving circuit in the i-th row is electrically connected to the second node N2 of the pixel driving circuit in the (i+1)-th row; i takes a positive integer from 1 to (M-1). Thus, by changing the potential of the second node N2 of the (i+1)-th row pixel driving circuit, the potential of the first node N1 of the pixel driving circuit in the i-th row is changed, thereby correcting the characteristic curve of the driving transistor (i.e., the third transistor T3 described below) in the driving sub-circuit 1.
[0056] like Figure 2 As shown, the bias compensation sub-circuit 3 is configured to write the data signal Data to the second node N2 in response to the first scan signal Gate1. The control terminal of the bias compensation sub-circuit 3 is electrically connected to the first scan signal line, which is used to transmit the first scan signal Gate1. The first terminal of the bias compensation sub-circuit 3 is electrically connected to the data signal line, which is used to transmit the data signal Data.
[0057] like Figure 2 As shown, for the (i+1)th row pixel driving circuit, the bias compensation sub-circuit 3 is further configured to, after writing the data signal Data to the second node N2 in response to the first scan signal Gate1, write the potential of the second node N2 to the first node N1 of the i-th row pixel driving circuit located in the same column. Here, as... Figure 2 As shown, for pixel driving circuits located in the same column, the first node N1 of the pixel driving circuit in the i-th row is electrically connected to the second node N2 of the pixel driving circuit in the (i+1)-th row. Therefore, changing the potential of the second node N2 of the pixel driving circuit in the (i+1)-th row will synchronously change the potential of the first node N1 of the pixel driving circuit in the i-th row.
[0058] like Figure 2 As shown, the data writing sub-circuit 2 is configured to write the potential of the second node N2 into the first node N1 in response to the first scan signal Gate1. The control terminal of the data writing sub-circuit 2 is electrically connected to the first scan signal line, which is used to transmit the first scan signal Gate1.
[0059] like Figure 2 As shown, the first light-emitting control sub-circuit 4 is configured to drive the light-emitting device to be displayed to emit light in response to the light-emitting control signal EM, through the driving current generated by the driving sub-circuit 1. The control terminal of the first light-emitting control sub-circuit 4 is electrically connected to the light-emitting control signal line, which is used to transmit the light-emitting control signal EM.
[0060] For example, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure. Figure 3 This is a schematic diagram showing the electrical connection between the pixel driving circuit in the i-th row and the pixel driving circuit in the (i+1)-th row, which are located in the same column, according to an embodiment of this disclosure.
[0061] like Figure 3 As shown, the pixel driving circuit may include eight transistors (first transistor T1 to eighth transistor T8) and a storage capacitor Cst. The pixel driving circuit may be electrically connected to seven signal lines (data signal line, first scan signal line, second scan signal line, light emission control signal line, initialization signal line, first power line and second power line).
[0062] It should be noted that the transistors used in the embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no distinction between their source and drain. In the embodiments of this disclosure and the following description, to distinguish between the source and drain of the transistor, one of them is called the first terminal, the other is called the second terminal, and the gate is called the control terminal. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged.
[0063] Furthermore, transistors can be classified into N-type and P-type based on their characteristics. When a P-type transistor is used, the first electrode is the source, and the second electrode is the drain. When a low-level signal is input to the gate, the source and drain are turned on. When an N-type transistor is used, the first electrode is the drain, and the second electrode is the source. When a high-level signal is input to the gate, the source and drain are turned on. This embodiment uses N-type transistors (T1 through T8) as an example for detailed explanation.
[0064] In some embodiments, such as Figure 3As shown, the driving sub-circuit 1 includes a third transistor T3; the control electrode of the third transistor T3 is electrically connected to the third node N3, the first electrode is electrically connected to the fourth node N4, and the second electrode is electrically connected to the first node N1. When the third transistor T3 is turned on, the resulting driving current passes through the first transistor T1 and is used to drive the light-emitting device D to emit light.
[0065] In some embodiments, such as Figure 3 As shown, the bias compensation sub-circuit 3 includes an eighth transistor T8. The control electrode of the eighth transistor T8 is electrically connected to the first scan signal line, the first electrode is electrically connected to the data signal line, and the second electrode is electrically connected to the second node N2. The second electrode of the eighth transistor T8 is also electrically connected to the second electrode of the third transistor T3 in the previous row pixel driving circuit located in the same column. When the eighth transistor T8 responds to the first scan signal Gate1 transmitted by the first scan signal line, the eighth transistor T8 is turned on, thereby transmitting the data signal Data transmitted by the data signal line to the second node N2, and then to the second electrode of the third transistor T3 in the previous row pixel driving circuit, so as to compensate the bias voltage of the second electrode of the third transistor T3 in the previous row pixel driving circuit.
[0066] In some embodiments, such as Figure 3 As shown, the data writing sub-circuit 2 includes a second transistor T2; the control electrode of the second transistor T2 is electrically connected to the first scan signal line, the first electrode is electrically connected to the second node N2, and the second electrode is electrically connected to the first node N1. When the second transistor T2 responds to the first scan signal Gate1 transmitted on the first scan signal line, the second transistor T2 is turned on, thereby writing the potential of the second node N2 into the first node N1.
[0067] For example, such as Figure 3 As shown, the second transistor T2 and the eighth transistor T8 are connected in series, and the second terminal of the eighth transistor T8 is electrically connected to the first terminal of the second transistor T2. At the same time, the control terminals of the second transistor T2 and the eighth transistor T8 are electrically connected to the same first scan signal line. The second transistor T2 and the eighth transistor T8 are simultaneously turned on or off. Therefore, compared with the prior art, this disclosure does not require the addition of a gate drive signal Gate0(i), which can meet the design requirements of a narrow bezel, and does not require the addition of a bias voltage signal Vbias, which is beneficial for providing a high PPI.
[0068] For example, such as Figure 3 As shown, the second transistor T2 and the eighth transistor T8 are connected in series and are simultaneously turned on for writing data signals, which can reduce leakage current.
[0069] In some embodiments, such as Figure 3As shown, the first light-emitting control sub-circuit 4 includes a first transistor T1; the control electrode of the first transistor T1 is electrically connected to the light-emitting control signal line, the first electrode is electrically connected to the first node N1, and the second electrode is electrically connected to the first electrode of the light-emitting device D. When the first transistor T1 responds to the light-emitting control signal EM transmitted by the light-emitting control signal line, the first transistor T1 is turned on, and then the driving current generated by the third transistor T3 drives the light-emitting device D to emit light.
[0070] In some embodiments, such as Figure 2 As shown, the pixel driving circuit also includes a threshold compensation sub-circuit 6. The first terminal of the threshold compensation sub-circuit 6 is electrically connected to the third node N3, the second terminal of the threshold compensation sub-circuit 6 is electrically connected to the fourth node N4, and the control terminal of the threshold compensation sub-circuit 6 is electrically connected to the first scan signal line, which is used to transmit the first scan signal Gate1. The threshold compensation sub-circuit 6 is configured to perform threshold voltage compensation on the driving sub-circuit 1 in response to the first scan signal Gate1.
[0071] In some embodiments, such as Figure 3 As shown, the threshold compensation sub-circuit 6 includes a fourth transistor T4; the control electrode of the fourth transistor T4 is electrically connected to the first scan signal line, the first electrode is electrically connected to the third node N3, and the second electrode is electrically connected to the fourth node N4. When the fourth transistor T4 responds to the first scan signal Gate1 transmitted on the first scan signal line, the fourth transistor T4 is turned on to perform threshold voltage compensation for the third transistor T3.
[0072] In some embodiments, such as Figure 2 As shown, the pixel driving circuit further includes a second light-emitting control sub-circuit 5; the first terminal of the second light-emitting control sub-circuit 5 is electrically connected to a first power supply line, which is used to transmit a first power supply voltage VDD; the second terminal of the second light-emitting control sub-circuit 5 is electrically connected to the second terminal of the driving sub-circuit 1; the control terminal of the second light-emitting control sub-circuit 5 is electrically connected to a light-emitting control signal line, which is used to transmit a light-emitting control signal EM. The second light-emitting control sub-circuit 5 is configured to transmit the first power supply voltage VDD to the driving sub-circuit 1 in response to the light-emitting control signal EM.
[0073] In some embodiments, such as Figure 3 As shown, the second light-emitting control sub-circuit 5 includes a sixth transistor T6; the control electrode of the sixth transistor T6 is electrically connected to the light-emitting control signal line, the first electrode is electrically connected to the first power supply line, and the second electrode is electrically connected to the fourth node N4. When the sixth transistor T6 responds to the light-emitting control signal EM transmitted by the light-emitting control signal line, the sixth transistor T6 is turned on, thereby transmitting the first power supply voltage VDD to the first electrode of the third transistor T3.
[0074] In some embodiments, such as Figure 2As shown, the pixel driving circuit also includes a first reset sub-circuit 7; the first terminal of the first reset sub-circuit 7 is electrically connected to a first power supply line, which is used to transmit a signal of the first power supply voltage VDD; the second terminal of the first reset sub-circuit 7 is electrically connected to a second scan signal line, which is used to transmit a second scan signal Gate2. For two adjacent pixel driving circuits located in the same column, the first scan signal Gate1(i) of the i-th row pixel driving circuit is multiplexed into the second scan signal Gate2(i+1) of the (i+1)-th row pixel driving circuit, that is, the first scan signal line of the i-th row pixel driving circuit is electrically connected to the second scan signal line of the (i+1)-th row pixel driving circuit. The first reset sub-circuit 7 is configured to transmit the first power supply voltage VDD to the driving sub-circuit 1 in response to the second scan signal Gate2.
[0075] In some embodiments, such as Figure 3 As shown, the first reset sub-circuit 7 includes a fifth transistor T5; the control electrode of the fifth transistor T5 is electrically connected to the second scan signal line, the first electrode is electrically connected to the first power supply line, and the second electrode is electrically connected to the third node N3. When the fifth transistor T5 responds to the second scan signal Gate2 transmitted by the second scan signal line, or in other words, when the fifth transistor T5 in the (i+1)th row pixel driving circuit responds to the first scan signal Gate1(i) transmitted by the first scan signal line in the i-th row pixel driving circuit, the fifth transistor T5 is turned on, thereby transmitting the first power supply voltage VDD to the control electrode of the third transistor T3 for resetting the control electrode of the third transistor T3.
[0076] In some embodiments, such as Figure 2 As shown, the pixel driving circuit also includes a second reset sub-circuit 8; the control terminal of the second reset sub-circuit 8 is electrically connected to a reset control signal line, which is used to transmit a reset control signal Rst; the first terminal of the second reset sub-circuit 8 is electrically connected to an initialization signal line, which is used to transmit an initialization signal Vinit; the second terminal of the second reset sub-circuit 8 is electrically connected to the second terminal of the first light-emitting control sub-circuit 4, or in other words, the second terminal of the second reset sub-circuit 8 is electrically connected to the first electrode of the light-emitting device D. The second reset sub-circuit 8 is configured to reset the first electrode of the light-emitting device D in response to the reset control signal Rst.
[0077] In some embodiments, such as Figure 3As shown, the second reset sub-circuit 8 includes a seventh transistor T7; the control electrode of the seventh transistor T7 is electrically connected to the reset control signal line, the first electrode is electrically connected to the initialization signal line, and the second electrode is electrically connected to the first electrode of the light-emitting device D. When the seventh transistor T7 responds to the reset control signal Rst transmitted through the reset control signal line, the seventh transistor T7 is turned on, thereby transmitting the initialization signal Vinit transmitted through the initialization signal line to the first electrode of the light-emitting device D to reset the first electrode of the light-emitting device D.
[0078] For example, the light-emitting device D can be an organic light-emitting diode (OLED).
[0079] For example, the first electrode of the light-emitting device D is, for example, the anode of the light-emitting device D.
[0080] For example, the second electrode of the light-emitting device D is, for example, the cathode of the light-emitting device D, and is electrically connected to the second power line, which is used to transmit the second power supply voltage VSS.
[0081] In some embodiments, such as Figure 2 As shown, the pixel driving circuit also includes a storage capacitor Cst; the first plate of the storage capacitor Cst is electrically connected to the driving sub-circuit 1, and the second plate is electrically connected to the first light-emitting control sub-circuit 4.
[0082] like Figure 3 As shown, the first plate of the storage capacitor Cst is electrically connected to the control terminal of the third transistor T3, the first terminal of the fourth transistor T4, and the second terminal of the fifth transistor T5. The second plate of the storage capacitor Cst is electrically connected to the second terminal of the first transistor T1 and the second terminal of the seventh transistor T7.
[0083] Figure 4 This disclosure provides a timing diagram of a pixel driving circuit according to an embodiment of the present disclosure. Figure 3 Taking the pixel driving circuit cascaded in adjacent rows as an example, each transistor is an N-type transistor.
[0084] Figure 5a This is a schematic diagram illustrating the working principle of the driving circuits for two adjacent pixels located in the same row in the first stage, as provided in an embodiment of this disclosure. Figure 5b This is a schematic diagram illustrating the working principle of the driving circuits for two adjacent pixels located in the same row in the second stage, as provided in an embodiment of this disclosure. Figure 5c This is a schematic diagram illustrating the working principle of the driving circuits for two adjacent pixels located in the same row in the third stage, as provided in an embodiment of this disclosure. Figure 5d This is a schematic diagram of the working principle of two adjacent pixel driving circuits located in the same row in the fourth stage, provided by an embodiment of this disclosure. The wide arrow indicates the direction of the electrical signal after the transistor is turned on.
[0085] The operation of the pixel driving circuit in the i-th row can include the following four stages: stage t1, stage t2, stage t3, and stage t4, where:
[0086] like Figure 4 and Figure 5a As shown, in the first stage t1, which is also the first reset stage, the light-emitting control signal EM(i) transmitted by the light-emitting control signal line is a low-level signal, and the sixth transistor T6 and the first transistor T1 are turned off. The reset control signal Rst(i) is a high-level signal, the seventh transistor T7 is turned on, and the initialization signal Vinit is transmitted to the first terminal of the light-emitting device D to initialize (reset) the first terminal of the light-emitting device D; and the initialization signal Vinit is transmitted to the second terminal of the storage capacitor Cst to initialize (reset) the second terminal. The second scan signal Gate2(i) is a high-level signal, the fifth transistor T5 is turned on, and the first power supply voltage VDD is transmitted to the control terminal of the third transistor T3 to reset the control terminal of the third transistor T3. The first scan signal Gate1(i) is a low-level signal, and the second transistor T2, the eighth transistor T8, and the fourth transistor T4 are all turned off.
[0087] like Figure 4 and Figure 5b As shown, in the second stage t2, which is the data writing and threshold compensation stage, the light emission control signal EM(i) is a low-level signal, and the sixth transistor T6 and the first transistor T1 are turned off. The reset control signal Rst(i) is a high-level signal, the seventh transistor T7 continues to conduct, and the initialization signal Vinit continuously resets the first electrode of the light-emitting device D and the second electrode of the storage capacitor Cst. The second scan signal Gate2(i) is a low-level signal, and the fifth transistor T5 is turned off. The first scan signal Gate1(i) is a high-level signal, and the second transistor T2, the eighth transistor T8, and the fourth transistor T4 are all turned on. Among them, the second transistor T2 and the eighth transistor T8 are turned on, writing the data signal Data(i) into the first node N1. Additionally, at this time, the signal at the control electrode of the third transistor T3 is the first power supply voltage VDD (high-level signal). Therefore, the third transistor T3 is turned on, and the signal of the first node N1 is transmitted to the third node N3 through the turned-on third transistor T3 and the fourth transistor T4. The difference between the voltage of the data signal Data and the threshold voltage of the third transistor T3 is stored in the storage capacitor Cst. The voltage of the first plate of the storage capacitor Cst is Vd+|Vth|, where Vd is the voltage of the data signal Data and Vth is the threshold voltage of the third transistor T3.
[0088] like Figure 5bAs shown, the second stage t2 of the pixel driving circuit in the i-th row is the first stage t1 of the pixel driving circuit in the (i+1)-th row. The working process of the pixel driving circuit in the (i+1)-th row is the same as that of the pixel driving circuit in the i-th row. The repeated parts will not be described again.
[0089] like Figure 4 and Figure 5c As shown, in the third stage t3, which is the bias compensation stage, the light emission control signal EM(i) is a low-level signal, and the sixth transistor T6 and the first transistor T1 are turned off. The reset control signal Rst(i) is a high-level signal, the seventh transistor T7 continues to conduct, and the initialization signal Vinit continuously resets the first electrode of the light-emitting device D and the second electrode of the storage capacitor Cst. The second scan signal Gate2 is a low-level signal, and the fifth transistor T5 is turned off. The first scan signal Gate1(i) is a low-level signal, and the second transistor T2, the eighth transistor T8, and the fourth transistor T4 are all turned off. It should be noted that the third stage t3 of the i-th row pixel driving circuit is also the second stage t2 of the (i+1)-th row pixel driving circuit. At this time, the first scan signal Gate1(i+1) of the (i+1)th row pixel driving circuit is a high-level signal, the eighth transistor T8 of the (i+1)th row pixel driving circuit is turned on, and the voltage of the data signal Data(i+1) is transmitted to the first node N1 of the (i)th row pixel driving circuit. The voltage of the first node N1 changes, and Vg-Vs shifts (i.e., bias voltage compensation). Here, Vg represents the gate voltage of the third transistor T3 of the (i)th row pixel driving circuit. Vg at this time is also Vd+|Vth| in stage t2. Vs represents the source voltage (N1 node voltage) of the third transistor T3 of the (i)th row pixel driving circuit. This bias voltage compensation process can correct the characteristic curve of the third transistor T3, thereby effectively improving the brightness change caused by the hysteresis effect of the third transistor T3 when the display panel is working at low frequency, and improving the uniformity of the display effect.
[0090] like Figure 5c As shown, the third stage t3 of the pixel driving circuit in the i-th row is also the second stage t2 of the pixel driving circuit in the (i+1)-th row. The working process of the pixel driving circuit in the (i+1)-th row is the same as the working process of the pixel driving circuit in the i-th row. The repeated parts will not be described again.
[0091] like Figure 4 and Figure 5dAs shown, in the fourth stage t4, which is the light-emitting stage, the light-emitting control signal EM(i) is a high-level signal, and the sixth transistor T6 and the first transistor T1 are turned on. The reset control signal Rst(i) is a low-level signal, and the seventh transistor T7 is turned off. The second scan signal Gate2(i) is a low-level signal, and the fifth transistor T5 is turned off. The first scan signal Gate1(i) is a low-level signal, and the second transistor T2, the eighth transistor T8, and the fourth transistor T4 are all turned off. The third transistor T3 continues the state after the bias voltage compensation in stage t3 and remains on. The sixth transistor T6 transmits the first power supply voltage VDD to the first terminal of the third transistor T3, and the third transistor T3 generates a driving current that flows through the on-conducting first transistor T1, thereby driving the light-emitting device D to emit light. The driving current generated by the third transistor T3 is determined by its Vg-Vs.
[0092] like Figure 5d As shown, the fourth stage t4 of the pixel driving circuit in the i-th row is also the third stage t3 of the pixel driving circuit in the (i+1)-th row. The working process of the pixel driving circuit in the (i+1)-th row is the same as that of the pixel driving circuit in the i-th row. The repeated parts will not be described again.
[0093] In addition, this disclosure also provides a display device, which includes the display substrate of any of the above embodiments. This display device can be, for example, any product with display functionality such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or in-vehicle device. Other essential components of this display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting this disclosure.
[0094] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.
Claims
1. A display substrate comprising M rows and N columns of pixel units; each pixel unit comprising a pixel driving circuit, wherein M and N are both positive integers greater than 1; the pixel driving circuit comprising a driving sub-circuit, a data writing sub-circuit, a bias compensation sub-circuit, and a first light emission control sub-circuit; The first terminal of the driving sub-circuit and the second terminal of the data writing sub-circuit are electrically connected to the first node; the first terminal of the data writing sub-circuit and the second terminal of the bias compensation sub-circuit are electrically connected to the second node; the first terminal of the first light-emitting control sub-circuit is electrically connected to the first node; For the pixel driving circuits located in the same column, the first node of the pixel driving circuit in the i-th row is electrically connected to the second node of the pixel driving circuit in the (i+1)-th row; i takes a positive integer from 1 to (M-1); The bias compensation sub-circuit is configured to write a data signal to the second node in response to a first scan signal; and, for the pixel driving circuit in the (i+1)th row, the bias compensation sub-circuit is further configured to write the potential of the second node to the first node of the pixel driving circuit in the same column and the i-th row after writing the data signal to the second node in response to the first scan signal. The data writing sub-circuit is configured to write the potential of the second node into the first node in response to the first scan signal; The first light emission control sub-circuit is configured to drive the light emission device to be displayed to emit light through the drive current generated by the drive sub-circuit in response to the light emission control signal.
2. The display substrate according to claim 1, wherein, The driving sub-circuit includes a third transistor; The control electrode of the third transistor is electrically connected to the third node, the first electrode is electrically connected to the fourth node, and the second electrode is electrically connected to the first node.
3. The display substrate according to claim 1, wherein, The bias compensation sub-circuit includes an eighth transistor; The control electrode of the eighth transistor is electrically connected to the first scan signal line, the first electrode is electrically connected to the data signal line, and the second electrode is electrically connected to the second node.
4. The display substrate according to claim 3, wherein, The data writing sub-circuit includes a second transistor; The control electrode of the second transistor is electrically connected to the first scan signal line, the first electrode is electrically connected to the second node, and the second electrode is electrically connected to the first node.
5. The display substrate according to claim 3, wherein, The pixel driving circuit also includes a threshold compensation sub-circuit; The threshold compensation sub-circuit is configured to perform threshold voltage compensation on the driving sub-circuit in response to the first scan signal.
6. The display substrate according to claim 5, wherein, The threshold compensation sub-circuit includes a fourth transistor; The control electrode of the fourth transistor is electrically connected to the first scan signal line, the first electrode is electrically connected to the third node, and the second electrode is electrically connected to the fourth node.
7. The display substrate according to claim 1, wherein, The first light-emitting control sub-circuit includes a first transistor; The control electrode of the first transistor is electrically connected to the light-emitting control signal line, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the first electrode of the light-emitting device.
8. The display substrate according to claim 7, wherein, The pixel driving circuit also includes a second light emission control sub-circuit; The second light-emitting control sub-circuit is configured to transmit a first power supply voltage to the driving sub-circuit in response to the light-emitting control signal.
9. The display substrate according to claim 8, wherein, The second light-emitting control sub-circuit includes a sixth transistor; The control electrode of the sixth transistor is electrically connected to the light-emitting control signal line, the first electrode is electrically connected to the first power supply line, and the second electrode is electrically connected to the fourth node.
10. The display substrate according to claim 1, wherein, The pixel driving circuit also includes a first reset sub-circuit; The first reset sub-circuit is configured to transmit a first power supply voltage to the drive sub-circuit in response to a second scan signal; For two adjacent pixel driving circuits located in the same column, the first scan signal of the pixel driving circuit in the i-th row is multiplexed as the second scan signal of the pixel driving circuit in the (i+1)-th row.
11. The display substrate according to claim 10, wherein, The first reset circuit includes a fifth transistor; The control electrode of the fifth transistor is electrically connected to the second scan signal line, the first electrode is electrically connected to the first power supply line, and the second electrode is electrically connected to the third node.
12. The display substrate according to claim 1, wherein, The pixel driving circuit also includes a second reset sub-circuit; The second reset sub-circuit is configured to reset the first electrode of the light-emitting device in response to a reset control signal.
13. The display substrate according to claim 12, wherein, The second reset circuit includes a seventh transistor; The control electrode of the seventh transistor is electrically connected to the reset control signal line, the first electrode is electrically connected to the initialization signal line, and the second electrode is electrically connected to the first electrode of the light-emitting device.
14. The display substrate according to claim 1, wherein, The pixel driving circuit also includes a storage capacitor; the first plate of the storage capacitor is electrically connected to the driving sub-circuit, and the second plate is electrically connected to the first light-emitting control sub-circuit.
15. A display device, wherein, Includes the display substrate as described in any one of claims 1 to 14.