Method of manufacturing a semiconductor device and corresponding semiconductor device

Abstract

The present disclosure relates to a method of manufacturing a semiconductor device and a corresponding semiconductor device. A semiconductor die is attached on a die attachment portion of a planar substrate. A planar conductive clip is mounted to the semiconductor die. The semiconductor die is clamped between the die attachment portion and the conductive clip. A distal end portion of the conductive clip extending away from the semiconductor die is spaced apart from a conductive lead of the planar substrate by a gap. The gap is filled by a gap-filling material mass transferred to an upper surface of the conductive lead via a laser-induced forward transfer (LIFT) process. The gap-filling material mass is sized and dimensioned to substantially fill the gap.

Description

[0001] CLAIM OF PRIORITY

[0002] This application claims priority to Italian Patent Application No. 102022000009839 filed May 12, 2022, the contents of which are hereby incorporated by reference in their entirety to the maximum extent legally permissible. TECHNICAL FIELD

[0003] The present specification relates to manufacturing semiconductor devices.

[0004] By way of example, the present specification relates to double-sided cooling packages for manufacturing semiconductor devices. BACKGROUND

[0005] Double-sided cooling packages for semiconductor power devices currently comprise a leadframe as a substrate and one or more semiconductor chips or dies sandwiched between the substrate and one or more flat clips (wherein “flat” means that the clip does not comprise any bending or curved portions; i.e., the clip is substantially planar).

[0006] The assembly thus created comprises a gap formed between the substrate and the mutually facing (distal) portions of the flat clip(s) due to the die thickness (such as 70 microns).

[0007] It can be attempted to accommodate such a gap by machining the clip material (e.g., via milling or extrusion), which can be expensive.

[0008] Another approach can involve clip end bending (such as by providing a bend with a corresponding curved portion to account for the die thickness gap); this is hardly feasible due to the clip thickness (more than 600 microns).

[0009] Yet another approach can involve using a leadframe with a double lead level or a leadframe created in two different portions connected later: this is again quite expensive. In any case, a dedicated leadframe and / or clip can reduce time to market and increase the final cost of the product.

[0010] It can also be considered to use solder paste or glue to mount a standoff / spacer (such as a thin copper foil). Such an approach is difficult to implement because the resulting assembly is exposed to a (first) oven reflow for die attachment before clip mounting. The temperature rise resulting from the reflow tends to cause unwanted spacer bending / peeling.

[0011] Thus, there is a need in the art to address the problems discussed in the foregoing. SUMMARY

[0012] One or more embodiments can relate to a method.

[0013] One or more embodiments are also directed to corresponding semiconductor devices.

[0014] In the solution as described herein, spacers (e.g., copper) are formed on the lead side via a laser-induced forward transfer (LIFT) process to compensate for die thickness.

[0015] For example, the LIFT process can accommodate high die thickness in a direct write approach.

[0016] For different die thicknesses, the related process can be easily tuned without having to manage different clip or leadframe references.

[0017] Within the context of use considered herein, it has been found that the LIFT process is largely advantageous over other “printing” processes.

[0018] The solution as presented herein provides one or more of the following advantages: adaptability (“customization”) to different types of power packages; applicability to leadframes and clips with a single thickness (“single thickness”); cost savings (only a leadframe preparation step can be added); ability to simply cover a variety of products / packages; and single assembly step has no significant impact on the rest of the assembly flow. BRIEF DESCRIPTION OF DRAWINGS

[0019] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings in which:

[0020] Figure 1 is a cross-sectional view of a semiconductor power device suitable for manufacture with embodiments of the present specification;

[0021] Figure 2A , Figure 2B and Figure 2C are illustrations of steps in a laser-induced forward transfer (LIFT) process, and

[0022] Figures 3A to 3F is an illustration of possible steps in implementing embodiments of the present specification. DETAILED DESCRIPTION

[0023] Unless otherwise indicated, corresponding numbers and symbols in different drawings generally refer to corresponding parts.

[0024] The drawings are drawn to clearly illustrate relevant aspects of the embodiments and are not necessarily drawn to scale.

[0025] Edges of features drawn in the drawings do not necessarily indicate termination of a range of the feature.

[0026] In the following description, one or more specific details are described to provide an example embodiment of the disclosure. One or more other embodiments of the disclosure can not use all of the specific details described below. In other instances, well-known structures, materials, or operations are not shown or described in detail in order to avoid obscuring aspects of the example embodiments.

[0027] Reference throughout this specification to "an embodiment" or "one embodiment" means that a particular configuration, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The appearances of the phrase "in an embodiment" or "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.

[0028] Furthermore, the particular configurations, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0029] The headings / reference herein are provided merely for convenience and thus do not limit the scope of protection or the embodiments.

[0030] For simplicity and ease of explanation, throughout this specification: like parts or elements are indicated with like reference numbers in the various figures, and corresponding descriptions will not be repeated for every figure; and a single device will be described, which is otherwise understood to mean that current manufacturing processes for semiconductor devices involve the simultaneous manufacture of multiple devices, which are separated into individual individual devices in a final singulation step.

[0031] Figure 1 is a cross-sectional view through a semiconductor (power) device 10, which includes, in a manner known per se to the skilled person: a metal base plate (lead frame) 12, which in turn includes a die mounting area (die pad) 12A onto which one or more semiconductor integrated circuit chips or dies 14 are mounted via a layer of solder paste (not visible due to scale); and one or more flat metal clips 16, which in turn are arranged onto the one or more chips 14 to provide electrical connections between the one or more chips 14 and a set of electrically conductive "distal" leads 12B (on the left-hand side of the figure) of the lead frame 12.

[0032] On the right-hand side of Figure 1 other leads 12B associated with the die mounting portion 12A of the lead frame 12 are visible. It will be noted that the upper surface of the die mounting portion 12A of the lead frame 12 and the upper surfaces of the set of electrically conductive "distal" leads 12B are coplanar.

[0033] The term “lead frame” (or “lead frame”) is currently used (see, for example, the USPC Combined Glossary of Terms) to refer to a metal frame that provides support for an integrated circuit chip or die, and electrical leads that interconnect the integrated circuit in the chip or die to other electrical components or contacts.

[0034] Basically, the lead frame includes an array of conductive formations (or leads, e.g., 12B) extending inward from the contour location in the direction of the semiconductor chip or die (e.g., 14) to form an array of conductive formations from a die pad (e.g., 12A) configured to have at least one semiconductor integrated circuit chip or die attached thereto.

[0035] For simplicity, the single chip or die 14 and the single flat clip 16 will be referred to throughout this specification. This is also to be understood that the solutions discussed herein are applicable to devices comprising multiple semiconductor chips or dies 14 and / or multiple clips 16.

[0036] Insulating material 18 (e.g., epoxy resin: the outline of material 18 is in) Figure 1 The package (shown in dashed lines) is molded onto the assembly described herein, leaving leads 12B accessible. Thus, a housing is provided that surrounds the semiconductor material to protect it from corrosion or physical damage, while facilitating mounting of the device onto a mounting substrate (not visible in the figure), such as a printed circuit board (PCB).

[0037] Figure 1 Observations show that, due to the thickness of the bare die 14, a gap G is formed between the "far end" of the clip 14 and the lead 12B arranged facing the far end of the clip 16.

[0038] By way of reference only (and without limitation), leadframe 12B may have a thickness of 500 micrometers and die 14 may instead have a thickness of 70 micrometers for the thickness of the die attachment material used to attach die 14 to leadframe 12.

[0039] Therefore, the gap G can have a thickness of approximately 70 ± 25 micrometers (in Figure 1 (width in the vertical direction). Of course, this quantitative figure is merely exemplary and does not limit the embodiments.

[0040] As discussed, the gap indicated by G (between the upper surface of lead 12B and the bottom surface of clip 16) can be attempted to be compensated (bridging) by resorting to different methods (milling / extrusion of clip material, bending of clip, lead frame with dual lead hierarchy or including two different elements connected).

[0041] These methods exhibit various types of drawbacks.

[0042] For example, in the case of clip material milling, it can be necessary to remove a considerable amount of clip material, possibly adhering to quite strict tolerances in terms of thickness and flatness. In addition, this can be a rather expensive solution.

[0043] Due to the thickness of the clip material 16 (e.g., 650 microns), clip bending can involve the risk of breaking (one or more) dies 14.

[0044] Recourse to a dual leadframe level or a leadframe comprising separate elements is generally expensive and can involve additional assembly steps.

[0045] The solution as discussed herein solves the problem of compensating (bridging) the gap (such as gap G) by growing an electrically conductive material and recourse to a laser-induced forward transfer (LIFT) technique, while supporting the use of a flat (planar) clip and a coplanar upper surface of the die mounting portion 12A and a set of electrically conductive “distal” leads 12B of the leadframe 12.

[0046] The acronym LIFT stands for a deposition process in which material from a donor tape or sheet is transferred to a receiver substrate with the help of a laser pulse.

[0047] General information on the LIFT process can be found in, for example, P. Serra et al., “Laser-Induced Forward Transfer: Fundamentals and Applications”, in Advanced Materials Technologies / Volume 4, Issue 1 (incorporated herein by reference).

[0048] Basically, the solution as discussed herein foresees the gap G to be filled or bridged (via the electrically conductive material mass 20) via an electrically conductive material mass 20 transferred via a LIFT process onto the lead 12A facing the distal end of the flat clip 16.

[0049] It is noted that the LIFT process facilitates providing a “customized” connection between the backside or bottom side of the flat clip 16 and the leads 12A in the leadframe 12, as compared to other “printing” processes which can be conceived to fill the gap G.

[0050] Advantageously, the LIFT process facilitates adapting the thickness of the material transferred via the LIFT process (typically in a subsequent layer) to the width of the gap G by precisely adapting to possible variations of the gap G (e.g., variations in die thickness of various dies in a batch).

[0051] Figure 2A、 Figure 2B and Figure 2C are exemplifications of possible implementations of LIFT processes advantageously configured for use in the context as considered herein.

[0052] In Figure 2A , reference 100 indicates a paste dispenser head configured to deposit a conductive paste 104 (such as Ag / Cu paste) on a donor film 102.

[0053] Figure 2B is an exemplification of the possibility of spreading the paste 104 via a laminator 106 (essentially a squeegee) to a desired width (and thickness).

[0054] As Figure 2C exemplified, a laser beam LB from a laser source 108 can then be used to transfer the paste 104 from the donor film 102 to a substrate such as, for example, the upper surface of a leadframe 12 (at lead 12B located at gap G).

[0055] Essentially, the role of the laser source 108 (such as a UV laser) is to “shoot” a laser beam LB onto the backside of the donor tape 102 so that the paste 104 spread on the front side of the donor tape 102 (in ultra-fast mode) is projected and dispensed onto the upper surface of the substrate 12 to provide a “gap-bridging” material 20 in one or more steps.

[0056] Figures 3A to 3F illustrates a possible sequence of steps to implement the solution as discussed herein.

[0057] It will additionally be appreciated that Figures 3A to 3F the order of the steps of is merely exemplary, in that: Figures 3A to 3F one or more of the steps illustrated in may be omitted, performed in a different manner (such as with other tools) and / or replaced by other steps; additional steps can be added; and one or more steps can be performed in a different order than the order illustrated.

[0058] Figure 3A is an exemplification of a leadframe 12 comprising a die-mounting portion (die pads) 12A and conductive leads, including “distal” leads (at the left-hand side of the figure) at which a gap G can be formed for the reasons discussed in the foregoing.

[0059] Figure 3B exemplifies depositing one or more layers of material (such as, for example, copper) onto the “distal” leads 12B of the leadframe 12 (via a LIFT process) up to a resulting thickness corresponding to the thickness of the gap G to be bridged.

[0060] This thickness is known in advance, as the thickness of the die 14 (and of the die attach material of the die 14 onto the die pads 12A of the leadframe 12) is known as a process parameter. It is further noted that the solution as discussed herein can adapt to different thicknesses of the die 14 (and of the die attach material) in a very flexible manner.

[0061] Figure 3C A die attach layer 14A such as of solder paste is exemplified to facilitate die attach as shown in Figure 3D

[0062] Figure 3E A material such as solder paste is exemplified to be dispensed onto the upper surface of the chip 14 (solder paste 140) and onto the upper surface of the one or more LIFT deposited layers 20 (solder paste material 200) to facilitate attachment of one or more flat clips 16 as exemplified in Figure 3F

[0063] It is noted from Figure 1 that the flat clip 16 comprises at its bottom surface a notch between the portion of the back surface that is attached to the chip 14 and the portion of the back surface that is attached to the layer 20. This notch is aligned with the peripheral edge of the chip 14 when the clip 16 is mounted.

[0064] It is noted that the solder paste layers 140 and 200 can have the same thickness and thus can not play a major role in compensating for the gap G.

[0065] As exemplified in dashed lines in Figure 3F the resulting assembly, an insulating encapsulation 18 can then be formed as otherwise customary in the art.

[0066] As mentioned above, Figures 3A to 3F the steps illustrated in

[0067] For example, the material 20 can be LIFT deposited onto the "distal" leads 12B of the leadframe 12 before the chip 14 is mounted on the leadframe 12 (as illustrated), after the chip 14 is mounted on the leadframe 12, or simultaneously with mounting the chip 14 on the leadframe 12.

[0068] The material 20 (such as copper) can be deposited via LIFT processing in one or more layers up to a resulting thickness that corresponds to the thickness of the gap G to be bridged.

[0069] The solution as discussed herein can adapt to different thicknesses of the die 14 (and of the die attach material) in a very flexible manner.

[0070] ​​The details and embodiments can vary, even considerably, with respect to what has been described by way of example only, without departing from the scope of protection.

[0071] The claims are an integral part of the technical teaching provided herein in relation to the embodiments.

[0072] The scope of protection is defined by the appended claims.

Claims

1. A method of manufacturing a semiconductor device, comprising: attaching a semiconductor integrated circuit die to an upper surface of a die attach portion of a substrate, the substrate further comprising a conductive lead having an upper surface coplanar with the upper surface of the die attach portion; prior to attaching the semiconductor integrated circuit die to the substrate, transferring a mass of conductive material onto the upper surface of the conductive lead by using a laser induced forward transfer (LIFT) process to form a gap fill spacer; and mounting a bottom surface of a flat conductive clip to the semiconductor integrated circuit die attached to the die attach portion of the substrate and to the gap fill spacer using a solder paste material; wherein the semiconductor integrated circuit die is sandwiched between the die attach portion of the substrate and the conductive clip; wherein the flat conductive clip has a distal end portion extending away from the semiconductor integrated circuit die; wherein the gap fill spacer is sandwiched between the conductive lead and the distal end portion of the flat conductive clip; and wherein the mass of conductive material comprises a mass made of copper or silver.

2. The method of claim 1, wherein transferring comprises: Multiple transfers of a mass of conductive material are performed using a corresponding plurality of LIFT process steps.

3. The method of claim 1, wherein a bottom surface of the flat conductive clip mounted to the semiconductor integrated circuit die is coplanar with a bottom surface of the flat conductive clip mounted to the gap fill spacer.

4. The method of claim 3, further comprising: A notch is formed in the flat conductive clip between a bottom surface of the flat conductive clip mounted to the semiconductor integrated circuit die and a bottom surface of the flat conductive clip mounted to the gap fill spacer.

5. The method of claim 4, wherein installing comprises: The notch is aligned with an edge of the semiconductor integrated circuit die.

6. A semiconductor device, comprising: a semiconductor integrated circuit die attached to an upper surface of a die attach portion of a substrate, the substrate further comprising a conductive lead having an upper surface coplanar with the upper surface of the die attach portion; a gap fill spacer at the upper surface of the conductive lead, the gap fill spacer formed by transferring a mass of conductive material onto the upper surface of the conductive lead using a laser induced forward transfer (LIFT) process prior to attaching the semiconductor integrated circuit die to the substrate; and a flat conductive clip having a bottom surface mounted to the semiconductor integrated circuit die and the gap fill spacer using a solder material; wherein the semiconductor integrated circuit die is sandwiched between the die attach portion of the substrate and the flat conductive clip; wherein the conductive clip has a distal end portion extending away from the semiconductor integrated circuit die; wherein the gap fill spacer is sandwiched between the conductive lead and the distal end portion of the flat conductive clip; and wherein the mass of conductive material for the gap fill spacer comprises copper or silver.

7. The apparatus of claim 6, wherein a bottom surface of the flat conductive clip mounted to the semiconductor integrated circuit die is coplanar with a bottom surface of the flat conductive clip mounted to the gap fill spacer.

8. The apparatus of claim 7, wherein the flat conductive clip includes a notch between the bottom surface of the flat conductive clip mounted to the semiconductor integrated circuit die and the bottom surface of the flat conductive clip mounted to the gap fill spacer.

9. The apparatus of claim 8, wherein the notch is aligned with an edge of the semiconductor integrated circuit die.

10. The apparatus of claim 6, wherein the gap fill spacer is formed by a plurality of transfers of a mass of conductive material using a corresponding plurality of LIFT processing steps.

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