An array substrate, a display panel, and a display device.

Abstract

This invention discloses an array substrate, a display panel, and a display device to improve the display defects caused by capacitive coupling due to data line voltage jumps in existing display panels. The array substrate includes: a substrate; a first metal layer located on one side of the substrate and having a plurality of transistor first electrodes; and a first conductive layer located on the side of the first metal layer opposite to the substrate, including: a plurality of first portions, at least a portion of which overlaps with at least a portion of the transistor first electrodes projected onto the substrate.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to an array substrate, a display panel, and a display device. Background Technology

[0002] Thin Film Transistor-Liquid Crystal Displays (TFT-LCDs) have several commonly used display modes, such as Twisted Nematic (TN), Vertically Aligned (VA), Fringe Field Switching (FFS), and In-Plane Switching (IPS). Among these, the VA mode offers better dark-state performance and higher contrast compared to other display modes.

[0003] However, existing display panels suffer from display defects caused by capacitive coupling due to voltage jumps in the data lines. Summary of the Invention

[0004] The present invention provides an array substrate, a display panel, and a display device to improve the display defects caused by capacitive coupling due to data line voltage jumps in existing display panels.

[0005] This invention provides an array substrate, comprising:

[0006] Substrate;

[0007] A first metal layer, located on one side of the substrate, has multiple transistor first electrodes;

[0008] A first conductive layer, located on the side of the first metal layer opposite to the substrate, includes: a plurality of first portions, at least a portion of which overlaps with at least a portion of which is projected onto the substrate.

[0009] In one possible implementation, the first electrode of the transistor includes: a main portion extending along a first direction, and a branch portion connected to one end of the main portion and extending perpendicular to the first direction;

[0010] The first portion extends along the first direction, and the first portion is projected onto the substrate, covering the main portion projected onto the substrate.

[0011] In one possible implementation, the plurality of transistor first electrodes includes: a first type of transistor first electrode and a second type of transistor first electrode; the length of the main portion of the first type of transistor first electrode in the first direction is greater than the length of the main portion of the second type of transistor first electrode in the first direction;

[0012] The plurality of first portions include: a first type of first portion and a second type of first portion; the orthographic projection of the first type of first portion on the substrate covers the orthographic projection of the main portion of the first electrode of the first type of transistor on the substrate; the orthographic projection of the second type of first portion on the substrate covers the orthographic projection of the main portion of the first electrode of the second type of transistor on the substrate; the length of the first type of first portion in the first direction is greater than the length of the second type of first portion in the first direction.

[0013] In one possible implementation, the length of the first portion of the first type in the first direction is equal to the length of the main portion of the first electrode of the first type of transistor in the first direction;

[0014] The length of the first part of the second type in the first direction is equal to the length of the main part of the first electrode of the second type transistor in the first direction.

[0015] In one possible implementation, the first metal layer further includes: a plurality of data lines extending along a second direction;

[0016] The first conductive layer further includes: a first trace extending along the second direction; the orthographic projection of the first trace on the substrate covers the orthographic projection of the data line on the substrate.

[0017] In one possible implementation, the array substrate further includes:

[0018] Multiple gate line groups are located between the substrate and the first metal layer and extend along the first direction. Each gate line group includes two gate lines extending along the first direction.

[0019] Multiple pixel electrodes are located on the same side of the substrate as the gate line group. The multiple pixel electrodes include: a first type of pixel electrode and a second type of pixel electrode located in the area formed by the intersection of the gate line group and the data line and connected to the same data line. The second type of pixel electrode is located on the side of the first type of pixel electrode away from the connected data line.

[0020] A plurality of transistors are located on the same side of the substrate as the gate line group, the plurality of transistors including: a first type of transistor and a second type of transistor; wherein the first type of transistor is electrically connected to a first type of pixel electrode, and the second type of transistor is electrically connected to a second type of pixel electrode; the first type of transistor includes a first electrode of the first type of transistor, and the second type of transistor includes a first electrode of the second type of transistor.

[0021] In one possible implementation, the first conductive layer is on the same layer as the pixel electrode, and the first portion is insulated from the pixel electrode.

[0022] In one possible implementation, the maximum length of the first part in the first direction is less than or equal to the maximum length of the pixel electrode in the first direction.

[0023] In one possible implementation, the orthographic projection of the first portion onto the substrate overlaps with the orthographic projection of the gap between two gate lines of the same gate line group onto the substrate.

[0024] In one possible implementation, the orthographic projection of the first part onto the substrate does not overlap with the orthographic projection of the gate line onto the substrate.

[0025] In one possible implementation, the array substrate further includes: a first common signal line group located between adjacent gate line groups and extending along the second direction, the first common signal line group including two first common signal lines located on different sides of the data line, and the first common signal line groups extending in the same direction are disconnected at the gate line groups;

[0026] The orthographic projection of the first common signal line onto the substrate at least partially overlaps with the orthographic projection of the pixel electrode onto the substrate.

[0027] In one possible implementation, the array substrate further includes: a second common signal line located between adjacent gate line groups and extending along the second direction, the second common signal line being located between the first type of pixel electrode and the second type of pixel electrode;

[0028] The orthographic projection of the second common signal line onto the substrate partially overlaps with the orthographic projection of the pixel electrode onto the substrate.

[0029] This invention also provides a display panel, including the array substrate as described in this invention embodiment, and a counter substrate disposed opposite to the array substrate, the counter substrate being provided with a common electrode layer.

[0030] In one possible implementation, the voltage applied to the first conductive layer is the same as the voltage applied to the common electrode layer.

[0031] This invention also provides a display device, including the display panel as described in this invention embodiment.

[0032] The beneficial effects of the embodiments of the present invention are as follows: In the embodiments of the present invention, the array substrate is further provided with a first conductive layer on the side of the first metal layer away from the substrate. The first conductive layer includes a plurality of first conductive parts. At least a portion of the first part projected onto the substrate overlaps with at least a portion of the first electrode of the transistor projected onto the substrate. This can shield the signal loaded on the first electrode of the transistor, reduce or eliminate the capacitive coupling effect between the first electrode of the transistor and the common electrode, thereby improving the signal jump caused by the first electrode of the transistor. The voltage of the common electrode will be pulled by the coupling capacitance, resulting in an abnormal voltage difference between the pixel electrode voltage and the common electrode, leading to abnormal grayscale brightness values, and thus causing crosstalk, head-shaking patterns and uneven flickering in specific images. Attached Figure Description

[0033] Figure 1A Show the schematic diagram for the Dual Gate driver architecture;

[0034] Figure 1B This is a pixel image of the Dual Gate driver structure.

[0035] Figure 1C This is a schematic diagram illustrating the coupling of Data voltage jumps with COM voltage fluctuations.

[0036] Figure 1D A schematic diagram illustrating a malfunction in the Dual Gate;

[0037] Figure 2A This is one of the top view schematic diagrams of the array substrate provided in the embodiments of the present invention;

[0038] Figure 2B for Figure 2A Schematic diagram of a single film layer of the middle gate line layer;

[0039] Figure 2C for Figure 2A A schematic diagram of a single-film layer with an active layer;

[0040] Figure 2D for Figure 2A A schematic diagram of a single film layer of the first metal layer in the middle;

[0041] Figure 2E for Figure 2A A schematic diagram of a single film layer of the first conductive layer in the middle;

[0042] Figure 3A for Figure 2AA schematic diagram of the cross section at the dashed line EF in the middle;

[0043] Figure 3B for Figure 2A A schematic diagram of the cross-section at the dashed line GH in the middle;

[0044] Figure 4A Schematic diagram of the shielded circuit design for the Dual Gate driven pixel coupling capacitor in related technologies;

[0045] Figure 4B This is a schematic diagram of the shielding circuit design for the Dual Gate driving pixel coupling capacitor of the present invention. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0047] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0048] As used herein, “approximately” or “substantially the same” includes the stated value and means within an acceptable range of deviations from the specific value, as determined by a person skilled in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., limitations of the measurement system). For example, “substantially the same” may mean a difference relative to the stated value within one or more standard deviations, or within ±30%, 20%, 10%, or 5%.

[0049] In the accompanying drawings, the thicknesses of layers, films, panels, regions, etc., are enlarged for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic diagrams of idealized embodiments. Thus, deviations from the shapes shown in the drawings will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include deviations in shape caused, for example, by manufacturing processes. For example, regions illustrated or described as flat may typically have rough and / or non-linear characteristics. Furthermore, sharp corners illustrated may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, nor are they intended to limit the scope of the claims.

[0050] To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0051] The dual-gate driving structure design, compared to the single-gate design, doubles the number of gate lines and halves the number of data lines at the same resolution. For display panels where the source driver chip is integrated with an external chip-on-film (COF) film, this means that COF usage can be reduced by half. Compared to the single-gate design, the dual-gate driving architecture integrates the gate driver chip into the array substrate layer (GOA), which can significantly reduce production costs. Compared to the single-gate pixel structure design, the dual-gate driving design shows a significant difference in the length of the source terminals on the left and right sides of the data lines, such as… Figure 1A As shown, in the existing Dual Gate driver design, the write signals for both the first pixel P1 and the second pixel P2 are provided by the data line D1; however, the lengths of the sources for the first pixel P1 and the second pixel P2 are different (e.g., ...). Figure 1B As shown), the Source length of the first pixel P1 is shorter than that of the second pixel P2; according to the data line signal waveform and the capacitive coupling effect of the common electrode Vcom, that is, as long as there is a jump in the electrical signal voltage, there will be a voltage jump effect due to capacitive coupling; when the common electrode Vcom is pulled by the data signal voltage jump coupling capacitor, the voltage of the common electrode Vcom changes (e.g. Figure 1C (As shown in the physical example), this causes a change in the voltage difference between the pixel electrode and the common electrode Vcom. The abnormal voltage difference between the pixel electrode and the common electrode results in abnormal grayscale brightness values, macroscopically manifesting as specific crosstalk, flickering, and other uneven display effects. Figure 1D(As shown). In the Dual Gate driver design, the source lengths of the pixels on the left and right sides of the data input are inconsistent, meaning the source lengths of the first pixel P1 and the second pixel P2 are different. This causes inconsistent coupling voltage transitions between the first pixel P1 and the second pixel P2 due to data voltage transitions. Simultaneously, the number of data lines in the Dual Gate driver design is halved, while the data output pulse signal is doubled. This means the data signal pulse signal transitions are doubled, and the frequency of voltage coupling transitions is doubled. The frequency of the pixel display voltage difference between the first pixel P1 and the second pixel P2 is further amplified, resulting in more pronounced differences in brightness and darkness. Macroscopically, this manifests as a deterioration in display effects such as crosstalk, head-shaking lines, and uneven flickering in specific scenes.

[0052] In view of this, see Figures 2A-2E , Figure 3A and Figure 3B As shown, where, Figure 2A This is one of the top view schematic diagrams of the array substrate provided in the embodiments of the present invention. Figure 2B for Figure 2A Schematic diagram of a single film layer of the middle gate line layer. Figure 2C for Figure 2A A schematic diagram of a single-film layer with an active layer. Figure 2D for Figure 2A A schematic diagram of the single-film layer of the first metal layer in the middle. Figure 2E for Figure 2A A schematic diagram of the single-film layer of the first conductive layer in the middle. Figure 3A for Figure 2A A schematic diagram of the cross-section at the dashed line EF. Figure 3B for Figure 2A A cross-sectional schematic diagram along the dashed line GH in the middle. An embodiment of the present invention provides an array substrate, comprising:

[0053] Substrate 1;

[0054] The first metal layer 3 is located on one side of the substrate 1 and has multiple transistor first electrodes S; specifically, the transistor first electrode S can be the source electrode of the transistor; specifically, the first metal layer 3 can be the metal layer where the source electrode is located; specifically, the first metal layer 3 can be the metal layer where the data line is located.

[0055] The first conductive layer 4, located on the side of the first metal layer 3 facing away from the substrate 1, includes: a plurality of first portions D, at least a portion of the first portions D projected onto the substrate 1 overlapping at least a portion of the transistor first electrode D projected onto the substrate 1. Specifically, the first portions D projected onto the substrate 1 cover the portion of the transistor first electrode D projected onto the substrate 1; specifically, the first portions D projected onto the substrate 1 cover the entirety of the transistor first electrode D projected onto the substrate 1.

[0056] In this embodiment of the invention, the array substrate is further provided with a first conductive layer 4 on the side of the first metal layer 3 facing away from the substrate 1. The first conductive layer 4 includes a plurality of first conductive portions D. At least a portion of the first portion D projected onto the substrate 1 overlaps with at least a portion of the first electrode D of the transistor projected onto the substrate 1. This can shield the signal loaded by the first electrode S of the transistor, reduce or eliminate the capacitive coupling effect between the first electrode S of the transistor and the common electrode Vcom, thereby improving the signal jump caused by the first electrode S of the transistor. The voltage of the common electrode Vcom will be pulled by the coupling capacitance, causing the voltage difference between the pixel electrode voltage and the common electrode to be abnormal, resulting in abnormal grayscale brightness values, and thus causing crosstalk, flickering and other display problems in specific images.

[0057] In one possible implementation, see Figures 2A-2E , Figure 3A and Figure 3B As shown, the first electrode S of the transistor includes: a main portion SA extending along a first direction X, and a branch portion SB connected to one end of the main portion SA and extending perpendicular to the first direction X; a first portion D extends along the first direction X, and the orthographic projection of the first portion D onto the substrate 1 covers the orthographic projection of the main portion SA onto the substrate 1. In this embodiment of the invention, the orthographic projection of the first portion D onto the substrate 1 only covers the orthographic projection of the main portion SA of the first electrode S of the transistor onto the substrate 1, so as to avoid the main portion SA overlapping with the gate line 20 and causing other adverse problems that are detrimental to the display.

[0058] In one possible implementation, see Figures 2A-2E , Figure 3A and Figure 3B As shown, the first electrode S of the plurality of transistors includes: a first electrode S1 of a first type of transistor and a first electrode S2 of a second type of transistor; the length b1 of the main part SA of the first electrode S1 of the first type of transistor in the first direction X is greater than the length b2 of the main part SA of the first electrode S2 of the second type of transistor in the first direction X.

[0059] The plurality of first parts D include: a first type of first part D1 and a second type of first part D2; the orthographic projection of the first type of first part D1 onto the substrate 1 covers the orthographic projection of the main part SA of the first electrode S1 of the first type of transistor onto the substrate 1; the orthographic projection of the second type of first part D2 onto the substrate 1 covers the orthographic projection of the main part SA of the first electrode S2 of the second type of transistor onto the substrate 1; the length c1 of the first type of first part D1 in the first direction X is greater than the length c2 of the second type of first part D2 in the first direction X.

[0060] Optionally, further, the first part D1 of the first type is projected onto the substrate 1, while simultaneously covering the projection of the branch SB of the first electrode S1 of the first type transistor onto the substrate 1; the first part D2 of the second type is projected onto the substrate 1, while simultaneously covering the projection of the branch SB of the first electrode S2 of the second type transistor onto the substrate 1.

[0061] In this embodiment of the invention, for transistors with different lengths of first electrode S, corresponding first-type first part D1 and second-type first part D2 of the same length can be respectively set. The orthographic projection of the first-type first part D1 onto the substrate 1 covers the orthographic projection of the main part SA of the first-type transistor S1 onto the substrate 1; the orthographic projection of the second-type first part D2 onto the substrate 1 covers the orthographic projection of the main part SA of the second-type transistor S2 onto the substrate 1. In this way, the problem of different brightness differences caused by the different lengths of the first electrode S of the transistors in the dual-gate driving architecture, resulting in different coupling capacitances with the common electrode Vcom, is reduced or eliminated. This leads to more obvious differences in brightness and darkness, and macroscopically manifests as a deterioration in display effects such as crosstalk, head-shaking lines, and uneven flickering. At the same time, the first part D of the present invention can be independently energized. For the coupling capacitance caused by the voltage jump of the first electrode S of the dual-gate driving transistor, voltage jump compensation can be performed to ensure the voltage stability of the common electrode Vcom, minimize the coupling capacitance to the display common electrode Vcom, and avoid display defects caused by capacitive coupling due to the voltage jump of the first electrode S of the transistor.

[0062] In one possible implementation, see Figures 2A-2E , Figure 3A and Figure 3B As shown, the length c1 of the first part D1 of the first type in the first direction X is equal to the length b1 of the main part SA of the first electrode S1 of the first type of transistor in the first direction X; the length b2 of the first part D2 of the second type in the first direction X is equal to the length c2 of the main part SA of the first electrode S2 of the second type of transistor in the first direction X.

[0063] In one possible implementation, see Figures 2A-2E , Figure 3A and Figure 3B As shown, the first metal layer 3 further includes: multiple data lines 30 extending along the second direction Y; the first conductive layer 4 further includes: a first trace D3 extending along the second direction Y; the orthographic projection of the first trace D3 onto the substrate 1 covers the orthographic projection of the data lines 30 onto the substrate 1.

[0064] In this embodiment of the invention, the first conductive layer 4 further includes a first trace D3. The orthographic projection of the first trace D3 onto the substrate 1 covers the orthographic projection of the data line 30 onto the substrate 1. This can shield the vertical signal 30, reduce or eliminate the coupling capacitance caused by the voltage jump of the dual-gate driving data line 30 in the dual-gate driving architecture, and directly couple the common electrode, causing the common electrode Vcom to jump, affecting the voltage difference of the display pixels, and thus affecting the display effect.

[0065] In one possible implementation, see Figures 2A-2E , Figure 3A and Figure 3B As shown, the array substrate also includes:

[0066] Multiple gate line groups 2 are located between the substrate 1 and the first metal layer 3 and extend along the first direction X. The gate line group 2 includes two gate lines 20 extending along the first direction X.

[0067] Multiple pixel electrodes 40 are located on the same side of the substrate 1 as the gate line group 2. The multiple pixel electrodes 40 include a first type pixel electrode 41 and a second type pixel electrode 42 located in the area formed by the intersection of the gate line group 2 and the data line 30 and connected to the same data line 30. The second type pixel electrode 42 is located on the side of the first type pixel electrode 41 away from the connected data line 30.

[0068] Multiple transistors T are located on the same side of the substrate 1 as the gate line group 2. The multiple transistors T include: a first type transistor T1 and a second type transistor T2; wherein, the first type transistor T1 is electrically connected to the first type pixel electrode 41, and the second type transistor T2 is electrically connected to the second type pixel electrode 42; the first type transistor T1 includes a first electrode S1 of the first type transistor, and the second type transistor T includes a first electrode S2 of the second type transistor.

[0069] Combination Figure 2A As shown, the pixels on both sides of data line 30 share the data signal provided by data line 30, but the lengths of the first terminals S of the transistors connecting the left and right pixels to data line 30 are different. For example, as Figure 2A In the middle, the length b1 of the first electrode S of the transistor in the left pixel is greater than the length b2 of the first electrode S of the transistor in the right pixel, combined with... Figure 1C As shown, at the instant the data signal on data line 30 jumps, the common electrode Vcom is coupled by the signal jump of data line 30, causing the signal on the common electrode Vcom to become unstable and cause it to jump up and down; combined with Figure 3A and Figure 3BAs shown, the first electrode S of the transistor and the common electrode 7 of the opposing substrate directly form a capacitor. The first electrode S of the transistor is directly connected to the data line 30, and the voltage of the first electrode S of the transistor jumps synchronously with the pulse signal of the data line 30. When the data line 30 sends a pulse signal, the signal of the first electrode S of the transistor is immediately coupled to the common electrode 7 of the opposing substrate, causing the voltage of the common electrode 7 of the opposing substrate to jump, increasing the voltage instability of the common electrode 7 of the opposing substrate. The capacitance is proportional to the area of ​​the capacitor plate. The coupling capacitance of the longer first electrode S1 of the first type of transistor is more severe than that of the shorter first electrode S2 of the second type of transistor, causing a difference in the display voltage caused by the coupling voltage of long and short pixels; for example... Figure 4A The existing dual-gate driving design pixel circuit schematic shown has a shorter coupling capacitor Csc value than the longer pixel Csc', resulting in an inconsistent display voltage difference between the short and long pixels Cst+Clc and the common electrode 7 of the opposing substrate. This leads to inconsistent grayscale brightness between the short and long pixels, exhibiting degraded display effects such as crosstalk, head-shaking patterns, and flickering in specific scenes. However, in the embodiment of this invention, combined with... Figures 2A-2E , Figure 3A and Figure 3B As shown, by setting the first part D and the first trace D3, that is, adding a shielding capacitor line DPS (including the first part D and the first trace D3) directly above the data line 30 and the transistor first electrode S connected to the left and right of the data line 30, the voltage of the shielding capacitor line DPS is at the same potential as the common electrode 7 of the opposing substrate, and the line width of the shielding capacitor line DPS is greater than or equal to the line width of the data line 30 or the transistor first electrode S. The shielding capacitor line DPS is located between the data line 30 (or the transistor first electrode S connected to the left and right of the data line 30) and the common electrode 7 of the opposing substrate. When the data line 30 sends a pulse signal, the voltage jump of the data line 30 is preferentially coupled to the shielding capacitor line DPS. The shielding capacitor line DPS is coupled and undergoes a voltage jump, and then coupled to the common electrode 7 of the opposing substrate; as Figure 4B This is a schematic diagram of the Dual Gate driving pixel coupling capacitor shielding design circuit of the present invention. Since the voltage of the shielding capacitor line DPS is set to the same potential as the common electrode 7 of the opposing substrate, the voltage jump caused by the data line 30 through the coupling shielding capacitor line DPS and then coupled to the common electrode 7 of the opposing substrate is greatly reduced. The difference in length between the first electrodes S of the different transistors on the left and right sides of the data line 30 is greatly reduced, which can effectively and significantly reduce the degree of voltage jump of the common electrode 7 of the opposing substrate caused by the direct coupling of the data line 30 to the first electrodes S of the different transistors on the left and right sides of the data line 30.

[0070] In one possible implementation, see Figures 2A-2E , Figure 3A and Figure 3BAs shown, the first conductive layer 4 is on the same layer as the pixel electrode 40, and the first part D is insulated from the pixel electrode 40. Thus, the first conductive layer 4 can be formed simultaneously with the pixel electrode 40, thereby improving the coupling capacitance between the first electrode S of the transistor and the common electrode Vcom, reducing the number of fabrication steps on the array substrate, and lowering the fabrication cost of the array substrate.

[0071] In one possible implementation, see Figures 2A-2E , Figure 3A and Figure 3B As shown, the maximum length (c1 or c2) of the first part D in the first direction X is less than or equal to the maximum length d of the pixel electrode 40 in the first direction X.

[0072] In one possible implementation, see Figures 2A-2E , Figure 3A and Figure 3B As shown, the orthographic projection of the first part D on the substrate 1 overlaps with the orthographic projection of the gap between the two gate lines 20 of the same gate line group 2 on the substrate 1.

[0073] In one possible implementation, see Figures 2A-2E , Figure 3A and Figure 3B As shown, the orthographic projection of the first part D onto the substrate 1 does not overlap with the orthographic projection of the gate line 20 onto the substrate 1. This is to avoid the main part SA overlapping with the gate line 20, which could cause other adverse problems to the display.

[0074] In one possible implementation, see Figures 2A-2E , Figure 3A and Figure 3B As shown, the array substrate further includes: a first common signal line group 51 located between adjacent gate line groups 2 and extending along the second direction Y. The first common signal line group 51 includes two first common signal lines 510 located on different sides of the data line 30, and the first common signal line group 510 in the same extending direction is interrupted at the gate line group 2. The orthographic projection of the first common signal line 510 onto the substrate 1 at least partially overlaps with the orthographic projection of the pixel electrode 40 onto the substrate 1. In this way, a first storage capacitor is formed between the first common signal line 510 and the pixel electrode 40.

[0075] In one possible implementation, see Figures 2A-2E , Figure 3A and Figure 3BAs shown, the array substrate further includes a second common signal line 52 located between adjacent gate line groups 2 and extending along the second direction Y. The second common signal line 52 is located between the first type pixel electrode 41 and the second type pixel electrode 42. The orthographic projection of the second common signal line 52 onto the substrate 1 partially overlaps with the orthographic projection of the pixel electrode 40 onto the substrate 1. In this way, a second storage capacitor is formed between the second common signal line 52 and the pixel electrode 40.

[0076] Specifically, in combination Figure 4B As shown, the storage capacitor Ccs may include a first storage capacitor and a second storage capacitor, and Clc may be the capacitance generated by the liquid crystal between the array substrate and the opposing substrate.

[0077] Based on the same inventive concept, embodiments of the present invention also provide a display panel, including an array substrate as provided in embodiments of the present invention, and a counter substrate disposed opposite to the array substrate, wherein the counter substrate is provided with a common electrode layer 7.

[0078] In one possible implementation, see Figures 2A-2E , Figure 3A and Figure 3B As shown, the voltage applied to the first conductive layer 4 is the same as the voltage applied to the common electrode layer 7.

[0079] Based on the same inventive concept, embodiments of the present invention also provide a display device, including a display panel as provided in the embodiments of the present invention. Implementation of this display device can refer to the embodiments of the display panel described above, and repeated details will not be repeated.

[0080] In specific implementations, in the embodiments of this disclosure, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0081] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0082] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. An array substrate, characterized by, The array substrate comprises: a substrate; a first metal layer located on one side of the substrate and comprising a plurality of first electrodes of transistors; a first conductive layer located on a side of the first metal layer away from the substrate and comprising a plurality of first portions, the first portions being overlapped with at least part of the first electrodes of the transistors in orthographic projection of the substrate; wherein the first electrodes of the transistors comprise a main portion extending along a first direction and a branch portion connected to one end of the main portion and extending along a direction perpendicular to the first direction; the first portions extend along the first direction, and the first portions cover the main portions in orthographic projection of the substrate; the plurality of the first electrodes of the transistors comprise first-type first electrodes of the transistors and second-type first electrodes of the transistors, and a length of the main portion of the first-type first electrodes of the transistors in the first direction is greater than a length of the main portion of the second-type first electrodes of the transistors in the first direction; the plurality of the first portions comprise first-type first portions and second-type first portions, the first-type first portions cover the main portions of the first-type first electrodes of the transistors in orthographic projection of the substrate, and the second-type first portions cover the main portions of the second-type first electrodes of the transistors in orthographic projection of the substrate, and a length of the first-type first portions in the first direction is greater than a length of the second-type first portions in the first direction.

2. The array substrate of claim 1, wherein, the length of the first-type first portions in the first direction is equal to the length of the main portion of the first-type first electrodes of the transistors in the first direction; the length of the second-type first portions in the first direction is equal to the length of the main portion of the second-type first electrodes of the transistors in the first direction.

3. The array substrate of claim 1, wherein, the first metal layer further comprises a plurality of data lines extending along a second direction; the first conductive layer further comprises a first trace extending along the second direction, and the first trace covers the data lines in orthographic projection of the substrate.

4. The array substrate of claim 3, wherein, The array substrate further comprises: a plurality of gate line groups located between the substrate and the first metal layer and extending along the first direction, and each of the gate line groups comprises two gate lines extending along the first direction; a plurality of pixel electrodes located on the same side of the substrate as the gate line groups, and the plurality of pixel electrodes comprise first-type pixel electrodes and second-type pixel electrodes located in an area formed by the intersection of the gate line groups and the data lines and connected to the same data line, and the second-type pixel electrodes are located on a side of the first-type pixel electrodes away from the data line; a plurality of transistors located on the same side of the substrate as the gate line groups, and the plurality of transistors comprise first-type transistors and second-type transistors, wherein the first-type transistors are electrically connected to the first-type pixel electrodes, and the second-type transistors are electrically connected to the second-type pixel electrodes, the first-type transistors comprise the first-type first electrodes of the transistors, and the second-type transistors comprise the second-type first electrodes of the transistors.

5. The array substrate of claim 4, wherein, The first conductive layer is in the same layer as the pixel electrode, and the first portion is insulated from the pixel electrode.

6. The array substrate of claim 4, wherein, A maximum length of the first portion in the first direction is less than or equal to a maximum length of the pixel electrode in the first direction.

7. The array substrate of claim 4, wherein, A projection of the first portion on the substrate overlaps a projection of a gap between two gate lines of the same gate line group on the substrate.

8. The array substrate of claim 4, wherein, The projection of the first portion on the substrate does not overlap the projection of the gate line on the substrate.

9. The array substrate of claim 4, wherein, The array substrate further comprises a first common signal line group located between adjacent gate line groups and extending in the second direction, the first common signal line group comprising two first common signal lines respectively located on different sides of the data line, the first common signal line groups in the same extension direction being disconnected at the gate line groups; A projection of the first common signal line on the substrate at least partially overlaps a projection of the pixel electrode on the substrate.

10. The array substrate of claim 9, wherein, The array substrate further comprises a second common signal line located between adjacent gate line groups and extending in the second direction, the second common signal line being located between the first type of pixel electrode and the second type of pixel electrode; A projection of the second common signal line on the substrate partially overlaps a projection of the pixel electrode on the substrate.

11. A display panel, characterized by, The display panel comprises the array substrate according to any one of claims 1-10 and an opposite substrate arranged opposite to the array substrate, the opposite substrate being provided with a common electrode layer.

12. The display panel of claim 11, wherein, The first conductive layer is loaded with a voltage same as a voltage loaded on the common electrode layer.

13. A display device comprising: The display panel comprises the display panel according to claim 11 or 12.

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