Scan driving circuit and display panel

Abstract

The present application relates to the field of display panel, provide a kind of scanning drive circuit and display panel, wherein, scanning drive circuit includes multiple stage shift register unit and a timing controller, wherein, each stage shift register unit includes 14 or 15 transistor and 3 capacitors, timing controller includes three timing control signal lines.The scanning drive circuit and display panel of the present application, by providing new shift register unit circuit, increase the number of components, so that in the process fluctuation of display panel, integrated circuit power supply signal noise and long time operation etc., strengthen the stability of shift register unit output signal waveform, improve the tolerance of shift register unit circuit, increase the reliability of display panel.

Description

Technical Field

[0001] This invention relates to the field of display panels, and more specifically, to a scanning driving circuit and a display panel. Background Technology

[0002] The display panel includes a pixel array and a scanning drive circuit and a light-emitting drive circuit for controlling the pixel array. The display panel adopts a line-by-line scanning display method. The scanning drive circuit is used to generate scanning signals so that each row of pixels is turned on sequentially.

[0003] The scan drive circuit includes multiple cascaded shift register units, each of which is typically composed of several transistors. By inputting a clock signal and a start pulse signal into the circuit, a scan signal is output at the output terminal.

[0004] US Patent US10019930B2 provides a scanning circuit, such as Figure 1 As shown, Figure 1 The circuit diagram of a prior art shift register unit is shown. In this circuit, due to the limited number of components and the fact that not all nodes N1' have a voltage source to keep T8' high when the output VOUT is high, the circuit has low tolerance and insufficient reliability under conditions such as display panel manufacturing process fluctuations, IC power supply signal noise, and long-term operation.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] In view of this, the present invention provides a scanning driving circuit and a display panel to at least solve the above-mentioned problems.

[0007] One aspect of the present invention provides a scan driving circuit, including a multi-stage shift register unit, the shift register unit comprising:

[0008] The first transistor has its first terminal connected to the fourth node, its second terminal connected to the signal input terminal, and its gate connected to the third timing control terminal.

[0009] The second transistor has its first terminal connected to the first power supply, its second terminal connected to the fourth node, and its gate connected to the first timing control terminal.

[0010] The third transistor has its first terminal connected to the first power supply, its second terminal connected to the third node, and its gate connected to the first timing control terminal.

[0011] The fourth transistor has its first terminal connected to the third node, its second terminal connected to the second timing control terminal, and its gate connected to the fourth node.

[0012] The fifth transistor has its first terminal connected to the third timing control terminal, its second terminal connected to the first node, and its gate connected to the third node;

[0013] A sixth transistor, wherein the second terminal of the sixth transistor is connected to the second node, and the gate is connected to the first node;

[0014] The seventh transistor has its first terminal connected to the first power supply, its second terminal connected to the signal output terminal, and its gate connected to the first node;

[0015] The eighth transistor has its first terminal connected to the signal output terminal, its second terminal connected to the second timing control terminal, and its gate connected to the second node;

[0016] The ninth transistor has its first terminal connected to the fourth node, its second terminal connected to the second node, and its gate connected to the second power supply.

[0017] The tenth transistor has its first terminal connected to the first node, its second terminal connected to the second power supply, and its gate connected to the third timing control terminal.

[0018] The eleventh transistor has its first terminal connected to the first power supply, its second terminal connected to the third node, and its gate connected to the third timing control terminal.

[0019] The twelfth transistor has its first terminal connected to the third timing control terminal, its second terminal connected to the first node, and its gate connected to the fourth node;

[0020] The thirteenth transistor has its first terminal connected to the first power supply, its second terminal connected to the first terminal of the sixth transistor, and its gate connected to the second timing control terminal.

[0021] The fourteenth transistor has its second terminal connected to the second power supply and its gate connected to the first timing control terminal.

[0022] A first capacitor, wherein the first terminal of the first capacitor is connected to the first power source, and the second terminal is connected to the first node;

[0023] The second capacitor has its first terminal connected to the second node and its second terminal connected to the signal output terminal.

[0024] The third capacitor has its first terminal connected to the first power source and its second terminal connected to the third node.

[0025] In some embodiments, the shift register unit further includes:

[0026] The fifteenth transistor has its first terminal connected to the first node, its second terminal connected to the first terminal of the fourteenth transistor, and its gate connected to the first node.

[0027] In some embodiments, the first terminal of the fourteenth transistor is connected to the first node.

[0028] In some embodiments, the scan driving circuit further includes a timing controller, which includes a first timing control signal line, a second timing control signal line, and a third timing control signal line.

[0029] In some embodiments, the first timing control signal line is used to output a first timing control signal; the second timing control signal line is used to output a second timing control signal; and the third timing control signal line is used to output a third timing control signal.

[0030] In some embodiments, the first timing control signal, the second timing control signal, and the third timing control signal are square wave signals with the same output frequency and a continuous low potential occupying 1 / 3 of the cycle.

[0031] In some embodiments, the shift register unit is used to perform delay processing on the signal received from the signal input terminal under the control of the first timing control signal, the second timing control signal and the third timing control signal, and the processed signal is output by the signal output terminal.

[0032] In some embodiments, the shift register unit at the previous stage outputs a scan signal to the shift register unit at the next stage, and the shift register unit at the last stage outputs a scan signal.

[0033] In some embodiments, in the shift register unit of the 3N-2th stage, the first timing control terminal is connected to the first timing control signal line, the second timing control terminal is connected to the second timing control signal line, and the third timing control terminal is connected to the third timing control signal line, where N is a positive integer.

[0034] In some embodiments, in the shift register unit of the 3N-1th stage, the first timing control terminal is connected to the third timing control signal line, the second timing control terminal is connected to the first timing control signal line, and the third timing control terminal is connected to the second timing control signal line, wherein N is a positive integer.

[0035] In some embodiments, in the shift register unit of the 3Nth stage, the first timing control terminal is connected to the second timing control signal line, the second timing control terminal is connected to the third timing control signal line, and the third timing control terminal is connected to the first timing control signal line, wherein N is a positive integer.

[0036] Another aspect of the present invention provides a display panel including the scanning drive circuit described in any of the preceding claims.

[0037] The beneficial effects of this invention compared to the prior art include at least the following:

[0038] The scanning drive circuit and display panel of the present invention, by providing a new shift register unit circuit and increasing the number of components, enhance the stability of the output signal waveform of the shift register unit under conditions such as display panel manufacturing process fluctuations, integrated circuit power signal noise, and long-term operation, improve the tolerance of the shift register unit circuit, and increase the reliability of the display panel.

[0039] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description

[0040] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention. It is obvious that the drawings described below are merely some embodiments of the invention, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0041] Figure 1 A circuit diagram of a prior art shift register unit is shown;

[0042] Figure 2 A schematic diagram of the display panel of the present invention is shown;

[0043] Figure 3 A schematic diagram of the cascaded scanning drive circuit of the present invention is shown;

[0044] Figure 4 A circuit diagram of a shift register unit according to a first embodiment of the present invention is shown;

[0045] Figure 5 Show Figure 4 The waveform diagram of the shift register unit in operation is shown below;

[0046] Figure 6 Show Figure 5 A schematic diagram of the conduction state of the shift register unit in stage t1;

[0047] Figure 7 Show Figure 5 A schematic diagram of the conduction state of the shift register unit in stage t2;

[0048] Figure 8 Show Figure 5 A schematic diagram of the conduction state of the shift register unit in stage t21;

[0049] Figure 9 Show Figure 5 A schematic diagram of the conduction state of the shift register unit in stage t3;

[0050] Figure 10 Show Figure 5 A schematic diagram of the conduction state of the shift register unit in stage t4;

[0051] Figure 11 Show Figure 5 A schematic diagram of the conduction state of the shift register unit in stage t5;

[0052] Figure 12 Show Figure 5 A schematic diagram of the conduction state of the shift register unit in stage t6;

[0053] Figure 13 A circuit diagram of a shift register unit according to a second embodiment of the present invention is shown.

[0054] Figure label:

[0055] 10 Display Panel

[0056] 11 Display Area

[0057] 20. Timing Controller

[0058] 30 Scan drive circuit

[0059] CKV1 First Timing Control Signal Line

[0060] CKV2 Second Timing Control Signal Line

[0061] CKV3 Third Timing Control Signal Line

[0062] c1 First timing control terminal

[0063] c2 Second timing control terminal

[0064] c3 Third timing control terminal

[0065] IN signal input terminal

[0066] Gout signal output terminal

[0067] T1 First Transistor

[0068] T2 second transistor

[0069] T3 Third Transistor

[0070] T4 fourth transistor

[0071] T5 fifth transistor

[0072] T6 sixth transistor

[0073] T7 Seventh Transistor

[0074] T8 Eighth Transistor

[0075] T9 Ninth Transistor

[0076] T10, the tenth transistor

[0077] T11 Eleventh Transistor

[0078] T12 Twelfth Transistor

[0079] T13, the thirteenth transistor.

[0080] T14, the fourteenth transistor

[0081] T15, the fifteenth transistor.

[0082] C1 First capacitor

[0083] C2, the second capacitor

[0084] C3 Third capacitor

[0085] VDD First Power Supply

[0086] VEE Second Power Supply

[0087] N1 First Node

[0088] N2 Second Node

[0089] N3 Third Node

[0090] N4 Fourth Node Detailed Implementation

[0091] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the invention will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore repeated descriptions of them will be omitted.

[0092] The use of terms such as "first," "second," and similar terms in the specific description does not indicate any order, quantity, or importance, but is merely used to distinguish different components. Furthermore, in the description of this invention, terms such as "upper," "lower," etc., indicate orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings. These are merely for ease of description and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation; therefore, they should not be construed as limitations on the invention.

[0093] It should be noted that, unless otherwise specified, the embodiments of the present invention and the features in different embodiments can be combined with each other.

[0094] The inventors in this case, through meticulous and in-depth research, have addressed the shortcomings of existing technologies, namely... Figure 1 This paper addresses the problems existing in intermediate shift register circuits and provides a solution. For example... Figures 2 to 4 as well as Figure 13 As shown, Figure 2 A schematic diagram of the display panel of the present invention is shown; Figure 3 A schematic diagram of the cascaded scanning drive circuit of the present invention is shown; Figure 4 A circuit diagram of a shift register unit according to a first embodiment of the present invention is shown;

[0095] Figure 13 A circuit diagram of a shift register unit according to a second embodiment of the present invention is shown. The present invention discloses a scan drive circuit 30 and a display panel 10. The scan drive circuit 30 includes a multi-stage shift register unit and a timing controller 20. Each stage of the shift register unit includes 14 or 15 transistors, 3 capacitors, 1 signal input terminal IN, 1 signal output terminal Gout, and 3 timing control terminals. The timing controller 20 includes 3 timing control signal lines. The scan drive circuit and display panel of the present invention, by providing a new shift register unit circuit and increasing the number of components, enhance the stability of the output signal waveform of the shift register unit under conditions such as display panel process fluctuations, integrated circuit power signal noise, and long-term operation, thereby improving the tolerance of the shift register unit circuit and increasing the reliability of the display panel.

[0096] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0097] like Figure 2As shown, the present invention provides a display panel 10, which includes a display area 11 and a non-display area. A scan driving circuit 30, a data driver, and a light-emitting driving circuit are located in the non-display area of ​​the display panel 10. The display area 11 includes an array of light-emitting pixels and pixel circuits. The light-emitting pixels emit light under the combined action of the scan driving circuit 30, the data driver, the light-emitting driving circuit, and the pixel circuits.

[0098] like Figure 2 and 3 As shown, the present invention also provides a scan driving circuit 30, which includes a multi-stage shift register unit and a timing controller 20.

[0099] In some embodiments, such as Figure 4 and 13 As shown, the shift register unit includes 14 or 15 transistors, 3 capacitors, 1 signal input terminal IN, 1 signal output terminal Gout, a first timing control terminal c1, a second timing control terminal c2, and a third timing control terminal c3. Each shift register unit outputs a scan signal, which is input to a row of pixel circuits in the display area 11 of the display panel 10 to drive the pixels in that row to emit light. The previous shift register unit simultaneously outputs its scan signal to the signal input terminal IN of the next shift register unit as a start signal. Since the last shift register unit does not have a next stage, its output scan signal is only input to the pixel circuit of that row.

[0100] Specifically, Figure 3Taking a cascaded shift register unit of 5 as an example, the first-stage shift register unit S1 receives the start pulse signal STV at its input terminal IN1. The first-stage shift register unit S1 outputs a scan signal at its output terminal Gout1, which serves as the input signal for the second-stage shift register unit S2. Gout1 is connected to the second-stage shift register unit S2's input terminal IN2. The second-stage shift register unit S2 outputs a scan signal at its output terminal Gout2, which serves as the input signal for the third-stage shift register unit S3. Gout2 is connected to the third-stage shift register unit S3's input terminal IN3. The third-stage shift register unit S3 outputs a scan signal at its output terminal Gout3, which serves as the input signal for the fourth-stage shift register unit S4. Gout3 is connected to the fourth-stage shift register unit S4's input terminal IN4. The signal output terminal Gout4 of the fourth-stage shift register unit S4 outputs a scan signal as the input signal of the fifth-stage shift register unit S5. The signal output terminal Gout4 of the fourth-stage shift register unit S4 is connected to the signal input terminal IN5 of the fifth-stage shift register unit S5... Subsequent shift register units repeat this process to form the scan drive circuit 30.

[0101] In some embodiments, such as Figure 3 As shown, the timing controller 20 includes a first timing control signal line CKV1, a second timing control signal line CKV2, and a third timing control signal line CKV3. The first timing control signal line CKV1 is used to output a first timing control signal. The second timing control signal line CKV2 is used to output a second timing control signal. The third timing control signal line CKV3 is used to output a third timing control signal. The first, second, and third timing control signals are square wave signals with the same output frequency and a continuous low potential occupying 1 / 3 of the cycle.

[0102] In some preferred embodiments, reference continues to be made to Figure 3Furthermore, in the 3N-2 stage shift register unit, the first timing control terminal c1 is connected to the first timing control signal line CKV1 to receive the first timing control signal. The second timing control terminal c2 is connected to the second timing control signal line CKV2 to receive the second timing control signal. The third timing control terminal c3 is connected to the third timing control signal line CKV3 to receive the third timing control signal. Here, N is a positive integer. In the 3N-1 stage shift register unit, the first timing control terminal c1 is connected to the third timing control signal line CKV3 to receive the third timing control signal. The second timing control terminal c2 is connected to the first timing control signal line CKV1 to receive the first timing control signal. The third timing control terminal c3 is connected to the second timing control signal line CKV2 to receive the second timing control signal. Here, N is a positive integer. In the 3N stage shift register unit, the first timing control terminal c1 is connected to the second timing control signal line CKV2 to receive the second timing control signal. The second timing control terminal c2 is connected to the third timing control signal line CKV3 to receive the third timing control signal. The third timing control terminal c3 is connected to the first timing control signal line CKV1 to receive the first timing control signal. Here, N is a positive integer. Each shift register unit of the scan drive circuit 30 receives the three timing control signals according to the above pattern.

[0103] In the first embodiment of the present invention, reference is made to... Figures 4 to 11 , Figure 5 Show Figure 4 The waveform diagram shown is of the shift register unit in operation. Figure 6 Show Figure 5 A schematic diagram of the conduction state of the shift register unit in stage t1. Figure 7 Show Figure 5 A schematic diagram of the conduction state of the shift register unit in stage t2. Figure 8 Show Figure 5 A schematic diagram of the conduction state of the shift register unit in stage t21. Figure 9 Show Figure 5 A schematic diagram of the conduction state of the shift register unit in stage t3. Figure 10 Show Figure 5 A schematic diagram of the conduction state of the shift register unit in stage t4. Figure 11 Show Figure 5 A schematic diagram of the conduction state of the shift register unit in stage t5. Figure 12 Show Figure 5 A schematic diagram of the conduction state of the shift register unit in stage t6.

[0104] like Figure 4As shown, the shift register unit of the first embodiment of the present invention includes a first transistor T1 to a fourteenth transistor T14, a first capacitor C1 to a third capacitor C3, a signal input terminal IN, a signal output terminal Gout, and a first timing control terminal c1 to a third timing control terminal c3. Specifically, the first transistor T1 has its first terminal connected to the fourth node N4, its second terminal connected to the signal input terminal IN, and its gate connected to the third timing control terminal c3. The second transistor T2 has its first terminal connected to the first power supply VDD, its second terminal connected to the fourth node N4, and its gate connected to the first timing control terminal c1. The third transistor T3 has its first terminal connected to the first power supply VDD, its second terminal connected to the third node N3, and its gate connected to the first timing control terminal c1. The fourth transistor T4 has its first terminal connected to the third node N3, its second terminal connected to the second timing control terminal c2, and its gate connected to the fourth node N4. The fifth transistor T5 has its first terminal connected to the third timing control terminal c3, its second terminal connected to the first node N1, and its gate connected to the third node N3. The sixth transistor T6 has its second terminal connected to the second node N2 and its gate connected to the first node N1. The seventh transistor T7 has its first terminal connected to the first power supply VDD, its second terminal connected to the signal output terminal Gout, and its gate connected to the first node N1. The eighth transistor T8 has its first terminal connected to the signal output terminal Gout, its second terminal connected to the second timing control terminal c2, and its gate connected to the second node N2. The ninth transistor T9 has its first terminal connected to the fourth node N4, its second terminal connected to the second node N2, and its gate connected to the second power supply VEE. The tenth transistor T10 has its first terminal connected to the first node N1, its second terminal connected to the second power supply VEE, and its gate connected to the third timing control terminal c3. The eleventh transistor T11 has its first terminal connected to the first power supply VDD, its second terminal connected to the third node N3, and its gate connected to the third timing control terminal c3. The twelfth transistor T12 has its first terminal connected to the third timing control terminal c3, its second terminal connected to the first node N1, and its gate connected to the fourth node N4. The first terminal of the thirteenth transistor T13 is connected to the first power supply VDD, the second terminal is connected to the first terminal of the sixth transistor T6, and the gate is connected to the second timing control terminal c2. The second terminal of the fourteenth transistor T14 is connected to the second power supply VEE, and the gate is connected to the first timing control terminal c1. The first terminal of the first capacitor C1 is connected to the first power supply VDD, and the second terminal is connected to the first node N1. The first terminal of the second capacitor C2 is connected to the second node N2, and the second terminal is connected to the signal output terminal Gout. The first terminal of the third capacitor C3 is connected to the first power supply VDD, and the second terminal is connected to the third node N3. Specifically, in this embodiment, the shift register unit also includes a fifteenth transistor T15, the first terminal of which is connected to the first node N1, the second terminal of which is connected to the first terminal of the fourteenth transistor T14, and the gate is connected to the first node N1.

[0105] In this embodiment, the first transistor T1 to the fifteenth transistor T15 are all P-type MOS transistors. The control terminal of the PMOS transistor is the gate, and its first terminal is the source and its second terminal is the drain, or vice versa. The PMOS transistor has a low on-state potential and a high off-state potential. In other embodiments, those skilled in the art can easily modify the shift register unit provided by this invention to consist entirely of N-type MOS transistors or CMOS transistors.

[0106] In this embodiment, refer to Figure 5 , Figure 5 The waveform diagram shown mainly includes six processes: t1 to t6, with an additional process t21 between t2 and t3. During these seven processes, the output signal of the shift register unit's output terminal Gout completes one cycle from set to reset. It should be noted that, for ease of understanding, high-level signals are represented by "H" and low-level signals by "L" in the attached diagram. The following section will further explain... Figure 5 waveform diagram and Figure 4 The circuit diagram is used to analyze the relationship between the input and output of the shift register unit in the above seven processes:

[0107] During process t1, refer to Figure 5 and 6When the start pulse signal STV or signal input terminal IN is input at a low potential, the first timing control signal line CKV1 is input at a high potential, the second timing control signal line CKV2 is input at a high potential, and the third timing control signal line CKV3 is input at a low potential. At this time, the second transistor T2, the third transistor T3, and the fourteenth transistor T14 are turned off by the high potential input to the first timing control signal line CKV1; the thirteenth transistor T13 is turned off by the high potential input to the second timing control signal line CKV2; the first transistor T1, the tenth transistor T10, and the eleventh transistor T11 are turned on by the low potential input to the third timing control signal line CKV3; and the ninth transistor T9 is turned on by the low potential input to the second power supply VEE. The fourth node N4 is written to a low potential by the start pulse signal STV or signal input terminal IN through the first transistor T1, thereby turning on the fourth transistor T4 and the twelfth transistor T12. The third node N3 is simultaneously written to a high potential by the first power supply VDD through the eleventh transistor T11 and by the second timing control signal line CKV2 through the fourth transistor T4, thereby turning off the fifth transistor T5. The second node N2 is written to a low potential by the fourth node N4 through the ninth transistor T9, thereby turning on the eighth transistor T8. The first node N1 is simultaneously written to a low potential by the third timing control signal line CKV3 through the twelfth transistor T12 and by the second power supply VEE through the tenth transistor T10, thereby turning on the seventh transistor T7. Finally, the signal output terminal Gout is output to a high potential by the first power supply VDD through the seventh transistor T7, and simultaneously by the second timing control signal line CKV2 through the eighth transistor T8.

[0108] During process t2, refer to Figure 5 and 7The initial pulse signal STV or signal input terminal IN is input at a high potential. The first timing control signal line CKV1 is input at a high potential, the second timing control signal line CKV2 is input at a low potential, and the third timing control signal line CKV3 is input at a high potential. At this time, the second transistor T2, the third transistor T3, and the fourteenth transistor T14 are turned off by the high potential input to the first timing control signal line CKV1; the thirteenth transistor T13 is turned on by the low potential input to the second timing control signal line CKV2; the first transistor T1, the tenth transistor T10, and the eleventh transistor T11 are turned off by the high potential input to the third timing control signal line CKV3; and the ninth transistor T9 is turned on by the low potential input to the second power supply VEE. The fourth node N4 maintains the low potential from the previous process, thus keeping the fourth transistor T4 and the twelfth transistor T12 on. The third node N3 is written to a low potential through the fourth transistor T4 by the second timing control signal line CKV2, thus turning on the fifth transistor T5. The second node N2 maintains the low potential from the previous process, thus keeping the eighth transistor T8 on. The first node N1 is written to a high potential by the third timing control signal line CKV3 through the fifth transistor T5 and the twelfth transistor T12, thereby turning off the sixth transistor T6, the fifteenth transistor T15, and the seventh transistor T7. Finally, the signal output terminal Gout is output to a low potential by the second timing control signal line CKV2 through the eighth transistor T8.

[0109] During process t21, refer to Figure 5 and 8The initial pulse signal STV or signal input terminal IN is input at a high potential. The first timing control signal line CKV1, the second timing control signal line CKV2, and the third timing control signal line CKV3 are all input at a high potential. At this time, the second transistor T2, the third transistor T3, and the fourteenth transistor T14 are turned off by the high potential input to the first timing control signal line CKV1; the thirteenth transistor T13 is turned off by the high potential input to the second timing control signal line CKV2; the first transistor T1, the tenth transistor T10, and the eleventh transistor T11 are turned off by the high potential input to the third timing control signal line CKV3; and the ninth transistor T9 is turned on by the low potential input to the second power supply VEE. The fourth node N4 maintains the low potential of the previous process, thus keeping the fourth transistor T4 and the twelfth transistor T12 on. The third node N3 is written with a high potential through the fourth transistor T4 by the second timing control signal line CKV2, thus turning off the fifth transistor T5. The second node N2 maintains the low potential of the previous process, thus keeping the eighth transistor T8 on. The first node N1 is written to a high potential by the third timing control signal line CKV3 through the twelfth transistor T12, thereby turning off the sixth transistor T6, the fifteenth transistor T15, and the seventh transistor T7. Finally, the signal output terminal Gout is output to a high potential by the second timing control signal line CKV2 through the eighth transistor T8.

[0110] During process t3, refer to Figure 5 and 9 The initial pulse signal STV or signal input terminal IN is input at a high potential. The first timing control signal line CKV1 is input at a low potential, the second timing control signal line CKV2 is input at a high potential, and the third timing control signal line CKV3 is input at a high potential. At this time, the second transistor T2, the third transistor T3, and the fourteenth transistor T14 are turned on by the low potential input to the first timing control signal line CKV1; the thirteenth transistor T13 is turned off by the high potential input to the second timing control signal line CKV2; the first transistor T1, the tenth transistor T10, and the eleventh transistor T11 are turned off by the high potential input to the third timing control signal line CKV3; and the ninth transistor T9 is turned on by the low potential input to the second power supply VEE. The fourth node N4 is written with a high potential by the first power supply VDD through the second transistor T2, thereby turning off the fourth transistor T4 and the twelfth transistor T12. The third node N3 is written with a high potential by the first power supply VDD through the third transistor T3, thereby turning off the fifth transistor T5. The second node N2 is written to a high potential by the fourth node N4 through the ninth transistor T9, thereby turning off the eighth transistor T8. The first node N1 maintains the high potential of the previous process, thereby keeping the sixth transistor T6, the fifteenth transistor T15, and the seventh transistor T7 off. Finally, the signal output terminal Gout maintains the high potential of the previous process.

[0111] During process t4, refer to Figure 5 and 10 When the start pulse signal STV or signal input terminal IN is high, the first timing control signal line CKV1 is high, the second timing control signal line CKV2 is high, and the third timing control signal line CKV3 is low. At this time, the second transistor T2, the third transistor T3, and the fourteenth transistor T14 are turned off by the high potential input to the first timing control signal line CKV1; the thirteenth transistor T13 is turned off by the high potential input to the second timing control signal line CKV2; the first transistor T1, the tenth transistor T10, and the eleventh transistor T11 are turned on by the low potential input to the third timing control signal line CKV3; and the ninth transistor T9 is turned on by the low potential input to the second power supply VEE. The fourth node N4 is written to a high potential by the start pulse signal STV or signal input terminal IN through the first transistor T1, thereby turning off the fourth transistor T4 and the twelfth transistor T12. The third node N3 is written to a high potential by the first power supply VDD through the eleventh transistor T11, thereby turning off the fifth transistor T5. The second node N2 is written to a high potential by the fourth node N4 through the ninth transistor T9, thereby turning off the eighth transistor T8. The first node N1 is written to a low potential by the second power supply VEE through the tenth transistor T10, thereby turning on the sixth transistor T6, the fifteenth transistor T15, and the seventh transistor T7. Finally, the signal output terminal Gout is output to a high potential by the first power supply VDD through the seventh transistor T7.

[0112] During the t5 process, refer to Figure 5 and 11The initial pulse signal STV or signal input terminal IN is input at a high potential. The first timing control signal line CKV1 is input at a high potential, the second timing control signal line CKV2 is input at a low potential, and the third timing control signal line CKV3 is input at a high potential. At this time, the second transistor T2, the third transistor T3, and the fourteenth transistor T14 are turned off by the high potential input to the first timing control signal line CKV1; the thirteenth transistor T13 is turned on by the low potential input to the second timing control signal line CKV2; the first transistor T1, the tenth transistor T10, and the eleventh transistor T11 are turned off by the high potential input to the third timing control signal line CKV3; and the ninth transistor T9 is turned on by the low potential input to the second power supply VEE. The fourth node N4 maintains the high potential from the previous process, thus turning off the fourth transistor T4 and the twelfth transistor T12. The third node N3 maintains the high potential from the previous process, thus turning off the fifth transistor T5. The first node N1 maintains the low potential from the previous process, thus turning on the sixth transistor T6, the fifteenth transistor T15, and the seventh transistor T7. The second node N2 is written to a high potential by the fourth node N4 through the ninth transistor T9, and simultaneously by the first power supply VDD through the thirteenth transistor T13 and the sixth transistor T6, thereby turning off the eighth transistor T8. Finally, the signal output terminal Gout is output to a high potential by the first power supply VDD through the seventh transistor T7.

[0113] During process t6, refer to Figure 5 and 12The initial pulse signal STV or signal input terminal IN is input at a high potential. The first timing control signal line CKV1 is input at a low potential, the second timing control signal line CKV2 is input at a high potential, and the third timing control signal line CKV3 is input at a high potential. At this time, the second transistor T2, the third transistor T3, and the fourteenth transistor T14 are turned on by the low potential input to the first timing control signal line CKV1; the thirteenth transistor T13 is turned off by the high potential input to the second timing control signal line CKV2; the first transistor T1, the tenth transistor T10, and the eleventh transistor T11 are turned off by the high potential input to the third timing control signal line CKV3; and the ninth transistor T9 is turned on by the low potential input to the second power supply VEE. The fourth node N4 is written with a high potential by the first power supply VDD through the second transistor T2, thereby turning off the fourth transistor T4 and the twelfth transistor T12. The third node N3 is written with a high potential by the first power supply VDD through the third transistor T3, thereby turning off the fifth transistor T5. The second node N2 is written to a high potential by the fourth node N4 through the ninth transistor T9, thereby turning off the eighth transistor T8. The first node N1 maintains the low potential of the previous process, while the fifteenth transistor T15 remains on, allowing the first node N1 to be written to a low potential by the second power supply VEE through the fourteenth transistor T14 and the fifteenth transistor T15. Consequently, the fifteenth transistor T15, the sixth transistor T6, and the seventh transistor T7 remain on. Finally, the signal output terminal Gout is output to a high potential by the first power supply VDD through the seventh transistor T7.

[0114] The shift register unit repeats the steps from t4 to t6 after process t6 until the next frame of the picture begins to be displayed. At this time, the start pulse signal STV or the signal input terminal IN is input with a low potential, and the next round of process t1 is restarted.

[0115] In this embodiment, the relationship between the input and output of the shift register unit is as follows: If the start pulse signal STV or the signal input terminal IN is low at a certain time, then under the action of the first timing control signal line CKV1, the second timing control signal line CKV2, and the third timing control signal line CKV3, the signal output terminal Gout will also output a low level in the next time. In other times, the start pulse signal STV or the signal input terminal IN and the signal output terminal Gout are maintained at a high level until the start pulse signal STV or the signal input terminal IN is low again, at which point the signal output terminal Gout will output a low level again. Essentially, the shift register unit delays the low-level signal from the start pulse signal STV or the signal input terminal IN before outputting it from the signal output terminal Gout.

[0116] In this embodiment, the 15T3C circuit of the shift register unit, compared with the prior art, adds 7 transistors and 1 capacitor, and changes some wiring settings, eliminating the N2' node in the prior art circuit. This ensures that when the second node N2 of the present invention outputs a high level at the signal output terminal Gout, the first power supply VDD is kept high to shut down the eighth transistor T8, avoiding the possibility of potential drift. It can effectively provide a stable output signal waveform under conditions such as display panel process fluctuations, integrated circuit power signal noise, and long-term operation, improving the tolerance of the shift register unit circuit and increasing the reliability of the display panel.

[0117] In a second embodiment of the present invention, reference is made to... Figure 2 , 3 In embodiment 13, the shift register unit includes first transistors T1 to fourteenth transistors T14, first capacitors C1 to third capacitors C3, signal input terminal IN, signal output terminal Gout, and first timing control terminals c1 to third timing control terminals c3. Specifically, this embodiment does not include a fifteenth transistor T15, and the first terminal of the fourteenth transistor T14 is connected to the first node N1. The connection methods of other components are the same as in the first embodiment of the present invention.

[0118] In this embodiment, the operation of the shift register unit is also divided into seven processes. During these seven processes, the output signal of the shift register unit's signal output terminal Gout completes one cycle from set to reset. The output result of this embodiment is the same as that of the first embodiment. Specifically, in the third process of this embodiment, the fourteenth transistor T14 is turned on due to the low potential of the first timing control signal line CKV1, the first node N1 receives the low potential of the second power supply VEE, the seventh transistor T7 is turned on, and the signal output terminal Gout outputs the high potential of the first power supply VDD.

[0119] In this embodiment, the relationship between the input and output of the shift register unit is the same as in the first embodiment, that is, the shift register unit delays the low-level signal from the start pulse signal STV or the signal input terminal IN and then outputs it from the signal output terminal Gout.

[0120] In this embodiment, the 14T3C circuit of the shift register unit adds 6 transistors and 1 capacitor compared with the prior art, and changes some wiring settings. The technical effect achieved is the same as that of the first embodiment, and will not be repeated here.

[0121] Based on the same inventive concept, embodiments of the present invention also provide a display device, including the display panel 10 described above in the embodiments of the present invention. This display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Implementation of this display device can refer to the embodiments of the display panel 10 described above; repeated details will not be repeated.

[0122] The scanning drive circuit and display panel of the present invention, by providing a new shift register unit circuit and increasing the number of components, enhance the stability of the output signal waveform of the shift register unit under conditions such as display panel manufacturing process fluctuations, integrated circuit power signal noise, and long-term operation, improve the tolerance of the shift register unit circuit, and increase the reliability of the display panel.

[0123] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A scanning drive circuit, characterized in that, Includes a multi-stage shift register unit, wherein the shift register unit includes: The first transistor has its first terminal connected to the fourth node, its second terminal connected to the signal input terminal, and its gate connected to the third timing control terminal. The second transistor has its first terminal connected to the first power supply, its second terminal connected to the fourth node, and its gate connected to the first timing control terminal. The third transistor has its first terminal connected to the first power supply, its second terminal connected to the third node, and its gate connected to the first timing control terminal. The fourth transistor has its first terminal connected to the third node, its second terminal connected to the second timing control terminal, and its gate connected to the fourth node. The fifth transistor has its first terminal connected to the third timing control terminal, its second terminal connected to the first node, and its gate connected to the third node; A sixth transistor, wherein the second terminal of the sixth transistor is connected to the second node, and the gate is connected to the first node; The seventh transistor has its first terminal connected to the first power supply, its second terminal connected to the signal output terminal, and its gate connected to the first node; The eighth transistor has its first terminal connected to the signal output terminal, its second terminal connected to the second timing control terminal, and its gate connected to the second node; The ninth transistor has its first terminal connected to the fourth node, its second terminal connected to the second node, and its gate connected to the second power supply. The tenth transistor has its first terminal connected to the first node, its second terminal connected to the second power supply, and its gate connected to the third timing control terminal. The eleventh transistor has its first terminal connected to the first power supply, its second terminal connected to the third node, and its gate connected to the third timing control terminal. The twelfth transistor has its first terminal connected to the third timing control terminal, its second terminal connected to the first node, and its gate connected to the fourth node; The thirteenth transistor has its first terminal connected to the first power supply, its second terminal connected to the first terminal of the sixth transistor, and its gate connected to the second timing control terminal. The fourteenth transistor has its first terminal connected to the first node, its second terminal connected to the second power supply, and its gate connected to the first timing control terminal. A first capacitor, wherein the first terminal of the first capacitor is connected to the first power source, and the second terminal is connected to the first node; The second capacitor has its first terminal connected to the second node and its second terminal connected to the signal output terminal. The third capacitor has its first terminal connected to the first power source and its second terminal connected to the third node.

2. The scanning drive circuit according to claim 1, characterized in that, The shift register unit further includes: The fifteenth transistor has its first terminal connected to the first node, its second terminal connected to the first terminal of the fourteenth transistor, and its gate connected to the first node.

3. The scanning drive circuit according to claim 2, characterized in that, It also includes a timing controller, which includes a first timing control signal line, a second timing control signal line and a third timing control signal line.

4. The scanning drive circuit according to claim 3, characterized in that, The first timing control signal line is used to output a first timing control signal; the second timing control signal line is used to output a second timing control signal; and the third timing control signal line is used to output a third timing control signal.

5. The scanning drive circuit according to claim 4, characterized in that, The first timing control signal, the second timing control signal, and the third timing control signal are square wave signals with the same output frequency and a continuous low potential occupying 1 / 3 of the cycle.

6. The scanning drive circuit according to claim 4, characterized in that, The shift register unit is used to perform delay processing on the signal received from the signal input terminal under the control of the first timing control signal, the second timing control signal and the third timing control signal, and the processed signal is output by the signal output terminal.

7. The scanning drive circuit according to claim 3, characterized in that, The shift register unit at the previous stage outputs a scan signal to the shift register unit at the next stage, and the shift register unit at the last stage outputs a scan signal.

8. The scanning drive circuit according to claim 4, characterized in that, In the shift register unit of the 3N-2 stage, the first timing control terminal is connected to the first timing control signal line, the second timing control terminal is connected to the second timing control signal line, and the third timing control terminal is connected to the third timing control signal line, where N is a positive integer.

9. The scanning drive circuit according to claim 8, characterized in that, In the shift register unit of the 3N-1 stage, the first timing control terminal is connected to the third timing control signal line, the second timing control terminal is connected to the first timing control signal line, and the third timing control terminal is connected to the second timing control signal line, where N is a positive integer.

10. The scanning drive circuit according to claim 9, characterized in that, In the shift register unit of the 3Nth stage, the first timing control terminal is connected to the second timing control signal line, the second timing control terminal is connected to the third timing control signal line, and the third timing control terminal is connected to the first timing control signal line, where N is a positive integer.

11. A display panel, characterized in that, Includes the scan drive circuit according to any one of claims 1 to 10.

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