A power semiconductor device and a method for manufacturing the same

Abstract

A power semiconductor device and a method for preparing the same. The present invention relates to a power semiconductor device. To provide a highly reliable chip structure, the present invention reduces the surface stress in the peripheral area of ​​the chip and improves the breakdown voltage and reliability of the terminal area by providing one or more source areas, one or more terminal areas, one or more floating trench areas, and a cutoff area located at the outermost periphery of the chip.

Description

Technical Field

[0001] The present invention relates to a power semiconductor device, in particular to the structure of a trench field effect transistor device and a manufacturing method thereof. Background Art

[0002] The following describes the relevant technical background of existing shielded gate trench field effect transistors. It should be noted that the corresponding position words described in this document, such as "upper", "lower", "left", "right", "front", "back", "vertical", "horizontal", and "vertical", correspond to the relative positions of the reference diagrams. There is no restriction on fixed directions in the specific implementation. It should be noted that the devices in the drawings are not necessarily drawn to a specific scale. The straight lines shown as the boundaries of the doped regions and trenches in the drawings, as well as the sharp angles formed by the boundaries, are generally not straight lines and precise angles in actual applications.

[0003] Shielded gate trench field effect transistors have the characteristics of low on-resistance and fast switching speed. Figure 1 The figure shows a schematic diagram of the cross-sectional structure of a traditional N-type shielded gate trench field-effect transistor. In this structure, as the voltage resistance of the shielded gate trench field-effect transistor increases, a deeper trench depth and a thicker trench oxide layer are required. In a medium-voltage shielded gate trench field-effect transistor design greater than 150V, a trench depth of 7-12um and a trench oxide layer of 1-2um are generally required. The high-density arrangement of deep trenches is prone to generate large stresses during the thermal process and filling process of device chip manufacturing, causing wafer warping and affecting process stability. One existing approach is to form multiple areas with different trench directions in a chip to alleviate wafer warping. However, due to the surface stresses generated in different directions in the above-mentioned different areas, mechanical deformation is prone to occur at the junction of different areas, resulting in cracks.

[0004] In shielded-gate trench FET devices, the outermost termination region must have a higher withstand voltage than the active region. This region is typically formed by multiple deep trenches surrounding the active region, which are typically deeper than the trenches within the active region. The deep trench structure can easily cause severe stress on the chip surface in the termination region, leading to delamination of the surface oxide layer and passivation layer at the chip's edge. This can lead to the intrusion of water vapor or foreign contaminant ions into the semiconductor, forming leakage paths on the upper surface of the semiconductor at the chip's edge. Therefore, a highly reliable chip periphery structure is required. Summary of the Invention

[0005] In order to solve the above-mentioned problems, the present invention provides the following technical solution:

[0006] One of the objectives of the present invention is to provide a power semiconductor device, comprising a drain metal layer at the bottom, a heavily doped substrate layer of the first conductivity type located above the drain metal layer, a first epitaxial layer of the first conductivity type located above the heavily doped substrate layer, a second epitaxial layer, a trench region, and source metal and gate metal layers located on the upper surface of the device; characterized in that the semiconductor device is provided with one or more active regions, one or more terminal regions surrounding the active regions, one or more floating trench regions located at the periphery of the chip surrounding all active regions and terminal regions, and a cutoff region located at the outermost periphery of the chip;

[0007] The active area includes a series of mutually parallel cellular trenches, each of which includes a gate electrode located above the trench and a shielding gate electrode located below the trench. A first conductivity type lightly doped drift region and a second conductivity type doped body region located above the drift region are provided between the cellular trenches. In one device, the active area includes at least two types of cellular trenches in different directions.

[0008] The terminal region includes one or more parallel terminal trenches, the terminal trenches are filled with shielding gate electrodes, and the shielding gate electrodes are connected to the source metal on the upper surface of the device or other potential between the source and the drain;

[0009] The floating groove area includes more than one section of mutually parallel floating grooves;

[0010] The cut-off region includes at least one cut-off trench and a cut-off metal layer on the upper surface of the device in the region. The cut-off trench is provided with at least a shielding gate electrode, and the shielding gate electrode is connected to the cut-off metal layer on the upper surface of the semiconductor.

[0011] Preferably, the floating trenches are filled with a low-stress insulating material, and a floating electrode is provided in at least one floating trench, and the floating electrode is connected to a floating potential.

[0012] Preferably, the floating grooves include a first type of parallel floating grooves parallel to the terminal grooves and a second type of vertical floating grooves perpendicular to the adjacent terminal grooves.

[0013] Furthermore, the floating electrodes are arranged in the second type of parallel floating grooves, and / or the floating electrodes extend toward the inside of the chip.

[0014] Preferably, the width and depth of the floating electrode are equal to the width and depth of the terminal groove.

[0015] Preferably, a second conductive type floating injection region is provided below the floating trench.

[0016] Furthermore, the floating trench region is surrounded by a second conductive type floating implant region.

[0017] Preferably, the distance between the floating trenches in the floating trench region gradually increases in a direction away from the central region of the chip.

[0018] Preferably, the floating electrodes are connected to the cut-off metal layer at the corners of the quadrilateral chip.

[0019] Preferably, the floating grooves and the cellular grooves are in different directions.

[0020] Preferably, the angle between the floating groove and one of the cell grooves is 45°.

[0021] Preferably, an extension trench having the same direction as the cell trench is provided at the end of at least one cell trench in the active area, the depth and width of the extension trench being no greater than the depth and width of the cell trench, and the extension trench is connected to the terminal trench.

[0022] Preferably, there is one or more inner circle terminal grooves connecting any two cellular grooves separated by one or more cellular grooves in the middle, and one or more outer circle terminal grooves connecting the cellular grooves on both sides of each inner circle terminal groove and surrounding the inner circle terminal groove. The structures of the inner circle terminal groove and the outer circle terminal groove are the same as those of the terminal groove.

[0023] Preferably, the cell trenches in adjacent active regions are perpendicular to each other.

[0024] Another object of the present invention is to provide a method for manufacturing a power semiconductor device, the method comprising the following steps:

[0025] The first step is to form a first conductivity type epitaxial layer on a first conductivity type semiconductor substrate;

[0026] In the second step, a nitride hard mask layer and an oxide hard mask layer thereon are formed on the upper surface of the semiconductor by deposition and photolithography, and then a semiconductor trench is etched;

[0027] The third step is to form a shielding gate isolation layer in the cell trench and the terminal trench;

[0028] In the fourth step, a shielding gate electrode material is first deposited, and then chemical mechanical polishing is performed to remove the shielding gate electrode material and the shielding gate isolation layer material on the upper surface of the semiconductor, and the polishing stops on the nitride hard mask layer on the upper surface of the semiconductor;

[0029] The fifth step is to perform photolithography and then etch the shielding gate isolation layer in the cell trench under the protection of photoresist;

[0030] After etching, the thickness of the shielding grid isolation layer remaining on the sidewalls of the etched holes in the cell trench is not less than 2000A;

[0031] Step 6: forming a gate oxide layer and a gate electrode;

[0032] The seventh step is to form a channel doping region, then form a surface oxide layer, and then form contact holes in the surface oxide layer, as well as source metal, gate metal layer and cutoff metal layer; the channel doping region at least includes a second conductive type doped body region located between the cell trenches.

[0033] Preferably, in the first step, a polysilicon layer is formed under the first conductive semiconductor substrate, an oxide layer is formed under the polysilicon layer, a polysilicon layer is first formed under the oxide layer and thermally oxidized to form a thick oxide layer, and the polysilicon layer, oxide layer and thick oxide layer are removed in subsequent processes.

[0034] Preferably, in the fifth step, the photoresist only protects the shielding gate isolation layer material on the terminal trench and the floating trench, the shielding gate isolation layer on the upper part of the cell trench is completely removed, and an inter-electrode isolation layer is formed by thermal oxidation in a subsequent process.

[0035] The present invention proposes a field effect transistor structure that can reduce the surface stress in the peripheral area of ​​the chip and ensure the breakdown voltage and reliability of the terminal area. The present invention proposes a new manufacturing process flow of a medium-voltage deep trench medium-voltage shielded gate trench field effect transistor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 The figure is a cross-sectional schematic diagram of an existing shielded gate trench field effect transistor device.

[0037] Figure 2 Schematic cross-sectional view of an embodiment of the device of the present invention.

[0038] Figure 3 Schematic cross-sectional view of another embodiment of the device of the present invention.

[0039] Figure 4 Schematic cross-sectional view of another embodiment of the device of the present invention.

[0040] Figure 5 Schematic cross-sectional view of another embodiment of the device of the present invention.

[0041] Figure 6 A top view of a trench structure of an embodiment of the device of the present invention.

[0042] Figure 7 A top view of a trench structure of another embodiment of the device of the present invention.

[0043] Figure 8 A top view of a trench structure of another embodiment of the device of the present invention.

[0044] Figure 9 A top view of the structure of the cell trench and the terminal trench of an embodiment of the device of the present invention.

[0045] Figure 10 A is a top view of the structure of the cell trench and the terminal trench of another embodiment of the device of the present invention.

[0046] Figure 10 B is a top view of the structure of the cell trench, terminal trench and gate metal layer of an embodiment of the device of the present invention.

[0047] Figure 11-16 This is a key step in the manufacturing process of an embodiment of the device of the present invention. DETAILED DESCRIPTION

[0048] The present invention is described in detail below with reference to the accompanying drawings and embodiments. It should be noted that in the following description of the shielded gate trench field effect transistor device and its manufacturing method of the present invention, the semiconductor substrate of the shielded gate trench field effect transistor device is considered to be composed of silicon (Si) material. However, the substrate can also be composed of any other material suitable for the manufacture of shielded gate trench field effect transistors, such as gallium nitride (GaN), silicon carbide (SiC), etc. In the following description, the conductivity type of the semiconductor region is divided into P-type (second conductivity type) and N-type (first conductivity type). A P-type conductive semiconductor region can be formed by doping one or more impurities into the original semiconductor region. These impurities can be, but are not limited to, boron (B), aluminum (Al), gallium (Ga), etc. An N-type conductive semiconductor region can also be formed by doping one or more impurities into the original semiconductor region. These impurities can be, but are not limited to, phosphorus (P), arsenic (As), tellurium (Sb), selenium (Se), protons (H + ) etc. In the following description, the heavily doped P-type conductive semiconductor region is marked as P + The heavily doped N-type conductive semiconductor region is marked as N + For example, in a silicon substrate, unless otherwise specified, the impurity concentration of a heavily doped region is generally around 1 × 10 19 cm -3 to 1 × 10 21 cm -3 Those skilled in the art should know that the P-type (second conductivity type) and the N-type (first conductivity type) described in the present invention can be interchanged.

[0049] Example 1

[0050] Figure 2The semiconductor field effect transistor device structure of the first embodiment is Figure 6 The cross-sectional view corresponding to the dotted line A. It includes: the drain metal layer (212) at the bottom; the N + Substrate layer (201); located at N + An N-type first epitaxial layer (200) is located above the substrate layer, and a second epitaxial layer (204) is located above the first epitaxial layer.

[0051] According to the groove structure and distribution, it can be divided into the following areas: active area (230), terminal area (231), floating groove area (232), and cut-off area (233).

[0052] The device includes two or more active regions (230), each of which includes a series of cellular grooves (220) in the same direction and parallel to each other. The cellular grooves (220) in the entire device have at least two different groove directions. The cellular groove (220) includes a gate electrode (206) located above the groove and a shielding gate electrode (207) located below. The gate electrode (206) and the sidewall of the groove are isolated by a gate oxide layer. The gate electrode (206) and the shielding gate electrode (207) are isolated by an inter-electrode isolation layer. The shielding gate electrode (207) is connected to the source metal (211) located on the upper surface of the device. In addition, there is a shielding gate isolation layer (215) between the shielding gate electrode (207) and the sidewall of the groove. There is a P-doped body region (208) located on the upper surface of the device between the cellular grooves. In one embodiment, there is an N-doped body region below the P-doped body region. - Type drift region (205).

[0053] The terminal trench region (231) is composed of one or several parallel terminal trenches (221). The terminal trench (221) surrounds the active region (230) located in the middle. The terminal trench has the same depth and width as the cell trench and is filled with a shielding gate electrode (207). A shielding gate isolation layer (215) is provided between the shielding gate electrode (207) and the trench sidewall. The shielding gate electrode (207) in the terminal trench is connected to the source metal (211) on the upper surface of the device or other potential between the source and the drain.

[0054] The floating trench region (232) is located at the periphery of the chip and surrounds multiple active regions (230) and terminal regions (231). The floating trench region (232) has multiple independent and parallel floating trenches (222). The width and depth of the floating trench are not greater than the terminal trench (221). The length of the floating trench (222) is usually less than the cell trench (220). The spacing between the multiple floating trenches (232) is usually greater than the spacing between the cell trenches (220), and the spacing is different at different locations on the chip. In one embodiment, the floating trench (222) is filled with a low-stress insulating material (216). In one embodiment, the floating trench (222) contains a floating electrode (217), which is usually connected to a floating potential. The floating electrode may be located at the top of the trench, and the depth of the floating electrode may be the same as the gate electrode in the cell trench (220). A gate metal layer (214) may be present on the semiconductor upper surface of the floating region, and the gate metal layer (214) is connected to a gate electrode (206) on a cell trench (220) in the active region. In one embodiment, a portion of the floating electrode (217) may be connected to the gate metal layer (214).

[0055] The floating groove (222) can alleviate the contaminant ions from entering the peripheral area and the terminal area of ​​the chip. The floating electrode (217) is conducive to limiting the electric field distribution near the upper surface of the semiconductor in the floating groove area (232), preventing the leakage path formed by the invasion of the contaminant ions.

[0056] The cut-off region (233) is located at the outermost periphery of the chip and includes at least a cut-off groove (224) surrounding the interior of the chip. The cut-off groove (224) has the same structure as the cell groove (220) or the terminal groove (221). All electrodes in the cut-off groove (224) are connected to the cut-off metal layer (213) on the upper surface of the semiconductor and are connected to the upper surface of the semiconductor outside the cut-off groove (224) through contact holes.

[0057] In one embodiment, the width of the cell groove (220) and the terminal groove (221) is between 1um and 4um, and the depth is between 5um and 14um. In one embodiment, the distance between adjacent cell grooves (220) is between 0.4um and 2um.

[0058] Figure 6 A top view of a possible trench structure of the device of the present invention is shown. The dotted line A corresponds to Figure 2 Partial cross section.

[0059] As shown in the figure, the center of the device chip has multiple active areas (230). A series of mutually parallel cellular grooves (220) are arranged in the active area (230). Generally, the directions of the series of cellular grooves (220) in adjacent active areas (230) are perpendicular to each other. Around each independent active area (230), there are one or more mutually parallel terminal grooves (221) surrounding the active area (230), forming a terminal groove area (231).

[0060] Typically, each active region (230) and the peripheral terminal trench (221) form a terminal trench region (231), and the aspect ratio of the terminal trench region (231) is between 4:1 and 1:4.

[0061] At the outermost periphery of the device chip, there is a cut-off groove (224) surrounding the quadrilateral device and forming a cut-off region (233). The cut-off groove (224) may form a smooth arc at the corner.

[0062] In the irregular region between the cut-off region (233) and the terminal groove (221), there are multiple independent and mutually parallel floating grooves (222) to form a floating groove region (232). Generally, the floating grooves (222) have multiple directions. Figure 6 As shown, the floating groove (222) has vertical and horizontal directions and is parallel to the adjacent terminal groove (221).

[0063] In one embodiment, the distance between the cell trench (220) and the adjacent terminal trench (221) is equal to the distance between the cell trench (220) and the adjacent cell trench (220) in the active area (230).

[0064] In one embodiment, the distance between the outermost cell trench (220) in the active region (230) and the adjacent terminal trench (221) is equal to the distance between the cell trench (220) in the active region (230) and the adjacent cell trench (220).

[0065] In one embodiment, the distance between adjacent floating trenches (222) in the floating trench region (232) is equal to the distance between adjacent cell trenches (220) in the active region (230).

[0066] In one embodiment, the distance between adjacent floating grooves (222) in the floating groove region (232) increases as the distance away from the central region of the chip increases.

[0067] In one embodiment, a floating electrode (217) is provided in a portion of the floating groove (222), and the floating electrode is connected to the cutoff metal layer (213) at the corner of the quadrilateral chip. Figure 6 shown.

[0068] Example 2

[0069] Figure 3 This is another field effect transistor device structure according to an embodiment of the present invention. Figure 2 The difference in structure is that the floating groove area (232) contains multiple independent floating grooves (222) in different directions, including a first type of parallel floating grooves (252) parallel to the terminal groove (221), and a second type of vertical floating grooves (262) perpendicular to the adjacent terminal groove (221). The above-mentioned first type of vertical floating grooves (252) and second type of parallel floating grooves (262) may have multiple sections and each section is parallel to each other. The multiple sections of the first type of parallel floating grooves (252) and the second type of vertical floating grooves (262) in the floating groove area (232) may be arranged alternately.

[0070] In one embodiment, the second type of parallel floating trenches (262) contain floating electrodes (217), and the floating electrodes (217) are connected to the cutoff metal layer (213) located on the upper surface of the semiconductor. A portion of the floating trenches (222) extends from the outside of the chip to the inside of the chip, or from the cutoff region (233) to the active region (230), such as Figure 3 As shown. The length of the floating electrode (217) extending inward may be shorter than the length of the floating groove (222). In one embodiment, the length of a section of the floating groove (222) is 3-15 um, and the floating electrode (217) therein is connected to the peripheral cut-off metal layer (213) and extends into the interior of the chip, with an extension distance of 2-12 um.

[0071] Example 3

[0072] Figure 4 This is another field effect transistor device structure according to an embodiment of the present invention. Figure 2 、 Figure 3 The difference in the device structure is that the floating groove (222) in the floating groove area (232) has the same width and depth as the terminal groove (221) in the terminal groove area (231), and a floating electrode (217) is provided in the floating groove (222), and the floating electrode (217) extends to the bottom of the groove.

[0073] Example 4

[0074] Figure 5 This is another field effect transistor device structure according to an embodiment of the present invention. The difference between this structure and the aforementioned device structure is that a P-type floating injection region (255) is provided below and between the floating trenches (222) in the floating trench region (232).

[0075] In one embodiment, the doping concentration of the P-type floating injection region (255) is lower than that of the P-doped body region (208).

[0076] In one embodiment, the P-type floating implant region (255) surrounds the terminal trench (221) located at the outermost periphery of the terminal region (231).

[0077] Example 5

[0078] Figure 7 A top view of another possible trench structure of the device of the present invention is shown. The dotted line B corresponds to Figure 3 Partial cross section of the floating groove region (232). Figure 6 The difference between the structures shown in FIG and FIG is that the floating grooves (222) in the floating groove region (232) on the same side have independent vertical and horizontal segments.

[0079] In one embodiment, a floating electrode (217) is provided in a portion of the floating groove (222), and the floating electrode (217) is connected to the cutoff metal layer (213) of the quad chip, such as Figure 7 shown.

[0080] Example 6

[0081] Figure 8 A top view of another possible trench structure of the device of the present invention is shown. The difference from the aforementioned structure is that the floating trench (222) in the floating trench region (232) has a different direction from the cell trench (220) in the active region (230).

[0082] In one embodiment, the direction of the floating trench (222) in the partially floating trench region (232) is 45 degrees to the direction of the cell trench (220) in the active region (230).

[0083] In the above Figure 6-8 In the embodiment, the structure of the chip edge is conducive to limiting the entry of pollutant ions into the interior of the chip, and can balance the surface stress of the four sides of the chip, reducing the risk of passivation layer fracture.

[0084] Example 7

[0085] Figure 9A top view of the structure of another possible cell groove (220) and terminal groove (221) of the device of the present invention is shown. In the active area (230), at the end of some cell grooves (220), there is an extension groove (253) in the same direction as the cell groove (220), and the extension groove (253) is connected to the terminal groove (221). Generally, the depth and width of the extension groove (253) are not greater than the depth and width of the cell groove (220). In some embodiments, the extension groove may be a floating groove (222). The extension groove (253) can ensure the breakdown voltage of the semiconductor region near the end of the cell groove (220).

[0086] Example 8

[0087] Figure 10 A shows a top view of the structure of another possible cellular groove (220) and terminal groove (221) of the device of the present invention. Among them, located in the active area (230), at the end of the cellular groove (220), there is an inner circle terminal groove (257) and an outer circle terminal groove (259) connected to the cellular groove (220). The inner circle terminal groove (257) and the outer circle terminal groove (259) are both terminal grooves (221). Among them, two sections of cellular grooves (220) separated by more than one section of cellular groove (220) are connected through the inner circle terminal groove (257) at their ends, that is, the two ends of the cellular grooves (220) connected by the inner circle terminal groove (257) are surrounded by at least one section of cellular groove (220). Figure 10 A shows that only one section of the cellular groove (220) is surrounded; the ends of the two sections of the cellular groove (220) on both sides of the periphery of each inner circle terminal groove (257) are connected by the peripheral terminal groove (259), that is, the two sections of the cellular groove (220) connected by the peripheral terminal groove (259) are surrounded by the inner circle terminal groove (257) and its corresponding cellular groove (220).

[0088] Figure 10 B shows a top view of a possible trench and gate metal layer structure of the device of the present invention.

[0089] The structure includes at least four active regions (230), and the series of cell grooves (220) in adjacent active regions (230) are perpendicular to each other in direction. A terminal groove region (231) composed of terminal grooves (221) is provided at the junction of adjacent active regions (230). Above the terminal groove region (231) and the edge of the active region (230), there is a cross-shaped or cross-windmill-shaped gate metal layer (214) structure. The gate metal layer (214) may be connected to the gate electrode (206) inside some of the cell grooves (220) through a contact hole.

[0090] Example 9

[0091] Figures 11 to 16 The key steps of the manufacturing process of an embodiment of the device of the present invention are shown.

[0092] In the first step, an N-type epitaxial layer (200) is formed on an N-type semiconductor substrate (201).

[0093] Below the N-type semiconductor substrate (201), there may be a polysilicon layer (280) and an oxide layer (281) below the polysilicon layer (280). The thickness of the polysilicon layer (280) is between 0.4um and 1um, and the thickness of the oxide layer (281) is between 0.2um and 0.8um. ​​In order to alleviate the wafer warping caused by subsequent processes, a thick oxide layer (282) may be formed below the oxide layer (281). In one embodiment, a polysilicon layer is first formed below the oxide layer (281) at the bottom of the wafer and thermally oxidized to form a thick oxide layer (282). The thickness of the thick oxide layer is between 0.2um and 1um. The above-mentioned polysilicon layer (280), oxide layer (281), and thick oxide layer (282) will be removed in subsequent processes.

[0094] In the second step, a nitride hard mask layer (254) and an oxide hard mask layer (256) thereon are formed on the upper surface of the semiconductor by deposition and photolithography. Then, semiconductor trenches (220, 221, 222) are etched, as shown in FIG. Figure 11 shown.

[0095] Before depositing the nitride hard mask layer (254), a thin oxide layer may first be formed with a thickness between 50 Å and 2000 Å.

[0096] In one embodiment, the cell trench (220) and the terminal trench (221) may be etched first, and then the floating trench (222) may be etched.

[0097] Typically, the width of the cellular groove (220) is between 0.5um and 4um, and the depth is between 5um and 14um. The width and depth of the terminal groove (221) are not less than the cellular groove. The width and depth of the floating groove (222) are not greater than the cellular groove.

[0098] In one embodiment, the cell groove (220) and the terminal groove (221) have the same groove width and depth.

[0099] In one embodiment, the cell trench (220) and the terminal trench (221) have the same trench width and depth, and the floating trench (222) has the same depth as the terminal trench (221).

[0100] In the third step, a shielding gate isolation layer (215) is formed in the cell trench (220) and the terminal trench (221), such as Figure 12shown.

[0101] The shield gate isolation layer may be composed of oxide, and the thickness is generally between 3000 Å and 2 μm. In one embodiment, a 1500 Å-6000 Å oxide layer is first formed by thermal oxidation, and then a 1000 Å-1.5 μm oxide layer is formed by deposition.

[0102] In one embodiment, the shielding gate isolation layer (215) material may completely fill the floating trench (222). In another embodiment, the shielding gate isolation layer (215) material in the floating trench (222) may be completely or partially removed by photolithography and etching steps, and then other low-stress insulating materials, such as silicon-rich silicon oxide, may be deposited therein.

[0103] In the fourth step, a shielding gate electrode material (258) is first deposited, and then chemical mechanical polishing is performed to remove the shielding gate electrode material (258) and the shielding gate isolation layer material (215) on the upper surface of the semiconductor, and the polishing stops on the nitride hard mask layer (254) on the upper surface of the semiconductor.

[0104] The shielding gate electrode material (258) is usually polysilicon. After deposition, the upper surface of the polysilicon is higher than the upper surface of the semiconductor. After chemical mechanical polishing, the shielding gate electrode material (258) may be further etched back.

[0105] In one embodiment, the nitride hard mask (254) layer in the second step may be omitted, and in the subsequent fourth step, a dry or wet etching process is used to etch back the shield gate electrode material (258).

[0106] The fifth step is to perform photolithography, and then etch the shielding gate isolation layer (215) in the cell groove (220) under the protection of the photoresist (260), as shown in FIG. Figure 14 shown.

[0107] The etching method may be dry etching. In some embodiments, dry etching may be performed first and then wet etching. After etching is completed, the width of the upper surface opening is 0.1um to 1um, and the etching depth is 0.2um to 1.5um. After etching, the shielding gate isolation layer (215) remaining on the sidewall of the etched hole in the cell groove (220) has a thickness of not less than 2000A.

[0108] After the etching is completed and the photoresist is removed, the nitride hard mask layer (254) on the upper surface of the semiconductor may be further removed.

[0109] In one embodiment, the photoresist only protects the shielding gate isolation layer (215) material on the terminal trench (221) and the floating trench, and the shielding gate isolation layer (215) on the upper portion of the cell trench (220) is completely removed, and an inter-electrode isolation layer is formed by thermal oxidation in a subsequent process.

[0110] Step 6: forming a gate oxide layer and a gate electrode (206), such as Figure 15 shown.

[0111] The gate electrode (206) is generally made of polysilicon, and the formation process may be polysilicon deposition followed by back etching. In one embodiment, chemical mechanical polishing may be performed after polysilicon deposition, followed by back etching of the polysilicon.

[0112] In one embodiment, the gate electrode (206) material located in the floating trench (222) after etching back is the floating electrode (217).

[0113] In the seventh step, a channel doping region is formed, and then a surface oxide layer (261) is formed, and then a contact hole (272) is formed in the surface oxide layer, and an upper surface metal layer (211, 212, 213), and finally a device is formed, such as Figure 16 As shown, the channel doping region at least includes a P-doped body region (208) located between the cell trenches.

[0114] Those skilled in the art should know that the above manufacturing steps only list key steps and do not show the complete steps for forming a device.

[0115] The specific detailed manufacturing steps can be obtained based on common manufacturing process steps and common sense knowledge in this field and can be appropriately increased, decreased or changed.

[0116] In addition, those skilled in the art should know that the structural features and process steps mentioned in the above-mentioned embodiments of the present invention can be combined with each other to form more embodiment device structures and manufacturing processes.

Claims

1. A power semiconductor device comprising a drain metal layer at the bottom, a heavily doped substrate layer of the first conductivity type located above the drain metal layer, a first epitaxial layer of the first conductivity type located above the heavily doped substrate layer of the first conductivity type, a second epitaxial layer, a trench region, and source metal and gate metal layers located on the upper surface of the device; characterized in that: The semiconductor device is provided with one or more active areas, one or more terminal areas surrounding the active areas, one or more floating trench areas surrounding all active areas and terminal areas at the periphery of the chip, and a cut-off area located at the outermost periphery of the chip; The active area includes a series of mutually parallel cellular trenches, each of which includes a gate electrode located above the trench and a shielding gate electrode located below the trench. A first conductivity type lightly doped drift region and a second conductivity type doped body region located above the cellular trench are provided between the cellular trenches. In one device, the active area includes at least two types of cellular trenches in different directions. The terminal region includes one or more parallel terminal trenches, the terminal trenches are filled with shielding gate electrodes, and the shielding gate electrodes are connected to the source metal on the upper surface of the device or other potential between the source and the drain; The floating groove area includes more than one section of mutually parallel floating grooves; The cut-off region includes at least one cut-off trench and a cut-off metal layer on the upper surface of the device in the region, the cut-off trench is provided with at least a shielding gate electrode, and the shielding gate electrode is connected to the cut-off metal layer on the upper surface of the semiconductor; An extension trench having the same direction as the cell trench is provided at the end of at least one cell trench in the active area, wherein the depth and width of the extension trench are not greater than the depth and width of the cell trench, and the extension trench is connected to the terminal trench; The floating grooves and the cellular grooves are in different directions.

2. The power semiconductor device according to claim 1, wherein: The floating trenches are filled with low-stress insulating materials, and at least one floating trench is provided with a floating electrode, which is connected to a floating potential.

3. The power semiconductor device according to claim 2, wherein: The floating grooves include a first type of parallel floating grooves parallel to the terminal grooves and a second type of vertical floating grooves perpendicular to the adjacent terminal grooves.

4. The power semiconductor device according to claim 3, wherein: The floating electrodes are arranged in the second type of vertical floating grooves, and / or the floating electrodes extend toward the inside of the chip.

5. The power semiconductor device according to claim 2, wherein: The width and depth of the floating electrode are equal to the width and depth of the terminal groove.

6. The power semiconductor device according to claim 1, wherein: A second conductive type floating injection region is provided below the floating trench.

7. The power semiconductor device according to claim 6, wherein: The floating trench area is surrounded by a second conductive type floating injection area.

8. The power semiconductor device according to claim 1, wherein: The distance between the floating grooves in the floating groove region gradually increases in a direction away from the central region of the chip.

9. The power semiconductor device according to claim 2, wherein: The floating electrodes are connected to the cut-off metal layer at the corners of the quadrilateral chip.

10. The power semiconductor device according to claim 1, wherein: The angle between the floating groove and one of the cell grooves is 45 degrees.

11. The power semiconductor device according to claim 1, wherein: The active area is provided with one or more inner circle terminal grooves connecting any two cellular grooves separated by one or more cellular grooves, and one or more outer circle terminal grooves connecting the cellular grooves on both sides of each inner circle terminal groove and surrounding the inner circle terminal groove. The structures of the inner circle terminal groove and the outer circle terminal groove are the same as those of the terminal groove.

12. The power semiconductor device according to claim 1, wherein: The cell trenches in adjacent active areas are perpendicular to each other.

13. The method for manufacturing a power semiconductor device according to any one of claims 1 to 12, wherein: The manufacturing method comprises the following steps: The first step is to form a first conductivity type epitaxial layer on a first conductivity type semiconductor substrate; In the second step, a nitride hard mask layer and an oxide hard mask layer thereon are formed on the upper surface of the semiconductor by deposition and photolithography, and then a semiconductor trench is etched; The third step is to form a shielding gate isolation layer in the cell trench and the terminal trench; In the fourth step, a shielding gate electrode material is first deposited, and then chemical mechanical polishing is performed to remove the shielding gate electrode material and the shielding gate isolation layer material on the upper surface of the semiconductor, and the polishing stops on the nitride hard mask layer on the upper surface of the semiconductor; The fifth step is to perform photolithography and then etch the shielding gate isolation layer in the cell trench under the protection of photoresist; After etching, the thickness of the shielding grid isolation layer remaining on the sidewalls of the etched holes in the cell trench is not less than 2000A; Step 6: forming a gate oxide layer and a gate electrode; The seventh step is to form a channel doping region, then form a surface oxide layer, and then form contact holes in the surface oxide layer, as well as source metal, gate metal layer and cutoff metal layer; the channel doping region at least includes a second conductive type doped body region located between the cell trenches.

14. The method for manufacturing a power semiconductor device according to claim 13, wherein: In the first step, a polysilicon layer is formed under the first conductive semiconductor substrate, and an oxide layer is formed under the polysilicon layer. A polysilicon layer is first formed under the oxide layer and thermally oxidized to form a thick oxide layer. The polysilicon layer, oxide layer, and thick oxide layer are removed in subsequent processes.

15. The method for manufacturing a power semiconductor device according to claim 13, wherein: In the fifth step, the photoresist only protects the terminal trench and the shielding gate isolation layer material. The shielding gate isolation layer on the upper part of the cell trench is completely removed, and an inter-electrode isolation layer is formed by thermal oxidation in a subsequent process. The inter-electrode isolation layer is located between the gate electrode and the shielding gate electrode.

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