Array substrate and display panel

Abstract

The application discloses an array substrate and a display panel. The array substrate comprises a substrate and a driving circuit layer on the substrate, wherein the driving circuit layer is provided with a pixel circuit and a light-emitting control signal line, the pixel circuit comprises a driving transistor, a first initialization transistor and a first connecting part, the first connecting part is connected between the first electrode of the driving transistor and the first initialization transistor, the first connecting part and the light-emitting control signal line have an overlapping part in the orthographic projection on the substrate, the orthographic projection of a shielding part provided in the driving circuit layer on the substrate overlaps with the overlapping part, the film layer where the shielding part is located is between the film layer where the light-emitting control signal line is located and the film layer where the first connecting part is located, and / or at least one organic insulating layer is arranged between the film layer where the first connecting part is located and the film layer where the light-emitting control signal line is located, and / or the thickness of the insulating layer between the two is greater than 3 microns. The technical scheme of the application improves the display uniformity of the display panel.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to an array substrate and a display panel. Background Technology

[0002] With the rapid development of display technology, organic light-emitting display (OLED) products are being used more and more widely.

[0003] However, the uniformity of current OLED display panels needs to be improved. Summary of the Invention

[0004] The present invention provides an array substrate and a display panel to improve the display uniformity of the display panel.

[0005] According to one aspect of the present invention, an array substrate is provided, the array substrate comprising: a substrate and a driving circuit layer located on the substrate, the driving circuit layer being provided with a pixel circuit and a light emission control signal line, the pixel circuit comprising a driving transistor, a first initialization transistor and a first connection portion, the first connection portion being connected between a first electrode of the driving transistor and the first initialization transistor; the first connection portion and the orthographic projection of the light emission control signal line on the substrate have an overlapping portion;

[0006] The driving circuit layer also includes a shielding portion, and the orthographic projection of the shielding portion on the substrate overlaps with the overlapping portion; the film layer where the shielding portion is located is situated between the film layer where the light emission control signal line is located and the film layer where the first connection portion is located.

[0007] And / or, at least one organic insulating layer is provided between the film layer where the first connection part is located and the film layer where the light emission control signal line is located;

[0008] And / or, the thickness of the insulating layer between the film layer where the first connection part is located and the film layer where the light-emitting control signal line is located is greater than 3 micrometers.

[0009] Optionally, the shielding part is connected to a DC potential;

[0010] Optionally, the driving circuit layer is further provided with a first power line and / or an initialization signal line, and the shielding part is electrically connected to the first power line or the initialization signal line.

[0011] Optionally, the driving circuit layer includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer stacked together;

[0012] The light emission control signal line is disposed on the first conductive layer;

[0013] The pixel circuit also includes a storage capacitor, the first plate of which is disposed on the second conductive layer;

[0014] The pixel circuit also includes a switching transistor, which is connected to the gate of the driving transistor, and the first gate of the switching transistor is disposed on the third conductive layer.

[0015] The first connection portion is disposed on the fourth conductive layer or on the side of the fourth conductive layer away from the substrate;

[0016] The fifth conductive layer is provided with a first power line, which is used to provide a first power supply voltage to the pixel circuit.

[0017] Optionally, the first connecting portion is disposed on the fifth conductive layer;

[0018] Optionally, an organic insulating layer is disposed between the fourth conductive layer and the fifth conductive layer;

[0019] Optionally, an inorganic insulating layer is disposed between any two adjacent layers of the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer.

[0020] Optionally, the overlapping portion is located within the orthographic projection of the shielding portion onto the substrate;

[0021] Optionally, the film layer containing the light-emitting control signal line, the film layer containing the shielding part, and the film layer containing the first connecting part are stacked sequentially in a direction away from the substrate.

[0022] Optionally, the pixel circuit further includes a second initialization transistor; the driving circuit layer is further provided with a first initialization signal line and a second initialization signal line, the first initialization transistor is connected between the first initialization signal line and the first terminal of the driving transistor, and the second initialization transistor is connected between the second initialization signal line and the first terminal of the light-emitting device.

[0023] The shielding part is electrically connected to either the first initialization signal line or the second initialization signal line;

[0024] Optionally, the gate of the first initialization transistor and the gate of the second initialization transistor are electrically connected to the same scan signal line;

[0025] Optionally, the driving circuit layer may further include a third conductive layer; the pixel circuit may further include a switching transistor.

[0026] The gate of the switching transistor is connected to the gate of the driving transistor; the first gate of the switching transistor is disposed in the third conductive layer.

[0027] Optionally, the shielding portion is disposed on the third conductive layer;

[0028] Optionally, the first initialization signal line and / or the second initialization signal line are disposed on the third conductive layer;

[0029] Optionally, the orthographic projection of the first initialization signal line on the substrate is located between the orthographic projection of the second initialization signal line on the substrate and the orthographic projection of the shielding portion on the substrate; the orthographic projection of the first initialization signal line on the substrate is located between the orthographic projection of the second initialization signal line on the substrate and the orthographic projection of the light emission control signal line on the substrate.

[0030] Optionally, the first initialization signal line, the second initialization signal line, and the light emission control signal line extend in the first direction and are arranged along the second direction, with the first direction and the second direction intersecting.

[0031] Optionally, the second initialization signal line is electrically connected to the shielding part via the second connecting part, and the second connecting part is provided with cross insulation from the first initialization signal line;

[0032] Optionally, the film layer where the second connection portion is located is located on the side of the film layer where the first initialization signal line is located that is away from the substrate;

[0033] Optionally, the first connecting part and the second connecting part are arranged on the same layer.

[0034] Optionally, the pixel circuit also includes a storage capacitor, the first plate of which is connected to the first power supply line.

[0035] The first electrode plate and the shielding part are electrically connected as an integral structure and are arranged on the same layer;

[0036] Optionally, the driving circuit layer further includes a second conductive layer, wherein the second conductive layer is provided with a first electrode of a storage capacitor;

[0037] Optionally, the second plate of the storage capacitor can be reused as the gate of the driving transistor.

[0038] Optionally, the driving circuit layer is provided with a first power line, which includes a first sub-line and a second sub-line that are electrically connected; the pixel circuit also includes a first light-emitting control transistor, which is electrically connected to the second sub-line.

[0039] The second sub-wire is electrically connected to the shielding section;

[0040] Optionally, the shielding portion extends along the first direction, the first sub-line extends along the first direction, and the extension direction of the second sub-line intersects with the first direction; the first sub-line and the second sub-line are arranged in the same layer;

[0041] Optionally, the first light-emitting control transistor is connected between the first electrode and the second sub-line of the driving transistor, or the first light-emitting control transistor is connected between the second electrode and the second sub-line of the driving transistor;

[0042] The gate of the first light-emitting control transistor is electrically connected to the light-emitting control signal line;

[0043] Optionally, the driving circuit layer further includes a fourth conductive layer and a fifth conductive layer, with the shield disposed on the fourth conductive layer; the first sub-line and the second sub-line disposed on the fifth conductive layer; and the second sub-line electrically connected to the shield through a via.

[0044] Optionally, in three adjacent pixel circuits along the first direction, the shielding part in the middle pixel circuit is connected to the shielding part in the pixel circuit on one side; the distance between the first connecting part in the middle pixel circuit and the first connecting part in the pixel circuit on one side is less than the distance between the first connecting part in the middle pixel circuit and the first connecting part in the pixel circuit on the other side.

[0045] Optionally, two adjacent pixel circuits along the first direction are arranged in a mirror-symmetrical configuration.

[0046] Optionally, the light emission control signal line includes a main body extending in a first direction and an extension extending in a third direction, the first direction intersecting the third direction;

[0047] The orthogonal projection of the shielding portion onto the substrate at least partially covers the orthogonal projection of the extension portion onto the substrate.

[0048] Optionally, the array substrate further includes a shielding layer located between the substrate and the driving circuit layer;

[0049] There is a gap between the orthographic projection of the first connecting part on the substrate and the orthographic projection of the light-emitting control signal line on the substrate;

[0050] The orthographic projection of the shielding layer onto the substrate at least partially overlaps with the gap;

[0051] Optionally, at least a portion of the shielding layer is connected to a DC potential;

[0052] Optionally, the shielding layer is electrically connected to the first power line;

[0053] Optionally, the orthographic projection of the shielding layer onto the substrate overlaps at least partially with the active portion of the channel region of the driving transistor;

[0054] Optionally, the shielding layer is an electrostatic shielding layer and / or a light-shielding layer.

[0055] Optionally, the driving circuit layer further includes a first initialization signal line; the first initialization transistor is connected between the first initialization signal line and the first terminal of the driving transistor.

[0056] The first initialization signal line and the light emission control signal line extend in the first direction and are arranged along the second direction; the orthographic projection of the first initialization signal line on the substrate and the orthographic projection of the light emission control signal line on the substrate are separate, and the first direction and the second direction intersect.

[0057] Optionally, the shielding part is electrically connected to the first initialization signal line to form an integral structure and is disposed on the same layer; the shielding part is connected to one of the two opposite sides of the first initialization signal line along the second direction;

[0058] Optionally, the driving circuit layer further includes a first active layer, a third conductive layer, a second active layer, and a first conductive layer, wherein the active portion of the driving transistor is located in the second active layer, the gate of the driving transistor is located in the first conductive layer, and the first initialization signal line is located in the third conductive layer or on the side of the third conductive layer away from the substrate.

[0059] Optionally, the pixel circuit further includes a threshold compensation transistor connected between the gate and the second terminal of the driving transistor; or, the pixel circuit further includes a threshold compensation transistor connected between the gate and the second terminal of the driving transistor, with the active portion of the threshold compensation transistor located in the first active layer and the gate of the threshold compensation transistor located in the third conductive layer.

[0060] And / or, the pixel circuit further includes a third initialization transistor, which is electrically connected to the gate of the driving transistor, the active portion of the third initialization transistor is located in the first active layer, and the gate of the third initialization transistor is located in the third conductive layer.

[0061] Optionally, the second active layer comprises polysilicon, and the first active layer comprises metal oxide.

[0062] Optionally, the pixel circuit further includes a first light-emitting control transistor, which is connected between the first electrode of the driving transistor and the first power supply line; the gate of the first light-emitting control transistor is electrically connected to the light-emitting control signal line.

[0063] And / or, the pixel circuit further includes a second light-emitting control transistor, which is connected between the second terminal of the driving transistor and the first terminal of the light-emitting device; the gate of the second light-emitting control transistor is electrically connected to the light-emitting control signal line;

[0064] And / or, the pixel circuit also includes a data writing transistor connected between the data line and the first pole of the driving transistor;

[0065] And / or, the pixel circuitry also includes a storage capacitor connected between the first power line and the gate of the driving transistor.

[0066] Optionally, the pixel circuit further includes a first light-emitting control transistor, which is connected between the second terminal of the driving transistor and the first power supply line; the gate of the first light-emitting control transistor is electrically connected to the light-emitting control signal line.

[0067] And / or, the pixel circuit further includes a second light-emitting control transistor, which is connected between the first terminal of the driving transistor and the first terminal of the light-emitting device; the gate of the second light-emitting control transistor is electrically connected to the light-emitting control signal line;

[0068] And / or, the pixel circuit also includes a data writing transistor connected between the data line and the second terminal of the driving transistor;

[0069] And / or, the pixel circuitry also includes a storage capacitor connected between the first power line and the gate of the driving transistor.

[0070] Optionally, the first connecting portion includes a first part, a second part, and a third part connected in sequence. The first part is electrically connected to the first electrode of the driving transistor, and the third part is electrically connected to the first initialization transistor. The first part and the third part extend along a first direction, and the second part extends along a second direction. The first direction and the second direction intersect, and the second part overlaps with the orthographic projection of the light-emitting control signal line on the substrate. The orthographic projections of the first part and the third part on the substrate are respectively located on opposite sides of the orthographic projection of the light-emitting control signal line on the substrate along the second direction.

[0071] Optionally, there is a gap between the orthographic projection of the first part on the substrate and the orthographic projection of the light-emitting control signal line on the substrate; there is also a gap between the orthographic projection of the third part on the substrate and the orthographic projection of the light-emitting control signal line on the substrate.

[0072] Optionally, a multilayer organic insulating layer is provided between the film layer where the first connection part is located and the film layer where the light emission control signal line is located;

[0073] And / or, the organic insulating layer includes an organic planarization layer;

[0074] And / or, at least one organic insulating layer and at least one inorganic insulating layer are stacked along the thickness direction of the substrate between the film layer where the first connection part is located and the film layer where the light emission control signal line is located;

[0075] And / or, an organic insulating layer is provided between the film layer where the first connection part is located and the film layer where the light emission control signal line is located, and the thickness of the insulating layer between the film layer where the first connection part is located and the film layer where the light emission control signal line is located is greater than 2.6 micrometers;

[0076] Alternatively, an inorganic insulating layer may be provided between the film layer where the first connection part is located and the film layer where the light emission control signal line is located, and the thickness of the insulating layer between the film layer where the first connection part is located and the film layer where the light emission control signal line is located is greater than 3 micrometers.

[0077] According to another aspect of the present invention, a display panel is provided, the display panel including an array substrate according to any embodiment of the present invention.

[0078] The technical solution of this invention provides a shielding portion. The orthographic projection of the shielding portion on the substrate overlaps with the overlapping portion. The film layer where the shielding portion is located is between the film layer where the light-emitting control signal line is located and the film layer where the first connection portion is located. This allows the shielding portion to shield the signal transmitted on the light-emitting control signal line, eliminating or reducing the coupling degree (e.g., the degree of potential pull-down) of the parasitic capacitance generated between the light-emitting control signal line and the first connection portion to the first electrode potential of the driving transistor in the overlapping portion. The coupling difference of the parasitic capacitance to the first electrode potential of the driving transistor in the pixel circuits at different positions will also be reduced, making the influence of the parasitic capacitance on the driving current of the pixel circuits at different positions the same or similar. As a result, the display brightness of the light-emitting devices at different positions tends to be consistent under the same gray level, which is beneficial to improving the display uniformity of the display panel and improving the display effect of the display panel. By providing at least one organic insulating layer between the film layer containing the first connection portion and the film layer containing the light-emitting control signal line, the distance between the light-emitting control signal line and the first connection portion is increased, and the dielectric constant of the parasitic capacitance in the overlapping portion is reduced, thereby reducing the parasitic capacitance and thus reducing the impact of the parasitic capacitance on the brightness of the light-emitting device, which is beneficial to improving the display effect of the display panel. Furthermore, by increasing the thickness of the insulating layer between the film layer containing the first connection portion and the film layer containing the light-emitting control signal line to greater than 3 micrometers, the distance between the light-emitting control signal line and the first connection portion is increased, thereby reducing the parasitic capacitance and thus reducing the impact of the parasitic capacitance on the brightness of the light-emitting device, which is beneficial to improving the display effect of the display panel.

[0079] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0080] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0081] Figure 1 This is a schematic diagram of the circuit structure of a pixel circuit in related technologies;

[0082] Figure 2 It is a timing diagram of a pixel circuit in related technologies;

[0083] Figure 3 This is a schematic diagram of the layout structure of a pixel circuit in related technologies;

[0084] Figure 4 This is a schematic diagram of the layout structure of an array substrate provided in an embodiment of the present invention;

[0085] Figure 5 yes Figure 4 A sectional view along the a0-a0' direction;

[0086] Figure 6 This is a schematic diagram of the circuit structure of a pixel circuit provided in an embodiment of the present invention;

[0087] Figure 7 This is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present invention;

[0088] Figure 8 yes Figure 7 A sectional view along the a1-a2 direction;

[0089] Figure 9 This is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present invention;

[0090] Figure 10 yes Figure 4 A sectional view along the b1-b2 direction;

[0091] Figure 11 This is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present invention;

[0092] Figure 12 This is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present invention;

[0093] Figure 13 This is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present invention;

[0094] Figure 14 This is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present invention;

[0095] Figure 15 yes Figure 14 A sectional view along the f1-f2 direction;

[0096] Figure 16 This is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present invention;

[0097] Figure 17 yes Figure 7 Another sectional view along the a1-a2 direction;

[0098] Figure 18 This is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present invention;

[0099] Figure 19 yes Figure 18 A cross-sectional view along the k1-k2 direction;

[0100] Figure 20 This is a schematic diagram of the layout structure of the first conductive layer and the second active layer of the array substrate provided in an embodiment of the present invention;

[0101] Figure 21 This is a schematic diagram of the layout structure of the second conductive layer of the array substrate provided in an embodiment of the present invention;

[0102] Figure 22 This is a schematic diagram of the layout structure of the third conductive layer and the first active layer of the array substrate provided in an embodiment of the present invention;

[0103] Figure 23 This is a schematic diagram of the layout structure of the fourth conductive layer of an array substrate provided in an embodiment of the present invention;

[0104] Figure 24 This is a schematic diagram of the layout structure of the fourth conductive layer of another array substrate provided in an embodiment of the present invention;

[0105] Figure 25 This is a schematic diagram of the layout structure of the fifth conductive layer of an array substrate provided in an embodiment of the present invention;

[0106] Figure 26 This is a schematic diagram of the layout structure of the sixth conductive layer of the array substrate provided in an embodiment of the present invention;

[0107] Figure 27 This is a schematic diagram of the layout structure of the shielding layer of the array substrate provided in an embodiment of the present invention;

[0108] Figure 28 This is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present invention;

[0109] Figure 29 This is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present invention;

[0110] Figure 30 This is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present invention;

[0111] Figure 31 This is a schematic diagram of the circuit structure of another pixel circuit provided in an embodiment of the present invention;

[0112] Figure 32 This is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present invention;

[0113] Figure 33 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Detailed Implementation

[0114] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0115] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0116] Figure 1 This is a schematic diagram of the circuit structure of a pixel circuit in related technologies, such as... Figure 1 As shown, the pixel circuit includes a first transistor T1', a second transistor T2', a third transistor T3', a fourth transistor T4', a fifth transistor T5', a sixth transistor T6', a seventh transistor T7', an eighth transistor T8', and a first capacitor C1. Figure 2 This is a timing diagram of a pixel circuit in related technologies, such as... Figure 2As shown, the driving process of the pixel circuit includes an initialization phase t1, a threshold compensation and data writing phase t2, and a light emission phase t3. In the initialization phase t1, the second scan signal S2 on the second scan line Scan2 is at a low level, controlling the seventh transistor T7' and the eighth transistor T8' to turn on. The third scan signal S3 on the third scan line Scan3 is at a high level, controlling the fourth transistor T4' to turn on. The eighth transistor T8' transmits the first reset signal transmitted on the first reset signal line Vr1 to the source of the first transistor T1', resetting the source of the first transistor T1'. The seventh transistor T7' transmits the second reset signal transmitted on the second reset signal line Vr2 to the anode of the light-emitting diode D1, resetting the anode of the light-emitting diode D1. The fourth transistor T4' transmits the third reset signal transmitted on the third reset signal line Vr3 to the gate of the first transistor T1', resetting the gate of the first transistor T1'. During the threshold compensation and data writing stage t2, the first scan signal S1 on the first scan line Scan1 is at a low level, controlling the second transistor T2' to turn on. The fourth scan signal S4 on the fourth scan line Scan4 is at a high level, controlling the third transistor T3' to turn on. The data voltage transmitted on the data line Data is transmitted to the gate of the first transistor T1' through the second transistor T2', the first transistor T1', and the third transistor T3'. The third transistor T3' also captures the threshold voltage of the first transistor T1', realizing threshold compensation and data writing for the first transistor T1'. During the light emission stage t3, when the enable signal E2 on the enable line E1 is at a low level, it controls the fifth transistor T5' and the sixth transistor T6' to turn on. The fifth transistor T5', the first transistor T1', and the sixth transistor T6' form a driving current path, providing driving current for the light-emitting diode D1, causing the light-emitting diode D1 to emit light.

[0117] Figure 3 This is a schematic diagram of the layout structure of a pixel circuit in related technologies, such as... Figure 3As shown, the source of the first transistor T1' and the drain of the eighth transistor T8' are electrically connected through the connection L1. The enable line E1 overlaps with the connection L1, forming a parasitic capacitance C2. During the light-emitting phase of the pixel circuit driving process, the parasitic capacitance C2 affects the source potential of the first transistor T1', thus affecting the voltage difference between the gate and source of the first transistor T1', consequently affecting the driving current of the first transistor T1', and consequently affecting the light-emitting effect of the light-emitting diode D1, preventing the light-emitting diode D1 from emitting light at the preset brightness. Furthermore, the enable line E1 is connected to the fifth transistor T5' and multiple sixth transistors T6' in multiple pixel circuits located in a row, causing the voltage drop of the signal transmitted on the enable line E1 to vary at different locations. This results in potential differences at different locations on the enable line E1, leading to differences in the coupling potential of the parasitic capacitance C2 to the first transistor T1' in different pixel circuits. The magnitudes of the high and low levels of the enable signal on the enable line E1 connecting pixel circuits located in different rows are related to the distance between enable line E1 and the driver chip. For example, the greater the distance between enable line E1 and the driver chip, the smaller the absolute values ​​of the positive high level and negative low level on enable line E1. This can lead to differences in the potential of enable line E1 connecting pixel circuits in different rows, resulting in differences in the coupling potential of parasitic capacitance C2 to the first transistor T1' in pixel circuits in different rows. Therefore, the magnitudes of the coupling potential corresponding to pixel circuits at different positions will differ, meaning that the degree of influence of parasitic capacitance C2 on the source potential of the first transistor T1' in pixel circuits at different positions will be different. This leads to different degrees of influence of parasitic capacitance C2 on the driving current in pixel circuits at different positions, and consequently, different influences of parasitic capacitance C2 on the brightness of light-emitting diode D1 in pixel circuits at different positions, resulting in a reduction in the display uniformity of the display panel. Moreover, as... Figure 2 As shown, when the target display brightness is low, pulse width modulation (PWM) technology is used for dimming, that is, the brightness of LED D1 is controlled by controlling the duration of LED D1's emission. The more pulses, the greater the voltage fluctuation on the enable line E1, and the greater the difference in coupling between the parasitic capacitance C2 and the source potential of the first transistor T1' in the pixel circuits at different locations. This means that the influence of parasitic capacitance C2 on the drive current varies significantly in different pixel circuit locations, resulting in large differences in the brightness of LED D1 in different locations, thus affecting the display uniformity of the display panel.

[0118] To address the aforementioned technical problems, this embodiment provides an array substrate. Figure 4 This is a schematic diagram of the layout structure of an array substrate provided in an embodiment of the present invention. Figure 5 yes Figure 4 A sectional view along the a0-a0' direction. Figure 6 This is a schematic diagram of a pixel circuit structure provided in an embodiment of the present invention, for reference. Figures 4 to 6 The array substrate includes a substrate 110 and a driving circuit layer on the substrate 110. The driving circuit layer contains pixel circuitry and a light-emitting control signal line EM. The pixel circuitry includes a driving transistor T1, a first initialization transistor T2, and a first connection portion 101. The first connection portion 101 is connected between the first electrode of the driving transistor T1 and the first initialization transistor T2. The first connection portion 101 and the orthographic projection of the light-emitting control signal line EM onto the substrate have an overlap portion 102. (Reference) Figure 4 The driving circuit layer also includes a shielding portion 103, the orthographic projection of the shielding portion 103 on the substrate 110 overlaps with the overlapping portion 102; the film layer containing the shielding portion 103 is located between the film layer containing the light-emitting control signal line EM and the film layer containing the first connection portion 101; and / or, at least one organic insulating layer is provided between the film layer containing the first connection portion 101 and the film layer containing the light-emitting control signal line EM; and / or, the thickness D of the insulating layer between the film layer containing the first connection portion 101 and the film layer containing the light-emitting control signal line EM is greater than 3 micrometers.

[0119] The array substrate may include multiple pixel circuits, each of which can be connected to an OLED light-emitting device in the display panel. The pixel circuit can be a circuit composed of thin-film transistors and capacitors, etc., and is used to provide driving current to the OLED so that the OLED emits light in response to the driving current. The first electrode of the driving transistor T1 can be either the source or the drain of the driving transistor T1. Optionally, the film layer containing the light-emitting control signal line EM, the film layer containing the shielding portion 103, and the film layer containing the first connection portion 101 are sequentially stacked along the thickness direction Z of the substrate (e.g., along the direction away from the substrate). The shielding portion 103 may include conductive materials such as metal or indium tin oxide (ITO).

[0120] Specifically, in some embodiments, by providing a shielding portion 103, located between the film layer containing the light-emitting control signal line EM and the film layer containing the first connecting portion 101, and between the light-emitting control signal line EM and the first connecting portion 101, the shielding portion 103 shields the signal on the light-emitting control signal line EM, eliminating or reducing the coupling degree (e.g., the degree of potential pull-down) of the parasitic capacitance generated at the overlap portion 102 between the light-emitting control signal line EM and the first connecting portion 101 to the first electrode potential of the driving transistor T1. The difference in coupling between the parasitic capacitance and the first electrode potential of the driving transistor T1 in different pixel circuits is also reduced. Thus, the influence of the parasitic capacitance on the driving current in pixel circuits at different locations is made to be the same or similar, thereby making the display brightness of different light-emitting OLED devices tend to be consistent under the same grayscale, which is beneficial to improving the display uniformity of the display panel and enhancing the display effect of the display panel.

[0121] In some embodiments, the film layer containing the first connection portion 101 and the film layer containing the light-emitting control signal line EM are stacked along the thickness direction Z of the substrate. By providing at least one organic insulating layer between the film layer containing the first connection portion 101 and the film layer containing the light-emitting control signal line EM, and by providing at least one organic insulating layer between the first connection portion 101 and the light-emitting control signal line EM, the orthographic projection of the at least one organic insulating layer on the substrate overlaps with the overlapping portion 102. This results in a larger dielectric layer thickness between the first connection portion 101 and the light-emitting control signal line EM, and a larger direct distance (distance along the thickness direction Z of the substrate) between the first connection portion 101 and the light-emitting control signal line EM, thereby reducing the parasitic capacitance of the overlapping portion 102. Furthermore, the organic insulating layer can reduce the dielectric constant of the parasitic capacitance, thereby further reducing the parasitic capacitance of the overlapping portion 102.

[0122] In some embodiments, after at least one organic insulating layer is provided between the film layer where the first connection portion 101 is located and the film layer where the light emission control signal line EM is located, a shielding portion 103 can also be provided, thereby further reducing the influence of the parasitic capacitance of the overlapping portion 102 on the potential of the first electrode of the driving transistor T1, reducing the influence of the parasitic capacitance on the driving current of the driving transistor T1, and further reducing the influence of the parasitic capacitance on the light emission brightness of the light emission device OLED, which is beneficial to improving the display effect of the display panel.

[0123] In some embodiments, the thickness D (thickness along the thickness direction Z of the substrate 110, where the insulating layer between the film layer containing the first connection portion 101 and the film layer containing the light-emitting control signal line EM is located) is greater than 3 micrometers. The insulating layer between the film layer containing the first connection portion 101 and the film layer containing the light-emitting control signal line EM can be a single-layer insulating layer, where D is the thickness of a single-layer insulating layer; or, the insulating layer between the film layer containing the first connection portion 101 and the film layer containing the light-emitting control signal line EM can be a multi-layer insulating layer, where D is the sum of the thicknesses of the multi-layer insulating layers) is greater than 3 micrometers. The orthographic projection of the insulating layer between the film layers containing the light control signal line EM onto the substrate overlaps with the overlapping portion 102, resulting in a larger dielectric layer thickness between the first connection portion 101 and the light-emitting control signal line EM, greater than 3 micrometers. This is equivalent to a direct facing distance of greater than 3 micrometers between the first connection portion 101 and the light-emitting control signal line EM at their overlapping point. The larger direct facing distance (the distance along the thickness direction Z of the substrate) between the first connection portion 101 and the light-emitting control signal line EM can reduce the parasitic capacitance of the overlapping portion 102, for example, to less than 0.85 fF, where 1 pF = 1000 fF.

[0124] The technical solution of this embodiment, by setting a shielding part, has an overlapping portion where the orthographic projection of the shielding part on the substrate overlaps with the overlapping portion. The film layer where the shielding part is located is between the film layer where the light-emitting control signal line is located and the film layer where the first connection part is located. This allows the shielding part to shield the signal transmitted on the light-emitting control signal line, eliminating or reducing the coupling degree (potential pull-down degree) of the parasitic capacitance generated between the light-emitting control signal line and the first connection part to the first electrode potential of the driving transistor in the overlapping portion. The coupling difference of the parasitic capacitance to the first electrode potential of the driving transistor in the pixel circuits at different positions will also be reduced, so that the influence of the parasitic capacitance on the driving current of the pixel circuits at different positions is the same or similar. As a result, the display brightness of the light-emitting devices at different positions tends to be consistent under the same gray level, which is beneficial to improving the display uniformity of the display panel and improving the display effect of the display panel. By providing at least one organic insulating layer between the film layer containing the first connection portion and the film layer containing the light-emitting control signal line, the distance between the light-emitting control signal line and the first connection portion is increased, and the dielectric constant of the parasitic capacitance of the overlapping portion is reduced, thereby reducing the parasitic capacitance and thus reducing the impact of the parasitic capacitance on the brightness of the light-emitting device, which is beneficial to improving the display effect of the display panel. By increasing the thickness of the insulating layer between the film layer containing the first connection portion and the film layer containing the light-emitting control signal line to greater than 3 micrometers, the distance between the light-emitting control signal line and the first connection portion is increased, thereby reducing the parasitic capacitance and thus reducing the impact of the parasitic capacitance on the brightness of the light-emitting device, which is beneficial to improving the display effect of the display panel. Optionally, based on the above technical solution, the shielding portion 103 can be connected to a DC potential.

[0125] Specifically, if the DC potential is a fixed potential signal, then when the potential of the light-emitting control signal line EM changes, the potential of the shielding part 103 will not change. Therefore, the amount of potential change in the first connection part 101 affected by the potential change of the light-emitting control signal line EM is reduced or zero. This reduces the coupling degree of the light-emitting control signal line EM to the potential of the first electrode of the driving transistor T1, that is, reduces the coupling degree of the changing potential on the light-emitting control signal line EM to the potential of the first electrode of the driving transistor T1. The coupling difference of parasitic capacitance in the pixel circuits at different positions to the potential of the first electrode of the driving transistor will also be reduced, making the influence of parasitic capacitance in the pixel circuits at different positions on the driving current the same or similar. This makes the display brightness of the OLEDs at different positions tend to be consistent under the same gray level, which is beneficial to further improve the display uniformity of the display panel. The DC potential can be the DC potential connected to the pixel circuits, scanning circuits, etc. on the array substrate. This means that the shielding part can be electrically connected to the pixel circuits, scanning circuits, etc. on the array substrate and connected to the same DC potential, thus eliminating the need for an additional power supply. The DC potential can also be obtained by additionally setting up a power supply and signal line.

[0126] Optionally, the driving circuit layer is further provided with a first power line and / or an initialization signal line, and the shielding part 103 is electrically connected to the first power line or the initialization signal line.

[0127] Specifically, a first power supply voltage is transmitted on the first power supply line. This first power supply voltage can be either a high-level voltage or a low-level voltage. Therefore, when the shielding part 103 is connected to the first power supply line, the signal transmitted on the shielding part 103 is a DC signal, i.e., a signal with a fixed potential, thereby reducing the coupling degree between the light-emitting control signal line EM and the potential of the first electrode of the driving transistor T1. An initialization signal is transmitted on the initialization signal line. This initialization signal is a signal with a fixed potential. Therefore, when the shielding part 103 is connected to the initialization signal line, the signal transmitted on the shielding part 103 is a signal with a fixed potential, which also reduces the coupling degree between the light-emitting control signal line EM and the potential of the first electrode of the driving transistor T1. A DC signal line connected to the shielding part 103, such as the first power supply line or the initialization signal line, can be selected nearby to reduce wiring difficulty.

[0128] Based on the above technical solutions, the following will further explain the specific arrangement of at least one organic insulating layer between the film layer where the first connecting part 101 is located and the film layer where the light emission control signal line is located, but this is not intended to limit this application.

[0129] Optionally, the driving circuit layer includes a first conductive layer M1, a second conductive layer M2, a third conductive layer M3, a fourth conductive layer M4, and a fifth conductive layer M5 stacked together; optionally, the light emission control signal line EM is disposed on the first conductive layer M1.

[0130] Optionally, the first conductive layer M1, the second conductive layer M2, the third conductive layer M3, the fourth conductive layer M4, and the fifth conductive layer M5 are sequentially stacked in a direction away from the substrate. Optionally, the first conductive layer M1, the second conductive layer M2, the third conductive layer M3, the fourth conductive layer M4, and the fifth conductive layer M5 may include one or more of the following: a metal layer, an indium tin oxide (ITO) layer, etc.

[0131] Optionally, the first connection portion 101 is disposed on the fourth conductive layer M4 or on the side of the fourth conductive layer M4 away from the substrate 110. Optionally, when a shielding portion 103 is provided in the driving circuit layer, the first connection portion 101 is disposed on the fourth conductive layer M4 or on the side of the fourth conductive layer M4 away from the substrate 110. Optionally, when at least one organic insulating layer is provided between the film layer where the first connection portion 101 is located and the film layer where the light emission control signal line is located, the first connection portion 101 is disposed on the side of the fourth conductive layer M4 away from the substrate 110.

[0132] In some implementations... Figure 7 This is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present invention. Figure 8 yes Figure 7 A sectional view along the a1-a2 direction, optionally, refer to Figure 7 and Figure 8 Optionally, the first connecting portion 101 is disposed on the side of the fourth conductive layer M4 away from the substrate 110. This results in a larger distance between the first connecting portion 101 and the light-emitting control signal line EM, which helps reduce the parasitic capacitance of the overlapping portion 102 between the first connecting portion 101 and the light-emitting control signal line EM. Furthermore, disposing the first connecting portion 101 on the side of the fourth conductive layer M4 away from the substrate 110 facilitates the placement of an organic insulating layer. This organic insulating layer can be disposed between any two of the second conductive layer M2, the third conductive layer M3, the fourth conductive layer M4, and the fifth conductive layer M5. Alternatively, organic insulating layers can be disposed between the second conductive layer M2 and the third conductive layer M3, between the third conductive layer M3 and the fourth conductive layer M4, and between the fourth conductive layer M4 and the fifth conductive layer M5, thereby significantly reducing the parasitic capacitance of the overlapping portion 102 and thus minimizing the impact of the parasitic capacitance of the overlapping portion 102 on the display panel's display effect.

[0133] It should be noted that, Figure 7 and Figure 8 The diagram illustrates the case where the first connection portion 101 is located in the fifth conductive layer M5, but does not limit it. Figure 8 The illustration shows a case where an organic insulating layer (a first organic planarization layer PLN1, for example, located between the fourth conductive layer M4 and the fifth conductive layer M5) is provided, but it is not limited to this case.

[0134] Optionally, the pixel circuit also includes a data writing transistor T3, such as Figure 8 As shown, a first electrode T31 and a second electrode T32 of a data writing transistor T3 are disposed on the fourth conductive layer M4, and the gate T33 of the data writing transistor T3 is disposed on the first conductive layer M1. Specifically, the first electrode T31 of the data writing transistor T3 is the source of the data writing transistor T3, and the second electrode T32 of the data writing transistor T3 is the drain of the data writing transistor T3. Alternatively, the first electrode T31 of the data writing transistor T3 is the drain of the data writing transistor T3, and the second electrode T32 of the data writing transistor T3 is the source of the data writing transistor T3.

[0135] Optionally, refer to Figure 6 and Figure 8 The pixel circuit includes a storage capacitor Cst, and the first plate C01 of the storage capacitor Cst is disposed on the second conductive layer M2.

[0136] Optionally, the pixel circuit also includes a switching transistor connected to the gate of the driving transistor T1. The first gate G1 of the switching transistor is disposed on the third conductive layer M3. The fifth conductive layer M5 is provided with a first power supply line VDD, which is used to provide a first power supply voltage to the pixel circuit.

[0137] Specifically, the switching transistor can be an N-type transistor, which results in a smaller leakage current and thus a smaller potential change at the gate of the driving transistor T1. This helps maintain the gate potential of the driving transistor T1, leading to a more stable driving current and consequently a more stable luminous brightness in the OLED. The first gate of the switching transistor is, for example, a top gate, and it is disposed on the third conductive layer M3. The third conductive layer M3 can be fabricated from nano-cesium tungsten oxide (GATO) material.

[0138] For example, refer to Figure 6 The switching transistor includes a threshold compensation transistor T4 and / or a third initialization transistor T5. The threshold compensation transistor T4 and the third initialization transistor T5 are connected to the gate of the driving transistor T1. The threshold compensation transistor T4 and the third initialization transistor T5 can be N-type transistors.

[0139] Optionally, refer to Figure 6 The first end of the OLED is connected to the pixel circuit, and the second end of the OLED is connected to the second power line VSS. The first end of the OLED is the anode, and the second end is the cathode; or, the first end of the OLED is the cathode, and the second end is the anode.

[0140] Optionally, such as Figure 8As shown, the first terminal T51 and the second terminal T52 of the third initialization transistor T5 are located in the fourth conductive layer M4, and the first gate G1 (top gate) of the third initialization transistor T5 is located in the third conductive layer M3. The third initialization transistor T5 may have a single gate or a dual-gate structure. Optionally, the second gate G2 (bottom gate) of the third initialization transistor T5 is located in the second conductive layer M2, and the first gate G1 and the second gate G2 of the third initialization transistor T5 are connected together and connected to the same signal, or they are isolated and connected to different signals. The first terminal T51 of the third initialization transistor T5 is the source of the third initialization transistor T5, and the second terminal T52 of the third initialization transistor T5 is the drain of the third initialization transistor T5; or, the first terminal T51 of the third initialization transistor T5 is the drain of the third initialization transistor T5, and the second terminal T52 of the third initialization transistor T5 is the source of the third initialization transistor T5. The active part of the third initialization transistor T5 is located between the first gate G1 and the second gate G2 of the third initialization transistor T5.

[0141] In some implementations, optionally, such as Figure 7 and Figure 8 As shown, the first connecting portion 101 is disposed on the fifth conductive layer M5. An organic insulating layer is disposed between the fourth conductive layer M4 and the fifth conductive layer M5. Optionally, an inorganic insulating layer is disposed between any two adjacent pairs of the first conductive layer M1, the second conductive layer M2, the third conductive layer M3, and the fourth conductive layer M4. In this way, further increasing the distance between the first connecting portion 101 and the light-emitting control signal line EM helps to further reduce the parasitic capacitance of the overlapping portion 102 of the first connecting portion 101 and the light-emitting control signal line EM.

[0142] Based on the above technical solutions, optionally, refer to Figure 4 The overlapping portion 102 is located within the orthographic projection of the shielding portion 103 onto the substrate 110. This ensures that the orthographic projection of the shielding portion 103 onto the substrate 110 completely covers the overlapping portion 102, achieving a better shielding effect. Furthermore, the orthographic projection of the shielding portion 103 onto the substrate 110 can also cover the portion where the orthographic projections of the first connecting portion 101 and the light-emitting control signal line EM do not overlap. This can shield part of the lateral capacitance between the first connecting portion 101 and the light-emitting control signal line EM, which is beneficial for better shielding of parasitic capacitance and further reduces the influence of parasitic capacitance on the potential of the first electrode of the driving transistor T1.

[0143] As a further implementation of this embodiment, based on the above implementations, the specific configuration of the shielding part will be described below, but this is not intended to limit the scope of this application.

[0144] In some implementations... Figure 9 This is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present invention. Figure 10 yes Figure 4 A sectional view along the b1-b2 direction, optionally, refer to Figure 6 , Figure 9 and Figure 10 The pixel circuit also includes a second initialization transistor T6; the driving circuit layer is further provided with a first initialization signal line Vref1 and a second initialization signal line Vref2, the first initialization transistor T2 is connected between the first initialization signal line Vref1 and the first terminal of the driving transistor T1, and the second initialization transistor T6 is connected between the second initialization signal line Vref2 and the first terminal of the light-emitting device OLED; the shielding part 103 is electrically connected to the first initialization signal line Vref1 or the second initialization signal line Vref2.

[0145] in, Figure 4 and Figure 10 The connection between the shielding part 103 and the first initialization signal line Vref1 is illustrated. The shielding part 103 and the first initialization signal line Vref1 (extending along the first direction X) can be disposed in the same layer. Optionally, the shielding part 103 is disposed in the third conductive layer M3. Figure 9 The connection between the shielding part 103 and the second initialization signal line Vref2 is illustrated, as follows: Figure 9 The shielding portion 103 is connected to the second initialization signal line Vref2 via a via and a second connection portion in a conductive layer (e.g., a fourth conductive layer) located on the side of the shielding portion 103 away from the substrate. The shielding portion 103 and the second initialization signal line Vref2 (extending along the first direction) can be disposed in the same layer. Optionally, the shielding portion 103 is disposed in the third conductive layer M3. Multiple structures disposed in the same layer can be obtained by patterning the same film layer, thereby simplifying the process. The materials of the multiple structures disposed in the same layer can be the same, and they can be fabricated simultaneously using the same process. The shielding portions 103 of pixel circuits at different locations can be connected to different signal lines or the same signal line.

[0146] Specifically, the aforementioned initialization signal lines include a first initialization signal line Vref1 and a second initialization signal line Vref2. The signals transmitted on the first initialization signal line Vref1 and the second initialization signal line Vref2 are DC signals, i.e., signals with a fixed potential. Therefore, by electrically connecting the shielding part 103 to the first initialization signal line Vref1 and / or the second initialization signal line Vref2, the potential on the shielding part 103 can remain unchanged, thereby reducing the coupling degree of the light-emitting control signal line EM to the potential of the first electrode of the driving transistor T1. The coupling difference between the parasitic capacitance in the pixel circuits at different locations and the potential of the first electrode of the driving transistor will also be reduced, thus making the luminous brightness of different light-emitting OLED devices at the same grayscale similar, which is beneficial to improving the display uniformity of the display panel. The shielding part 103 is close to the first initialization signal line Vref1 and / or the second initialization signal line Vref2, thus facilitating wiring connections.

[0147] Optionally, the gates of the first initialization transistor T2 and the second initialization transistor T6 are electrically connected to the same scan signal line. This allows the first initialization transistor T2 and the second initialization transistor T6 to be turned on simultaneously, thereby initializing both the first electrode of the driving transistor T1 and the light-emitting device OLED at the same time, facilitating control; and also reducing the number of scan signal lines, simplifying wiring design.

[0148] Optionally, the driving circuit layer further includes a third conductive layer M3; the pixel circuit further includes a switching transistor; the switching transistor is connected to the gate of the driving transistor T1; the third conductive layer M3 is provided with the first gate of the switching transistor.

[0149] Optionally, the first initialization signal line Vref1 and / or the second initialization signal line Vref2 are disposed on the third conductive layer M3. Thus, when the first connection portion 101 is disposed on the fourth conductive layer M4 or on the side of the fourth conductive layer M4 away from the substrate 110 (e.g., on the fifth conductive layer M5), the shielding portion 103 can shield the first connection portion 101 from the light-emitting control signal line EM, thereby reducing the coupling degree of the light-emitting control signal line EM to the potential of the first electrode of the driving transistor T1. The coupling difference between the parasitic capacitance in the pixel circuit at different locations and the potential of the first electrode of the driving transistor will also be reduced, which helps to reduce the impact of parasitic capacitance on the display effect of the display panel.

[0150] Optionally, such as Figure 10As shown, the gate T11 of the driving transistor T1 and the light-emitting control signal line EM are disposed on the first conductive layer M1, and the first plate C01 of the storage capacitor Cst is disposed on the second conductive layer M2; the shielding part 103 is disposed on the third conductive layer M3; the first connection part 101 and the first electrode T21 of the first initialization transistor T2 (the electrode connected to the first electrode of the driving transistor T1) are disposed on the fourth conductive layer M4. This facilitates the connection of the shielding part 103 to the first initialization signal line Vref1 located on the third conductive layer M3, allowing the shielding part 103 to receive a DC signal, thus more effectively shielding the first connection part 101 and the light-emitting control signal line EM.

[0151] Optionally, such as Figure 10 As shown, the driving circuit layer further includes a first buffer layer B1, a first gate insulating layer GI1, a capacitor insulating layer CI, a second buffer layer B2, a second gate insulating layer, a first organic planarization layer PLN1, and a second organic planarization layer PLN2. The first buffer layer B1 is located between the substrate 110 and the first conductive layer M1. The first buffer layer B1 has an isolation function, preventing damage to the substrate 110 during subsequent film etching and improving the adhesion of the first conductive layer M1. The first gate insulating layer GI1 is located between the first buffer layer B1 and the first conductive layer M1, used to isolate the gate on the first conductive layer M1 (e.g., the first electrode T11 of the driving transistor T1). The capacitor insulating layer CI is located between the first conductive layer M1 and the second conductive layer M2, used to isolate the first electrode C01 of the storage capacitor Cst on the second conductive layer M2, preventing signals on the first conductive layer M1 from interfering with the potential on the first electrode C01. The second buffer layer B2 is located between the second conductive layer M2 and the third conductive layer M3, and the second buffer layer B2 has buffering, protective, and insulating functions. The second gate insulating layer is located between the third conductive layer M3 and the first active layer, and the interlayer insulating layer ILD is located between the third conductive layer M3 and the fourth conductive layer M4. The second gate insulating layer is used to isolate the gate on the third conductive layer M3 (such as the top gate of the aforementioned switching transistor) to achieve an insulating effect. The first organic planarization layer PLN1 is located on the side of the third conductive layer M3 away from the substrate 110, and the second planarization layer PLN2 is located on the side of the first organic planarization layer PLN1 away from the substrate 110.

[0152] Figure 11 This is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present invention. Optionally, as shown... Figure 11As shown, the orthographic projection of the first initialization signal line Vref1 on the substrate 110 is located between the orthographic projection of the second initialization signal line Vref2 on the substrate 110 and the orthographic projection of the shielding part 103 on the substrate 110; the orthographic projection of the first initialization signal line Vref1 on the substrate 110 is located between the orthographic projection of the second initialization signal line Vref2 on the substrate 110 and the orthographic projection of the light emission control signal line EM on the substrate 110.

[0153] Optionally, such as Figure 11 As shown, the extension directions (which can be the extension trend or the general extension direction) of the first initialization signal line Vref1, the second initialization signal line Vref2, and the light emission control signal line EM are the first direction X and arranged along the second direction Y. The first direction X and the second direction Y intersect. That is to say, the first initialization signal line Vref1 and the light emission control signal line EM do not overlap, and the second initialization signal line Vref2 and the light emission control signal line EM do not overlap.

[0154] Optionally, such as Figure 9 and Figure 11 As shown, the second initialization signal line Vref2 is electrically connected to the shielding part 103 via the second connecting part 104, and the second connecting part 104 is cross-insulated from the first initialization signal line Vref1. Optionally, as shown... Figure 11 As shown, the film layer containing the second connection portion 104 is located on the side of the film layer containing the first initialization signal line Vref1 that is away from the substrate 110. Optionally, as... Figure 11 As shown, the first connecting part 101 and the second connecting part 104 are arranged on the same layer. This facilitates the electrical connection of the second initialization signal line Vref2 to the shielding part 103, and prevents the first initialization signal line Vref1 and the second initialization signal line Vref2 from being connected together, allowing the first initialization signal line Vref1 and the second initialization signal line Vref2 to be set with different initialization signals as needed.

[0155] In some implementations... Figure 12 This is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present invention. Optionally, refer to... Figure 6 and Figure 12 The pixel circuit also includes a storage capacitor Cst, whose first electrode C01 is connected to the first power line VDD; the first electrode C01 and the shielding part 103 are electrically connected to each other as an integral structure and are arranged on the same layer.

[0156] Specifically, the first plate C01 of the storage capacitor Cst is connected to a DC signal, which in turn connects the shielding part 103 to a DC signal, i.e., a signal with a fixed potential. This ensures that the potential on the shielding part 103 does not change, thereby reducing the coupling degree between the light emission control signal line EM and the potential of the first electrode of the driving transistor T1. The coupling difference between the parasitic capacitance in the pixel circuit at different locations and the potential of the first electrode of the driving transistor will also be reduced, thus making the luminous brightness of different light-emitting devices OLEDs at the same gray level similar, which is beneficial to improving the display uniformity of the display panel.

[0157] Optionally, refer to Figure 12 The driving circuit layer also includes a second conductive layer M2, on which a first electrode C01 of a storage capacitor Cst is disposed. Optionally, the second electrode of the storage capacitor Cst is reused as the gate of the driving transistor T1. Thus, when the first connection portion 101 is disposed on the fourth conductive layer M4 or on the side of the fourth conductive layer M4 away from the substrate 110 (e.g., on the fifth conductive layer M5), the shielding portion 103 can shield the first connection portion 101 from the light emission control signal line EM, thereby reducing the coupling degree of the light emission control signal line EM to the potential of the first electrode of the driving transistor T1. The coupling difference of parasitic capacitance to the potential of the first electrode of the driving transistor in pixel circuits at different locations will also be reduced, which is beneficial to reducing the impact of parasitic capacitance on the display effect of the display panel.

[0158] In some implementations... Figure 13 This is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present invention. Optionally, refer to... Figure 13 The driving circuit layer includes a first power line VDD, which comprises a first sub-line L1 and a second sub-line L2 electrically connected. The pixel circuit also includes a first light-emitting control transistor T7, which is electrically connected to the second sub-line L2. The second sub-line L2 is electrically connected to a shielding portion 103. Optionally, the shielding portion 103 extends along a first direction, the first sub-line L1 extends along the first direction X, and the extension direction of the second sub-line L2 intersects the first direction X. The first sub-line L1 and the second sub-line L2 are disposed on the same layer. Optionally, the first light-emitting control transistor T7 is connected between the first electrode of the driving transistor T1 and the second sub-line L2, and the gate of the first light-emitting control transistor T7 is electrically connected to the light-emitting control signal line EM. This allows the shielding portion 103 to be connected to a DC potential, which helps to reduce the coupling degree of parasitic capacitance to the potential of the first electrode of the first transistor T1.

[0159] Optionally, the driving circuit layer further includes a fourth conductive layer M4 and a fifth conductive layer M5, with the first connecting portion 101 disposed on the fifth conductive layer M5 and the shielding portion 103 disposed on the fourth conductive layer M4. Thus, the film layer containing the shielding portion 103 is located between the film layer containing the first connecting portion 101 and the film layer containing the light-emitting control signal line EM, which can shield the signal transmitted on the light-emitting control signal line EM, thereby reducing the coupling degree of the light-emitting control signal line EM to the potential of the first electrode of the driving transistor T1. The coupling difference between the parasitic capacitance in the pixel circuits at different locations and the potential of the first electrode of the driving transistor will also be reduced, which helps to reduce the impact of parasitic capacitance on the display effect of the display panel.

[0160] Wherein, the first direction X can be the row direction of the array substrate, that is, the row direction of the pixel circuit array arrangement. The first sub-line L1 can be electrically connected to the first plate C01 of the storage capacitor Cst.

[0161] Optionally, such as Figure 13 As shown, the first sub-line L1 and the second sub-line L2 are disposed on the fifth conductive layer M5; the second sub-line L2 is electrically connected to the shielding part 103 through a via.

[0162] Specifically, by electrically connecting the second sub-line L2 of the first power line VDD to the shielding part 103, a DC signal is applied to the shielding part 103, thereby preventing a sudden change in potential on the shielding part 103. This helps to reduce the coupling degree of the light emission control signal line EM to the potential of the first electrode of the driving transistor T1. The coupling difference of parasitic capacitance in the pixel circuits at different locations to the potential of the first electrode of the driving transistor will also be reduced, thereby making the luminous brightness of different light-emitting devices OLEDs at the same gray level similar, which is beneficial to further improve the display uniformity of the display panel.

[0163] Optionally, such as Figure 13 As shown, in three adjacent pixel circuits along the first direction X, the shielding portion 103 in the middle pixel circuit is connected to the shielding portion 103 in the pixel circuit on one side; the distance (which can be the distance along the first direction X) between the first connecting portion 101 in the middle pixel circuit and the first connecting portion 101 in the pixel circuit on one side is less than the distance (which can be the distance along the first direction X) between the first connecting portion 101 in the middle pixel circuit and the first connecting portion 101 in the pixel circuit on the other side. In other words, the shielding portions 103 in two adjacent pixel circuits along the first direction X are connected, and the first connecting portions 101 in these two adjacent pixel circuits are arranged adjacent to each other. This means that one shielding portion 103 corresponds to two adjacent pixel circuits in the first direction. The first direction X can be a row direction. The second direction Y can be a column direction. Figure 13An exemplary 2x4 pixel circuit is drawn, wherein, among the four pixel circuits in the same row, the distance between the first connection portions 101 of the two left pixel circuits is smaller than the distance between the first connection portions 101 of the two middle pixel circuits. Optionally, two adjacent pixel circuits in the first direction are arranged in a mirror-symmetrical manner. This reduces the number of shielding portions 103, eliminating the need to fabricate a shielding portion 103 for each pixel circuit, simplifying and facilitating wiring.

[0164] Optionally, such as Figure 4 , Figure 9 and Figure 13 As shown, one shielding part 103 corresponds to one pixel circuit. Each pixel circuit is provided with its own shielding part 103, and the shielding parts 103 in two adjacent pixel circuits are arranged at intervals.

[0165] Based on the above technical solutions, the parasitic capacitance corresponding to the overlapping portion 102 of the first connection portion 101 on the substrate and the light emission control signal line EM on the substrate is an orthogonal capacitance. The portion where the first connection portion 101 and the light emission control signal line EM do not overlap may generate lateral capacitance. In order to further reduce the influence of parasitic capacitance on the potential of the first electrode of the driving transistor T1, the strategy for reducing lateral capacitance is described below, but it is not intended to limit this application.

[0166] Optionally, refer to Figure 4 The light-emitting control signal line EM includes a main body EM1 extending along a first direction X and an extension EM2 extending along a third direction H, wherein the first direction X intersects with the third direction H; the orthogonal projection of the shielding portion 103 onto the substrate 110 at least partially covers the orthogonal projection of the extension EM2 onto the substrate 110.

[0167] Specifically, if the third direction H is oblique relative to the first direction X, then the main body EM1 and the extension EM2 have an angle. The first connecting part 101 is close to the angle, which easily leads to lateral capacitance at the angle. By setting the orthogonal projection of the shielding part 103 on the substrate 110 to at least partially cover the orthogonal projection of the extension EM2 on the substrate 110, it can be ensured that the shielding part 103 covers the angle between the main body EM1 and the extension EM2. This allows the shielding part 103 to shield the signal on the light-emitting control signal line EM, thereby reducing the lateral capacitance at the angle. This further reduces the impact of parasitic capacitance on the potential of the first connecting part 101, thereby reducing the impact of parasitic capacitance on the potential of the first electrode of the driving transistor T1, and further reducing the impact of parasitic capacitance on the driving current generated by the driving transistor T1. This reduces the impact of parasitic capacitance on the luminous brightness of the OLED, which is beneficial to further improving the display effect of the display panel.

[0168] Figure 14This is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present invention. Figure 15 yes Figure 14 A sectional view along the f1-f2 direction, optionally, refer to Figure 14 and Figure 15 The array substrate also includes a shielding layer M0, which is located between the substrate 110 and the driving circuit layer; the orthographic projection of the first connection portion 101 on the substrate 110 and the orthographic projection of the light emission control signal line EM on the substrate 110 have a gap 120; the orthographic projection of the shielding layer M0 on the substrate 110 and the gap 120 at least partially overlap.

[0169] Specifically, the first connection portion 101 and the light-emitting control signal line EM will couple at the gap 120, generating a lateral capacitance. The orthographic projection of the shielding layer M0 onto the substrate 110 at least partially overlaps with the gap 120. Although the shielding layer M0 is not located between the film layer containing the first connection portion 101 and the film layer containing the light-emitting control signal line EM, the electric field lines formed by the lateral capacitance are multi-directional. Therefore, the shielding layer M0 can shield part of the electric field lines, thereby reducing the lateral capacitance. This is beneficial for further reducing the parasitic capacitance generated by the coupling between the light-emitting control signal line EM and the first connection portion 101, thereby reducing the influence of the parasitic capacitance on the potential of the first electrode of the driving transistor T1.

[0170] Optionally, at least a portion of the shielding layer M0 is connected to a DC potential.

[0171] Optionally, the shielding layer M0 is electrically connected to the first power supply line VDD. Therefore, when a DC signal is applied to the shielding layer M0, the potential on the shielding layer M0 will not fluctuate, allowing the shielding layer M0 to provide good shielding and helping to reduce the lateral capacitance between the first connection portion 101 and the light-emitting control signal line EM. Furthermore, by applying a stable voltage to the shielding layer M0, electrostatic shielding can be achieved. The shielding layer M0 may include a metal layer, etc.

[0172] Optionally, the orthographic projection of the shielding layer M0 onto the substrate 110 overlaps at least partially with the active portion of the channel region of the driving transistor T1. In this way, the shielding portion M0 can provide electrostatic shielding for the driving transistor T1, preventing static electricity from affecting the characteristics of the driving transistor T1, avoiding changes in the threshold voltage of the driving transistor T1, and thus ensuring the stability of the driving current of the driving transistor T1. Furthermore, it can prevent electrostatic charges from damaging the gate of the driving transistor T1, achieving the effect of protecting the driving transistor T1.

[0173] Optionally, the shielding layer M0 is an electrostatic shielding layer and / or a light-shielding layer.

[0174] Specifically, when the shielding layer M0 is an electrostatic shielding layer, it can prevent electrostatic discharge from affecting the characteristics of the driving transistor T1 and the display effect of the display panel. When the shielding layer M0 is a light-shielding layer, it can reduce the impact of ambient light on the characteristics of the driving transistor T1, thereby ensuring the stability of the driving current of the driving transistor T1 and improving the display effect of the display panel.

[0175] Based on the above technical solutions, optionally, refer to Figure 4 The driving circuit layer also includes a first initialization signal line Vref1. A first initialization transistor T2 is connected between the first initialization signal line Vref1 and the first terminal of the driving transistor T1. The extension direction (or extension trend) of the first initialization signal line Vref1 and the light-emitting control signal line EM is a first direction X, and they are arranged along a second direction Y. The orthographic projection of the first initialization signal line Vref1 on the substrate 110 and the orthographic projection of the light-emitting control signal line EM on the substrate 110 are separate, meaning they do not overlap. In other words, the original position of the first initialization signal line Vref1 remains unchanged; the first initialization signal line Vref1 is not moved to serve as the shielding part 103. When the shielding part 103 is connected to the first initialization signal line Vref1, the shielding part 103 and the first initialization signal line Vref1 can be a single unit or separate structures connected together; this is not limited here.

[0176] Optionally, refer to Figure 4 The shielding portion 103 is electrically connected to the first initialization signal line Vref1 as an integral structure and disposed on the same layer. The shielding portion 103 is connected to one of the two opposite sides of the first initialization signal line Vref1 along the second direction Y, where the first direction X and the second direction Y intersect, for example, they can be perpendicular. In other words, the shielding portion 103 can be the part of the first initialization signal line Vref1 extending to one of the two opposite sides along the second direction Y, that is, the part extending to the overlapping portion 102, thereby ensuring that the orthogonal projection of the shielding portion 103 on the substrate 110 overlaps with the overlapping portion 102, achieving a better shielding effect, thereby effectively reducing the influence of the parasitic capacitance corresponding to the overlapping portion 102 on the potential of the first electrode of the driving transistor T1.

[0177] Optionally, Figure 16 This is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present invention, with reference to... Figure 16 The driving circuit layer also includes a first active layer 130, a third conductive layer M3, a second active layer 140 and a first conductive layer M1. The active part of the driving transistor T1 is located in the second active layer 140, the gate of the driving transistor T1 is located in the first conductive layer M1, and the first initialization signal line Vref1 is located in the third conductive layer M3 or on the side of the third conductive layer M3 away from the substrate 110.

[0178] Optionally, the second active layer 140, the first conductive layer M1, the first active layer 130 and the third conductive layer M3 are stacked sequentially in a direction away from the substrate 110.

[0179] Optionally, the pixel circuit further includes a threshold compensation transistor T4, which is connected between the gate and the second electrode of the driving transistor T1. The active portion of the threshold compensation transistor T4 is located in the first active layer 130, and the gate of the threshold compensation transistor T4 is located in the third conductive layer M3. And / or, the pixel circuit further includes a third initialization transistor T5, which is electrically connected to the gate of the driving transistor T1. The active portion of the third initialization transistor T5 is located in the first active layer 130, and the gate of the third initialization transistor T5 is located in the third conductive layer M3. Optionally, the second active layer 140 includes polysilicon, and the first active layer 130 includes metal oxide.

[0180] Specifically, the second active layer 140 includes polysilicon, such as Psi, and the driving transistor T1 can be a P-type transistor, with its active portion located in the second active layer 140. The gate of the driving transistor T1 is located in the first conductive layer M1, facilitating overlap with the active portion located in the second active layer 140. The threshold compensation transistor T4 and the third initialization transistor T5 can be N-type transistors, with their gates located in the third conductive layer M3, facilitating overlap with the active portion located in the first active layer 130.

[0181] Optionally, the shielding layer M0, the first buffer layer B1, the second active layer 140, the first gate insulating layer GI1, the first conductive layer M1, the capacitor insulating layer CI, the second conductive layer M2, the second buffer layer B2, the first active layer 130, the second gate insulating layer GI2, the third conductive layer M3, the interlayer insulating layer ILD, the fourth conductive layer M4, the first organic planarization layer PLN1, the fifth conductive layer M5, the second organic planarization layer PLN2, and the sixth conductive layer M6 are sequentially stacked in a direction away from the substrate 110.

[0182] Optionally, the pixel circuit further includes a first light-emitting control transistor T7, which is connected between the first terminal of the driving transistor T1 and the first power supply line VDD; the gate of the first light-emitting control transistor T7 is electrically connected to the light-emitting control signal line EM; and / or, the pixel circuit further includes a second light-emitting control transistor T8, which is connected between the second terminal of the driving transistor T1 and the first terminal of the light-emitting device OLED; the gate of the second light-emitting control transistor T8 is electrically connected to the light-emitting control signal line EM; and / or, the pixel circuit further includes a data writing transistor T3, which is connected between the data line Data and the first terminal of the driving transistor T1; and / or, the pixel circuit further includes a storage capacitor Cst, which is connected between the first power supply line VDD and the gate of the driving transistor T1.

[0183] Optionally, refer to Figure 4 and Figure 6 The driving circuit layer also includes a first scan signal line SP1, which is electrically connected to the gate of the data writing transistor T3. The first scan signal line SP1 is used to control the data writing transistor T3 to be turned on during the data writing phase, so as to write the data voltage on the data line Data to the first terminal of the driving transistor T1. Optionally, the first scan signal line SP1 is disposed on the first conductive layer M1.

[0184] Optionally, refer to Figure 4 and Figure 6 The driving circuit layer also includes a second scan signal line SP2, which is electrically connected to the gates of the first initialization transistor T1 and the second initialization transistor T6. The second scan signal line SP2 is used to control the first initialization transistor T1 and the second initialization transistor T6 to be turned on during the first initialization phase, so as to initialize the first electrode of the driving transistor T1 and the light-emitting device OLED. Optionally, the second scan signal line SP2 is disposed on the first conductive layer M1.

[0185] Optionally, refer to Figure 4 and Figure 6 The driving circuit layer also includes a third scan signal line SN1, which is electrically connected to the gate of the third initialization transistor T5. The third scan signal line SN1 is used to control the third initialization transistor T5 to be turned on during the second initialization phase to initialize the gate of the driving transistor T1. Optionally, the third scan signal line SN1 is disposed on the second conductive layer M2 and the third conductive layer M3. Optionally, the third scan signal line SN1 on the second conductive layer M2 is connected to the third scan signal line SN1 on the third conductive layer M3, for example, at a position near the bezel area of ​​the display area of ​​the display panel.

[0186] Optionally, refer to Figure 4 and Figure 6 The driving circuit layer also includes a fourth scan signal line SN2, which is electrically connected to the gate of the threshold compensation transistor T4. The fourth scan signal line SN2 is used to control the threshold compensation transistor T4 to turn on during the threshold compensation stage, so that the threshold compensation transistor T4 performs threshold compensation on the driving transistor T1. Optionally, the fourth scan signal line SN2 is disposed on the third conductive layer M3 and the second conductive layer M2. Optionally, the fourth scan signal line SN2 on the second conductive layer M2 is connected to the fourth scan signal line SN2 on the third conductive layer M2, for example, at a position near the bezel area of ​​the display area of ​​the display panel.

[0187] Optionally, refer to Figure 9 The first connection portion 101 includes a first portion 1011 and a second portion 1012. The first portion 1011 is electrically connected to the first electrode of the driving transistor T1, and the second portion 1012 is electrically connected to the first initialization transistor T2. The first portion 1011 extends along a first direction X, and the second portion 1012 extends along a second direction Y. The first direction X and the second direction Y intersect, and the second portion 1012 overlaps with the orthographic projection of the light-emitting control signal line EM on the substrate 110 at a portion 102. The orthographic projection of the first portion 1011 on the substrate 110 is located on one of the two opposite sides of the orthographic projection of the light-emitting control signal line EM on the substrate 110 along the second direction Y. This arrangement ensures that when the shielding portion 103 shields the overlapping portion 102, it will not overlap with the via, thus avoiding the via and preventing damage or short circuit to the shielding portion 103. Optionally, there is a gap 120 between the orthographic projection of the first portion 1011 on the substrate 110 and the orthographic projection of the light-emitting control signal line EM on the substrate 110. By setting the orthographic projection of the shielding layer M0 on the substrate 110 to at least partially overlap with the gap 120, the shielding layer M0 can shield part of the electric field lines, thereby reducing the lateral capacitance.

[0188] Optionally, refer to Figure 14The first connecting portion 101 includes a first portion 1011, a second portion 1012, and a third portion 1013 connected in sequence. The first portion 1011 is electrically connected to the first electrode of the driving transistor T1, and the third portion 1013 is electrically connected to the first initialization transistor T2. The first portion 1011 and the third portion 1013 extend along a first direction X, and the second portion 1012 extends along a second direction Y. The first direction X and the second direction Y intersect, and the second portion 1012 overlaps with the orthographic projection of the light-emitting control signal line EM on the substrate 110. The orthographic projections of the first portion 1011 and the third portion 1013 on the substrate 110 are respectively located on opposite sides of the orthographic projection of the light-emitting control signal line EM on the substrate 110 along the second direction Y. Optionally, there is a gap 120 between the orthographic projection of the first portion 1011 on the substrate 110 and the orthographic projection of the light-emitting control signal line EM on the substrate 110. There is also a gap 120 between the orthographic projection of the third portion 1013 on the substrate 110 and the orthographic projection of the light-emitting control signal line EM on the substrate 110.

[0189] Specifically, for ease of routing design, the first connection portion 101 is configured as a first part 1011, a second part 1012, and a third part 1013 connected sequentially, for example, the first part 1011, the second part 1012, and the third part 1013 are an integral structure. This ensures that the shielding portion 103 does not overlap with vias when shielding the overlapping portion 102, thus avoiding vias and preventing damage or short circuits to the shielding portion 103. The first part 1011 and the third part 1013 have the same extension direction (or extension trend) as the light-emitting control signal line EM. There is a gap 120 between the orthographic projection of the first part 1011 on the substrate 110 and the orthographic projection of the light-emitting control signal line EM on the substrate 110, and there is also a gap 120 between the orthographic projection of the third part 1013 on the substrate 110 and the orthographic projection of the light-emitting control signal line EM on the substrate 110. Lateral capacitance is easily formed at the gap 120. In this embodiment, the shielding layer M0, by having its orthographic projection on the substrate 110 at least partially overlap with the gap 120, can shield some of the electric field lines, thereby reducing lateral capacitance. Furthermore, the shielding portion 103 can also cover the gap 120, meaning that the orthographic projection of the shielding portion 103 on the substrate 110 at least partially overlaps with the gap 120, further reducing lateral capacitance.

[0190] Figure 17 yes Figure 7 Another sectional view along the a1-a2 direction, optionally, refer to Figure 17Multiple organic insulating layers are provided between the film layer where the first connecting part 101 is located and the film layer where the light emission control signal line EM is located; and / or, the organic insulating layer includes an organic planarization layer; and / or, at least one organic insulating layer and at least one inorganic insulating layer are provided between the film layer where the first connecting part 101 is located and the film layer where the light emission control signal line EM is located, stacked along the thickness direction Z of the substrate 110.

[0191] Specifically, by providing multiple organic insulating layers between the film layer containing the first connection portion 101 and the film layer containing the light-emitting control signal line EM, the dielectric layer thickness between the first connection portion 101 and the light-emitting control signal line EM is increased, and the direct facing distance between the first connection portion 101 and the light-emitting control signal line EM is increased, which can reduce the parasitic capacitance of the overlapping portion 102. Furthermore, the multiple organic insulating layers can effectively reduce the dielectric constant of the parasitic capacitance, thereby further reducing the parasitic capacitance of the overlapping portion 102. Figure 15 As shown, the organic insulating layer includes a first organic planarization layer PLN1 and a third organic planarization layer PLN3. The first organic planarization layer PLN1 is located on the side of the third conductive layer M3 away from the substrate 110, and the third organic planarization layer PLN is located on the surface of the first organic planarization layer PLN1 away from the substrate 110. The second planarization layer PLN2 is located on the surface of the third organic planarization layer PLN away from the substrate 110. For example, the third organic planarization layer PLN3 can be an additional organic planarization layer. This allows the first organic planarization layer PLN1 and the third organic planarization layer PLN3 to isolate the first connection portion 101 and the light-emitting control signal line EM, which helps reduce the parasitic capacitance between the light-emitting control signal line EM and the first connection portion 101, further reducing the influence of the parasitic capacitance on the potential of the first electrode of the driving transistor T1.

[0192] By providing at least one organic insulating layer and at least one inorganic insulating layer (e.g., one or more of the following: capacitor insulating layer CI, second buffer layer B2, second gate insulating layer GI2, interlayer insulating layer ILD) stacked along the thickness direction Z of the substrate 110 between the film layer where the first connection portion 101 is located and the film layer where the light-emitting control signal line EM is located, the orthogonal projection of one or more organic insulating layers on the substrate 110 overlaps with the overlapping portion 102, and the orthogonal projection of one or more inorganic insulating layers on the substrate 110 overlaps with the overlapping portion 102, the distance between the first connection portion 101 and the light-emitting control signal line EM in the thickness direction Z of the display panel is further increased, which is beneficial to further reduce the parasitic capacitance of the light-emitting control signal line EM and the first connection portion 101. The inorganic insulating layer may include one or more of silicon oxide, silicon nitride, silicon oxynitride, etc. The organic insulating layer may include one or more of polyimide, polyacrylate, polyetherimide, polyethylene terephthalate, polyethylene naphthalate, etc.

[0193] Optionally, an organic insulating layer is provided between the film layer where the first connecting part 101 is located and the film layer where the light-emitting control signal line EM is located, or at least one organic insulating layer and at least one inorganic insulating layer. The thickness D of the insulating layer between the film layer where the first connecting part 101 is located and the film layer where the light-emitting control signal line EM is located is greater than 2.6 micrometers, which is equivalent to the direct distance between the first connecting part 101 and the light-emitting control signal line EM at their overlap being greater than 2.6 micrometers, so as to reduce the parasitic capacitance between the light-emitting control signal line EM and the first connecting part 101, for example, less than 0.85 fF.

[0194] Optionally, only an inorganic insulating layer is provided between the film layer where the first connecting part 101 is located and the film layer where the light-emitting control signal line EM is located. The thickness D of the insulating layer between the film layer where the first connecting part 101 is located and the film layer where the light-emitting control signal line EM is located (corresponding to the insulating layer at the overlapping part 102) is greater than 3 micrometers. This is equivalent to the direct distance between the first connecting part 101 and the light-emitting control signal line EM at the overlapping part being greater than 3 micrometers, so as to reduce the parasitic capacitance between the light-emitting control signal line EM and the first connecting part 101, for example, less than 0.85fF.

[0195] Based on the above technical solutions, Figure 18 This is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present invention. Figure 19 yes Figure 18 A cross-sectional view along the k1-k2 direction, see reference. Figure 18 and Figure 19 Optionally, the driving circuit layer further includes a sixth conductive layer M6, which is located on the side of the fifth conductive layer M5 away from the substrate 110. The sixth conductive layer M6 includes a first power supply line VDD and a data line Data. The first power supply line VDD provides a first power supply voltage to the pixel circuit, and the data line Data provides a data voltage to the pixel circuit, so that the pixel circuit generates a driving current according to the data voltage and the first power supply voltage.

[0196] like Figure 19 As shown, the fourth conductive layer M4 also includes the first electrode of the driving transistor T1 (e.g., the source electrode of the driving transistor T1).

[0197] Optionally, in some embodiments, after the routing of the first power line VDD and the data line Data is completed, if there is space in the sixth conductive layer M6 to place the first connection portion 101, the first connection portion 101 can be disposed in the sixth conductive layer M6. This further increases the distance between the first connection portion 101 and the light-emitting control signal line EM, further reducing the parasitic capacitance generated by the coupling between the first connection portion 101 and the light-emitting control signal line EM, thereby ensuring the stability of the first electrode potential of the driving transistor T1, and thus ensuring the stability of the driving current generated by the driving transistor T1. An organic insulating layer may be disposed between the fifth conductive layer M5 and the sixth conductive layer M6. The sixth conductive layer M6 may include one or more of the following: a metal layer, an indium tin oxide (ITO) layer, etc.

[0198] When the first connection portion 101 is disposed on the sixth conductive layer M6, the shielding portion 103 can be disposed on the third conductive layer M3, the fourth conductive layer M4, or the fifth conductive layer M5. When the shielding portion 103 is disposed on the fifth conductive layer M5, the shielding portion 103 can be connected to the first power line VDD on the fifth conductive layer M5, so that the shielding portion 103 is connected to a DC potential, which facilitates better shielding of the light-emitting control signal line EM and the first connection portion 101.

[0199] Based on the above technical solutions, the structure of each film layer of the array substrate will be described in detail below, but this is not intended to limit this application.

[0200] Figure 20 This is a schematic diagram of the layout structure of the first conductive layer and the second active layer of the array substrate provided in an embodiment of the present invention. Optionally, refer to... Figure 20 The first conductive layer M1 includes a light emission control signal line EM extending in the first direction X, a first scan signal line SP1, a second scan signal line SP2, a third initialization signal line Vref3, and the second plate CO2 of the storage capacitor Cst (i.e., the gate of the driving transistor T1).

[0201] Figure 21 This is a schematic diagram of the layout structure of the second conductive layer of the array substrate provided in an embodiment of the present invention. Optionally, refer to... Figure 21 The second conductive layer M2 includes a first electrode C01 of the storage capacitor Cst, a third scan signal line SN1 extending in a first direction X, and a fourth scan signal line SN2. The overlapping area between the third scan signal line SN1 on the second conductive layer M2 and the first active layer 130 can form the bottom gate of the third initialization transistor T5. The overlapping area between the fourth scan signal line SN2 on the second conductive layer M2 and the first active layer 130 can form the bottom gate of the threshold compensation transistor T4.

[0202] Figure 22 This is a schematic diagram of the layout structure of the third conductive layer and the first active layer of the array substrate provided in an embodiment of the present invention. Optionally, refer to... Figure 22 The third conductive layer M3 includes a first initialization signal line Vref1, a second initialization signal line Vref2, a third scan signal line SN1, and a fourth scan signal line SN2, all extending in a first direction X. The overlapping region between the third scan signal line SN1 on the third conductive layer M3 and the first active layer 130 can form the top gate of the third initialization transistor T5. The overlapping region between the fourth scan signal line SN2 on the third conductive layer M3 and the first active layer 130 can form the top gate of the threshold compensation transistor T4.

[0203] The third scan signal line SN1 on the second conductive layer M2 is electrically connected to the third scan signal line SN1 on the third conductive layer M3, for example, through a via. The fourth scan signal line SN2 on the second conductive layer M2 is also electrically connected to the fourth scan signal line SN2 on the third conductive layer M3, for example, through a via. This connects the bottom and top gates of the threshold compensation transistor T4 and the bottom and top gates of the third initialization transistor T5.

[0204] It should be noted that, Figure 22 The diagram shows the shield 103 on the third conductive layer M3 and electrically connected to the first initialization signal line Vref1, but is not limited thereto.

[0205] Figure 23 This is a schematic diagram of the layout structure of the fourth conductive layer of an array substrate provided in an embodiment of the present invention. Optionally, refer to... Figure 23 The fourth conductive layer M4 includes a first connection portion 101, a first initialization signal line Vref1 extending in the second direction Y, a second initialization signal line Vref2, and a third initialization signal line Vref3. For example... Figure 22As shown, the first initialization signal line Vref1 (extending along the first direction X) on the third conductive layer M3 and the first initialization signal line Vref1 (extending along the second direction Y) on the fourth conductive layer M4 form a mesh structure. This makes the first initialization signals transmitted by the first initialization signal line Vref1 to different positions (different pixel circuits) closer together, which is beneficial to improving the display uniformity of the display panel. Similarly, the second initialization signal line Vref2 (extending along the first direction X) on the third conductive layer M3 and the second initialization signal line Vref2 (extending along the second direction Y) on the fourth conductive layer M4 form a mesh structure, and the third initialization signal line Vref3 (extending along the first direction X) on the first conductive layer M1 and the third initialization signal line Vref3 (extending along the second direction Y) on the fourth conductive layer M4 form a mesh structure, which is beneficial to improving the display uniformity of the display panel. The first power line (extending along the first direction X) on the fifth conductive layer M5 and the first power line (extending along the second direction Y) on the sixth conductive layer M6 form a mesh structure.

[0206] Each signal line can extend in a straight line, a broken line, a curve, or other irregular shape (such as a tree-like shape) along its extension direction (general extension direction or extension trend).

[0207] Optionally, the shielding portion 103 can be electrically connected to the third initialization signal line Vref3 to access a DC potential. Among the first initialization signal lines Vref1, second initialization signal line Vref2, and third initialization signal line Vref3 extending along the first direction X, the orthographic projection of the third initialization signal line Vref3 on the substrate 110 is located on the side where the orthographic projection of the shielding portion 103 on the substrate 110 is far away from the orthographic projections of the first initialization signal lines Vref1 and Vref2 on the substrate 110. Compared to the third initialization signal line Vref3, the first initialization signal lines Vref1 and Vref2 are closer to the shielding portion 103. Therefore, connecting the shielding portion 103 to the first initialization signal line Vref1 or the second initialization signal line Vref2 makes wiring easier.

[0208] Figure 24 This is a schematic diagram of the layout structure of the fourth conductive layer of an array substrate provided in another embodiment of the present invention. Optionally, refer to... Figure 24 When the first connection portion 101 is disposed on the side of the fourth conductive layer M4 away from the substrate 110, the first connection portion 101 is not disposed on the fourth conductive layer M4.

[0209] Figure 25This is a schematic diagram of the layout structure of the fifth conductive layer of an array substrate provided in an embodiment of the present invention. Optionally, refer to... Figure 25 The fifth conductive layer M5 includes a first power line VDD extending in the first direction X, a first sub-line L1 corresponding to the main body, and a second sub-line L2 corresponding to the branch. Figure 25 The case of the first connection portion 101 in the fifth conductive layer M5 is shown, but it is not limited thereto.

[0210] Figure 26 This is a schematic diagram of the layout structure of the sixth conductive layer of the array substrate provided in an embodiment of the present invention. Optionally, refer to... Figure 26 The sixth conductive layer M6 includes a first power line VDD extending in the second direction Y and a data line Data extending in the second direction Y.

[0211] Optionally, such as Figure 26 As shown, the sixth conductive layer M6 also includes a data connection line Fa, which is used to connect the driver chip and the data line Data. By placing the data connection line Fa in the sixth conductive layer M6, the traces in the display panel bezel area (non-display area) can be reduced, which is beneficial for achieving a narrow bezel.

[0212] Figure 27 This is a schematic diagram of the layout structure of the shielding layer of the array substrate provided in an embodiment of the present invention. Optionally, refer to... Figure 27 The orthographic projection of the shielding layer M0 on the substrate 110 at least partially overlaps with the gap 120.

[0213] Figure 28 This is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present invention. Figure 28 The first connection portion 101 is shown when it is located in the fifth conductive layer M5. Figure 29 This is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present invention. Figure 29 This illustrates a situation where the first connection portion 101 is located in the fourth conductive layer M4, and the shielding portion 103 is electrically connected to the first plate C01 of the storage capacitor Cst. Figure 30 This is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present invention. Figure 30 This illustration shows a case where the first connection portion 101 is located in the fifth conductive layer M5, and the shielding portion 103 is located in the fourth conductive layer M4. Optionally, refer to... Figures 28 to 30 The orthographic projection of the first initialization signal line Vref1 onto the substrate 110 is separate from the orthographic projection of the light emission control signal line EM onto the substrate 110, i.e., they do not overlap.

[0214] Optionally, Figure 31This is a schematic diagram of a pixel circuit structure provided in another embodiment of the present invention. The pixel circuit further includes a first light-emitting control transistor T7, which is connected between the second terminal of the driving transistor T1 and the first power supply line VDD; the gate of the first light-emitting control transistor T7 is electrically connected to the light-emitting control signal line EM; and / or, the pixel circuit further includes a second light-emitting control transistor T8, which is connected between the first terminal of the driving transistor T1 and the first terminal of the light-emitting device OLED; the gate of the second light-emitting control transistor T8 is electrically connected to the light-emitting control signal line EM; and / or, the pixel circuit further includes a data writing transistor T3, which is connected between the data line Data and the second terminal of the driving transistor T1; and / or, the pixel circuit further includes a storage capacitor Cst, which is connected between the first power supply line VDD and the gate of the driving transistor T1. Optionally, the pixel circuit further includes a threshold compensation transistor T4, which is connected between the gate of the driving transistor T1 and the first terminal.

[0215] Figure 31 circuit structure and Figure 6 The difference in circuit structure lies in the different connection positions of the first initialization transistor T2, which is equivalent to... Figure 31 The first initialization transistor T2 is connected to the drain of the driving transistor T1. Figure 6 The first initialization transistor T2 is connected to the source of the driving transistor T1. Figure 31 circuit structure and Figure 6 The corresponding components of the circuit structure are the same or similar in structure and function, and will not be described in detail here. Figure 31 The first terminal of the driving transistor T1 is equivalent to the drain, and the second terminal of the driving transistor T1 is equivalent to the source. Figure 6 The first terminal of the driving transistor T1 is equivalent to the source, and the second terminal of the driving transistor T1 is equivalent to the drain.

[0216] Figure 32 This is a schematic diagram of the layout structure of another array substrate provided in an embodiment of the present invention. Figure 32 China's map structure and Figure 31 The circuit corresponds to that. Figure 6 The circuits in Figures 4 to 30 The layout structure corresponds to the film structure. (This is followed by a seemingly unrelated sentence: "will...") Figure 6 In the circuit layout and film structure, the first connection part 101 connected to the driving transistor T1 can be changed from being connected to the source of the driving transistor to being connected to the drain of the driving transistor. The positions and functions of the corresponding shielding part 103 and other components are the same or similar, and will not be described in detail here. Pixel circuit (e.g.) Figure 6 The circuits and Figure 31The circuit can use pulse width modulation (PWM) technology for dimming, and the light emission control signal can include multiple pulses in the light emission phase within a screen refresh cycle. Figure 6 The circuits and Figure 31 The timing waveforms and operating process of the circuit, and Figure 1 and Figure 2 Similar or identical examples will not be elaborated upon here.

[0217] Optionally, the first light-emitting control transistor T7 is connected between the second terminal of the driving transistor T1 and the second sub-line L2.

[0218] This embodiment also provides a display panel. Figure 33 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Figure 33 As shown, the display panel includes the array substrate provided in any of the above embodiments. The display panel can be any product or component with display functionality, such as a mobile phone, tablet computer, television, monitor, laptop computer, or digital photo frame. Since the display panel includes the array substrate provided in any embodiment of the present invention, it possesses the same beneficial effects as the array substrate provided in any embodiment of the present invention, which will not be elaborated further here.

[0219] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. An array substrate, characterized in that, include: A substrate and a driving circuit layer on the substrate, wherein a pixel circuit and a light emission control signal line are disposed in the driving circuit layer, the pixel circuit including a driving transistor, a first initialization transistor and a first connection portion, the first connection portion being connected between the first electrode of the driving transistor and the first initialization transistor; the first connection portion and the orthographic projection of the light emission control signal line on the substrate have an overlapping portion. The driving circuit layer is further provided with a shielding part, and the orthographic projection of the shielding part on the substrate overlaps with the overlapping part; the film layer where the shielding part is located is located between the film layer where the light emission control signal line is located and the film layer where the first connection part is located.

2. The array substrate according to claim 1, characterized in that, The shielding part is connected to a DC potential.

3. The array substrate according to claim 1, characterized in that, The driving circuit layer is further provided with a first power line and / or an initialization signal line, and the shielding part is electrically connected to the first power line or the initialization signal line.

4. The array substrate according to claim 1, characterized in that, The driving circuit layer includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer stacked together. The light emission control signal line is disposed on the first conductive layer; The pixel circuit also includes a storage capacitor, the first plate of which is disposed on the second conductive layer; The pixel circuit also includes a switching transistor, which is connected to the gate of the driving transistor, and the first gate of the switching transistor is disposed on the third conductive layer. The first connection portion is disposed on the fourth conductive layer or on the side of the fourth conductive layer away from the substrate; The fifth conductive layer is provided with a first power line, which is used to provide a first power supply voltage to the pixel circuit.

5. The array substrate according to claim 4, characterized in that, The first connection portion is disposed on the fifth conductive layer.

6. The array substrate according to claim 4, characterized in that, An organic insulating layer is disposed between the fourth conductive layer and the fifth conductive layer.

7. The array substrate according to claim 4, characterized in that, An inorganic insulating layer is disposed between any two adjacent layers of the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer.

8. The array substrate according to any one of claims 1-7, characterized in that, The overlapping portion is located within the orthographic projection of the shielding portion onto the substrate.

9. The array substrate according to any one of claims 1-7, characterized in that, The film layer containing the light-emitting control signal line, the film layer containing the shielding portion, and the film layer containing the first connecting portion are sequentially stacked in a direction away from the substrate.

10. The array substrate according to any one of claims 1-7, characterized in that, The pixel circuit further includes a second initialization transistor; the driving circuit layer is further provided with a first initialization signal line and a second initialization signal line, the first initialization transistor is connected between the first initialization signal line and the first terminal of the driving transistor, and the second initialization transistor is connected between the second initialization signal line and the first terminal of the light-emitting device. The shielding part is electrically connected to the first initialization signal line or the second initialization signal line.

11. The array substrate according to claim 10, characterized in that, The gates of the first initialization transistor and the second initialization transistor are electrically connected to the same scan signal line.

12. The array substrate according to claim 10, characterized in that, The driving circuit layer further includes a third conductive layer; the pixel circuit further includes a switching transistor. The switching transistor is connected to the gate of the driving transistor; the third conductive layer is provided with the first gate of the switching transistor.

13. The array substrate according to claim 12, characterized in that, The shielding portion is disposed on the third conductive layer.

14. The array substrate according to claim 12, characterized in that, The first initialization signal line and / or the second initialization signal line are disposed on the third conductive layer.

15. The array substrate according to claim 10, characterized in that, The orthographic projection of the first initialization signal line on the substrate is located between the orthographic projection of the second initialization signal line on the substrate and the orthographic projection of the shielding portion on the substrate; The orthographic projection of the first initialization signal line on the substrate is located between the orthographic projection of the second initialization signal line on the substrate and the orthographic projection of the light emission control signal line on the substrate.

16. The array substrate according to claim 10, characterized in that, The first initialization signal line, the second initialization signal line, and the light emission control signal line extend in a first direction and are arranged along a second direction, with the first direction and the second direction intersecting.

17. The array substrate according to claim 10, characterized in that, The second initialization signal line is electrically connected to the shielding part via the second connecting part, and the second connecting part is provided with cross insulation from the first initialization signal line.

18. The array substrate according to claim 17, characterized in that, The film layer containing the second connection portion is located on the side of the film layer containing the first initialization signal line that is away from the substrate.

19. The array substrate according to claim 17, characterized in that, The first connecting part and the second connecting part are arranged on the same layer.

20. The array substrate according to any one of claims 1-7, characterized in that, The pixel circuit also includes a storage capacitor, the first plate of which is connected to a first power line.

21. The array substrate according to claim 20, characterized in that, The first electrode plate and the shielding part are electrically connected as an integral structure and are arranged in the same layer.

22. The array substrate according to claim 20, characterized in that, The driving circuit layer further includes a second conductive layer, on which the first electrode of the storage capacitor is disposed.

23. The array substrate according to claim 20, characterized in that, The second plate of the storage capacitor is reused as the gate of the driving transistor.

24. The array substrate according to any one of claims 1-7, characterized in that, The driving circuit layer is provided with a first power line, which includes a first sub-line and a second sub-line that are electrically connected; the pixel circuit also includes a first light-emitting control transistor, which is electrically connected to the second sub-line.

25. The array substrate according to claim 24, characterized in that, The second sub-wire is electrically connected to the shield.

26. The array substrate according to claim 24, characterized in that, The shielding portion extends along a first direction, the first sub-line extends along the first direction, and the extension direction of the second sub-line intersects with the first direction; the first sub-line and the second sub-line are arranged in the same layer.

27. The array substrate according to claim 24, characterized in that, The first light-emitting control transistor is connected between the first electrode of the driving transistor and the second sub-line, or the first light-emitting control transistor is connected between the second electrode of the driving transistor and the second sub-line; The gate of the first light-emitting control transistor is electrically connected to the light-emitting control signal line.

28. The array substrate according to claim 24, characterized in that, The driving circuit layer further includes a fourth conductive layer and a fifth conductive layer, and the shielding part is disposed on the fourth conductive layer; the first sub-line and the second sub-line are disposed on the fifth conductive layer; the second sub-line is electrically connected to the shielding part through a via.

29. The array substrate according to claim 24, characterized in that, In the three adjacent pixel circuits along the first direction, the shielding portion in the middle pixel circuit is connected to the shielding portion in the pixel circuit on one side; the distance between the first connecting portion in the middle pixel circuit and the first connecting portion in the pixel circuit on one side is less than the distance between the first connecting portion in the middle pixel circuit and the first connecting portion in the pixel circuit on the other side.

30. The array substrate according to claim 29, characterized in that, The two adjacent pixel circuits along the first direction are set up in a mirror-symmetrical manner.

31. The array substrate according to claim 1, characterized in that, The light emission control signal line includes a main body extending in a first direction and an extension extending in a third direction, wherein the first direction intersects the third direction. The orthogonal projection of the shielding portion onto the substrate at least partially covers the orthogonal projection of the extension portion onto the substrate.

32. The array substrate according to claim 1, characterized in that, The array substrate further includes a shielding layer located between the substrate and the driving circuit layer.

33. The array substrate according to claim 32, characterized in that, There is a gap between the orthographic projection of the first connecting portion on the substrate and the orthographic projection of the light-emitting control signal line on the substrate; The orthographic projection of the shielding layer onto the substrate at least partially overlaps with the gap.

34. The array substrate according to claim 32, characterized in that, At least a portion of the shielding layer is connected to a DC potential.

35. The array substrate according to claim 32, characterized in that, The shielding layer is electrically connected to the first power line.

36. The array substrate according to claim 32, characterized in that, The orthographic projection of the shielding layer onto the substrate overlaps at least partially with the active portion of the channel region of the driving transistor.

37. The array substrate according to claim 32, characterized in that, The shielding layer is an electrostatic shielding layer and / or a light-shielding layer.

38. The array substrate according to any one of claims 1-7, characterized in that, The driving circuit layer also includes a first initialization signal line; the first initialization transistor is connected between the first initialization signal line and the first terminal of the driving transistor. The first initialization signal line and the light emission control signal line extend in a first direction and are arranged along a second direction; the orthographic projection of the first initialization signal line on the substrate and the orthographic projection of the light emission control signal line on the substrate are separate, and the first direction and the second direction intersect.

39. The array substrate according to claim 38, characterized in that, The shielding part is electrically connected to the first initialization signal line to form an integral structure and is disposed on the same layer; the shielding part is connected to one of the two opposite sides of the first initialization signal line along the second direction.

40. The array substrate according to claim 38, characterized in that, The shielding part is located on one side of the two opposite sides of the first initialization signal line along the second direction.

41. The array substrate according to claim 38, characterized in that, The driving circuit layer further includes a first active layer, a third conductive layer, a second active layer, and a first conductive layer. The active portion of the driving transistor is located in the second active layer, the gate of the driving transistor is located in the first conductive layer, and the first initialization signal line is located in the third conductive layer or on the side of the third conductive layer away from the substrate.

42. The array substrate according to claim 41, characterized in that, The pixel circuit further includes a threshold compensation transistor connected between the gate and the second electrode of the driving transistor; or, the pixel circuit further includes a threshold compensation transistor connected between the gate and the first electrode of the driving transistor, the active portion of the threshold compensation transistor being located in the first active layer, and the gate of the threshold compensation transistor being located in the third conductive layer. And / or, the pixel circuit further includes a third initialization transistor, the third initialization transistor being electrically connected to the gate of the driving transistor, the active portion of the third initialization transistor being located in the first active layer, and the gate of the third initialization transistor being located in the third conductive layer.

43. The array substrate according to claim 41, characterized in that, The second active layer comprises polysilicon, and the first active layer comprises metal oxide.

44. The array substrate according to claim 1, characterized in that, The pixel circuit further includes a first light-emitting control transistor, which is connected between the first electrode of the driving transistor and the first power supply line; the gate of the first light-emitting control transistor is electrically connected to the light-emitting control signal line. And / or, the pixel circuit further includes a second light-emitting control transistor, the second light-emitting control transistor being connected between the second terminal of the driving transistor and the first terminal of the light-emitting device; the gate of the second light-emitting control transistor is electrically connected to the light-emitting control signal line; And / or, the pixel circuit further includes a data writing transistor connected between the data line and the first pole of the driving transistor; And / or, the pixel circuit further includes a storage capacitor connected between the first power line and the gate of the driving transistor.

45. The array substrate according to claim 1, characterized in that, The pixel circuit further includes a first light-emitting control transistor, which is connected between the second terminal of the driving transistor and the first power supply line; the gate of the first light-emitting control transistor is electrically connected to the light-emitting control signal line. And / or, the pixel circuit further includes a second light-emitting control transistor, the second light-emitting control transistor being connected between the first electrode of the driving transistor and the first terminal of the light-emitting device; the gate of the second light-emitting control transistor is electrically connected to the light-emitting control signal line; And / or, the pixel circuit further includes a data writing transistor connected between the data line and the second terminal of the driving transistor; And / or, the pixel circuit further includes a storage capacitor connected between the first power line and the gate of the driving transistor.

46. ​​The array substrate according to claim 1 or 32, characterized in that, The first connection portion includes a first part, a second part, and a third part connected in sequence. The first part is electrically connected to the first electrode of the driving transistor, the third part is electrically connected to the first initialization transistor, and the second part overlaps with the orthographic projection of the light-emitting control signal line on the substrate. The orthographic projections of the first part and the third part on the substrate are respectively located on opposite sides of the orthographic projection of the light-emitting control signal line on the substrate along a second direction.

47. The array substrate according to claim 46, characterized in that, There is a gap between the orthographic projection of the first portion on the substrate and the orthographic projection of the light-emitting control signal line on the substrate; there is a gap between the orthographic projection of the third portion on the substrate and the orthographic projection of the light-emitting control signal line on the substrate.

48. The array substrate according to claim 46, characterized in that, The first part and the third part extend along a first direction, and the second part extends along a second direction, and the first direction and the second direction intersect.

49. The array substrate according to claim 1, characterized in that, The array substrate further includes a shielding layer, which is located between the substrate and the driving circuit layer; The first connecting portion includes a first part and a second part connected in sequence. The first part extends along a first direction, and the second part extends along a second direction. The first direction and the second direction intersect. The second part overlaps with the orthographic projection of the light-emitting control signal line on the substrate. The orthographic projection of the first part on the substrate is located on one of the two opposite sides of the orthographic projection of the light-emitting control signal line on the substrate along the second direction. There is a gap between the orthographic projection of the first part on the substrate and the orthographic projection of the light-emitting control signal line on the substrate. Alternatively, the first connection portion includes a first part, a second part, and a third part connected in sequence. The first part is electrically connected to the first electrode of the driving transistor, and the third part is electrically connected to the first initialization transistor. The first part and the third part extend along a first direction, and the second part extends along a second direction. The first direction and the second direction intersect, and the second part overlaps with the orthographic projection of the light-emitting control signal line on the substrate. The orthographic projections of the first part and the third part on the substrate are respectively located on opposite sides of the orthographic projection of the light-emitting control signal line on the substrate along the second direction. There is a gap between the orthographic projection of the first portion on the substrate and the orthographic projection of the light-emitting control signal line on the substrate; there is also a gap between the orthographic projection of the third portion on the substrate and the orthographic projection of the light-emitting control signal line on the substrate. The orthographic projection of the shielding layer onto the substrate at least partially overlaps with the gap.

50. The array substrate according to claim 1, characterized in that, At least one organic insulating layer is disposed between the film layer where the first connection part is located and the film layer where the light emission control signal line is located; And / or, the thickness of the insulating layer between the film layer where the first connection portion is located and the film layer where the light emission control signal line is located is greater than 3 micrometers.

51. The array substrate according to claim 50, characterized in that, A multilayer organic insulating layer is provided between the film layer where the first connecting part is located and the film layer where the light emission control signal line is located; And / or, the organic insulating layer includes an organic planarization layer; And / or, at least one organic insulating layer and at least one inorganic insulating layer are stacked along the thickness direction of the substrate between the film layer where the first connection portion is located and the film layer where the light emission control signal line is located; And / or, an organic insulating layer is provided between the film layer where the first connection part is located and the film layer where the light emission control signal line is located, and the thickness of the insulating layer between the film layer where the first connection part is located and the film layer where the light emission control signal line is located is greater than 2.6 micrometers; Alternatively, an inorganic insulating layer may be provided between the film layer where the first connecting part is located and the film layer where the light emission control signal line is located, and the thickness of the insulating layer between the film layer where the first connecting part is located and the film layer where the light emission control signal line is located is greater than 3 micrometers.

52. An array substrate, characterized in that, include: A substrate and a driving circuit layer on the substrate, wherein a pixel circuit and a light emission control signal line are disposed in the driving circuit layer, the pixel circuit including a driving transistor, a first initialization transistor and a first connection portion, the first connection portion being connected between the first electrode of the driving transistor and the first initialization transistor; the first connection portion and the orthographic projection of the light emission control signal line on the substrate have an overlapping portion. At least one organic insulating layer is disposed between the film layer where the first connection part is located and the film layer where the light emission control signal line is located; And / or, the thickness of the insulating layer between the film layer where the first connection portion is located and the film layer where the light emission control signal line is located is greater than 3 micrometers.

53. The array substrate according to claim 52, characterized in that, A multilayer organic insulating layer is provided between the film layer where the first connecting part is located and the film layer where the light emission control signal line is located; And / or, the organic insulating layer includes an organic planarization layer; And / or, at least one organic insulating layer and at least one inorganic insulating layer are stacked along the thickness direction of the substrate between the film layer where the first connection portion is located and the film layer where the light emission control signal line is located; And / or, an organic insulating layer is provided between the film layer where the first connection part is located and the film layer where the light emission control signal line is located, and the thickness of the insulating layer between the film layer where the first connection part is located and the film layer where the light emission control signal line is located is greater than 2.6 micrometers; Alternatively, an inorganic insulating layer may be provided between the film layer where the first connecting part is located and the film layer where the light emission control signal line is located, and the thickness of the insulating layer between the film layer where the first connecting part is located and the film layer where the light emission control signal line is located is greater than 3 micrometers.

54. A display panel, characterized in that, The display panel includes the array substrate as described in any one of claims 1-53.

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