Display panel and display device

Abstract

This disclosure provides a display panel and a display device. The display panel includes: a substrate (1) having a first surface (1a) and a second surface (1b) disposed opposite to each other, and a side surface (1c) connecting the first surface (1a) and the second surface (1b); the first surface (1a) includes a display area (AA) and an epitaxial area (NA); a plurality of first bonding electrodes (2) located in the epitaxial area (NA), each first bonding electrode (2) being electrically connected to a display signal line (16) located in the first surface (1a) and extending from the display area (AA) to the epitaxial area (NA). Connection; multiple drive signal lines (3) disposed on the second surface (1b) of the substrate (1), wherein at least one of the multiple drive signal lines (3) is a ground line (3a); multiple side traces (4), each of the side traces (4) electrically connecting one of the drive signal lines (3) to a first bonding electrode (2) via the side surface (1c); electrostatic discharge protection layer (5) electrically connected to the ground line (3a), and the orthographic projection of the electrostatic discharge protection layer (5) on the side surface (1c) at least partially overlaps with the orthographic projection of the side traces (4) on the side surface (1c).

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically to a display panel and a display device. Background Technology

[0002] Electrostatic discharge (ESD) breakdown occurs during the display panel manufacturing process when a large amount of static electricity accumulates and, during charge transfer, encounters a thin trace or a point where wires cross, a sudden surge of current causes damage to electronic components. ESD breakdown can negatively impact the yield rate of display panels during manufacturing or testing. Summary of the Invention

[0003] This disclosure provides a display panel and a display device.

[0004] In a first aspect, this disclosure provides a display panel, comprising:

[0005] The substrate has a first surface and a second surface disposed opposite to each other, and a side surface connecting the first surface and the second surface; the first surface includes a display area and an epitaxial area;

[0006] A plurality of first bonding electrodes are located in the epitaxial region, and each first bonding electrode is electrically connected to a display signal line located on the first surface and extending from the display area to the epitaxial region;

[0007] Multiple driving signal lines are disposed on the second surface of the substrate, wherein at least one of the multiple driving signal lines is a ground line;

[0008] Multiple side traces, each of which connects a drive signal line to a first bonding electrode via the side;

[0009] An electrostatic discharge (ESD) shielding layer is electrically connected to the ground wire, and the orthographic projection of the ESD shielding layer on the side surface at least partially overlaps with the orthographic projection of the side trace on the side surface.

[0010] In some embodiments, the electrostatic discharge protective layer includes at least:

[0011] A first electrostatic discharge (ESD) protection unit and a second ESD protection unit are connected. The first ESD protection unit is located on the second surface of the substrate, and its orthographic projection on the second surface covers the orthographic projection of the side trace located on the second surface. The first ESD protection unit is connected to the ground wire. The orthographic projection of the second ESD protection unit on the side surface covers the orthographic projection of the side trace on the side surface.

[0012] In some embodiments, the display panel further includes:

[0013] A first insulating layer is located on the side of the plurality of drive signal lines away from the substrate, and each of the side traces is connected to one of the drive signal lines through a first via on the first insulating layer.

[0014] The first electrostatic protection part is located on the side of the first insulating layer away from the substrate and is connected to the ground wire through a second via on the first insulating layer.

[0015] In some embodiments, the closest distance between the orthographic projection of the boundary of the first electrostatic protection portion away from the second electrostatic protection portion on the substrate and the orthographic projection of the second via on the substrate is between 15 and 25 μm.

[0016] In some embodiments, the display panel further includes:

[0017] The second insulating layer is disposed on the side of the electrostatic protection layer near the side trace.

[0018] The second insulating layer includes a first insulating portion and a second insulating portion. The first insulating portion is located between the first electrostatic protection portion and the side trace, and the second insulating portion is located between the second electrostatic protection portion and the side trace. The orthographic projection of the first insulating portion on the substrate does not overlap with the orthographic projection of the second via on the substrate.

[0019] In some embodiments, the first insulating portion has a first side extending away from the second insulating portion and along a first direction, the first direction intersecting the direction from the display area to the extension area;

[0020] The portion of the side trace located on the second surface has a first end close to the first side, and the interval between the orthographic projection of the first side on the substrate and the orthographic projection of the first end on the substrate is between 15 and 25 μm.

[0021] In some embodiments, the second insulating layer further includes:

[0022] The third insulating portion is located on the side of the side trace on the second surface away from the second surface, and the third insulating portion is connected to the second insulating portion;

[0023] The third insulating portion has a second side extending away from the side of the substrate and along a first direction, the first direction intersecting the direction from the display area to the epitaxial area; the portion of the side trace located on the first surface has a second end near the second side, and the interval between the second side and the second end is between 15 and 25 μm.

[0024] In some embodiments, the electrostatic protective layer further includes:

[0025] The third electrostatic discharge protection part is located on the first surface of the substrate and within the epitaxial region, and is connected to the second electrostatic discharge protection part.

[0026] In some embodiments, the first electrostatic discharge protection unit, the second electrostatic discharge protection unit, and the third electrostatic discharge protection unit are connected as an integral structure. The orthographic projection of the third electrostatic discharge protection unit on the first surface penetrates the first surface along a first direction, and the orthographic projection of the first electrostatic discharge protection unit on the second surface penetrates the second surface along the first direction. The first direction intersects with the direction from the display area to the extension area.

[0027] In some embodiments, the display panel further includes:

[0028] A third insulating layer, at least a portion of which is located on the side of the second electrostatic protection portion away from the substrate.

[0029] In some embodiments, the third insulating layer covers all of the second electrostatic protection portion and at least a portion of the first electrostatic protection portion.

[0030] In some embodiments, the display area includes a plurality of sub-pixels, each sub-pixel being provided with a light-emitting element, and each light-emitting element being connected to the display signal line.

[0031] In some embodiments, the display panel further includes:

[0032] A driving structure is connected to the plurality of driving signal lines and is used to provide driving signals to the plurality of driving signal lines.

[0033] In some embodiments, the display panel further includes:

[0034] A first insulating layer is located on the side of the plurality of drive signal lines away from the substrate, and the side traces are connected to the corresponding drive signal lines through a first via on the first insulating layer.

[0035] The driving structure is connected to the driving signal line through a third via on the first insulating layer.

[0036] In a second aspect, this disclosure provides a display device, comprising:

[0037] The display panel described in the first aspect;

[0038] An outer frame, at least a portion of which is located on the side of the substrate away from the display signal lines;

[0039] An adhesive is located on the side of the substrate away from the display signal lines and connects the display panel and the outer frame.

[0040] In some embodiments, the outer frame is a metal frame;

[0041] The adhesive is a conductive adhesive and is used to connect the metal frame and the electrostatic protection layer. Attached Figure Description

[0042] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings:

[0043] Figure 1 A schematic diagram of the side line technique provided in an example;

[0044] Figure 2 This is a plan view of the display structure layer and the first bonding electrode on the display panel provided in the embodiments of this disclosure;

[0045] Figure 3 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present disclosure;

[0046] Figure 4 A plan view of the drive signal lines provided in an embodiment of this disclosure;

[0047] Figure 5 This is a plan view of the vias and drive signal lines on the first insulating layer provided in the embodiments of this disclosure;

[0048] Figure 6 A plan view of the first electrostatic discharge protection section and the drive signal line provided in an embodiment of this disclosure;

[0049] Figure 7 A plan view of the third electrostatic protection section provided in an embodiment of this disclosure;

[0050] Figure 8 A plan view of the first insulating portion and side wiring provided in an embodiment of this disclosure;

[0051] Figure 9 This is a schematic diagram of the structure of another display panel provided in an embodiment of this disclosure;

[0052] Figure 10 This is a schematic diagram of the structure of another display panel provided in an embodiment of this disclosure;

[0053] Figure 11 This is a schematic diagram of the structure of another display panel provided in an embodiment of this disclosure;

[0054] Figure 12 Rear view of the display panel provided in an embodiment of this disclosure;

[0055] Figure 13 This is a front view of the display structure layer provided in an embodiment of the present disclosure;

[0056] Figure 14 This is a schematic diagram of the display structure layer provided in an embodiment of the present disclosure;

[0057] Figure 15 A schematic diagram of the pixel circuit provided in the embodiments of this disclosure;

[0058] Figure 16 A plan view of the encapsulation layer provided in an embodiment of this disclosure;

[0059] Figure 17 This is a schematic diagram of the structure of a display device provided in an embodiment of the present disclosure;

[0060] Figure 18 A plan view of the outer frame provided in an embodiment of this disclosure;

[0061] Figure 19 This is a schematic diagram of the structure of another display device provided in an embodiment of this disclosure. Detailed Implementation

[0062] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0063] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0064] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0065] Currently, micro LED (or Mini LED) display technology is developing rapidly. Its outstanding advantages—miniature size, low power consumption, high color saturation, fast response time, and long lifespan—have attracted widespread research investment. However, the immaturity of mass transfer technology has hindered the development of micro LED displays in terms of high resolution and large size. Existing mass transfer technology is best suited for televisions and large-screen displays. Seamless splicing display technology can compensate for the shortcomings of current mass transfer technology to achieve large-screen displays. Achieving truly seamless splicing in micro LED splicing displays requires the use of side wiring technology. Figure 1 A schematic diagram of the side line technique provided in one example, such as Figure 1 As shown, at least one display signal line extends from the display area AA on the front side to the epitaxial area NA and is connected to the first bonding electrode 2 in the epitaxial area NA. The first bonding electrode 2 is connected to the side trace 4. The side trace 4 passes through the side of the substrate 1 and goes around to the back side of the substrate 1, and is connected to the driving signal line 3 on the back side. The driving signal line is bonded to the 3 driving chip (IC bonding) and other connections.

[0066] like Figure 1 As shown, when forming a large-size splicing display screen using seamless splicing display technology, in order to prevent the side traces of the display panel from interfering with adjacent display panels, an insulating protective layer 4A needs to be set on the outer layer of the side traces 4 to separate adjacent display panels and avoid affecting the display effect of the splicing display screen. Because the seamless splicing requirements of the splicing display screen need to be met, the insulating protective layer 4A is generally set to be relatively thin (e.g., 2-10). μWithin a range of m, during the manufacturing or testing process of the display panel, when static electricity is generated at the edge of the display panel, the insulating protective layer 4A cannot achieve a good electrostatic protection effect. In this case, a conductive layer needs to be connected to the metal conductive layer on the side of the electrostatic protective layer 4A away from the substrate 1 using conductive adhesive or silver paste to release static electricity. However, since the conductive adhesive or silver paste is relatively thick, placing it on the side of the display panel will affect the width of the display panel bezel, which is not conducive to the narrow bezel design of the display panel, and thus affects the display effect of the splicing screen.

[0067] To address the aforementioned technical problems, this disclosure provides a display panel that effectively achieves electrostatic protection while meeting the display panel's requirement for a narrow bezel.

[0068] Figure 2 This is a plan view of the display structure layer and the first bonding electrode on the display panel provided in this embodiment of the disclosure. Figure 3 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present disclosure, such as... Figure 2 , 3 As shown, this disclosure provides a display panel including: a substrate 1, a plurality of first bonding electrodes 2, a display structure layer 10, a plurality of side traces 4, and an electrostatic discharge protection layer 5. The substrate 1 has a first surface 1a and a second surface 1b disposed opposite to each other, and a side surface 1c connecting the first and second surfaces. The first surface includes a display area AA and an epitaxial area NA, with the epitaxial area NA located on at least one side of the display area AA. The display area AA includes a plurality of sub-pixels. The display structure layer 10 includes a plurality of display signal lines 16 and a plurality of light-emitting elements. Each sub-pixel has a light-emitting element, such as a Micro LED or Mini LED. The plurality of display signal lines 16 provide driving signals to the plurality of light-emitting elements, and at least a portion of the display signal lines 16 extend from the display area to the epitaxial area NA.

[0069] Multiple first bonding electrodes 2 are located in the epitaxial region NA, and each first bonding electrode 2 is electrically connected to a display signal line 16 extending from the display region AA to the epitaxial region NA. In one example, the first bonding electrode 2 can be rectangular, with a length between 0.08 and 0.2 mm and a width between 0.06 and 0.1 mm.

[0070] Figure 4 A plan view of the drive signal lines provided in the embodiments of this disclosure, such as Figure 4As shown, multiple drive signal lines 3 are disposed on the second surface 1b, and at least one of the drive signal lines 3 is a ground line. Each side trace 4 electrically connects one drive signal line 3 to a first bonding electrode 2 via the side. The end of the drive signal line 3 away from the side trace can be connected to the drive structure 9 (e.g., a drive circuit board) to receive the drive signal provided by the drive structure 9. The side trace 4 transmits the drive signal on the drive signal line 3 to the display signal line 16, and then provides it to the light-emitting element.

[0071] The electrostatic discharge (ESD) shielding layer 5 is electrically connected to the ground wire 3a, and the orthographic projection of the ESD shielding layer 5 on side 1c covers the orthographic projection of the side trace 4 on side 1c. This embodiment does not limit the material of the ESD shielding layer; for example, the ESD shielding layer 5 can be a corrosion-resistant metallic material, such as Ti. The side trace 4 on the display panel can be fabricated using a sputtering process.

[0072] It should be noted that, Figure 3 A chamfer N is formed at the edge where the first surface 1a intersects with the side surface 1c of the substrate 1, and a chamfer is also formed at the edge where the second surface 1b intersects with the side surface 1c. The formation of these chamfer structures facilitates the fabrication of side traces 4 on the display panel via sputtering, preventing breakage of the side traces 4 at the edges, and also preventing breakage at the aforementioned edges when depositing other film layers on the substrate. The width of the chamfer N can be d0, for example, d0 is 1 / 30 to 1 / 5 of the substrate thickness, and its specific dimension is not limited. Optionally, the chamfer N can be a beveled surface or an outwardly convex arc surface structure.

[0073] In the structural schematic diagrams of other display panels provided in this disclosure embodiment, although the substrate is illustrated with a right-angled structure at the edge, its edge can also be fabricated in a similar manner. Figure 3 The chamfered structure shown is not limited in this disclosure.

[0074] Optionally, at least one of the multiple drive signal lines 3 is a ground line 3a, specifically meaning that part of the multiple drive signal lines 3 is a ground line 3a, and the other part is a non-ground line 3b. For example... Figure 4 As shown, the electrostatic shielding layer 5 and the non-ground line 3b are separated by an insulating layer to prevent different drive signal lines 3 from short-circuiting through the electrostatic shielding layer 5. In this embodiment, the drive signal lines are made of a metallic material, which can be a single layer of metal or a stack of multiple metals, such as Ti / Al / Ti, Mo / Cu / Mo, Ti / Cu / Ti, or Mo / Cu / ITO, etc. This embodiment does not limit the specific materials used. Multiple drive signal lines 3 can be formed by depositing a metal layer on the second surface 1b of the substrate 1 and performing a patterning process on the metal layer.

[0075] In the display panel provided in this embodiment, an electrostatic discharge (ESD) protection layer 5 is provided, and the orthographic projection of the ESD protection layer 5 on side 1c covers the orthographic projection of the side trace 4 on side 1c. Since the ESD protection layer 5 is also connected to the ground wire 3a, static electricity generated on the side of the display panel can be discharged through the ESD protection layer during ESD testing, thereby improving the ESD protection capability of the display panel. On the other hand, since the ESD protection layer 5 can play an anti-static role, there is no need to provide an excessively thick insulating layer or conductive adhesive structure on the side of the display panel, which is beneficial for achieving a narrow bezel in the display panel.

[0076] In some embodiments, the thickness of the electrostatic protective layer 5 can be set to 0.06–0.5 mm. μ The distance between m is such that while achieving a good anti-static effect, the impact of the electrostatic protection layer 5 on the width of the display panel bezel is reduced.

[0077] like Figure 3 As shown, in some embodiments, the electrostatic discharge (ESD) shielding layer 5 includes at least: a first ESD shielding portion 51 and a second ESD shielding portion 52 connected together. The first ESD shielding portion 51 is located on the second surface 1b of the substrate, and its orthographic projection on the second surface 1b covers the orthographic projection of the portion of the side trace 4 located on the second surface 1b on the second surface 1b. The first ESD shielding portion 51 is connected to the ground line 3a. The second ESD shielding portion 52 is opposite to the side surface 1c of the substrate 1, and its orthographic projection on the side surface 1c at least partially overlaps with the orthographic projection of the side trace 4 on the side surface 1c. Optionally, in one example, the orthographic projection of the second ESD shielding portion 52 on the side surface 1c may cover the orthographic projection of the side trace 4 on the side surface 1c; in another example, the orthographic projection of the second ESD shielding portion 52 on the side surface 1c may cover the entire side surface 1c.

[0078] like Figure 3 As shown, in some embodiments, the display panel further includes a first insulating layer 6, on which a plurality of vias are provided. Figure 5 This is a plan view of the vias and drive signal lines on the first insulating layer provided in the embodiments of this disclosure, such as... Figure 3 and Figure 5 As shown, the first insulating layer 6 is located on the side of the multiple drive signal lines 3 away from the substrate 1. The first insulating layer 6 can cover a portion of the second surface 1b or the entire area of ​​the second surface 1b. Multiple first vias 61 are provided on the first insulating layer 6, and each side trace 4 is connected to a drive signal line 3 through a first via 61 on the first insulating layer 6. The first electrostatic discharge protection part 51 is located on the side of the first insulating layer 6 away from the substrate 1 and is connected to the ground line 3a through a second via 62 on the first insulating layer 6.

[0079] It should be noted that the embodiment disclosed herein is illustrated by taking the side trace directly connecting to the drive signal line 3 through the first via 61 as an example. In other embodiments, an adapter electrode may also be provided, with a portion of the adapter electrode located in the first via 61, and the side trace 4 and the drive signal line 3 are connected through the adapter electrode.

[0080] In addition, a third via 63 is provided in the first insulating layer 6 corresponding to the position of each drive signal line. The third via 63 is used to connect the drive structure to each drive signal line. The drive structure will be described below, and will not be repeated here.

[0081] The material of the first insulating layer can be any one of silicon nitride, silicon oxide, and silicon oxynitride, and each via can be fabricated by photolithography.

[0082] In some embodiments, such as Figure 3 As shown, the electrostatic protection layer 5 may further include a third electrostatic protection section 53, which is connected to the second electrostatic protection section 52. The third electrostatic protection section 53 is located on the first surface 1a of the substrate 1 and within the epitaxial region NA. That is, the third electrostatic protection section 53 does not extend to the display area AA. Therefore, the arrangement of the third electrostatic protection section 53 will not affect the display function of the display panel.

[0083] In some embodiments, the first electrostatic discharge protection part 51, the second electrostatic discharge protection part 52, and the third electrostatic discharge protection part 53 are connected as a single structure. Figure 6 This is a plan view of the first electrostatic discharge protection section and the drive signal line provided in an embodiment of this disclosure. Figure 7 A plan view of the third electrostatic protection section provided in an embodiment of this disclosure. Figure 6 As shown, the orthographic projection of the third electrostatic protection part 53 onto the first surface 1a penetrates the first surface 1a along the first direction; as Figure 7 As shown, the orthographic projection of the first electrostatic discharge (ESD) protection layer 51 onto the second surface 1b extends through the second surface 1b along a first direction. This first direction intersects the direction from the display area AA to the epitaxial area NA; for example, the first direction is perpendicular to the direction from the display area AA to the epitaxial area NA. In this case, regardless of where static electricity is generated on the side trace 4, the ESD protection layer 5 can discharge the static electricity, preventing damage to the internal components and / or circuits of the display panel and improving the ESD protection capability of the display panel.

[0084] In some embodiments, such as Figure 6As shown, the orthographic projection of the first electrostatic discharge (ESD) protection portion 51 on the substrate 1 completely covers the orthographic projection of the second via 62 on the substrate 1. Optionally, the closest distance d1 between the orthographic projection of the boundary of the first ESD protection portion 51 away from the second ESD protection portion 52 on the substrate 1 and the orthographic projection of the second via 62 on the substrate 1 is between 15 μm and 25 μm to ensure the reliable connection between the first ESD protection portion 51 and the second via 62. For example, d1 can be 15 μm, 18 μm, 20 μm, 22 μm, or 25 μm.

[0085] In some embodiments, such as Figure 3 As shown, the display panel also includes a second insulating layer 7, which is disposed on the side of the electrostatic protection layer 5 near the side trace 4.

[0086] Specifically, the second insulating layer 7 includes a first insulating portion 71 and a second insulating portion 72. The first insulating portion 71 is located between the first electrostatic protection portion 51 and the side trace 4, and the second insulating portion 72 is located between the second electrostatic protection portion 52 and the side trace 4. The orthographic projection of the first insulating portion 71 on the substrate 1 does not overlap with the orthographic projection of the second via 62 on the substrate 1, that is, the boundary of the first insulating portion 71 does not extend to the second via 62, and it will not affect the connection between the second via 62 and the first electrostatic protection portion 51.

[0087] Figure 8 A plan view of the first insulating portion and side traces provided in an embodiment of this disclosure, in some embodiments, such as Figure 3 and Figure 8 As shown, the first insulating portion 71 has a first side 71a extending away from the second insulating portion 72 and along a first direction, which intersects the direction from the display area AA to the epitaxial area NA. The portion of the side trace 4 located on the second surface 1b has a first end 4a close to the first side. The interval d2 between the orthographic projection of the first side 71a on the substrate 1 and the orthographic projection of the first end 4a on the substrate 1 is between 15μm and 25μm, to ensure that the first insulating portion 71 completely covers the portion of the side trace 4 located on the second surface 1b and does not affect the connection of the first electrostatic discharge protection portion 51 to the ground line 3a through the second via 62. For example, d2 can be 15μm, 18μm, 20μm, 22μm, or 25μm.

[0088] In some embodiments, such as Figure 3 As shown, the second insulating layer 7 also includes a third insulating portion 73, which is connected to the second insulating portion 72. The third insulating portion 73 is disposed on the side of the side trace 4 located on the first surface 1a of the substrate 1 away from the substrate 1, and the orthographic projection of the third insulating portion 73 on the substrate 1 covers the orthographic projection of the side trace 4 located on the first surface 1a of the substrate 1 on the substrate 1.

[0089] The third insulating portion 73 has a second side that is far from the second insulating portion 72 and extends along the first direction. The portion of the side trace 4 located on the first surface 1a has a second end near the second side. The interval d3 between the orthographic projection of the second side on the substrate 1 and the orthographic projection of the second end on the substrate 1 is between 15 μm and 25 μm.

[0090] The second insulating part 72, the first insulating part 71 and the third insulating part 73 can be an integral structure that can completely cover the side wiring 4.

[0091] Figure 9 This is a schematic diagram of the structure of another display panel provided in an embodiment of this disclosure, such as... Figure 9 As shown, in some embodiments, the display panel further includes a third insulating layer 8, at least a portion of which is located on the side 1c of the second electrostatic protection portion 52 away from the substrate 1.

[0092] The orthographic projection of the third insulating layer 8 on the side 1c of the substrate covers the orthographic projection of the second electrostatic protection part 52 on the side 1c. In this way, the third insulating layer 8 can at least protect the second electrostatic protection part 52. Furthermore, when multiple display panels are spliced ​​together to form a large-size display screen, the third insulating layer 8 can prevent the static electricity generated on the display panel from affecting the adjacent display panel.

[0093] In one example, such as Figure 9 As shown, the third insulating layer 8 may specifically include a fourth insulating portion 81, a fifth insulating portion 82, and a sixth insulating portion 83. The fourth insulating portion 81 is located on the side of the first electrostatic discharge protection portion 51 away from the substrate, the fifth insulating portion 82 is located on the side of the second electrostatic discharge protection portion 52 away from the substrate 1, and the sixth insulating portion 83 is located on the side of the third electrostatic discharge protection portion 53 away from the substrate 1. In one example, the orthographic projection of the fourth insulating portion 81 on the second surface 1b overlaps the orthographic projection of the first electrostatic discharge protection portion 51 on the second surface 1b, the orthographic projection of the fifth insulating portion 82 on the side surface 1c overlaps the orthographic projection of the second electrostatic discharge protection portion 52 on the side surface 1c, and the orthographic projection of the sixth insulating portion 83 on the substrate 1 overlaps the orthographic projections of the third insulating portion 73 and the third electrostatic discharge protection portion 53 on the substrate 1.

[0094] Figure 10 This is a schematic diagram of the structure of another display panel provided in an embodiment of this disclosure, such as... Figure 10As shown, the fourth insulating portion 81 in the third insulating layer 8 is located on the side of the first electrostatic discharge protection portion 51 away from the second surface of the substrate, and the orthographic projection of the first electrostatic discharge protection portion 51 on the second surface 1b exceeds the orthographic projection of the fourth insulating portion 81 on the second surface 1b. For example, a portion of the first electrostatic discharge protection portion 51 away from the edge of the display panel is exposed by the fourth insulating portion 81, wherein the width d4 of the portion of the first electrostatic discharge protection portion 51 exposed by the fourth insulating portion 81 in the second direction can be between 0.5mm and 1.5mm, for example, 0.5mm, 1mm, or 1.5mm. Other structures of the display panel are the same as described above. Figure 9 The same applies here, so it will not be repeated. The second direction is the direction from the display area AA to the extension area NA.

[0095] In addition, the materials of the second insulating layer 7 and the third insulating layer 8 in the embodiments of this disclosure can be inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride, or they can be epoxy resin materials. This disclosure does not limit them in this regard.

[0096] Figure 11 This is a schematic diagram of another display panel provided in an embodiment of the present disclosure. In some embodiments, the display panel further includes a driving structure 9, which is connected to multiple driving signal lines 3 and is used to provide driving signals to the multiple driving signal lines 3. Here, Figure 11 The structure on the display panel, excluding the driving structure 9, can be the same as described above. Figure 9 Same as above.

[0097] As described above, a third via 63 is also provided on the first insulating layer 6 (see...). Figure 5 and Figure 11 As shown, the driving structure 9 is connected to the driving signal line 3 through the third via 63 of the first insulating layer 6. The first via 61 is located near the edge of the display panel, the third via 63 is located near the center of the display panel, and the second via 62 is located between the third via 63 and the second via 62. The driving structure 9 is connected to each driving signal line 3 through the third via 63.

[0098] Figure 12 A rear view of the display panel provided in an embodiment of this disclosure, such as... Figure 11 and Figure 12 As shown, the driving structure 9 may specifically include a driving circuit board 91 and a flexible circuit board 92, wherein the driving circuit board 91 is connected to the flexible circuit board 92, the flexible circuit board 92 is connected to the driving signal line 3 through the third via 63, and the driving circuit board 92 provides driving signals to the driving signal line 3 through the flexible circuit board 92.

[0099] In some embodiments, when connecting the flexible circuit board 92 to the drive signal line 3, conductive adhesive 93 can be applied to the position of the third via 63. Then, the flexible circuit board 92 is pressed with the substrate 1, so that the bonding electrode on the flexible circuit board 92 is connected to the drive signal line 3 through the conductive adhesive 93 in the third via 63. In addition, the conductive adhesive 93 remaining in the third via 63 can also play a role in fixing the flexible circuit board 92.

[0100] Figure 13 This is a front view of the display structure layer provided in an embodiment of the present disclosure. Figure 14 This is a schematic diagram of the display structure layer provided in an embodiment of the present disclosure, such as... Figure 13 and Figure 14 As shown, the display structure layer includes a light-emitting element 11 located in each sub-pixel, and also includes pixel circuitry connected to the light-emitting element 11. The light-emitting element 11 can be a miniature light-emitting diode, and its emission color can be blue, red, or green. In one example, multiple light-emitting elements 11 can form multiple repeating units, each repeating unit including a red light-emitting element R, a green light-emitting element G, and a blue light-emitting element B.

[0101] Figure 15 This is a schematic diagram of the pixel circuit provided in the embodiments of this disclosure, such as... Figure 15As shown, the pixel circuit may specifically include: a first reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, a switching transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a second reset transistor T7, and a first storage capacitor C1; wherein, the first terminal of the first transistor T1 is connected to the initial voltage signal terminal Vint, the second terminal of the first reset transistor T1 is connected to the second terminal of the first storage capacitor C1, the first terminal of the threshold compensation transistor T2, and the control terminal of the driving transistor T3, and the control terminal of the first reset transistor T1 is connected to the reset signal terminal Reset; the second terminal of the threshold compensation transistor T2 is connected to the second terminal of the driving transistor T3 and the first terminal of the second light-emitting control transistor T6, and the control terminal of the threshold compensation transistor T2 is connected to the gate line Gate; the first terminal of the driving transistor T3 is connected to the first... The power supply voltage terminal VD is connected to the data line Data; the second terminal of the switching transistor T4 is connected to the second terminal of the first light-emitting control transistor T5, the second terminal of the second reset transistor T7, and the first terminal of the first storage capacitor C1; the control terminal of the switching transistor T4 is connected to the gate line; the first terminal of the first light-emitting control transistor T5 is connected to the reference voltage signal terminal Vref, and the control terminal of the first light-emitting control transistor T5 is connected to the light-emitting control line EM; the second terminal of the second light-emitting control transistor T6 is connected to the first terminal of the light-emitting element 11, and the control terminal of the second light-emitting control transistor T6 is connected to the light-emitting control line EM; the first terminal of the second reset transistor T7 is connected to the reference voltage signal terminal Vref, and the control terminal of the second reset transistor T7 is connected to the reset signal terminal Reset; the second terminal of the light-emitting element 11 is connected to the second power supply voltage terminal VSS.

[0102] The following is about Figure 14 The positional relationship of each film layer in the displayed structure is explained. It should be understood that... Figure 14 The diagram only shows some of the devices, such as the switching transistor T4 and the driving transistor T3. The switching transistor T4 and the driving transistor T3 are illustrated as top-gate thin-film transistors.

[0103] The display structure layer 10 includes: a buffer layer 141 on the substrate 1; an active layer of a switching transistor T4 and an active layer of a driving transistor T3 disposed on the same layer as the buffer layer 141; a gate insulating layer 142 disposed on the same layer as the active layers of the switching transistor T4 and the driving transistor T3, the gate insulating layer 142 covering the display area AA and the epitaxial area NA; the gate of the switching transistor T4 and the gate of the driving transistor T3 disposed on the same layer as the gate insulating layer 142; a fourth insulating layer 143 disposed on the same layer as the gate of the switching transistor T4 and the gate of the driving transistor T3, the fourth insulating layer 143 covering the display area AA and the epitaxial area NA; and a fourth insulating layer 143 disposed on the same layer as the gate of the switching transistor T4 and the gate of the driving transistor T3. Above the insulating layer 143 and disposed on the same layer are the source and drain of the switching transistor T4, the source and drain of the driving transistor T3, and the data line connected to the source of the switching transistor T4; a first planarization layer 144 is located above the layer containing the source and drain of the switching transistor T4, the source and drain of the driving transistor T3, and the data line connected to the source of the switching transistor T4, and this first planarization layer 144 is located only in the display area AA; a first passivation layer 145 is located above the first planarization layer 144, and this first passivation layer 145 covers the display area AA and the epitaxial area NA; a second sub-signal input line 14b and a first connection electrode 14c are located above the first planarization layer 144 and disposed on the same layer; the second sub-signal input line 14b The first connection electrode 14c is connected to the data line through a fourth via penetrating the first planarization layer 144 and the first passivation layer 145. The first connection electrode 14c is connected to the drain of the driving transistor T3 through the fourth via penetrating the first planarization layer 144 and the first passivation layer 145. The second planarization layer 146 is located above the layer where the second sub-signal input line 14b and the first connection electrode 14c are located. The second planarization layer 146 is located only in the display area AA. The second passivation layer 147 is located above the second planarization layer 146. The second passivation layer 147 can cover the display area AA and the epitaxial area NA. The first sub-signal input line 14a, the first pad 14d, and the second pad 14e are located on the second passivation layer 147 and are disposed in the same layer. The input line 14a extends from the display area AA to the epitaxial area NA, and is connected to the second sub-signal input line 14b through a fifth via penetrating the second planarization layer 146 and the second passivation layer 147; the first pad 14d is connected to the first connecting electrode 14c through a fifth via penetrating the second planarization layer 146 and the second passivation layer 147; a third passivation layer 148 is located above the first sub-signal input line 14a, the first pad 14d, and the second pad 14e, and this third passivation layer 148 can cover the display area AA and the epitaxial area NA; a first bonding electrode 2 is located in the epitaxial area NA and above the third passivation layer 148, and the first bonding electrode 2 is connected to the first sub-signal input line 14a through a sixth via penetrating the third passivation layer 148;The first electrode of the light-emitting element 11 is connected to the first pad 14d through a seventh via penetrating the third passivation layer 148, and the second electrode of the light-emitting element 11 is connected to the second pad 14e through an eighth via penetrating the third passivation layer 148.

[0104] It should be noted that the pixel structure described above is for illustrative purposes only, and other pixel structures may be used in other examples.

[0105] Figure 16 A plan view of the encapsulation layer provided for embodiments of this disclosure, in some embodiments, such as Figure 16 As shown, the display panel may also be provided with an encapsulation layer 13, which is disposed on the side of the plurality of light-emitting elements 11 away from the substrate 1. The encapsulation layer 13 may include: a plurality of light-transmitting portions and light-shielding portions that space the plurality of light-transmitting portions apart from each other. The light-transmitting portions are disposed one-to-one with the light-emitting elements 11 to transmit the light emitted by the light-emitting elements 11. The material of the light-shielding portions may be a black insulating material, such as inorganic materials like silicon nitride, silicon oxide, or silicon oxynitride, or it may be an epoxy resin material. The light-transmitting portions may be a perforated structure or a film layer made of transparent material.

[0106] When the light-emitting element 11 uses a micro light-emitting diode, its light emission direction is not collimated, but emitted in all directions. As a result, some light will be directed toward the substrate 1. The setting of the light-shielding part can prevent the light from being reflected by the metal structure of the light-emitting element 11 and the substrate 1. In addition, the setting of the light-shielding part can also prevent crosstalk between adjacent light-emitting elements 11.

[0107] Figure 17 This is a schematic diagram of the structure of a display device provided in an embodiment of the present disclosure. Figure 18 A plan view of the outer frame provided in the embodiments of this disclosure, such as Figure 17 and Figure 18 As shown, the display device provided in this embodiment includes the aforementioned display panel and an outer frame 14, with at least a portion of the outer frame 14 located on the side of the substrate 1 away from the display signal lines 16. The display device also includes an adhesive 15, which is located on the side of the substrate 1 away from the display signal lines 16 and connects the display panel and the outer frame 14.

[0108] In the splicing display device, the outer frame 14 is fixedly connected to the housing of the splicing display device, thereby fixing the display panel.

[0109] In one example Figure 17 The structure of the display panel included in the display device is as follows: Figure 9 As shown, the fourth insulating part 81 completely covers the first electrostatic protection part 51, and at this time the adhesive is only used to fix the outer frame 14.

[0110] Figure 19 This is a schematic diagram of the structure of another display device provided in an embodiment of this disclosure, such as... Figure 19 As shown, the structure of the display panel included in its display device is as follows: Figure 10 As shown, the fourth insulating part 81 does not completely cover the first electrostatic discharge protection part 51. In this case, the adhesive can be conductive adhesive, and the outer frame can be a metal frame (for example, an aluminum frame with good heat dissipation and light weight). This allows the first electrostatic discharge protection part 51 to be connected to the metal frame 14 through the conductive adhesive 15, thereby discharging the static electricity on the first electrostatic discharge protection part 51 through the metal frame. This allows for more complete release of static electricity and avoids affecting the display effect of the display panel.

[0111] It should be noted that the aforementioned display devices can be: electronic paper, mobile phones, tablet computers, televisions, monitors, laptops, digital photo frames, navigators, or any other products or components with display functions.

[0112] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A display panel for tiling with an adjacent display panel to form a tiled display device, wherein, include: The substrate has a first surface and a second surface disposed opposite to each other, and a side surface connecting the first surface and the second surface; The first surface includes a display area and an extension area; A plurality of first bonding electrodes are located in the epitaxial region, and each first bonding electrode is electrically connected to a display signal line located on the first surface and extending from the display area to the epitaxial region; Multiple driving signal lines are disposed on the second surface of the substrate, wherein at least one of the multiple driving signal lines is a ground line; Multiple side traces, each of which connects a drive signal line to a first bonding electrode via the side; An electrostatic discharge (ESD) shielding layer is electrically connected to the ground wire, and the orthographic projection of the ESD shielding layer on the side surface at least partially overlaps with the orthographic projection of the side trace on the side surface. The thickness of the electrostatic protective layer is set between 0.06 and 0.5 μm; the electrostatic protective layer is a corrosion-resistant metal material; The orthographic projection of the electrostatic protective layer on the first surface penetrates the first surface along a first direction, and the orthographic projection on the second surface penetrates the second surface along the first direction, wherein the first direction intersects the direction from the display area to the extension area; The electrostatic protective layer includes at least: A first electrostatic discharge (ESD) protection unit, a second ESD protection unit, and a third ESD protection unit are connected. The first ESD protection unit is located on the second surface of the substrate, and its orthographic projection on the second surface covers the orthographic projection of the portion of the side trace located on the second surface. The first ESD protection unit is connected to the ground wire. The orthographic projection of the second ESD protection unit on the side surface covers the orthographic projection of the side trace on the side surface. The third ESD protection unit is located on the first surface of the substrate and within the epitaxial region, and is connected to the second ESD protection unit. The first ESD protection unit, the second ESD protection unit, and the third ESD protection unit are connected as a single structure. The orthographic projection of the third ESD protection unit on the first surface penetrates the first surface along a first direction, and the orthographic projection of the first ESD protection unit on the second surface penetrates the second surface along the first direction. The display panel further includes a first insulating layer and a first insulating portion; the first insulating layer is located on the side of the plurality of driving signal lines away from the substrate; the first electrostatic discharge protection portion is located on the side of the first insulating layer away from the substrate and is connected to the ground line through a second via on the first insulating layer; the first insulating portion is located between the first electrostatic discharge protection portion and the side trace; the orthographic projection of the first insulating portion on the substrate does not overlap with the orthographic projection of the second via on the substrate.

2. The display panel of claim 1, wherein, Each of the side traces is connected to a drive signal line through a first via on the first insulating layer.

3. The display panel of claim 2, wherein, The closest distance between the orthographic projection of the boundary of the first electrostatic protection part away from the second electrostatic protection part on the substrate and the orthographic projection of the second via on the substrate is between 15 and 25 μm.

4. The display panel of claim 2, wherein, The display panel also includes: The second insulating layer is disposed on the side of the electrostatic protection layer near the side trace. The second insulating layer includes a first insulating portion and a second insulating portion, wherein the second insulating portion is located between the second electrostatic protection portion and the side trace.

5. The display panel of claim 4, wherein, The first insulating portion has a first side that is away from the second insulating portion and extends along a first direction, the first direction intersecting the direction from the display area to the extension area; The portion of the side trace located on the second surface has a first end close to the first side, and the interval between the orthographic projection of the first side on the substrate and the orthographic projection of the first end on the substrate is between 15 and 25 μm.

6. The display panel of claim 4, wherein, The second insulating layer further includes: The third insulating portion is located on the side of the side trace on the second surface away from the second surface, and the third insulating portion is connected to the second insulating portion; The third insulating portion has a second side extending away from the side of the substrate and along a first direction, the first direction intersecting the direction from the display area to the epitaxial area; the portion of the side trace located on the first surface has a second end close to the second side, and the interval between the second side and the second end is between 15 and 25 μm.

7. The display panel of claim 1, wherein, The display panel also includes: A third insulating layer, at least a portion of which is located on the side of the second electrostatic protection portion away from the substrate.

8. The display panel of claim 7, wherein, The third insulating layer covers all of the second electrostatic protection portion and at least a portion of the first electrostatic protection portion.

9. The display panel of any one of claims 1 to 8, wherein, The display area includes multiple sub-pixels, each sub-pixel is provided with a light-emitting element, and each light-emitting element is connected to the display signal line.

10. The display panel of any one of claims 1 to 8, wherein, The display panel also includes: A driving structure is connected to the plurality of driving signal lines and is used to provide driving signals to the plurality of driving signal lines.

11. The display panel of claim 10, wherein, The display panel also includes: A first insulating layer is located on the side of the plurality of drive signal lines away from the substrate, and the side traces are connected to the corresponding drive signal lines through a first via on the first insulating layer. The driving structure is connected to the driving signal line through a third via on the first insulating layer.

12. A display device, wherein, The display device includes: The display panel according to any one of claims 1 to 11; An outer frame, at least a portion of which is located on the side of the substrate away from the display signal lines; An adhesive is located on the side of the substrate away from the display signal lines and connects the display panel and the outer frame.

13. The display device according to claim 12, wherein, The outer frame is a metal frame; The adhesive is a conductive adhesive and is used to connect the metal frame and the electrostatic protection layer.

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