Memory device and operating method thereof
By introducing redundant word lines and redundant memory cells into the memory device, programming its threshold voltage to gradually increase and establish downward coupling, the problem of temporary read errors in the memory device is solved, and higher read accuracy and stability are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- MACRONIX INTERNATIONAL CO LTD
- Filing Date
- 2022-05-31
- Publication Date
- 2026-07-24
AI Technical Summary
When a memory device is idle for a period of time, it is prone to temporary read errors on the first read, and existing technologies have difficulty effectively solving this problem.
Multiple redundant word lines and redundant memory cells are introduced into the memory device. The threshold voltages of these redundant word lines and memory cells are programmed to gradually increase in a specific direction, and a downward coupling environment is established after the first read to maintain the memory serialization in a strong inversion state.
It effectively suppresses temporary read errors, reduces current changes during the second read, improves read accuracy, and does not require additional circuit area cost.
Smart Images
Figure CN117095723B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a memory device and a method of operating the same. Background Technology
[0002] In memory devices, after a long period of inactivity, a read operation (hereinafter referred to as the first read) will have a higher read current, typically inducing a low threshold voltage (Vt), which can easily lead to a temporary read error. However, temporary read errors usually do not occur in the next read (i.e., the second read) because the idle time between two consecutive reads is usually not very long.
[0003] Figure 1A The display shows the read waveforms for the first and second reads. The idle time between the first read (100 μs) and the second read (100 μs) is approximately 10 μs. Figure 1A As shown, the read voltage Vread and threshold voltage Vt are both 1.5V, the drain voltage Vd is 0.6V, and the pass voltage Vpass is 8V.
[0004] Figure 1B This displays a graph showing the read current (ID) and read time for the first and second reads. (Example) Figure 1B As shown, the read current ID of the first read is higher than that of the second read. Timing T1 represents the sensing timing, which is where the read current is retrieved to determine the threshold voltage value of the memory cell. For the first read, it will correspond to a lower threshold voltage, making it prone to temporary read errors; and for the second read, it will correspond to a normal threshold voltage, making it less likely to experience temporary read errors.
[0005] Figure 1C (The X-axis represents the "second read time") and Figure 1D (The X-axis represents "idle time") This graph displays the second read current versus read time under different idle times. For example... Figure 1C and Figure 1D As shown, the longer the idle time (e.g., 1s), the higher the current for the second read, meaning that temporary read errors are more likely to occur; and the shorter the idle time (e.g., 10μs), the lower the current for the second read, meaning that temporary read errors are less likely to occur.
[0006] Therefore, avoiding temporary read errors in memory devices is one of the directions of our efforts. Summary of the Invention
[0007] According to an embodiment of the present invention, an operation method for a memory device is provided. The memory device includes a plurality of ground select lines, a plurality of serial select lines, a plurality of word lines, and a plurality of redundant word lines. A first portion of the redundant word lines is adjacent to the serial select lines, and a second portion of the redundant word lines is adjacent to the ground select lines. The word lines are located between the first portion and the second portion of the redundant word lines. The operation method for the memory device includes, during a programming operation, programming a plurality of threshold voltages of a plurality of switches on the serial select lines and the ground select lines to have a first reference threshold voltage; and programming a plurality of threshold voltages of a plurality of redundant memory cells on the redundant word lines to gradually increase along a first direction or a second direction, wherein the threshold voltages of the redundant memory cells are higher than the first reference threshold voltage, wherein the first direction is from the serial select lines to the word lines, and the second direction is from the ground select lines to the word lines.
[0008] According to another embodiment of the present invention, a memory device is provided, comprising: a plurality of bit lines; a plurality of ground select lines, wherein a plurality of first switches are located at the intersections of the bit lines and the ground select lines; a plurality of serial select lines, wherein a plurality of second switches are located at the intersections of the bit lines and the serial select lines; a plurality of word lines, wherein a plurality of memory cells are located at the intersections of the bit lines and the word lines; and a plurality of redundant word lines, wherein a plurality of redundant memory cells are located at the intersections of the bit lines and the redundant word lines; wherein a first portion of the redundant word lines is adjacent to the serial select lines, and a second portion of the redundant word lines is adjacent to the ground select lines. These word lines are located between the first portion and the second portion of these redundant word lines. The multiple threshold voltages of the first and second switches on the string select lines and the ground select lines are programmed to have a first reference threshold voltage. The multiple threshold voltages of the redundant memory cells on these redundant word lines are programmed to gradually increase along a first direction or a second direction, and the threshold voltages of these redundant memory cells are higher than the first reference threshold voltage. The first direction is from the string select lines to the word lines, and the second direction is from the ground select lines to the word lines.
[0009] To provide a better understanding of the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings: Attached Figure Description
[0010] Figure 1A Displays the waveforms of the first and second reads.
[0011] Figure 1B This graph displays the read current (ID) and read time for the first and second reads.
[0012] Figure 1C and Figure 1D The graph shows the second read current versus read time under different idle times.
[0013] Figure 2 This diagram shows an equivalent circuit diagram of a memory device according to an embodiment of the present invention.
[0014] Figure 3 This diagram illustrates the channel voltage and signal line positions of an embodiment of the present invention compared to conventional techniques.
[0015] Figure 4A The waveform diagrams of the first and second reads are shown in an embodiment of the present invention.
[0016] Figure 4B The idle time at the first word line (between the first and second reads) is shown in the current graph for the second read.
[0017] Figure 4C The idle time at the second word line (between the first and second reads) is shown in the current graph for the second read.
[0018] Figure 5 A flowchart illustrating a method for operating a memory device according to yet another embodiment of the present invention is shown.
[0019] Explanation of reference numerals in the attached figures
[0020] T1: Sensing Timing
[0021] 200: Memory device B0~BQ: Memory block
[0022] CSL: Common Source Line
[0023] WL0~WLN: Word lines; BL0~BLP: Bit lines
[0024] SW: Switch SSL0~SSL2: Serial select line
[0025] DWLT0-DWLT2, DWLB0-DWLB2: Redundant word lines
[0026] GSL0~GSL2: Grounding selection line
[0027] SS: Memory String; MC: Memory Unit
[0028] DMC: Redundant Memory Unit
[0029] L31, L32: Channel voltage curves 510: Steps Detailed Implementation
[0030] The technical terms used in this specification refer to those commonly used in the field. Where this specification provides explanations or definitions for certain terms, the interpretation of those terms shall be based on the explanations or definitions provided in this specification. Each embodiment of this disclosure has one or more technical features. Where feasible, those skilled in the art may selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.
[0031] Figure 2 This diagram shows an equivalent circuit diagram of a memory device 200 according to an embodiment of the present invention. The memory device 200 is, for example, but not limited to, a three-dimensional (3D) memory device. Figure 2 As shown, the memory device 200 includes multiple memory blocks B0 to BQ (Q is a positive integer), a common source line CSL, multiple word lines WL0 to WLN (N is a positive integer), multiple redundant word lines, multiple bit lines BL0 to BLP (P is a positive integer), multiple string select lines, and multiple ground select lines (GSL). Although Figure 1 shows three string select lines SSL0 to SSL2, three ground select lines GSL0 to GSL2, and six redundant word lines DWLT0 to DWLT2 and DWLB0 to DWLB2, the invention is not limited to this; other numbers of these string select lines, ground select lines, and redundant word lines are also within the spirit of the invention. Furthermore, the redundant word lines DWLT0 to DWLT2 near the serial select lines SSL0 to SSL2 can also be referred to as a first portion of these redundant word lines, and the redundant word lines DWLB0 to DWLB2 near the ground select lines GSL0 to GSL2 can also be referred to as a second portion of these redundant word lines. Word lines WL0 to WLN lie between the first portion and the second portion of these redundant word lines.
[0032] Taking memory device 200 as an example, the order from bottom to top is as follows: ground select lines GSL0~GSL2, redundant word lines DWLB0~DWLB2, word lines WL0~WLN, redundant word lines DWLT0~DWLT2, and serial select lines SSL0~SSL2. That is, ground select line GSL0 is located at the bottom, while serial select line SSL2 is located at the top.
[0033] Each of these memory blocks B0-BQ includes multiple switches SW and multiple memory strings SS. Each memory string SS includes multiple memory cells MC. These memory cells MC are located at the intersections of word lines WL0-WLN and bit lines BL0-BLP. Furthermore, each memory string SS includes multiple redundant memory cells DMC, which are located at the intersections of redundant word lines DWLB0-DWLB2 and bit lines BL0-BLP, or alternatively, at the intersections of redundant word lines DWLT0-DWLT2 and bit lines BL0-BLP. Within the same memory block, these memory cells MC and redundant memory cells DMC coupled to the same bit line form a memory string SS. These memory cells MC and redundant memory cells DMC are, for example, but not limited to, composed of MOSFET transistors, but it should be understood that the invention is not limited thereto. These memory cells MC and redundant memory cells DMC can be composed of other similar elements, which are also within the spirit and scope of the invention.
[0034] These switches SW are located at the intersections of the string select lines SSL0-SSL2 with the bit lines BL0-BLP, or at the intersections of the ground select lines GSL0-GSL2 with the bit lines BL0-BLP. When an associated memory string SS is selected, the associated switch SW is turned on. These switches SW are, for example, but not limited to, MOSFET transistors, but it is understood that the invention is not limited thereto. These switches SW may be composed of other similar components, which are also within the spirit of the invention.
[0035] The current flowing through the multiple cells of these memory strings SS will flow through the common source line CSL to the relevant back-end circuitry for related operations.
[0036] In one embodiment of the present invention, when programming, the threshold voltage programming conditions for the redundant memory cells DMC and / or the switches SW on the serial select lines SSL0-SSL2, ground select lines GSL0-GSL2, redundant word lines DWLB0-DWLB2, and redundant word lines DWLT0-DWLT2 are as follows, but it should be understood that this is only for illustrative purposes and the present invention is not limited thereto.
[0037] The threshold voltages of the switches SW on the series select lines SSL0-SSL2 and the ground select lines GSL0-GSL2 are programmed to have a first reference threshold voltage. In one embodiment of the invention, the first reference threshold voltage is, for example, but not limited to, 2V.
[0038] The threshold voltages of these redundant memory cells (DMCs) on redundant word lines DWLB0 and DWLT2 are programmed to have a second reference threshold voltage, which is higher than the first reference threshold voltage. In one embodiment of the invention, the second reference threshold voltage is, for example, but not limited to, 3V.
[0039] The threshold voltages of these redundant memory cells (DMCs) on redundant word lines DWLB1 and DWLT1 are programmed to have a third reference threshold voltage, which is higher than the second reference threshold voltage. In one embodiment of the invention, the third reference threshold voltage is, for example, but not limited to, 4V.
[0040] The threshold voltages of these redundant memory cells (DMCs) on redundant word lines DWLB2 and DWLT0 are programmed to have a fourth reference threshold voltage, which is higher than the third reference threshold voltage. In one embodiment of the invention, the fourth reference threshold voltage is, for example, but not limited to, 5V.
[0041] That is, in one embodiment of the present invention, the threshold voltage of the redundant memory cells DMC on these redundant word lines DWLB0~DWLB2 and DWLT0~DWLT2 is programmed to gradually increase along a first direction or a second direction, wherein the first direction is, for example, from the serial select lines SSL0~SSL2 toward these word lines WL0-WLN; and the second direction is, for example, from the ground select lines GSL0~GSL2 toward these word lines WL0-WLN.
[0042] In one embodiment of the present invention, after the first read is completed, the pass voltage applied to these unselected word lines will be reduced to a logic low potential, and the region between the high threshold voltage redundant memory cells (located between redundant word lines DWLT0 and DWLB2) (that is, these memory cells MC of word lines WL0 to WLN) can establish a downcoupled environment during the idle time between the first read and the second read.
[0043] For ease of explanation, an example of N=47 will be used here, but it should be understood that the present invention is not limited thereto. For example, in the above example, memory cells on certain word lines (word lines WL10 and WL30 are used as examples here, but it should be understood that the present invention is not limited thereto) will have high threshold voltages, while memory cells on other word lines (word lines WL20 and WL40 are used as examples here, but it should be understood that the present invention is not limited thereto) will have low threshold voltages.
[0044] In conventional technology, after the first read operation, the voltage across the unselected word line drops to a logic low potential (e.g., to ground). Consequently, the memory cells on word line WL20 (with low threshold voltage) will be in the downward-coupled region formed by word lines WL10 and WL30, because these cells are located between memory cells with high threshold voltages (i.e., memory cells on word lines WL10 and WL30). However, the memory cells on word line WL40 (with low threshold voltage) are not in the downward-coupled region formed by word lines WL10 and WL30. This is because, in conventional technology, the switches on the SSL and GSL sides typically have low threshold voltages. Therefore, in conventional technology, the memory cells on word line WL40 (with low threshold voltage) are not in the downward-coupled region, making it more difficult to maintain the memory serialization in a strong inversion state, thus leading to more severe temporary read errors.
[0045] Conversely, in one embodiment of the present invention, after the first read is completed, the through voltage of the unselected word line drops to a logic low potential (e.g., to ground). As a result, the memory cells on word line WL20 (with low threshold voltage) will be in the downward coupling region formed by word lines WL10 and WL30, and the memory cells on word line WL40 (with low threshold voltage) will be in the downward coupling region formed by word line WL30 and redundant word lines DWLT0-DWLT2. Therefore, in one embodiment of the present invention, it is easier to maintain the memory serialization in a strongly inverted state, thus temporarily suppressing read errors.
[0046] In one embodiment of the present invention, during the idle time between the first read and the second read, a down-coupling condition and environment are established using a redundant memory cell (DMC) with a high threshold voltage.
[0047] In one embodiment of the present invention, downcoupling refers to the following: after a read operation is completed, if there are high-threshold-voltage redundant memory cells around (e.g., above or below) the memory cell, these memory cells located in the region of the high-threshold-voltage memory cells will enter downcoupling when the voltage Vpass drops to 0V. When downcoupling occurs, electrons in the memory channel can be temporarily trapped, allowing the memory cell to remain in a strong inversion state for a longer period. The advantage of this is that it reduces the de-trapping behavior of grain boundary traps in the polysilicon channel of the memory cell, preserving the memory cell in the trapping state of the grain boundary trap as much as possible. Reducing the risk of de-trapping behavior reduces the change in threshold voltage (Vt) during the next read operation, making it easier to read the correct read current and minimizing problems in threshold voltage (Vt) determination, thus improving the effectiveness of temporary read errors.
[0048] In one embodiment of the present invention, during the idle time between the first read and the second read, a redundant memory cell with a high threshold voltage (Vt = 5V) on both the GSL side and the SSL side is used to maintain the memory serial array in a strong inversion state by downward coupling, thereby delaying the occurrence of trap loss behavior of grain boundary traps in the polysilicon channels of the memory cell.
[0049] In one embodiment of the present invention, a gradually increasing threshold voltage distribution of redundant memory cells is established on the GSL side and SSL side. This reduces the band-to-band leakage current near the high threshold voltage (Vt = 5V) redundant memory cells, and further extends the duration of the memory array in a strong inversion state, thereby further delaying the occurrence of trap loss behavior of grain boundary traps in the polysilicon channels of the memory cells.
[0050] In one embodiment of the present invention, temporary read errors can be effectively suppressed without requiring additional circuit area costs.
[0051] Figure 3 This diagram shows a channel voltage diagram of an embodiment of the present invention compared to conventional technology. Figure 3 The horizontal axis represents the position of the signal line. The leftmost position represents the bottom ground select line GSL0, and the rightmost position represents the top serial select line SSL2. Figure 3The vertical axis represents the channel voltage. Curve L31 represents, in one embodiment of the invention, the channel voltage measured at each signal line position at the end of the first read operation; curve L32 represents, in conventional technology, the channel voltage measured at each signal line position at the end of the first read operation. Figure 3 In the above, the threshold voltage distribution of these memory cells MC and / or redundant memory cells DMC on the ground selection lines GSL0~GSL2, redundant word lines DWLB0~DWLB2, word lines WL0~WLN, redundant word lines DWLT0~DWLT2 and serial selection lines SSL0~SSL21 is as described above.
[0052] Comparing curves L31 and L32, it can be seen that in one embodiment of the present invention, by establishing a gradually increasing threshold voltage distribution of redundant memory cells on the GSL side and SSL side, the channel voltage difference near the high threshold voltage redundant memory cells can be reduced, thereby reducing the band leakage current and extending the duration of the memory array in the strong inversion state. This further delays the occurrence of trap loss behavior of grain boundary traps in the polysilicon channel of the memory cell, thereby reducing the threshold voltage (Vt) change of the memory cell and improving temporary read errors.
[0053] Figure 4A The diagram shows the read waveforms of the first and second reads according to an embodiment of the present invention. The idle time between the first and second reads can be 10 μs, 100 μs, 1 ms, 10 ms, 100 ms, 1 s, 10 s, 100 s, or 1000 s, etc. Figure 4A As shown, the read voltage Vread and threshold voltage Vt are both 1.5V, the drain voltage Vd is 0.6V, and the pass voltage Vpass is 8V. It should be noted that this is only for illustrative purposes and the present invention is not limited thereto.
[0054] Figure 4B This diagram shows a comparison of the idle time (between the first and second reads) at word line WL40 in one embodiment of the present invention and in conventional technology, in relation to the second read current. Figure 4C This graph shows a comparison of the idle time at word line WL20 (between the first and second reads) with the second read current in an embodiment of the present invention and a conventional technique.
[0055] like Figure 4B and Figure 4C As shown, regardless of the idle time, the second read current of an embodiment of the present invention is significantly lower than that of conventional technology 1 and conventional technology 2. A higher second read current corresponds to a lower threshold voltage (Vt), which is prone to temporary read errors. Therefore, an embodiment of the present invention can effectively suppress temporary read errors.
[0056] Figure 5 A flowchart illustrating a method for operating a memory device according to yet another embodiment of the present invention is shown. Figure 5 As shown, the memory device operation method includes: during a programming operation, programming a plurality of threshold voltages of a plurality of switches on the string select lines and the ground select lines to have a first reference threshold voltage; and programming a plurality of threshold voltages of a plurality of redundant memory cells on the redundant word lines to gradually increase along a first direction or a second direction and such threshold voltages of the redundant memory cells are higher than the first reference threshold voltage, wherein the first direction is from the string select lines to the word lines, and the second direction is from the ground select lines to the word lines (510).
[0057] One embodiment of the present invention can be applied to polysilicon channel-type three-dimensional memory devices, such as, but not limited to, 3D NAND type memory devices, 3D NOR type memory devices, etc., to improve temporary read errors.
[0058] In summary, although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.
Claims
1. A method of operating a memory device, the memory device comprising a plurality of ground select lines, a plurality of serial select lines, a plurality of word lines, and a plurality of redundant word lines, wherein a first portion of the redundant word lines is adjacent to the serial select lines, a second portion of the redundant word lines is adjacent to the ground select lines, and the word lines are located between the first portion and the second portion of the redundant word lines, characterized in that... The operation method of the memory device includes: During programming operations, multiple threshold voltages of multiple switches on the string select lines and the ground select lines are programmed to have a first reference threshold voltage; and multiple threshold voltages of multiple redundant memory cells on the redundant word lines are programmed to gradually increase along a first direction or a second direction and the threshold voltages of the redundant memory cells are higher than the first reference threshold voltage, wherein the first direction is from the string select lines to the word lines, and the second direction is from the ground select lines to the word lines; In the first direction, the threshold voltages of the redundant memory cells on the first portion of the redundant word lines are programmed to gradually increase along the first direction and be higher than the first reference threshold voltage; In the second direction, the threshold voltages of the redundant memory cells on the second portion of these redundant word lines are programmed to gradually increase along the second direction and be higher than the first reference threshold voltage.
2. The method of operating the memory device according to claim 1, characterized in that, The first portion of these redundant word lines includes at least a first redundant word line, a second redundant word line and a third redundant word line, the first redundant word line being adjacent to these string select lines; The threshold voltages of these redundant memory cells on the first redundant word line are programmed to a second reference threshold voltage, which is higher than the first reference threshold voltage. The threshold voltages of these redundant memory cells on the second redundant word line are programmed to a third reference threshold voltage, which is higher than the second reference threshold voltage. The threshold voltages of these redundant memory cells on the third redundant word line are programmed to a fourth reference threshold voltage, which is higher than the third reference threshold voltage.
3. The method of operating the memory device according to claim 2, characterized in that, The second portion of these redundant word lines includes at least a fourth redundant word line, a fifth redundant word line, and a sixth redundant word line, the fourth redundant word line being adjacent to these ground select lines; The threshold voltages of these redundant memory cells on the fourth redundant word line are programmed to the second reference threshold voltage. The threshold voltages of these redundant memory cells on the fifth redundant word line are programmed as the third reference threshold voltage; and the threshold voltages of these redundant memory cells on the sixth redundant word line are programmed as the fourth reference threshold voltage.
4. A memory device, characterized in that, include: Multiple bit lines; Multiple grounding selection lines, with multiple first switches located at the intersections of these position lines and these grounding selection lines; Multiple serial select lines, with multiple second switches located at the intersections of these bit lines and these serial select lines; Multiple word lines, and multiple memory cells located at the intersections of these bit lines and these word lines; And multiple redundant word lines, with multiple redundant memory cells located at the intersections of these bit lines and these redundant word lines; In this configuration, a first portion of the redundant word lines is close to the string select lines, a second portion of the redundant word lines is close to the ground select lines, the word lines are located between the first portion and the second portion of the redundant word lines, multiple threshold voltages of the first and second switches on the string select lines and the ground select lines are programmed to have a first reference threshold voltage, and multiple threshold voltages of the redundant memory cells on the redundant word lines are programmed to gradually increase along a first direction or a second direction, and the threshold voltages of the redundant memory cells are higher than the first reference threshold voltage, wherein the first direction is from the string select lines to the word lines, and the second direction is from the ground select lines to the word lines; In the first direction, the threshold voltages of the redundant memory cells of the first portion of these redundant word lines are programmed to gradually increase along the first direction and be higher than the first reference threshold voltage; In the second direction, the threshold voltages of the redundant memory cells on the second portion of these redundant word lines are programmed to gradually increase along the second direction and be higher than the first reference threshold voltage.
5. The memory device according to claim 4, characterized in that, The first portion of these redundant word lines includes at least a first redundant word line, a second redundant word line and a third redundant word line, the first redundant word line being adjacent to these string select lines; The threshold voltages of these redundant memory cells on the first redundant word line are programmed to a second reference threshold voltage, which is higher than the first reference threshold voltage. The threshold voltages of these redundant memory cells on the second redundant word line are programmed to a third reference threshold voltage, which is higher than the second reference threshold voltage. The threshold voltages of these redundant memory cells on the third redundant word line are programmed to a fourth reference threshold voltage, which is higher than the third reference threshold voltage.
6. The memory device according to claim 5, characterized in that, The second portion of these redundant word lines includes at least a fourth redundant word line, a fifth redundant word line, and a sixth redundant word line, the fourth redundant word line being adjacent to these ground select lines; The threshold voltages of these redundant memory cells on the fourth redundant word line are programmed to the second reference threshold voltage. The threshold voltages of these redundant memory cells on the fifth redundant word line are programmed as the third reference threshold voltage; and the threshold voltages of these redundant memory cells on the sixth redundant word line are programmed as the fourth reference threshold voltage.