Display panel and display device

Abstract

The application discloses a display panel and a display device, and relates to the technical field of display panels, and specifically discloses a display panel and a display device. The display panel comprises: sub-pixels arranged in an array and a plurality of data lines; the plurality of data lines comprise first data lines and second data lines; the load on the first data lines is greater than the load on the second data lines; a load compensation line is located in a display area of the display panel, a first end of the load compensation line is connected with one end of a corresponding second data line, and the load compensation line is used for compensating the load of the second data line connected with the load compensation line, so that the difference between the total load of the second data line and the total load of the first data line is less than a preset value. The application satisfies the matching of the loads on different data lines, and reduces the frame width of the display panel.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of display, and in particular, to a display panel and a display device. BACKGROUND

[0002] With the development of display technology, people have higher and higher requirements for full display screens.

[0003] When the existing organic light-emitting display panel displays a picture, a corresponding data voltage needs to be provided to each sub-pixel through a data line. For data lines of different lengths, the loads on the data lines are different; the loads of the data lines need to be compensated to meet the requirement that the loads on different data lines are matched.

[0004] However, in the prior art, the loads of the data lines are usually compensated in the frame area of the display panel, which is not conducive to the development requirement of narrow frame of the display panel. SUMMARY

[0005] Embodiments of the present application provide a display panel and a display device to meet the requirement that the total loads on different data lines are matched while reducing the frame width of the display panel.

[0006] According to an aspect of the present application, a display panel is provided, comprising:

[0007] arrayed sub-pixels and a plurality of data lines; each data line is connected with a corresponding sub-pixel; wherein the plurality of data lines comprises at least one first data line and at least one second data line; the load of the first data line is greater than the load of the second data line;

[0008] at least one load compensation line located in the display area of the display panel; a first end of the load compensation line is connected with one end of a corresponding second data line; the load compensation line is used to compensate the load of the second data line connected with the load compensation line, so that the difference between the total load of the second data line and the total load of the first data line is less than a preset value.

[0009] Optionally, the length of at least one of the load compensation lines is less than the length of the second data line connected with the load compensation line.

[0010] Optionally, the display panel further comprises:

[0011] at least one functional auxiliary line arranged in the same layer as the load compensation line; each functional auxiliary line is arranged on a length line smaller than the load compensation line; the functional auxiliary line is electrically isolated from the corresponding load compensation line; the functional auxiliary line is used to be connected with a functional signal line in the display panel to reduce the voltage drop on the functional signal line.

[0012] Preferably, the length of the second data line connected with the load compensation line is equal to the sum of the length of the load compensation line, the length of the functional auxiliary line located on the extension line of the load compensation line and the distance between them.

[0013] Optionally, the functional auxiliary line is connected with the power signal line in the display panel through a via hole.

[0014] Alternatively, the functional auxiliary line is connected with the initialization signal line in the display panel through a via hole.

[0015] Optionally, the sub-pixels are uniformly spaced in the column direction; and the length of the second data line is less than the length of the first data line.

[0016] The total resistance of the line resistance of the second data line and the line resistance of the load compensation line connected with the second data line is less than the difference between the line resistance of the first data line by a first preset value.

[0017] The sum of the parasitic capacitance formed by the second data line and the parasitic compensation capacitance formed by the load compensation line connected with the second data line is less than the difference between the parasitic capacitance formed by the first data line by a second preset value.

[0018] Optionally, the first end of each load compensation line is connected with the corresponding second data line in the frame area of the display panel.

[0019] Optionally, the first end of each load compensation line is connected with the corresponding second data line in the top frame area of the display panel, or the first end of each load compensation line is connected with the corresponding second data line in the bottom frame area of the display panel.

[0020] Optionally, the at least one second data line includes a plurality of second data lines.

[0021] The lengths of at least part of the second data lines are different, and the lengths of the load compensation lines connected with the second data lines of different lengths are also different.

[0022] Optionally, the plurality of second data lines are distributed on both sides of the at least one first data line; and along the direction away from the at least one first data line, the lengths of the second data lines gradually decrease, and the lengths of the load compensation lines gradually increase.

[0023] Preferably, the shape of the display area of the display panel includes a circle, an ellipse or a racetrack shape.

[0024] Optionally, the display panel includes:

[0025] A substrate, a driving circuit layer disposed on the substrate, and a light-emitting structure layer disposed on a side of the driving circuit layer away from the substrate; the driving circuit layer comprises pixel driving units arranged in an array and a plurality of data lines; the light-emitting structure layer comprises a plurality of light-emitting structures; each pixel driving unit and a corresponding light-emitting structure are used to form a sub-pixel;

[0026] Each data line is connected with a corresponding column of pixel driving units, and each data line is used to form a parasitic capacitance with a first electrode plate of a storage capacitor in the corresponding connected column of pixel driving units;

[0027] Each load compensation line forms a parasitic compensation capacitance with a first electrode plate of a storage capacitor in at least one pixel driving unit;

[0028] Preferably, the load compensation line is disposed in the same layer as the data line; the metal layer in which the first electrode plate is located is located on a side of the metal layer in which the data line is located close to the substrate.

[0029] Optionally, the driving circuit layer further comprises a plurality of power signal lines, each power signal line being connected with a corresponding sub-pixel;

[0030] At least a part of each power signal line is disposed in the same layer as the first electrode plate; each load compensation line forms the parasitic compensation capacitance with the first electrode plate of the storage capacitor in at least one pixel driving unit and the power signal line disposed in the same layer as the first electrode plate.

[0031] According to another aspect of the present application, a display device is provided, comprising the display panel according to any one of the embodiments of the present application.

[0032] The technical scheme provided by the embodiments of the present application compensates for the parasitic capacitance formed by the second data line and the parasitic compensation capacitance formed by the load compensation line, and compensates for the line resistance of the second data line, so that the difference between the total load of the second data line and the total load of the first data line is less than a preset value, thereby realizing the matching of the total load of the second data line and the total load of the first data line. The load compensation line is arranged in the display area of the display panel, which does not occupy the frame area of the display panel, thereby meeting the matching of the total loads on different data lines while reducing the frame width of the display panel, which is beneficial to the development of narrow frame of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 is a structural schematic diagram of a display panel provided by an embodiment of the present application;

[0034] Figure 2 is a connection schematic diagram of a second data line and a load compensation line provided by an embodiment of the present application;

[0035] Figure 3 is Figure 1 is a structural schematic diagram of a driving circuit unit in region 1 in the structure shown in FIG. 1;

[0036] Figure 4 is a layout schematic diagram of a load compensation line and a function auxiliary line provided by an embodiment of the present application;

[0037] Figure 5 is Figure 1 is a structural schematic diagram of a driving circuit unit in region 2 in the structure shown in FIG. 1;

[0038] Figure 6 is Figure 1 is a structural schematic diagram of another driving circuit unit in region 2 in the structure shown in FIG. 1;

[0039] Figure 7 is a circuit diagram of a driving circuit unit provided by an embodiment of the present application;

[0040] Figure 8 is Figure 1 is a structural schematic diagram of an active structure in region 1 or region 2 in FIG. 1;

[0041] Figure 9 is Figure 1 is a structural schematic diagram of an active structure and a first metal layer in region 1 or region 2 in FIG. 1;

[0042] Figure 10 is Figure 1 is a structural schematic diagram of an active structure, a first metal layer and a second metal layer in region 1 or region 2 in FIG. 1;

[0043] Figure 11 is a structural schematic diagram of a display device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0044] The present application will be further described below in conjunction with the drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application. In addition, it should be noted that, for the convenience of description, only the parts related to the present application are shown in the drawings, but not all the structures.

[0045] As background, in order to meet the increasingly high experience needs of consumers for electronic products, display devices use organic light-emitting full display screens with higher screen-to-body ratios. In existing organic light-emitting display panels, a plurality of sub-pixels and a plurality of data lines are included; each data line is connected to a corresponding sub-pixel. When displaying a picture, a corresponding data voltage needs to be provided to each sub-pixel to achieve display of different gray scales. The load of the data line is related to the line resistance of the data line itself and the parasitic capacitance generated by the data line and other metal film layers (i.e., conductive film layers). Similarly, the line load in the following is also related to the resistance of the line and the parasitic capacitance generated by the line and the conductive film layer.

[0046] The data line extends along the column direction, and in the process of extension, the data line and the conductive film layer in the display panel have an overlapping area, thereby forming a parasitic capacitance of the data line. For a non-rectangular display screen containing an arc region, such as a circular screen, an elliptical screen, or a racetrack screen, the data lines therein have different lengths. For data lines of different lengths, the longer data line has a larger area of the overlapping region formed with the conductive film layer in the display panel in the process of extension, and a larger parasitic capacitance is formed, and the shorter data line has a smaller area of the overlapping region formed with the conductive film layer in the display panel in the process of extension, and a smaller parasitic capacitance is formed. Moreover, for data lines of different lengths, the longer data line has a larger line resistance, and the shorter data line has a smaller line resistance.

[0047] In other words, for data lines of different lengths, the load of the longer data line is greater than that of the shorter data line. Different loads of the data lines will result in different charging capabilities and / or voltage drops of the data lines to the data voltage, thereby causing different data voltages obtained on the data lines of different lengths when the same data voltage is provided, so that the brightness of the sub-pixels on the data lines of different lengths has differences. In order to ensure that the loads on all data lines are the same or have small differences, compensation is usually made to the data line with a smaller load. At present, a load compensation capacitor of the data line is usually arranged in a frame region of the display panel, and the load compensation capacitor requires a large space, which is not conducive to the development of narrow frames of the display panel.

[0048] In view of this, the embodiment of the present application provides a display panel, Figure 1 is a structural schematic diagram of a display panel provided by the embodiment of the present application, Figure 2 is a connection schematic diagram of a second data line and a load compensation line provided by the embodiment of the present application, referring to Figure 1 and Figure 2 The display panel comprises:

[0049] The arrayed sub-pixels and the plurality of data lines; each data line is connected with a corresponding sub-pixel; wherein the plurality of data lines comprises at least one first data line 10 and at least one second data line 20; the load of the first data line 10 is greater than the load of the second data line 20;

[0050] At least one load compensation line 30 is located in the display area of the display panel; the first end of the load compensation line 30 is connected with one end of a corresponding second data line 20, and the load compensation line 30 is used to compensate the load of the second data line 20 connected with the load compensation line 30, so that the difference between the total load of the second data line 20 and the total load of the first data line 10 is less than a preset value. It is worth noting that the total load of the second data line 20 includes the load of the second data line 20 and the load of the load compensation line 30; since the first data line 10 is not provided with a compensation line, the total load of the first data line 10 is equal to the load of the first data line 10.

[0051] Specifically, the display panel includes a display area and a non-display area. The non-display area includes a scan driver 100 and a light-emitting driver 200, a data driver 300, a timing controller 400, and the like as shown. Figure 1 The display area includes an array substrate and a light-emitting structure layer disposed on the array substrate. The array substrate refers to a film layer structure capable of providing driving signals for the display panel and playing a role of buffering, protection, or support, etc., which includes a substrate and a driving circuit layer disposed on the substrate. The driving circuit layer includes a plurality of driving circuit units, a plurality of data lines (D1 to Dn), a plurality of scan lines (S1 to Sm), a plurality of light-emitting control signal lines (E1 to Eo), and a plurality of power supply traces. The data driver 300 is connected with the plurality of data lines (D1 to Dn) respectively, the scan driver 100 is connected with the plurality of scan lines (S1 to Sm) respectively, and the light-emitting driver 200 is connected with the plurality of light-emitting control signal lines (E1 to Eo) respectively.

[0052] The light-emitting structure layer includes a plurality of light-emitting structures, the driving circuit unit and the light-emitting structure connected with the driving circuit unit constitute a sub-pixel, and the display area can include a plurality of sub-pixels Pxij, i and j can be non-zero natural numbers. The driving circuit unit can at least include a pixel driving circuit, and the pixel driving circuit is connected with the scan line, the light-emitting control signal line, and the data line respectively. The data line is configured to provide a data signal to the pixel driving circuit, the scan line is configured to provide a scan signal to the pixel driving circuit, and the light-emitting control signal line is configured to provide a light-emitting control signal to the pixel driving circuit, thereby realizing light-emitting control of the light-emitting structure.

[0053] The timing controller 400 can provide grayscale values ​​and control signals suitable for the specifications of the data driver 300 to the data driver 300, clock signals, scan start signals, etc. suitable for the specifications of the scan driver 100 to the scan driver 100, and clock signals, emission stop signals, etc. suitable for the specifications of the light emitting driver 200 to the light emitting driver 200. The data driver 300 can use the grayscale values ​​and control signals received from the timing controller 400 to generate data voltages to be provided to the data signal lines D1, D2, D3, ..., and Dn. For example, the data driver 300 can use the clock signal to sample the grayscale values ​​and apply data voltages corresponding to the grayscale values ​​to the data signal lines D1 to Dn in units of pixel rows, where n can be a non-zero natural number. The scan driver 100 can generate scan signals to be provided to the scan signal lines S1, S2, S3, ..., and Sm by receiving the clock signal, scan start signal, etc. from the timing controller 400, where m can be a non-zero natural number. The light emitting driver 200 may generate light emitting control signals to be provided to the light emitting control signal lines E1 , E2 , E3 , . . . , and Eo by receiving a clock signal, an emission stop signal, etc. from a timing controller, where o may be a non-zero natural number.

[0054] Among them, multiple data lines include Figure 2 At least one first data line 10 and at least one second data line 20 are shown. The load on the first data line 10 is greater than the load on the second data line 20. That is, the area of ​​the overlapped region formed by the first data line 10 and the conductive film layer in the display panel during extension is greater than the area of ​​the overlapped region formed by the second data line 20 during extension, and / or the line resistance of the first data line 10 is greater than the line resistance of the second data line 20. The first data line 10 can be understood as the data line with the heaviest load in the display panel. The reasons for the overlapped region formed by the first data line 10 and the conductive film layer in the display panel during extension being greater than the area of ​​the overlapped region formed by the second data line 20 during extension include at least the fact that the number of sub-pixels connected to the first data line 10 is greater than the number of sub-pixels connected to the second data line 20, resulting in the first data line 10 passing through a greater number of driving circuit units than the second data line 20. The reason why the line resistance of the first data line 10 is greater than the line resistance of the second data line 20 at least includes that the length of the first data line 10 is greater than the length of the second data line.

[0055] The load compensation line 30 is arranged in the display area of the display panel. One end of the load compensation line 30 is connected to one end of a corresponding second data line 20. Each second data line 20 can be connected to one load compensation line 30 or multiple load compensation lines 30. However, it should be noted that one load compensation line 30 is connected to one second data line 20 to prevent the data voltage on multiple second data lines 20 from interfering with each other when one load compensation line 30 is connected to multiple second data lines 20. When a second data line 20 is connected to multiple load compensation lines 30, one load compensation line 30 is connected to one second data line 20 to prevent the data voltage on multiple second data lines 20 from interfering with each other when one load compensation line 30 is connected to multiple second data lines 20.

[0056] The second data line 20 and the load compensation line 30 are connected in series, which can compensate for the line resistance of the second data line 20, thereby achieving compensation for the load of the second data line 20. In addition, Figure 3 is Figure 1 The structure of the driving circuit unit in region 1 in the structure shown in FIG. 1 is shown in FIG. 2. Referring to FIG. 2, Figure 3 and Figure 1 The load compensation line 30 can form a parasitic compensation capacitor C3 with the original conductive film layer in the display panel during extension. One end of the load compensation line 30 is connected to one end of a corresponding second data line 20, which can connect the second data line 20 and the load compensation line 30 in series, thereby increasing the parasitic capacitor formed by the second data line 20, and achieving compensation for the parasitic capacitor formed by the second data line 20 connected to the load compensation line 30 by the parasitic compensation capacitor C3 formed by the load compensation line 30. Therefore, further compensation for the load of the second data line 20 is achieved.

[0057] The compensation for the load of the second data line 20 connected to the load compensation line 30 by the load compensation line 30 makes the difference between the total load of the second data line 20 and the total load of the first data line 10 less than a preset value, and the size of the preset value can be set according to actual conditions. The total load on the second data line 20 is matched with the total load on the first data line 10. The load compensation line 30 is arranged in the original area of the display area, which can utilize the space of the display area to arrange the load compensation line 30 without occupying the frame area of the display panel, thereby meeting the matching of the total load on data lines of different lengths while being conducive to the development of narrow frames of display panels.

[0058] The load compensation line 30 and the second data line 20 can be arranged in the same layer or different layers. The length of the load compensation line 30 can be smaller than the length of the second data line 20 connected with the load compensation line 30, or the length of the load compensation line 30 can be equal to the length of the second data line 20 connected with the load compensation line 30. The load compensation line 30 can be arranged on one side of the second data line 20 and extend along the edge of the second data line 20, or the load compensation line 30 can not extend along the edge of the second data line 20. The total load of the load compensation line 30 and the corresponding connected second data line 20 is smaller than the total load on the first data line 10 by a preset value.

[0059] The display panel provided by the embodiment of the present application comprises sub-pixels arranged in an array and a plurality of data lines; each data line is connected with a corresponding sub-pixel; wherein the plurality of data lines comprises at least one first data line and at least one second data line; the load of the first data line is greater than the load of the second data line; at least one load compensation line is arranged in the display area of the display panel; the first end of the load compensation line is connected with one end of the corresponding second data line, and the load compensation line is used for compensating the load of the second data line connected with the load compensation line, so that the difference between the total load of the second data line and the total load of the first data line is smaller than a preset value. The load compensation line is arranged in the display area of the display panel, and can not occupy the frame area of the display panel, so that the total loads of different data lines are matched, the frame width of the display panel is reduced, and the development of the narrow frame of the display panel is facilitated.

[0060] In an embodiment of the present application, Figure 4 is a schematic diagram of the arrangement of a load compensation line and a functional auxiliary line provided by the embodiment of the present application, referring to Figure 4 The length of the at least one load compensation line 30 is smaller than the length of the second data line connected with the load compensation line 30.

[0061] In other embodiments, the display panel further comprises:

[0062] At least one functional auxiliary line 40 arranged in the same layer as the load compensation line 30; each functional auxiliary line 40 is arranged on the extension line of the load compensation line 30 with a length smaller than the second data line; the functional auxiliary line 40 is electrically isolated from the corresponding load compensation line 30; the functional auxiliary line 40 is used for being connected with a functional signal line in the display panel, so as to reduce the voltage drop on the functional signal line.

[0063] Specifically, when the length of the load compensation line 30 is less than the length of the second data line connected with the load compensation line 30, the second end of the load compensation line 30 is still a distance away from the position of the frame of the display panel in the extension direction of the load compensation line 30. A conductive trace can be continuously arranged in the extension direction of the load compensation line 30 to form a function auxiliary line 40. The first end of the function auxiliary line 40 is disconnected from the second end of the load compensation line 30 to achieve electrical isolation between the function auxiliary line 40 and the load compensation line 30. The function auxiliary line 40 is used to be connected with a function signal line in the display panel to reduce the resistance of the function signal line, thereby reducing the voltage drop on the function signal line. The load compensation line 30 and the function auxiliary line 40 are arranged in the same layer, which can make the load compensation line 30 and the function auxiliary line 40 formed in the same preparation process, thereby simplifying the preparation process of the display panel.

[0064] In the preparation of the load compensation line 30 and the function auxiliary line 40, a metal trace extending along the second data line can be arranged on the side of the second data line. The metal trace and the second data line 20 can be arranged in the same layer or different layers. The metal trace is divided into a first connection section and a second connection section by etching, and the first connection section and the second connection section are electrically isolated. The first connection section is used as the load compensation line 30, and the second connection section is used as the function auxiliary line 40 located on the extension line of the load compensation line 30. One end of the first connection section is connected with one end of the corresponding second data line and extends along part of the length of the second data line, and the first connection section is used to form a parasitic compensation capacitor with a conductive film layer in the driving circuit of at least one sub-pixel. The second connection section extends along another part of the length of the second data line, and the second connection section is connected with a function signal line in the display panel to reduce the voltage drop on the function signal line.

[0065] In addition, the load compensation line 30 and the second data line are arranged in the same layer, and the second data line, the load compensation line 30 and the function auxiliary line 40 can be formed in the same preparation process. Therefore, the preparation process of the display panel can be further simplified. Moreover, the second data line, the load compensation line 30 and the function auxiliary line 40 are prepared by using the same metal layer in the display panel, which can reduce the thickness of the display panel.

[0066] In an embodiment of the present application, please continue to refer to Figure 4 The length of the second data line connected with the load compensation line 30 is equal to the sum of the length of the load compensation line 30, the length of the function auxiliary line 40 located on the extension line of the load compensation line 30, and the distance between them.

[0067] Specifically, the length of the second data line 20 connected with the load compensation line 30 is set to be equal to the sum of the length of the load compensation line 30, the length of the functional auxiliary line 40 located on the extension line of the load compensation line 30, and the distance between the load compensation line 30 and the functional auxiliary line 40. The length of the metal trace for preparing the load compensation line 30 and the functional auxiliary line 40 can be set according to the length of the second data line, and the setting mode of the length of the metal trace is unified, thereby simplifying the setting mode of the length of the metal trace. In the metal trace, the length of the load compensation line 30 is determined based on the size of the parasitic compensation capacitance and the line resistance of the corresponding second data line of the load compensation line 30, and the remaining trace in the metal trace is used as the functional auxiliary line 40. Therefore, the length of the second data line connected with the load compensation line 30 is set to be equal to the sum of the length of the load compensation line 30, the length of the functional auxiliary line 40 located on the extension line of the load compensation line 30, and the distance between the load compensation line 30 and the functional auxiliary line 40, which can ensure that the load on the second data line is compensated, and the length of the functional auxiliary line 40 can be maximized, thereby improving the connectable length of the functional auxiliary line 40 and the functional signal line.

[0068] In an embodiment of the present application, Figure 5 Figure 1 FIG. 2 is a structural schematic diagram of a drive circuit unit in region 2 in the structure shown in FIG. 1, with reference to Figure 5 Figure 1 The functional auxiliary line 40 can be connected with the power signal line (ELVDD line) in the display panel through the via hole B, which reduces the voltage drop on the power signal line (ELVDD line) and makes the voltage signal on the power signal line in the display panel more stable, thereby improving the display effect of the display panel. Alternatively, in another embodiment of the present application, the functional auxiliary line 40 can be connected with the initialization signal line (Vref line) in the display panel through the via hole A1, which reduces the voltage drop on the initialization signal line and makes the initialization signal on the initialization signal line in the display panel more stable, thereby improving the reset function of the initialization signal line on the sub-pixel and improving the display effect of the display panel. The via hole A1 and the via hole B do not exist at the same time, and the positions of the via hole A1 and the via hole B in the drawing are only used to illustrate the positions. Figure 6 Figure 1 FIG. 3 is a structural schematic diagram of another drive circuit unit in region 2 in the structure shown in FIG. 1, with reference to Figure 6 The functional auxiliary line 40 can be connected with the initialization signal line (Vref line) in the display panel through the via hole A2. The via hole A2 is the original via hole in the display panel, and the functional auxiliary line 40 and the initialization signal line are connected by using the original via hole, which can avoid adding a new via hole and reducing the modification of the structure of the display panel.

[0069] In an embodiment of the present application, with reference to Figure 1 Figure 2 ​​​​The sub-pixels are arranged at equal intervals in the column direction; and the length of the second data line 20 is less than the length of the first data line 10.

[0070] The total resistance of the line resistance of the second data line and the line resistance of the load compensation line connected with the second data line is less than the difference of the line resistance of the first data line by a first preset value; the first preset value is set according to actual design conditions.

[0071] The sum of the parasitic capacitance load formed by the second data line and the parasitic compensation capacitance formed by the load compensation line connected with the second data line is less than the difference of the parasitic capacitance formed by the first data line by a second preset value; the second preset value is set according to actual design conditions.

[0072] Specifically, the sub-pixels are arranged at equal intervals in the column direction, so that the number of sub-pixels connected by the data line in unit length is the same, the number of driving circuit units passed by the data line in unit length is the same, and the parasitic capacitance formed by the data line in unit length is the same. In the preparation process, the width of the data line is usually the same, and the conductive material is the same, that is, the width of the first data line 10 is the same as the width of the second data line 20, and the material of the first data line 10 is the same as the material of the second data line 20, so that the line resistance of the data line in unit length is the same. Since the length of the first data line 10 is greater than the length of the second data line 20, the load of the first data line 10 is greater than the load of the second data line 20. One end of the load compensation line 30 is connected with one end of the corresponding second data line 20, so that the second data line 20 and the load compensation line 30 are connected in series, so that the line resistance of the second data line 20 and the line resistance of the load compensation line 30 are connected in series, and at the same time, the load compensation line 30 can also form a parasitic compensation capacitance, so as to increase the load of the second data line 20, thereby realizing the compensation of the load of the second data line 20 by the load compensation line 30, so that the difference between the total load of the second data line 20 and the total load of the first data line 10 is less than a preset value. The total resistance of the line resistance of the second data line 20 and the line resistance of the load compensation line 30 connected with the second data line 20 is less than the difference of the line resistance of the first data line 10 by a first preset value; the sum of the parasitic capacitance formed by the second data line 20 and the parasitic compensation capacitance formed by the load compensation line 30 connected with the second data line 20 is less than the difference of the parasitic capacitance formed by the first data line 10 by a second preset value. The first preset value and the second preset value can be set according to actual conditions.

[0073] In an embodiment of the present application, the first end of each load compensation line 30 is connected with the corresponding second data line 20 in the frame area of the display panel. For example, please continue to refer to Figure 2The first end of each load compensation line 30 is connected to the corresponding second data line 20 in the top frame area of the display panel, or the first end of each load compensation line 30 is connected to the corresponding second data line 20 in the bottom frame area of the display panel.

[0074] Specifically, connecting the first end of the load compensation line 30 to the corresponding second data line 20 in the frame area 101 of the display panel can facilitate the connection of the load compensation line 30 and the corresponding second data line 20. It should be noted that the first end of each load compensation line 30 is connected to the end of the second data line 20 away from the data driver, so that the load compensation line 30 and the second data line 20 satisfy a series connection relationship.

[0075] In an embodiment of the present application, please continue to refer to Figure 2 Optionally, the at least one second data line 20 includes a plurality of second data lines 20.

[0076] The lengths of at least part of the second data lines 20 are different, and the lengths of the load compensation lines 30 connected to the second data lines 20 of different lengths are different.

[0077] Specifically, the display panel includes a plurality of second data lines 20, and the load of the display panel needs to be compensated. Based on the shape of the display panel, the lengths of at least part of the second data lines 20 are different, and the loads on the different second data lines 20 are different, so the compensation of the loads on the second data lines 20 is also different. Therefore, the lengths of the load compensation lines 30 connected to the second data lines 20 of different lengths are different. By setting the length of the load compensation line 30 for each second data line 20, the compensation of the load of the second data line 20 of different lengths can be adapted, so that the total load on each second data line 20 is the same as or close to the total load on the first data line 10.

[0078] In an embodiment of the present application, please continue to refer to Figure 2 The plurality of second data lines 20 are distributed on both sides of the at least one first data line 10, and the length of the second data line 20 gradually decreases and the length of the load compensation line 30 gradually increases along the direction away from the at least one first data line 10.

[0079] The shape of the display area of the display panel can include a circular shape, an elliptical shape, or a racetrack shape.

[0080] In an embodiment of the present application, please continue to refer to Figure 3 The display panel includes:

[0081] The display panel comprises a substrate, a driving circuit layer arranged on the substrate, and a light-emitting structure layer arranged on a side of the driving circuit layer away from the substrate; the driving circuit layer comprises pixel driving units arranged in an array and a plurality of data lines; the light-emitting structure layer comprises a plurality of light-emitting structures; each pixel driving unit and a corresponding light-emitting structure are used to form a sub-pixel.

[0082] Each data line is connected with a corresponding column of pixel driving units, and each data line is used to form a parasitic capacitance with a first electrode plate of a storage capacitor in the corresponding column of pixel driving units.

[0083] Each load compensation line 30 forms a parasitic compensation capacitance C3 with a first electrode plate of a storage capacitor in at least one pixel driving unit.

[0084] Specifically, the display panel comprises a substrate, a driving circuit layer arranged on the substrate, and a light-emitting structure layer arranged on a side of the driving circuit layer away from the substrate. The substrate can be flexible and can be formed of any suitable insulating material having flexibility. The driving circuit layer can comprise a plurality of driving circuit units, a plurality of data lines, a plurality of scan lines, a plurality of light-emitting control signal lines, a plurality of power supply lines, and a plurality of initialization signal lines. The light-emitting structure comprises a first electrode, a second electrode, and a light-emitting material layer between the first electrode and the second electrode. The first electrode is electrically connected to a source electrode or a drain electrode of a thin film transistor through a contact hole. Each first electrode corresponds to a driving circuit unit comprising at least two control transistors, and each driving circuit unit is a pixel driving circuit.

[0085] For example, the pixel driving circuit can be a "7T1C" circuit in the prior art, comprising seven thin film transistors and one storage capacitor. Figure 7 is a circuit diagram of a driving circuit unit provided by an embodiment of the present application, referring to Figure 7 , and combining Figure 3 Each driving circuit unit comprises seven thin film transistors (T1-T7) and one storage capacitor C1, and the working principle of the "7T1C" circuit is the prior art, which will not be described here.

[0086] Figure 8 is a structural diagram of an active structure in the region 1 or the region 2 in Figure 1 Figure 9 is a structural diagram of an active structure and a first metal layer in the region 1 or the region 2 in Figure 1 Figure 10 is a structural diagram of an active structure, a first metal layer, and a second metal layer in the region 1 or the region 2 in Figure 1 , referring to Figures 7-10 ​​, the first metal layer (M1) is provided with a first scan signal line for transmitting a first scan signal Scan1, a second scan signal line for transmitting a second scan signal Scan2, a second electrode plate c11 of a storage capacitor C1, a light-emitting control signal line for transmitting a light-emitting control signal EM, and a third scan signal line for transmitting a third scan signal Scan3 in the pixel driving circuit. The second metal layer (M2) is provided with an initialization signal line for transmitting an initialization signal Vref in the pixel driving circuit, a shielding layer 9 for shielding the data line and the T1 gate, and a first electrode plate c12 of the storage capacitor C1. Referring to Figure 3 and Figure 5 , the third metal layer (M3) is provided with a data line for transmitting a data voltage Data, a power signal line for transmitting a power signal ELVDD,

[0087] Each data line is connected with a corresponding column of pixel driving units, and during the extension of each data line, the data line has an overlapping area with the first electrode plate c12 of the storage capacitor C1 in the corresponding connected column of pixel driving units, forming at least part of the parasitic capacitance C2 on the data line. In other embodiments of the present application, the data line can also form a parasitic capacitance with other structure wires or structures in the driving circuit layer during the extension.

[0088] Wherein, the load compensation line 30 is provided in the same layer as the data line, and each load compensation line 30 can form a parasitic compensation capacitor C3 with the first electrode plate c12 of the storage capacitor C1 in at least one pixel driving unit during the extension. Optionally, the metal layer where the first electrode plate c12 of the storage capacitor is located is located on the side close to the substrate of the metal layer where the data line is located. The load compensation line 30 and the data line are provided in the M3 metal layer in the driving circuit layer, and the first electrode of the storage capacitor C1 is provided in the M2 metal layer in the driving circuit layer.

[0089] In an embodiment of the present application, the driving circuit layer further comprises a plurality of power signal lines, each of which is connected with a corresponding sub-pixel;

[0090] At least part of the interval section of each power signal line is provided in the same layer as the first electrode plate c12; each load compensation line 30 forms a parasitic compensation capacitor C3 with the first electrode plate of the storage capacitor in at least one pixel driving unit, and with the power signal line provided in the same layer as the first electrode plate. Wherein, the shielding layer 9 for shielding the data line and the T1 gate is connected with the power signal line through a via hole, that is, the shielding layer 9 can serve as part of the interval section of the power signal line provided in the same layer as the first electrode plate c12.

[0091] In the process of determining the parasitic compensation capacitance of the load compensation line 30, the parasitic capacitance formed between the data line (10 / 20) and each sub-pixel can be calculated based on the simulation results; then the total number of sub-pixels connected to the first data line 10 is determined, so that the parasitic compensation capacitance on the first data line 10 can be calculated based on the parasitic capacitance formed between the first data line 10 and each sub-pixel and the total number of sub-pixels connected to the first data line 10; the total number of sub-pixels connected to the second data line 20 is determined, so that the parasitic capacitance formed by the second data line can be calculated based on the parasitic capacitance formed between the second data line 20 and each sub-pixel and the total number of sub-pixels connected to the second data line 20; based on the difference between the parasitic capacitance formed by the first data line 10 and the parasitic capacitance formed by each second data line 20, the parasitic capacitance that needs to be compensated for each second data line 20 can be determined.

[0092] Next, the parasitic capacitance formed between the load compensation capacitor line 30 and each sub-pixel is determined based on the simulation results. The number of pixels to be compensated is calculated by dividing the parasitic capacitance required for the second data line 20 by the parasitic capacitance formed between the load compensation line 30 and a single pixel. If a single load compensation line 30 is connected to the second data line 20, the length of the load compensation line 30 corresponding to each second data line 20 can be determined based on the number of pixels to be compensated by each second data line 20, and can be adaptively adjusted based on actual conditions.

[0093] Figure 11 is a schematic structural diagram of a display device provided by an embodiment of the present invention, with reference to Figure 11 The embodiment of the present invention further provides a display device, comprising: the display panel 1001 described in any of the above embodiments. The display device has the same technical effects and will not be described in detail here.

[0094] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the concept of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, characterized by, The display panel comprises: a plurality of sub-pixels and a plurality of data lines arranged in an array; each data line is connected to a corresponding sub-pixel; wherein the plurality of data lines comprises at least one first data line and at least one second data line; the load of the first data line is greater than the load of the second data line; at least one load compensation line located in the display area of the display panel; the first end of the load compensation line is connected to one end of a corresponding second data line; the load compensation line is used to compensate the load of the second data line connected to the load compensation line, so that the difference between the total load of the second data line and the total load of the first data line is less than a preset value; the length of at least one load compensation line is less than the length of the second data line connected to the load compensation line; The display panel further comprises: at least one functional auxiliary line arranged in the same layer as the load compensation line; each functional auxiliary line is arranged on the extension line of the load compensation line with a length less than the second data line; the functional auxiliary line is electrically isolated from the corresponding load compensation line; the functional auxiliary line is used to connect with the functional signal line in the display panel to reduce the voltage drop on the functional signal line.

2. The display panel of claim 1, wherein, The length of the second data line connected to the load compensation line is equal to the sum of the length of the load compensation line, the length of the functional auxiliary line located on the extension line of the load compensation line, and the distance between them.

3. The display panel of claim 1, wherein the functional auxiliary line is connected to the power signal line in the display panel through a via hole; or, the functional auxiliary line is connected to the initialization signal line in the display panel through a via hole.

4. The display panel of claim 1, wherein, The sub-pixels are uniformly spaced in the column direction; the length of the second data line is less than the length of the first data line; the total resistance of the line resistance of the second data line and the line resistance of the load compensation line connected to the second data line is less than the difference between the line resistance of the first data line; the difference between the sum of the parasitic capacitance formed by the second data line and the parasitic compensation capacitance formed by the load compensation line connected to the second data line, and the parasitic capacitance formed by the first data line, is less than a second preset value.

5. The display panel of claim 1, wherein, The first end of each load compensation line is connected to a corresponding second data line in the frame area of the display panel.

6. The display panel of claim 5, wherein, The first end of each load compensation line is connected to a corresponding second data line in the top frame area of the display panel, or the first end of each load compensation line is connected to a corresponding second data line in the bottom frame area of the display panel.

7. The display panel of claim 1, wherein, The at least one second data line comprises a plurality of second data lines; The lengths of at least some of the second data lines are different, and the lengths of the load compensation lines connected to the second data lines with different lengths are different.

8. The display panel of claim 7, wherein the plurality of second data lines are distributed on both sides of the at least one first data line; and along the direction away from the at least one first data line, the lengths of the second data lines gradually decrease, and the lengths of the load compensation lines gradually increase.

9. The display panel of claim 8, wherein, The shape of the display area of the display panel comprises a circle, an ellipse or a racetrack.

10. The display panel of claim 1, wherein, Comprise: a substrate, a driving circuit layer disposed on the substrate, and a light-emitting structure layer disposed on a side of the driving circuit layer away from the substrate; the driving circuit layer comprises an array of pixel driving units and a plurality of data lines; the light-emitting structure layer comprises a plurality of light-emitting structures; each pixel driving unit and a corresponding light-emitting structure are used to constitute a sub-pixel; each data line is connected to a corresponding column of pixel driving units, and each data line forms a parasitic capacitance with the first electrode plate of the storage capacitor in the corresponding column of pixel driving units; each load compensation line forms a parasitic compensation capacitance with the first electrode plate of the storage capacitor in at least one pixel driving unit.

11. The display panel of claim 10, wherein, The load compensation line is disposed in the same layer as the data line; the metal layer where the first electrode plate is located is located on the side of the metal layer where the data line is located close to the substrate.

12. The display panel of claim 10, wherein, The driving circuit layer further comprises a plurality of power signal lines, each power signal line being connected to a corresponding sub-pixel; At least part of each power signal line is disposed in the same layer as the first electrode plate; each load compensation line forms the parasitic compensation capacitance with the first electrode plate of the storage capacitor in at least one pixel driving unit and the power signal line disposed in the same layer as the first electrode plate.

13. A display device comprising: Comprise: The display panel of any one of claims 1-12.

Images