Semiconductor memory device and method of operation thereof and method of operating a controller

Abstract

The present application relates to a semiconductor memory device and an operating method thereof and a method of operating a controller. A semiconductor memory device includes a memory cell array, a peripheral circuit, and control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit performs a read operation on a selected memory cell among the plurality of memory cells. The control logic controls the read operation of the peripheral circuit in response to a read command received from an external device, and determines whether to perform a discharge operation on a word line connected to the plurality of memory cells based on a type of the read command.

Description

Technical Field

[0001] This disclosure relates to electronic devices, and more specifically, to semiconductor memory devices and controllers for reading data at increased speeds, and methods for operating semiconductor memory devices and controllers. Background Technology

[0002] Semiconductor memory devices can be formed as two-dimensional structures in which strings are arranged horizontally on a semiconductor substrate, or as three-dimensional structures in which strings are stacked vertically on a semiconductor substrate. Three-dimensional semiconductor memory devices are memory devices designed to address the integration limitations of two-dimensional semiconductor memory devices, and can include multiple memory cells stacked vertically on a semiconductor substrate.

[0003] The controller can control the operation of the semiconductor memory device. Specifically, in response to a request received from the host, the controller controls the semiconductor memory device to perform an operation corresponding to the request by sending commands to the semiconductor memory device. Alternatively, regardless of requests from the host, the controller can control the semiconductor memory device to perform internal operations such as garbage collection. Summary of the Invention

[0004] According to embodiments of this disclosure, a semiconductor memory device includes a memory cell array, peripheral circuitry, and control logic. The memory cell array includes a plurality of memory cells. The peripheral circuitry performs a read operation on a selected memory cell among the plurality of memory cells. The control logic controls the read operation of the peripheral circuitry in response to a read command received from an external device, and determines whether to perform a discharge operation on word lines connected to the plurality of memory cells based on the type of the read command.

[0005] According to another embodiment of the present disclosure, an operation method of a semiconductor memory device including multiple memory cells includes receiving a read command from an external device, reading data from a selected memory cell among the multiple memory cells in response to the read command, and determining whether to perform a discharge operation on word lines connected to the multiple memory cells based on the type of the read command.

[0006] According to another embodiment of this disclosure, a method of operating a controller is used to control read operations of a semiconductor memory device comprising a plurality of memory cells. The method of operating the controller includes sending one of a first type of read command and a second type of read command to the semiconductor memory device; receiving data from the semiconductor memory device; and determining whether to send a discharge command to the semiconductor memory device based on the type of read command sent to the semiconductor memory device. The first type of read command controls the semiconductor memory device to perform a read operation including a word line discharge operation, and the second type of read command controls the semiconductor memory device to perform a read operation without a word line discharge operation.

[0007] According to another embodiment of this disclosure, a method of operating a controller is used to control read operations of a semiconductor memory device comprising multiple memory cells. The method of operating the controller includes sending a first type of read command to the semiconductor memory device; receiving first data from the semiconductor memory device; and determining whether to send a second type of read command to the semiconductor memory device based on whether an error correction operation on the first data was successful. The first type of read command controls the semiconductor memory device to perform a read operation including a word line discharge operation, and the second type of read command controls the semiconductor memory device to perform a read operation without a word line discharge operation. Attached Figure Description

[0008] Figure 1 This is a block diagram illustrating a memory system and a host device.

[0009] Figure 2 This is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0010] Figure 3 This is an example Figure 2 The circuit diagram of any one of the memory blocks BLKa from BLK1 to BLKz.

[0011] Figure 4 This is a graph illustrating the threshold voltage distribution of a multi-level unit.

[0012] Figure 5 This is a timing diagram illustrating an example of a read operation of a semiconductor memory device.

[0013] Figure 6 This is a timing diagram illustrating another example of a read operation of a semiconductor memory device.

[0014] Figure 7 This diagram illustrates the operation of the controller and semiconductor memory device when error correction for read data fails.

[0015] Figure 8 This is an example based on Figure 7 The following is a timing diagram of the operation of an example semiconductor memory device.

[0016] Figure 9A and Figure 9B This is a diagram illustrating the operation of a controller and a semiconductor memory device that outputs a first type of read command according to an embodiment of the present disclosure, based on the first type of read command.

[0017] Figure 10A and Figure 10B This is a diagram illustrating the operation of a controller and a semiconductor memory device that output a second type of read command according to an embodiment of the present disclosure, based on the second type of read command.

[0018] Figure 11A and Figure 11B This is a diagram illustrating the operation of a controller and a semiconductor memory device based on a discharge command, according to an embodiment of the present disclosure.

[0019] Figure 12A and Figure 12B This is a diagram illustrating the operation of a controller and a semiconductor memory device that use a first type of read command and a second type of read command together, based on the first type of read command and the second type of read command.

[0020] Figure 13A and Figure 13B This is a diagram illustrating the operation of a controller and a semiconductor memory device based solely on the first type of read command.

[0021] Figure 14 This is a flowchart illustrating the operation of a semiconductor memory device according to an embodiment of the present disclosure.

[0022] Figure 15 This is an example Figure 14 The flowchart shows an exemplary implementation of step S120.

[0023] Figure 16 This is a flowchart illustrating the operation of a semiconductor memory device according to another embodiment of the present disclosure.

[0024] Figure 17 This is a flowchart illustrating the operation of a controller according to an embodiment of the present disclosure.

[0025] Figure 18 This is a flowchart illustrating the operation of a controller according to another embodiment of the present disclosure.

[0026] Figure 19 This is a block diagram illustrating an implementation of a memory system including a semiconductor memory device and a controller.

[0027] Figure 20 This is an example Figure 19 A block diagram illustrating an application example of a memory system.

[0028] Figure 21 This illustrates the example including references. Figure 20 A block diagram of the computing system describing the memory system. Detailed Implementation

[0029] The specific structural or functional descriptions of embodiments based on the concepts disclosed in this specification or application are merely illustrative for the purpose of describing embodiments based on the concepts disclosed herein, and embodiments based on the concepts disclosed herein may be implemented in various forms and should not be construed as limited to the embodiments described in this specification or application.

[0030] Embodiments of this disclosure provide a semiconductor memory, a controller, and a method for operating the semiconductor memory and the controller that can improve read speed during repeated read operations.

[0031] This technology can provide semiconductor memory, controller, and methods for operating semiconductor memory and controller that can improve read speed during repeated read operations.

[0032] Figure 1 This is a block diagram illustrating a memory system and a host device.

[0033] Reference Figure 1 The memory system 1000 may include a semiconductor memory device 100 and a controller 200. Furthermore, the memory system 1000 can communicate with a host device 300. The controller 200 can control the overall operation of the semiconductor memory device 100. Additionally, the controller 200 can control the operation of the semiconductor memory device 100 based on an operation request (RQ) received from the host device 300.

[0034] The semiconductor memory device 100 can operate in response to control by the controller 200. The semiconductor memory device 100 may include an array of memory cells having multiple memory blocks. In some embodiments, the semiconductor memory device 100 may be a flash memory device.

[0035] The controller 200 can exchange user data based on requests (RQs) from the host device 300. Specifically, the controller 200 can receive write requests, read requests, or trim requests from the host device 300, and can control the semiconductor memory device 100 based on the received requests. More specifically, the controller 200 can generate commands (CMDs) for controlling the operation of the semiconductor memory device 100 and can send the commands (CMDs) to the semiconductor memory device 100. Furthermore, the controller 200 can exchange data (DATA) with the semiconductor memory device 100.

[0036] In one implementation, the controller 200 can control the operation of the semiconductor memory device 100 independently of requests from the host device 300. For example, the controller 200 can control the operation of the semiconductor memory device 100 such that the memory system 1000 performs a garbage collection operation internally.

[0037] Semiconductor memory device 100 can be configured to receive commands and addresses from controller 200 and access a region in the memory cell array selected by the address. In other words, semiconductor memory device 100 can perform internal operations corresponding to commands for the region selected by the address.

[0038] For example, the semiconductor memory device 100 can perform programming, reading, and erasing operations. During a programming operation, the semiconductor memory device 100 can program data into a region selected by an address. During a reading operation, the semiconductor memory device 100 can read data from the region selected by an address. During an erasing operation, the semiconductor memory device 100 can erase data stored in the region selected by an address.

[0039] Figure 2 This is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0040] Reference Figure 2 The semiconductor memory device 100 may include a memory cell array 110, an address decoder 120, a read / write circuit 130, control logic 140, and a voltage generator 150.

[0041] The memory cell array 110 may include a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz can be connected to the address decoder 120 via word lines WL. The plurality of memory blocks BLK1 to BLKz can be connected to the read / write circuitry 130 via bit lines BL1 to BLm. Each of the plurality of memory blocks BLK1 to BLKz may include a plurality of memory cells. In one embodiment, the plurality of memory cells may be non-volatile memory cells and may be configured using non-volatile memory cells with a vertical channel structure. The memory cell array 110 may be configured as a two-dimensional memory cell array. According to another embodiment, the memory cell array 110 may be configured as a three-dimensional memory cell array. Furthermore, each of the plurality of memory cells included in the memory cell array may store at least one bit of data. In one embodiment, each of the plurality of memory cells included in the memory cell array 110 may be a single-level cell (SLC) storing one bit of data. In another embodiment, each of the plurality of memory cells included in the memory cell array 110 may be a multi-level cell (MLC) storing two bits of data. In another embodiment, each of the plurality of memory cells included in the memory cell array 110 may be a tertiary cell storing three bits of data. In yet another embodiment, each of the plurality of memory cells included in the memory cell array 110 may be a quadrilateral cell storing four bits of data. According to embodiments, the memory cell array 110 may include a plurality of memory cells each storing five or more bits of data.

[0042] Address decoder 120, read / write circuitry 130, and voltage generator 150 can operate as peripheral circuitry to drive memory cell array 110. The peripheral circuitry can perform read, write, and erase operations on memory cell array 110 based on control logic 140. Address decoder 120 can be connected to memory cell array 110 via word line WL. Address decoder 120 can be configured to operate in response to control logic 140. Address decoder 120 can receive addresses via an input / output buffer (not shown) within semiconductor memory device 100.

[0043] Address decoder 120 can be configured to decode block addresses from received addresses. Address decoder 120 can select at least one memory block based on the decoded block address. Additionally, during a read operation, address decoder 120 can apply a read voltage Vread generated by voltage generator 150 to the selected word lines in the selected memory block and can apply a pass voltage Vpass to the remaining unselected word lines. Furthermore, during a programming verification operation, address decoder 120 can apply a verification voltage generated by voltage generator 150 to the selected word lines in the selected memory block and can apply a pass voltage Vpass to the remaining unselected word lines.

[0044] Address decoder 120 can be configured to decode the column address in a received address. Address decoder 120 can then send the decoded column address to read / write circuit 130.

[0045] Read and programming operations of the semiconductor memory device 100 can be performed on a page-by-page basis. The address received when requesting a read or programming operation may include a block address, a row address, and a column address. The address decoder 120 can select a memory block and a word line based on the block and row addresses. The column address can be decoded by the address decoder 120 and provided to the read / write circuitry 130.

[0046] Address decoder 120 may include block decoder, row decoder, column decoder, address buffer, etc.

[0047] The read / write circuit 130 may include multiple page buffers PB1 to PBm. The read / write circuit 130 can operate as a "read circuit" during read operations of the memory cell array 110 and as a "write circuit" during write operations of the memory cell array 110. The multiple page buffers PB1 to PBm can be connected to the memory cell array 110 via bit lines BL1 to BLm. During read and program verification operations, in order to sense the threshold voltage of the memory cells, the multiple page buffers PB1 to PBm can sense changes in current flowing according to the programming state of the corresponding memory cells through sensing nodes while continuously providing sensing current to the bit lines connected to the memory cells, and can latch the sensed changes as sensed data. The read / write circuit 130 can operate in response to page buffer control signals output from control logic 140.

[0048] During a read operation, the read / write circuit 130 can sense the data in the memory cell, temporarily store the read data, and output the data DATA to the input / output buffer (not shown) of the semiconductor memory device 100. In an exemplary embodiment, in addition to a page buffer (or page register), the read / write circuit 130 may also include a column select circuit, etc.

[0049] Control logic 140 can be connected to address decoder 120, read / write circuitry 130, and voltage generator 150. Control logic 140 can receive commands CMD and control signals CTRL via input / output buffers (not shown) of semiconductor memory device 100. Control logic 140 can be configured to control the overall operation of semiconductor memory device 100 in response to control signal CTRL. Additionally, control logic 140 can output control signals for adjusting the precharge potential levels of sensing nodes in multiple page buffers PB1 to PBm. Control logic 140 can control read / write circuitry 130 to perform read operations on memory cell array 110.

[0050] Voltage generator 150 can generate a read voltage Vread and a pass voltage Vpass in response to a control signal output from control logic 140 during a read operation. To generate multiple voltages with various voltage levels, voltage generator 150 may include multiple pump capacitors that receive an internal power supply voltage, and multiple voltages can be generated by selectively activating the multiple pump capacitors in response to control by control logic 140. Furthermore, in addition to the multiple pump capacitors, voltage generator 150 may also include a voltage regulator.

[0051] Figure 3 This is an example Figure 2 The circuit diagram of any one of the memory blocks BLKa from BLK1 to BLKz.

[0052] Reference Figure 3 The storage block BLKa may include multiple cell strings CS11 to CS1m and CS21 to CS2m. In an implementation, each of the multiple cell strings CS11 to CS1m and CS21 to CS2m may be formed along the +Z direction. In the storage block BLKa, m cell strings may be arranged in the row direction (i.e., the +X direction). Figure 3 In this context, two unit strings can be arranged in the column direction (i.e., the +Y direction). However, this is for ease of description, and it can be understood that three or more unit strings can be arranged in the column direction.

[0053] Each of the multiple cell strings CS11 to CS1m and CS21 to CS2m may include at least one source selection transistor SST, a first memory cell MC1 to the nth memory cell MCn, and at least one drain selection transistor DST.

[0054] The selected transistors SST and DST, and each of the memory cells MC1 to MCn, can have similar structures. In an embodiment, each of the selected transistors SST and DST, and each of the memory cells MC1 to MCn, may include a channel layer, a tunneling insulating layer, a charge storage layer, and a barrier insulating layer. In an embodiment, pillars for providing the channel layer may be provided in each cell string. In an embodiment, pillars for providing at least one of the channel layer, tunneling insulating layer, charge storage layer, and barrier insulating layer may be provided in each cell string.

[0055] The source selection transistor SST of each cell string can be connected between the common source line CSL and memory cells MC1 to MCn.

[0056] In one implementation, source-select transistors in cell strings arranged in the same row can be connected to source-select lines extending in the row direction, while source-select transistors in cell strings arranged in different rows can be connected to different source-select lines. Figure 3 In the first row, the source selection transistors CS11 to CS1m can be connected to the first source selection line SSL1. The source selection transistors CS21 to CS2m in the second row can be connected to the second source selection line SSL2.

[0057] In another embodiment, the source selection transistors of cell strings CS11 to CS1m and CS21 to CS2m can be connected together to a single source selection line.

[0058] The first memory cell MC1 to the nth memory cell MCn of each cell string can be connected between the source selection transistor SST and the drain selection transistor DST.

[0059] The drain select transistor (DST) of each cell string can be connected between the corresponding bit line and memory cells MC1 to MCn. The drain select transistors (DST) of cell strings arranged in the row direction can be connected to drain select lines extending in the row direction. The drain select transistors of cell strings CS11 to CS1m in the first row can be connected to the first drain select line DSL1. The drain select transistors of cell strings CS21 to CS2m in the second row can be connected to the second drain select line DSL2.

[0060] A string of cells arranged in the column direction can be connected to a bit line extending in the column direction. Figure 3 In the diagram, the cell strings CS11 and CS21 in the first column can be connected to the first bit line BL1. The cell strings CS1m and CS2m in the m-th column can be connected to the m-th bit line BLm.

[0061] In a row-oriented cell string, memory cells connected to the same word line can be configured as a page. For example, in the cell strings CS11 to CS1m of the first row, memory cells connected to the first word line WL1 can be configured as a page. In the cell strings CS21 to CS2m of the second row, memory cells connected to the first word line WL1 can be configured as another page. A cell string arranged in a row direction can be selected by selecting either drain select line DSL1 or DSL2. A page in the selected cell string can be selected by selecting any of the word lines WL1 to WLn.

[0062] In another embodiment, even-numbered bit lines and odd-numbered bit lines can be provided to replace the first bit line BL1 to the m-th bit line BLm. Additionally, the even-numbered cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction can be connected to the even-numbered bit lines, while the odd-numbered cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction can be connected to the odd-numbered bit lines.

[0063] In this implementation, at least one of the first memory cells MC1 to the nth memory cell MCn can be used as a dummy memory cell. For example, at least one or more dummy memory cells can be provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCn. Alternatively, at least one or more dummy memory cells can be provided to reduce the electric field between the drain selection transistor DST and the memory cells MC1 to MCn. The more dummy memory cells provided, the higher the operational reliability of the memory block BLKa, but the larger the size of the memory block BLKa. Conversely, the smaller the number of memory cells provided, the smaller the size of the memory block BLKa, but the lower the operational reliability of the memory block BLKa.

[0064] To effectively control at least one dummy memory cell, each dummy memory cell can have a required threshold voltage. Programming operations on all or part of the dummy memory cells can be performed before or after an erase operation on the memory block BLKa.

[0065] like Figure 3 As shown, the memory block BLKa has a three-dimensional structure, but this disclosure is not limited thereto. For example, the memory cell array of the semiconductor memory device according to this disclosure may include memory blocks with a two-dimensional structure.

[0066] Figure 4 This is a graph illustrating the threshold voltage distribution of a multi-level unit.

[0067] Reference Figure 4The threshold voltage of a multilevel cell (MLC) can be included in any one of the erase state E, the first programming state PV1, the second programming state PV2, and the third programming state PV3. The semiconductor memory device and method of operating the semiconductor memory device according to this disclosure may be applied not only to MLCs, but also to three-level cell (TLC), four-level cell (QLC), or memory cells storing five or more bits of data. However, for ease of discussion, the following description is based on MLCs.

[0068] During the read operation, a first read voltage R1 can be applied to the selected word line to distinguish between the erase state E and the first programming state PV1. Additionally, a second read voltage R2 can be applied to the selected word line to distinguish between the first programming state PV1 and the second programming state PV2. Furthermore, a third read voltage R3 can be applied to the selected word line to distinguish between the second programming state PV2 and the third programming state PV3. During the read operation, a read pass voltage Vpass can be applied to the unselected word line. Furthermore, during the verification operation performed during the programming operation, the first verification voltage Vvr1, the second verification voltage Vvr2, and the third verification voltage Vvr3 can be used to verify the first programming state PV1 through the third programming state PV3.

[0069] Figure 5 This is a timing diagram illustrating an example of a read operation of a semiconductor memory device.

[0070] Reference Figure 5 A read operation on a selected memory cell can be performed based on a method for operating a semiconductor memory device according to embodiments of the present disclosure. The read operation on the selected memory cell may include a channel initialization step, a threshold voltage sensing step for the selected memory cell, a word line equalization step, and a word line discharge step. Figure 5 In this process, a channel initialization step can be performed during time period t1 to t2, a threshold voltage sensing step can be performed during time period t2 to t5, a word line equalization step can be performed during time period t5 to t6, and a word line discharge step can be performed during time period t6 to t7.

[0071] At time t1, a turn-on voltage Von can be applied to the selected drain select line and the selected source select line, and also to the unselected drain select line and the unselected source select line. Furthermore, a read pass voltage Vpass can be applied to the selected word line connected to the memory cell to be read, and also to the unselected word line. With the turn-on voltage Von applied to the drain select line and the source select line, the read pass voltage Vpass can be applied to all word lines, thus enabling channel initialization operations.

[0072] The solid line illustrates the application of the read pass voltage Vpass to the selected and unselected word lines during time intervals t1 and t2. However, due to RC delay, the voltages of the selected and unselected word lines can increase as shown by the dashed line. Taking into account the RC delay of the word lines, time intervals t1 and t2 can be determined such that the voltage applied to the word lines has sufficient time to increase to the read pass voltage Vpass.

[0073] At time t2, a cutoff voltage Voff can be applied to the unselected drain-select and unselected source-select lines. The cutoff voltage Voff can be a voltage capable of turning off the drain-select and source-select transistors, and in this embodiment, the cutoff voltage Voff can be ground. Figure 3 or Figure 4 As shown, when two cell strings are arranged in the column direction (i.e., the +Y direction), the drain select line and source select line connected to the cell string that includes the memory cell to be read can become the selected drain select line and the selected source select line, respectively. Furthermore, the drain select line and source select line connected to the cell string that does not include the memory cell to be read can become the unselected drain select line and the unselected source select line, respectively. Additionally, a conduction voltage Von can be continuously applied to the selected drain select line and the selected source select line.

[0074] At time t2, a first read voltage R1 can be applied to the selected word line. During the period t2 to t3, it can be determined whether the threshold voltage of the selected memory cell is higher than the first read voltage R1. The application of the first read voltage R1 to the selected word line during the period t2 to t3 is shown by the solid line. However, due to RC delay, the voltage of the selected word line can be reduced as shown by the dashed line. Taking into account the RC delay, the period t2 to t3 can be determined such that the voltage of the selected word line is given sufficient time to decrease to the first read voltage R1. In the following text, the repeated description of the dashed lines related to the RC delay has been omitted.

[0075] At time t3, a second read voltage R2 can be applied to the selected word line. During the period t3 to t4, it can be determined whether the threshold voltage of the selected memory cell is higher than the second read voltage R2. Additionally, at time t4, a third read voltage R3 can be applied to the selected word line. During the period t4 to t5, it can be determined whether the threshold voltage of the selected memory cell is higher than the third read voltage R3.

[0076] At time t5, a cutoff voltage Voff can be applied to the selected drain select line DSL and the selected source select line SSL. Additionally, to balance the word lines at time t5, balancing voltages can be applied to the selected and unselected word lines. Figure 5 In the example, the equalization voltage is shown as equal to the read-through voltage Vpass. However, this is merely an example, and the equalization voltage can be determined to be different from the read-through voltage Vpass.

[0077] At time t6, a cutoff voltage Voff can be applied to the word line, which enables a word line discharge operation. Considering RC delay, the time period t6 to t7 for performing the word line discharge operation can be determined, allowing sufficient time for the voltage applied to the word line to decrease. The read operation can then end after time t7.

[0078] Reference Figure 5 A first read voltage R1 can be applied to the selected word line during time periods t2 to t3, a second read voltage R2 can be applied during time periods t3 to t4, and a third read voltage R3 can be applied during time periods t4 to t5. That is, the read voltage can be applied sequentially from the lowest read voltage R1 to the highest read voltage R3, depending on its magnitude. In this case, the difference between the read pass voltage Vpass applied to the selected word line during time periods t1 to t2 and the first read voltage R1 applied during time periods t2 to t3 can be relatively large.

[0079] Figure 6 This is a timing diagram illustrating another example of a read operation of a semiconductor memory device.

[0080] Reference Figure 6 In addition to applying read voltages sequentially to the selected word line from the highest read voltage R3 to the lowest read voltage R1, it is also possible to... Figure 5 The operation shown is similar to the method used to perform the read operation. Therefore, repeated descriptions have been omitted.

[0081] exist Figure 6 During the time period t11 to t12, a channel initialization step can be performed; a threshold voltage sensing step can be performed during the time period t12 to t15; a word line equalization step can be performed during the time period t15 to t16; and a word line discharge step can be performed during the time period t16 to t17.

[0082] At time t11, a conduction voltage Von can be applied to the selected drain select line and the selected source select line, and also to the unselected drain select line and the unselected source select line. Furthermore, a read pass voltage Vpass can be applied to the selected word line connected to the memory cell to be read, and also to the unselected word line. With the conduction voltage Von applied to the drain select line and the source select line, the read pass voltage Vpass can be applied to all word lines, thus enabling channel initialization.

[0083] At time t12, a cutoff voltage Voff can be applied to the unselected drain-selected line and the unselected source-selected line. Furthermore, a turn-on voltage Von can be continuously applied to the selected drain-selected line and the selected source-selected line.

[0084] At time t12, a third read voltage R3 can be applied to the selected word line. During time periods t2 and t3, it can be determined whether the threshold voltage of the selected memory cell is higher than the third read voltage R3. At time t13, a second read voltage R2 can be applied to the selected word line. During time periods t13 and t14, it can be determined whether the threshold voltage of the selected memory cell is higher than the second read voltage R2. Additionally, at time t14, a first read voltage R1 can be applied to the selected word line. During time periods t14 and t15, it can be determined whether the threshold voltage of the selected memory cell is higher than the first read voltage R1.

[0085] At time t15, a cutoff voltage Voff can be applied to the selected drain select line DSL and the selected source select line SSL. Additionally, to balance the word lines at time t15, balancing voltages can be applied to the selected and unselected word lines. Figure 6 In the example, the equalization voltage is shown as equal to the read-through voltage Vpass. However, this is merely an example, and the equalization voltage can be determined to be different from the read-through voltage Vpass.

[0086] At time t16, a cutoff voltage Voff can be applied to the word line, which enables a word line discharge operation. Taking into account RC delay, the period t16 to t17 for performing the word line discharge operation can be determined, allowing sufficient time for the voltage applied to the word line to decrease. The read operation can then end after time t17.

[0087] Figure 7 This diagram illustrates the operation of the controller and semiconductor memory device when error correction for read data fails.

[0088] Reference Figure 7 The controller 200 can send a read command (CMD) to the semiconductor memory device 100. RD (①). In response to the received read command CMD RD The semiconductor memory device 100 can perform a read operation. Furthermore, the semiconductor memory device 100 can send read data DATA (②) to the controller 200. The controller 200 can perform error correction on the received data DATA.

[0089] Error correction may fail when the received data DATA contains more error bits than a certain threshold. When error correction fails (③), the controller 200 may send a read command CMD to the semiconductor memory device 100 to reread the corresponding data. RD(④). In this process, the controller 200 can control the semiconductor memory device to change the value of the read voltage used for the read operation. This is in response to the received read command CMD. RD The semiconductor memory device 100 can then perform a read operation again. According to an embodiment, the semiconductor memory device 100 can reread data at the same location where the previous read operation was performed by using a modified read voltage. The semiconductor memory device 100 can send the reread data DATA (⑤) to the controller 200. The controller 200 can then perform an error correction operation on the received data DATA again.

[0090] like Figure 7 As shown, when error correction for reading data fails, the same data can be read again.

[0091] Figure 8 This is an example based on Figure 7 The following is a timing diagram of the operation of an example semiconductor memory device. Figure 8 The use of reference is shown Figure 6 The timing diagram describes the read operation of the method. That is, in Figure 8 In the timing diagram, the read voltage can be applied to the selected word line sequentially from the highest read voltage R3 to the lowest read voltage R1. For ease of discussion, in Figure 8 The timing diagram only shows the voltage of the word line, and the voltages of the drain select line and the source select line have been omitted.

[0092] When the controller 200 sends the first read command CMD to the semiconductor memory device 100 RD At time (①), the semiconductor memory device 100 can begin a first read operation. Specifically, during time periods t21 to t22, a first channel initialization step can be performed, and during time periods t22 to t25, a first threshold voltage sensing step can be performed. Additionally, during time periods t25 to t26, a first word line equalization step can be performed, and during time periods t26 to t27, a first word line discharge step can be performed. The first read operation of the semiconductor memory device 100 can be performed during time periods t21 to t27, and the read data can be sent to the controller 200 (②).

[0093] The controller 200 can perform error correction on the received data. When error correction fails (③), the controller 200 can send the read command CMD to the semiconductor memory device 100 again. RD(④). Therefore, the semiconductor memory device 100 can begin a second read operation. Specifically, a second channel initialization step can be performed during time periods t31 to t32, and a second threshold voltage sensing step can be performed during time periods t32 to t35. In addition, a second word line equalization step can be performed during time periods t35 to t36, and a second word line discharge step can be performed during time periods t36 to t37. The second read operation of the semiconductor memory device 100 can be performed during time periods t31 to t37, and the read data can be sent to the controller 200 (⑤).

[0094] In continuous read operations of word lines at the same location, the time required for word line discharge operations increases because the RC delay indicated by multiple word lines is relatively large. (Refer to...) Figure 8 In two consecutive read operations, the overall read time can be reduced by omitting the first word line discharge step that is performed after the first word line equalization step.

[0095] In addition to a first type of read command used to control normal read operations of the semiconductor memory device 100, the controller 200 can also use a second type of read command sent when repeatedly performing read operations on word lines at the same location. When the first type of read command is received, the semiconductor memory device 100 can perform a read operation including a word line discharge step during the read operation. Furthermore, when the second type of read command is received, the semiconductor memory device 100 can choose not to perform a word line discharge operation during the read operation. Additionally, after performing a read operation corresponding to the second type of read command, the controller can use a word line discharge command to control the semiconductor memory device 100 to perform a word line discharge step.

[0096] Figure 9A and Figure 9B This is a diagram illustrating the operation of a controller and a semiconductor memory device that outputs a first type of read command according to an embodiment of the present disclosure, based on the first type of read command.

[0097] Reference Figure 9A The controller 200 can send a first type read command (CMD) to the semiconductor memory device 100. RDA When the controller 200 needs to control the semiconductor memory device 100 to perform a normal read operation, it can send a first type read command (CMD) to the semiconductor memory device 100. RDA In response to the first type of read command CMD RDA The semiconductor memory device 100 can perform a read operation including a word line discharge step.

[0098] More specifically, refer to Figure 9B In response to the first type of read command CMDRDA The semiconductor memory device 100 can perform a channel initialization step in time period t41 to t42, a threshold voltage sensing step in time period t42 to t45, a word line equalization step in time period t45 to t46, and a word line discharge step in time period t46 to t47. That is, the semiconductor memory device 100 can respond to a first type read command CMD. RDA The read operation includes a word line discharge step.

[0099] Figure 10A and Figure 10B This is a diagram illustrating the operation of a controller and a semiconductor memory device that output a second type of read command according to an embodiment of the present disclosure, based on the second type of read command.

[0100] Reference Figure 10A The controller 200 can send a second type of read command (CMD) to the semiconductor memory device 100. RDB When the controller 200 needs to control the semiconductor memory device 100 to repeatedly perform read operations on the same word line location, it can send a second type of read command (CMD) to the semiconductor memory device 100. RDB In response to the second type of read command CMD RDB The semiconductor memory device 100 can perform a read operation without a word line discharge step.

[0101] More specifically, refer to Figure 10B In response to the second type of read command CMD RDB The semiconductor memory device 100 can perform a channel initialization step in time period t51 to t52, a threshold voltage sensing step in time period t52 to t55, and a word line equalization step in time period t55 to t56. That is, the semiconductor memory device 100 can respond to a second type read command CMD. RDB This involves performing a read operation without a word line discharge step. Therefore, the semiconductor memory device 100 can perform a read operation based on the second type of read command CMD. RDB After a read operation is performed, the voltage on the word line can also maintain the read pass voltage Vpass.

[0102] Figure 11A and Figure 11B This is a diagram illustrating the operation of a controller and a semiconductor memory device based on a discharge command, according to an embodiment of the present disclosure.

[0103] like Figure 10A and Figure 10B As shown, during repeated execution of the second type of read command CDM RDBAt a specific point in time following the corresponding read operation, the semiconductor memory device 100 may no longer need to rely on the second type of read command (CDM). RDB Perform a read operation. In this case, the controller 200 can send a discharge command CMD to the semiconductor memory device 100 to control the semiconductor memory device 100 to perform a word line discharge operation. DSC The semiconductor memory device 100 can respond to a discharge command CMD. DSC A cutoff voltage is applied to the word line that holds the read voltage Vpass.

[0104] Figure 12A and Figure 12B This is a diagram illustrating the operation of a controller and a semiconductor memory device that use a first type of read command and a second type of read command together, based on the first type of read command and the second type of read command.

[0105] Reference Figure 12A Only the commands sent from controller 200 to semiconductor memory device 100 are shown, and the data sent from semiconductor memory device 100 to controller 200 has been omitted. Controller 200 may first send a first type read command (CMD) to semiconductor memory device 100. RDA When used with the first type of read command CMD RDA When error correction for the corresponding read data fails, the controller 200 can determine to repeat the read operation on the word line at the same location. Therefore, the controller 200 can send a second type of read command (CMD) to the semiconductor memory device 100. RDB To reduce read time. In one implementation, the controller 200 may send a second type of read command (CMD) to the semiconductor memory device 100. RDB This continues until the error correction operation on the received data is successful. Alternatively, even if the error correction operation on the received data ultimately fails, the controller 200 may send a second type of read command (CMD) to the semiconductor memory device 100. RDB Number of reservations.

[0106] according to Figure 12A As shown, when sending a first type read command (CMD) to the semiconductor memory device 100... RDA Subsequently, the controller 200 can send a second type of read command (CMD) to the semiconductor memory device 100. RDB Three times. Therefore, the semiconductor memory device 100 can perform a total of four read operations. Finally, the controller 200 can send a discharge command CMD to the semiconductor memory device 100. DSC .

[0107] Reference Figure 12BRegarding the voltage applied to the word line, this illustrates the command input to the semiconductor memory device 100 and the corresponding read operation. This can be in response to the first type of read command CMD input. RDA The first read operation is then performed in response to the first type of read command CMD. RDA The first read operation may include a word line discharge operation. That is, the first read operation may include a step of reducing the voltage of the selected word line and the unselected word line to the cutoff voltage.

[0108] In addition, the second input read command can be a second type read command CMD. RDB In response to the second type of read command CMD RDB The second read operation may not include a word line discharge operation. Therefore, even after the second read operation is completed, the word line voltage can remain at the read pass voltage Vpass.

[0109] In addition, the third input read command can be the second type read command CMD. RDB A third read operation can be performed in response to a read command from a third input. Since the word line voltage is maintained even after the preceding second read operation, the channel initialization step can be omitted in the third read operation. Alternatively, the time required for the channel initialization operation can be relatively shortened in the third read operation. Additionally, in response to a second type read command CMD... RDB The third read operation may not include a word line discharge operation. Therefore, even after the third read operation is completed, the word line voltage can remain at the read pass voltage Vpass.

[0110] In addition, the fourth input read command can be the second type read command CMD. RDB The repeated description of the fourth read operation performed in response to the read command of the fourth input has been omitted.

[0111] After performing the fourth read operation, a discharge command CDM can be input to the semiconductor memory device 100. DSC The semiconductor memory device 100 can respond to a discharge command CDM. DSC A cutoff voltage is applied to the word line.

[0112] Figure 13A and Figure 13B This is a diagram illustrating a controller that uses only first-type read commands and the operation of a semiconductor memory device based solely on first-type read commands.

[0113] Reference Figure 13A The controller 200 can first send a first type of read command (CMD) to the semiconductor memory device 100.RDA When used with the first type of read command CMD RDA If the error correction for the corresponding read data fails, a first type read command CMD can be sent again to the semiconductor memory device 100. RDA In one implementation, the controller 200 may send a first type read command (CMD) to the semiconductor memory device 100. RDA This continues until the error correction operation on the received data is successful. Alternatively, even if the error correction operation on the received data ultimately fails, the controller 200 may send a first-type read command (CMD) to the semiconductor memory device 100. RDA Number of reservations.

[0114] according to Figure 13A As shown, the controller 200 can send a first type read command (CMD) to the semiconductor memory device 100. RDA Four times. Therefore, the semiconductor memory device 100 can perform a total of four read operations. Figure 12A Conversely, the controller 200 may not send a discharge command CMD to the semiconductor memory device 100. DSC .

[0115] Reference Figure 13B Regarding the voltage applied to the word line, this illustrates the command input to the semiconductor memory device 100 and the corresponding read operation. This can be in response to the first type of read command CMD input. RDA The first read operation is then performed in response to the first type of read command CMD. RDA The first read operation may include a word line discharge operation. That is, the first read operation may include a step of reducing the voltage of the selected word line and the unselected word line to the cutoff voltage.

[0116] In addition, it can respond to the first type of read command CMD in response to the second input. RDA Then, the second read operation is performed in response to the first type of read command CMD. RDA The second read operation may also include a word line discharge step. This is in response to the first type of read command CMD input on the third and fourth inputs. RDA The semiconductor memory device 100 can repeatedly perform read operations including word line discharge steps. Therefore, the read command CMD of the first type has been omitted. RDA The corresponding read operation is described repeatedly.

[0117] like Figure 13B As shown, when repeatedly executing the first type of read command CMD RDADuring the corresponding read operation, each read operation may include both a word line discharge step and a channel initialization step. As mentioned above, since the RC delay indicated by multiple word lines is relatively large, the time required for the word line discharge operation or the channel initialization operation can also be relatively longer.

[0118] Refer to together Figure 12B and Figure 13B You can see in Figure 12B In the case of a total of four read operations, the time required can be compared to Figure 13B In this case, the total time required for the four read operations in the read operation is short. That is, when it is expected that read operations will be repeated at the same location, this can be achieved by appropriately using the second type of read command CMD, which omits the word line discharge step. RDB This reduces the overall read time.

[0119] Figure 14 This is a flowchart illustrating the operation of a semiconductor memory device according to an embodiment of the present disclosure. (Refer to...) Figure 14 The operation of the semiconductor memory device according to embodiments of the present disclosure may include: receiving a read command from a controller (S110), performing a read operation corresponding to the received read command (S120), and determining whether the received read command is a first type read command (S130). In this case, the operation of the semiconductor memory device may further include: performing a word line discharge operation (S140) when the received read command is a first type read command (S130: yes). Additionally, the operation of the semiconductor memory device may further include: maintaining the word line voltage when the received read command is a second type read command instead of a first type read command (S130: no).

[0120] In step S110, the semiconductor memory device 100 may receive a read command from the controller 200. In response to the received read command and the address corresponding to the read command, the semiconductor memory device 100 may perform a read operation corresponding to the read command (S120). Step S120 may correspond to... Figure 9B During the period from t41 to t46 or in Figure 10B The operations performed during the time period t51 to t56. (Refer to...) Figure 15 Describe the detailed configuration of step S120.

[0121] Subsequently, the semiconductor memory device can determine whether the received read command is a first type read command (S130). When the received read command is a first type read command (S130: Yes), the semiconductor memory device 100 can perform a word line discharge operation (S140). The word line discharge operation in step S140 can correspond to Figure 9BThe time period is from t46 to t47.

[0122] When the received read command is a second type read command (S130: No), the semiconductor memory device 100 may not perform a word line discharge operation and may maintain the voltage of the word line (S150). Step S150 may correspond to Figure 10B The period following time t56.

[0123] Figure 15 This is an example Figure 14 The flowchart shows an exemplary implementation of step S120.

[0124] Reference Figure 15 Executing the read operation corresponding to the received read command (S120) may include: applying a read pass voltage to the word line (S121), applying at least one read voltage to the selected word line, and applying a read pass voltage to the selected word line (S123).

[0125] Applying a read pass voltage to the word line (S121) can correspond to the channel initialization step and can also correspond to the following steps: Figure 9B During the period from t41 to t42 or Figure 10B The operation performed during the time period t51 to t52. Additionally, applying at least one read voltage to the selected word line (S122) can correspond to the threshold voltage sensing step and can also correspond to... Figure 9B During the period from t42 to t45 or Figure 10B The operation performed during the time period t52 to t55. Furthermore, applying a read pass voltage to the selected word line (S123) can correspond to the word line equalization step and can also correspond to... Figure 9B During the period t45 to t46 or Figure 10B The operations performed during the time period t55 to t56.

[0126] Figure 16 This is a flowchart illustrating the operation of a semiconductor memory device according to another embodiment of the present disclosure. Specifically, Figure 16 The steps shown can be performed after a read operation according to a second type of read command to discharge the word line. That is, Figure 16 The steps shown can be performed in Figure 14 Execute after step S150.

[0127] Reference Figure 16 Operation of a semiconductor memory device according to another embodiment of the present disclosure may include: receiving a discharge command CMD from a controller 200. DSC (S210) and in response to the discharge command CMD DSCThen, a word line discharge operation is performed (S220). As described above, the discharge command CMD is received. DSC (S210) can be executed while the word line is held at the read voltage. That is, it can be performed... Figure 14 After step S150, step S210 is executed. Performing the word line discharge operation (S220) can correspond to applying a cutoff voltage to the selected word line and the unselected word line, and can correspond to... Figure 11B The operations performed during the time period t57 to t58.

[0128] Figure 17 This is a flowchart illustrating the operation of a controller according to an embodiment of the present disclosure.

[0129] Reference Figure 17 The operation of controller 200 may include: sending a first type read command (CMD) to the semiconductor memory device. RDA (S310) Data is received from the semiconductor memory device (S320), and it is determined whether the error correction operation on the received data was successful (S330). When the error correction operation on the received data is successful (S330: Yes), the operation of the controller can end.

[0130] When the error correction operation on the received data fails (S330: No), the controller can determine that the semiconductor memory device should re-execute the read operation. Therefore, the controller's operation may further include: when the error correction operation on the received data fails (S330: No), sending a second type of read command CMD to the semiconductor memory device. RDB (S340) Data is received from the semiconductor memory device (S350), and it is determined whether the error correction operation on the received data was successful (S360). When the error correction operation on the received data is successful (S360: Yes), the controller can control the semiconductor memory device to perform a word line discharge operation. Therefore, the controller operation may further include: when the error correction operation on the received data is successful (S360: Yes), sending a discharge command CMD to the semiconductor memory device. DSC (S370).

[0131] When the error correction operation on the received data fails (S360: No), the controller can determine that the semiconductor memory device should re-execute the read operation. Therefore, when the error correction operation on the received data fails (S360: No), the controller 200 can return to step S340 to control the semiconductor memory device to repeat the read operation that omits the word line discharge operation. Figure 17As shown, the process of sending a second type of read command to the semiconductor memory device (S340), receiving data from the semiconductor memory device (S350), and performing an error correction operation on the received data can be repeated until the error correction operation on the received data is successful. Alternatively, the process of sending a second type of read command to the semiconductor memory device (S340), receiving data from the semiconductor memory device (S350), and performing an error correction operation on the received data can be repeated only a predetermined number of times.

[0132] Reference Figure 17 When the error correction operation fails in step S330, a second type of read command can be sent to the semiconductor memory device. However, this is exemplary and the present disclosure is not limited thereto. That is, according to Figure 17 For example, when an error correction operation fails, controller 200 can determine that the semiconductor memory device should re-execute the read operation. However, controller 200 can determine that the semiconductor memory device should re-execute the read operation based on various factors other than error correction failure.

[0133] Figure 18 This is a flowchart illustrating the operation of a controller according to another embodiment of the present disclosure. Figure 18 From and Figure 17 Different viewpoints illustrate flowcharts of the operation of the controller according to this disclosure.

[0134] Reference Figure 18 The controller's operations may include: sending a read command to the semiconductor memory device (S410); receiving data from the semiconductor memory device (S420); determining whether the error correction operation on the received data was successful (S430); when the error correction operation on the received data was successful (S430: Yes), determining whether the read command sent to the semiconductor memory device is a first type read command (S450); when the read command sent to the semiconductor memory device is a second type read command other than the first type read command (S450: No), sending a discharge command CMD to the semiconductor memory device. DSC (S460).

[0135] In step S410, the controller 200 may send a read command to the semiconductor memory device 100. When the read command sent in step S410 is a first type read command, the semiconductor memory device 100 may perform a read operation including a word line discharge step. Furthermore, when the read command sent in step S410 is a second type read command, the semiconductor memory device 100 may perform a read operation without a word line discharge step.

[0136] In step S420, the controller can receive read data from the semiconductor memory device and perform error correction on the received data. Subsequently, in step S430, it can be determined whether the error correction operation on the received data was successful. If the error correction operation fails (S430: No), the operation can return to step S410 to control the semiconductor memory device to perform the read operation again. In step S410, the controller can send a first type of read command to the semiconductor memory device, and can also send a second type of read command to the semiconductor memory device as needed. Steps S410, S420, and S430 can be repeated until the error correction operation on the received data is successful. Alternatively, steps S410, S420, and S430 can be repeated only a predetermined number of times.

[0137] When the error correction operation on the received data is successful (S430: Yes), the controller can determine whether the read command immediately following it sent to the semiconductor memory device 100 is a first-type read command. If the read command sent to the semiconductor memory device is a first-type read command (S450: Yes), the semiconductor memory device can perform a read operation including a word line discharge step. Therefore, the controller can avoid sending a separate discharge command CMD to the semiconductor memory device. DSC And you can end the operation.

[0138] When the read command sent to the semiconductor memory device is a second type read command (S450: No), the semiconductor memory device can perform a read operation without a word line discharge step. In this case, the word lines of the semiconductor memory device can maintain the read pass voltage. Therefore, the controller can send a discharge command CMD to the semiconductor memory device. DSC (S460). When step S460 is executed, the semiconductor memory device 100 may apply a cutoff voltage to the word line to perform a word line discharge operation.

[0139] Figure 19 This is a block diagram illustrating an embodiment of a memory system 1000 including a semiconductor memory device 100 and a controller 200.

[0140] Reference Figure 19 The memory system 1000 may include a semiconductor memory device 100 and a controller 200. The semiconductor memory device 100 may be a reference... Figure 2 The semiconductor memory device described.

[0141] Controller 200 can be connected to both the host computer and the semiconductor memory device 100. Figure 19 In this context, the host can be Figure 1The host device 300 is shown. The controller 200 can be configured to access the semiconductor memory device 100 in response to a request from the host. For example, the controller 200 can be configured to control read operations, write operations, erase operations, and background operations of the semiconductor memory device 100. The controller 200 can be configured to provide an interface between the semiconductor memory device 100 and the host. The controller 200 can be configured to drive firmware for controlling the semiconductor memory device 100.

[0142] The controller 200 may include random access memory (RAM) 210, a processing unit 220, a host interface 230, a memory interface 240, and an error correction block 250. RAM 210 may serve as at least one of the following: operational memory of the processing unit 220, a cache memory between the semiconductor memory device 100 and the host, and a buffer memory between the semiconductor memory device 100 and the host. The processing unit 220 can control the overall operation of the controller 200. Additionally, the controller 200 may temporarily store programming data provided by the host during write operations.

[0143] The host interface 230 may include protocols for performing data exchange between the host and the controller 200. In an exemplary embodiment, the controller 200 may be configured to communicate with the host via at least one of a variety of interface protocols such as: Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, PCI-Fast (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, and proprietary protocols.

[0144] The memory interface 240 can be interfaced with the semiconductor memory device 100. For example, the memory interface 240 may include a NAND interface or a NOR interface.

[0145] Error correction block 250 can be configured to detect and correct errors in data received from semiconductor memory device 100 using error correction codes (ECC). Processing unit 220 can control semiconductor memory device 100 to adjust read voltage and perform reread based on the error detection results of error correction block 250. In an exemplary embodiment, the error correction block can be provided as a component of controller 200.

[0146] The controller 200 and the semiconductor memory device 100 can be integrated into a single semiconductor device. In an exemplary embodiment, the controller 200 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a memory card. For example, the controller 200 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a memory card such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a compact flash memory card (CF), a smart media card (SM or SMC), a memory stick, a multimedia card (MMC, RS-MMC, or micro MMC), an SD card (SD, mini SD, micro SD, or SDHC), and universal flash memory (UFS).

[0147] The controller 200 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a semiconductor drive (solid-state drive (SSD)). The semiconductor drive (SSD) can include a storage device configured to store data in the semiconductor memory. When the memory system 1000 is used as a semiconductor drive (SSD), the operating speed of a host connected to the memory system 1000 can be significantly improved.

[0148] In another example, the memory system 1000 may be configured as one of the components of various electronic devices such as computers, ultra-mobile PCs (UMPCs), workstations, netbooks, personal digital assistants (PDAs), portable computers, network tablets, cordless phones, mobile phones, smartphones, e-books, portable multimedia players (PMPs), portable game consoles, navigation devices, black boxes, digital cameras, 3D televisions, digital audio recorders, digital audio players, digital picture recorders, digital picture players, digital video recorders, and digital video players; a device capable of transmitting and receiving information in a wireless environment; one of the various electronic devices for configuring a home network; one of the various electronic devices for configuring a computer network; one of the various electronic devices for configuring a telematics network; an RFID device; or one of the components for configuring a computing system.

[0149] In exemplary embodiments, the semiconductor memory device 100 or memory system 1000 can be mounted as various types of packages. For example, the semiconductor memory device 100 or memory system 1000 can be packaged and mounted in ways such as: package stack (PoP), ball grid array (BGA), chip-scale package (CSP), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), wafer-in-package, wafer-in-wafer, chip-on-board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat package (MQFP), thin quad flat package (TQFP), small outline integrated circuit package (SOIC), shrink small outline package (SSOP), thin small outline package (TSOP), system-in-package (SIP), multi-chip package (MCP), wafer-level fabrication package (WFP), or wafer-level fabrication stack-up package (WSP).

[0150] Figure 20 This is an example Figure 19 A block diagram illustrating an application example of a memory system.

[0151] Reference Figure 20 The memory system 2000 may include a semiconductor memory device 2100 and a controller 2200. The semiconductor memory device 2100 may include multiple semiconductor memory chips. The multiple semiconductor memory chips may be divided into multiple groups.

[0152] exist Figure 20 In this process, multiple groups can communicate with the controller 2200 via channels CH1 to CHk, respectively. Each semiconductor memory chip can communicate with a reference... Figure 2 The semiconductor memory device 100 described is similarly configured and can operate similarly thereto.

[0153] Each group can be configured to communicate with controller 2200 via a common channel. Controller 2200 can communicate with reference to... Figure 19 The controller 200 described is similarly configured and can be configured to control multiple memory chips of the semiconductor memory device 2100 via multiple channels CH1 to CHk.

[0154] Figure 21 This illustrates the example including references. Figure 20 A block diagram of the computing system describing the memory system.

[0155] The computing system 3000 includes a central processing unit 3100, random access memory (RAM) 3200, a user interface 3300, a power supply 3400, a system bus 3500, and a memory system 2000.

[0156] The memory system 2000 can be electrically connected to the central processing unit 3100, RAM 3200, user interface 3300, and power supply 3400 via the system bus 3500. Data provided through the user interface 3300 or processed by the central processing unit 3100 is stored in the memory system 2000.

[0157] exist Figure 21 In this configuration, the semiconductor memory device 2100 can be connected to the system bus 3500 via the controller 2200. However, the semiconductor memory device 2100 can also be configured to be directly connected to the system bus 3500. In this case, the functions of the controller 2200 can be performed by the central processing unit 3100 and the RAM 3200.

[0158] exist Figure 21 The middle provides a reference. Figure 20 The memory system 2000 is described. However, the memory system 2000 can be referenced... Figure 19 The memory system 1000 described is used instead. In an exemplary embodiment, the computing system 3000 may be configured to include reference... Figure 19 The described memory system 1000 and reference Figure 20 The memory system described in 2000 is both.

[0159] Cross-references to related applications

[0160] This application claims priority to Korean Patent Application No. 10-2022-0063740, filed on May 24, 2022, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: A memory cell array comprising multiple memory cells; Peripheral circuitry that performs a read operation on a selected memory cell among the plurality of memory cells; as well as The control logic controls the read operation of the peripheral circuitry in response to a read command received from an external device, and determines whether to perform a word line discharge operation on multiple word lines connected to the plurality of memory cells based on the type of the read command. During the word line discharge operation, the voltage of the multiple word lines is reduced to ground voltage. The read command has a first type for discharging the plurality of word lines or a second type for skipping the discharge of the plurality of word lines. Specifically, if the error correction operation of the data read in the read operation executed by the first type of read command fails, a second type of read command is received.

2. The semiconductor memory device according to claim 1, wherein, The control logic controls the peripheral circuitry to perform a channel initialization operation by applying a first voltage to the plurality of word lines in response to the read command, to perform a threshold voltage sensing operation by applying at least one read voltage to the selected word line among the plurality of word lines connected to the selected memory cell, and to perform a word line equalization operation by applying a second voltage to the plurality of word lines.

3. The semiconductor memory device according to claim 2, wherein, In response to determining that the read command is the first type of read command, the control logic controls the peripheral circuitry to perform the word line discharge operation by applying a third voltage lower than the second voltage to the plurality of word lines after the word line equalization operation.

4. The semiconductor memory device according to claim 3, wherein, The first voltage is a read pass voltage that is higher than the at least one read voltage, and The second voltage is the same as the first voltage.

5. The semiconductor memory device according to claim 4, wherein, The third voltage is the ground voltage.

6. The semiconductor memory device according to claim 2, wherein, The control logic controls the peripheral circuitry to apply the first read voltage to the Nth read voltage to the selected word line in the order of lowest to highest voltage among the first read voltage to the Nth read voltage during the threshold voltage sensing operation, where N is a natural number greater than 1.

7. The semiconductor memory device according to claim 2, wherein, The control logic controls the peripheral circuitry to apply the first read voltage to the Nth read voltage to the selected word line in the order of the highest to the lowest voltage among the first read voltage to the Nth read voltage during the threshold voltage sensing operation, where N is a natural number greater than 1.

8. The semiconductor memory device according to claim 2, wherein, In response to determining that the read command is the second type of read command, the control logic controls the peripheral circuitry to maintain the voltage of the multiple word lines after the word line equalization operation.

9. The semiconductor memory device according to claim 8, wherein, In response to a discharge command received from the external device while maintaining the voltage of the plurality of word lines, the control logic controls the peripheral circuitry to perform the word line discharge operation by applying a third voltage, which is lower than the second voltage, to the plurality of word lines.

10. A method of operating a semiconductor memory device comprising a plurality of memory cells, the method comprising the steps of: Receive a first read command of the first type from an external device; Data is read from a selected memory cell among the plurality of memory cells in response to the first read command; Perform error correction on the data read in the read operation executed by the first read command; as well as When the error correction operation fails, a second read command of the second type is received from the external device. In response to the first read command, multiple word lines connected to the memory cell are discharged, and the discharged word lines have a ground voltage. In response to the second read command, the discharge of the multiple word lines is skipped.

11. The method according to claim 10, wherein, The step of reading data from a selected memory cell among the plurality of memory cells in response to the first read command or the second read command includes the following steps: Channel initialization is performed by applying a first voltage to the plurality of word lines in response to the first read command; A threshold voltage sensing operation is performed by applying at least one read voltage to a selected word line among the plurality of word lines connected to the selected memory cell; and Word line equalization is performed by applying a second voltage to the multiple word lines.

12. The method according to claim 11, wherein, In response to the first read command, after the word line equalization operation, a word line discharge operation is performed by applying a third voltage, which is lower than the second voltage, to the plurality of word lines.

13. The method according to claim 12, wherein, The first voltage is a read pass voltage that is higher than the at least one read voltage, and The second voltage is the same as the first voltage.

14. The method according to claim 13, wherein, The third voltage is the ground voltage.

15. The method according to claim 11, wherein, In response to the second read command, the voltage of the multiple word lines is maintained after the word line equalization operation.

16. The method of claim 15, further comprising the step of: After maintaining the voltage of the multiple word lines: Receive a discharge command from the external device; as well as A word line discharge operation is performed by applying a third voltage, lower than the second voltage, to the plurality of word lines in response to the discharge command.

17. A method of operating a controller for controlling read operations of a semiconductor memory device comprising a plurality of memory cells, the method comprising the steps of: Send one of a first type of read command and a second type of read command to the semiconductor memory device; Receive data from the semiconductor memory device; Based on the type of the read command sent to the semiconductor memory device, determine whether to send a discharge command to the semiconductor memory device; as well as The read operation is performed by applying a pass voltage to the selected word line and then applying a read voltage that is lower than the pass voltage and gradually decreases. The first type of read command controls the semiconductor memory device to perform a read operation, including a word line discharge operation that reduces the voltage of multiple word lines to ground voltage, after applying the read voltage to the selected word line. The second type of read command controls the semiconductor memory device to perform a read operation without word line discharge after the read voltage is applied to the selected word line, and In response to the failure of error correction operation on the data read by the first type of read command, a second type of read command is sent to the semiconductor memory device.

18. The method according to claim 17, wherein, The step of determining whether to send the discharge command to the semiconductor memory device based on the type of the read command includes the following steps: when the read command is the second type of read command, sending the discharge command to the semiconductor memory device to control the semiconductor memory device to perform the word line discharge operation.

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