Method for manufacturing a chip and chip

Abstract

The application provides a chip preparation method and a chip. The chip preparation method comprises the following steps: manufacturing a plurality of first grooves which are distributed at intervals on a surface of a wafer close to a first orientation; manufacturing a first plastic sealing layer on one side of the wafer close to the first orientation, and the first plastic sealing layer fills the first grooves. Thus, the first plastic sealing layer can be used as a carrier to perform a first grinding treatment on a surface of the wafer close to a second orientation, so as to thin the wafer and expose the first grooves and the first plastic sealing layer in the first grooves on a first grinding surface of the wafer formed by the first grinding treatment. The grinding treatment does not need to use a special carrier, and the cost can be reduced. A second groove is manufactured on the first plastic sealing layer exposed in the first grooves on the first grinding surface, that is, after the wafer is thinned, the wafer is not directly sliced, but the slicing is realized by manufacturing the second groove on the first plastic sealing layer in the first grooves, so that the risks of back edge collapse, wafer warping and fragments of the wafer during slicing can be avoided.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a method for fabricating a chip and the chip itself. Background Technology

[0002] The realization of ultrathin wafers currently commonly employs temporary bonding and debonding technology. This involves temporarily bonding the wafer to a carrier to provide strength support, performing back-side thinning, debonding, and then directly slicing the thinned wafer. This process requires temporary bonding and debonding, utilizes specific carriers, and is complex and costly. Furthermore, due to the extremely thin wafer, direct slicing can easily lead to risks such as back-side chipping, wafer warping, and fragmentation. Summary of the Invention

[0003] The main objective of this application is to propose a chip fabrication method. The method involves first pre-cutting to form a first groove, then molding to obtain a first molding layer, and finally using the first molding layer as a carrier to grind and thin the wafer before slicing along the first groove. This reduces costs while avoiding the risks of back-side chipping, wafer warping, and fragmentation during slicing.

[0004] To achieve the above objectives, a first aspect of this application provides a method for fabricating a chip using a wafer, wherein one side of the wafer along the thickness direction is a first orientation, and the other side of the wafer along the thickness direction is a second orientation. The method includes the following steps: A plurality of first grooves are formed at intervals on the surface of the wafer near the first orientation; A first molding compound is formed on the side of the wafer near the first orientation, and the first molding compound fills the first groove; A first grinding process is performed on the surface of the wafer near the second position to thin the wafer and expose the first groove and the first molding layer in the first groove on the first grinding surface formed by the first grinding process. A second groove is made in the first groove of the first molding compound exposed on the first grinding surface. The depth of the second groove is greater than or equal to the thickness of the wafer after the first grinding process, and less than the total thickness of the first molding compound. A second grinding process is performed on the surface of the first molding layer near the first orientation until the wafer and the second groove are exposed on the surface of the first molding layer near the first orientation, so that the wafer is broken along the second groove to form a plurality of wafer units.

[0005] In one embodiment of this application, a chip electrode is disposed on the surface of the wafer near the first orientation. Before the step of forming a first molding compound layer on the side of the wafer near the first orientation, the method further includes: Metal bumps are fabricated on the chip electrodes of the wafer; In this process, after the step of fabricating metal bumps on the chip electrodes of the wafer, all wafers are wafers with the metal bumps. In the step of performing a second grinding process on the surface of the first molding layer near the first orientation, the second grinding process is performed until the metal protrusion and the second groove are exposed on the surface of the first molding layer near the first orientation.

[0006] In one embodiment of this application, the step of forming metal bumps on the chip electrodes of the wafer is performed after the step of forming a plurality of spaced-apart first grooves on the surface of the wafer near the first orientation.

[0007] In one embodiment of this application, after performing a second polishing process on the surface of the first molding layer near the first orientation, the method further includes: A film expansion process is performed between adjacent wafer units to form a first gap between them. The wafer monomers after the film expansion treatment are bonded so that the metal protrusions of the two wafer monomers distributed on both sides of the first gap are connected together along the bonding member. The structure after bonding is cut along the location of the bonded component.

[0008] In one embodiment of this application, bonding processing is performed on the wafer monomers after the film expansion treatment, including: A second molding layer is formed on the side of the plurality of wafer units near the second orientation and between adjacent wafer units; The metal protrusions of the two wafer units distributed on both sides of the first gap are connected together by a bonding component; A third molding compound is formed on one side of the plurality of wafer units near the first orientation. The third molding compound covers the bonding points of the bonding components and the metal protrusions, and a portion of the bonding components are exposed on the surface of the third molding compound.

[0009] In one embodiment of this application, the first molding layer includes a resin material layer.

[0010] In one embodiment of this application, the first groove is formed by cutting the wafer; The second groove is formed by cutting the wafer.

[0011] In one embodiment of this application, the depth of the first groove is greater than or equal to the thickness of the wafer in the finished chip, which is less than the thickness of the wafer in the step of forming the first groove on the surface of the wafer near the first orientation.

[0012] A second aspect of this application provides a chip manufactured by the fabrication method described in any embodiment of this application, the chip comprising: a wafer, chip electrodes, metal bumps, and a first molding layer; The wafer has a first surface formed at one end along the thickness direction and a second surface formed at the other end along the thickness direction. The chip electrode is disposed on the first surface, and the metal protrusion is disposed on the side of the chip electrode opposite to the wafer. The first molding compound covers the side of the wafer and the first surface. The chip electrode and the metal protrusion are embedded in the first molding compound on the first surface. The end of the metal protrusion away from the chip electrode is exposed on the surface of the first molding compound.

[0013] In one embodiment of this application, the chip further includes a bonding member, a second molding compound, and a third molding compound. The bonding member is connected to the metal protrusion. The second molding compound covers the second surface of the wafer and the first molding compound on the side surface of the wafer. The third molding compound is disposed on the first molding compound on the first surface of the wafer and covers the bonding points between the bonding member and the metal protrusion. A portion of the bonding member is exposed on the surface of the third molding compound.

[0014] In the technical solution provided in this application embodiment, a chip is fabricated using a wafer, wherein one side of the wafer along the thickness direction is a first orientation, and the other side of the wafer along the thickness direction is a second orientation. The fabrication method includes creating a plurality of spaced-apart first grooves on the surface of the wafer near the first orientation, and then creating a first molding compound layer on the side of the wafer near the first orientation, with the first molding compound layer filling the first grooves. Thus, the first molding compound layer can be used as a carrier to perform a first polishing process on the surface of the wafer near the second orientation, thereby thinning the wafer and exposing the first grooves and the first molding compound layer within the first grooves on the first polished surface formed by the first polishing process. This eliminates the need for additional specific carrier wafers for polishing, reducing costs. Furthermore, polishing can be performed directly using the first molding compound layer as a carrier, which is simpler than traditional polishing processes that require temporary bonding and debonding. A second groove is created within the first groove of the first polished surface, the depth of which is greater than or equal to the thickness of the wafer after the first polishing process, and less than the total thickness of the first molding compound layer. That is, after the wafer is thinned, the wafer is no longer sliced ​​directly. Instead, the slicing is completed by creating a second groove in the first groove of the first molding layer exposed on the first grinding surface. This can avoid the risk of back-side chipping, wafer warping and fragmentation during slicing. Attached Figure Description

[0015] Figure 1 This is a flowchart of a chip fabrication method provided in an embodiment of this application; Figure 2 This is a schematic diagram of the state corresponding to the step of creating a plurality of spaced first grooves on the surface of a wafer near the first position, as provided in an embodiment of this application. Figure 3 This is a schematic diagram of the state corresponding to the step of fabricating the first molding layer on the side of the wafer close to the first position, as provided in the embodiments of this application; Figure 4 This is a schematic diagram of the state of the wafer after the first grinding process is performed on the surface of the wafer near the second position, as provided in an embodiment of this application. Figure 5 This is a schematic diagram of the state corresponding to the step of creating a second groove for the first encapsulation layer exposed in the first groove of the first grinding surface, provided in the embodiments of this application; Figure 6 This is a schematic diagram of the state of performing a second grinding process on the surface of the first molding layer near the first position, provided in an embodiment of this application; Figure 7 This is a flowchart of the steps performed after the second grinding process is performed on the surface of the first molding layer near the first position, as provided in an embodiment of this application. Figure 8This is a schematic diagram of the state corresponding to the film expansion process between adjacent wafer units provided in the embodiments of this application; Figure 9 This is a flowchart of the steps for bonding wafer monomers after the film expansion process provided in the embodiments of this application; Figure 10 This is a schematic diagram of the state corresponding to the fabrication of a second molding compound layer on one side of multiple wafer units near the second position and between adjacent wafer units, provided in the embodiments of this application. Figure 11 This is a schematic diagram of the state corresponding to the metal protrusions of two wafer units distributed on both sides of the first gap being connected together by a bonding component, as provided in the embodiments of this application. Figure 12 This is a schematic diagram of the state corresponding to the fabrication of a third molding compound layer on one side of multiple wafer units near the first position, provided in an embodiment of this application. Figure 13 This is a schematic diagram of the state corresponding to the cutting of the structure after bonding treatment along the position of the bonded component, provided in the embodiments of this application; Figure 14 This is a schematic diagram of the chip structure provided in the embodiments of this application; Figure 15 This is another schematic diagram of the chip structure provided in the embodiments of this application.

[0016] Explanation of reference numerals in the attached figures: Wafer - 10; First orientation - 20; Second orientation - 30; Surface of wafer near the first orientation - 11; First groove - 111; First molding layer - 13; Chip electrode - 14; Metal bump - 15; Surface of wafer near the second orientation - 12; First polished surface - 121; Second groove - 131; Wafer unit - 101; First gap - 60; Second molding layer - 16; Bonding component - 17; Third molding layer - 18. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0018] It should be noted that although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart. The terms "first," "second," etc., in the specification, claims, and the aforementioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0020] Integrated circuit chips are constantly evolving towards higher density, higher performance, and thinner and smaller dimensions. To meet the requirements of IC (chip) packaging, the thickness of chips is constantly decreasing. In the chip manufacturing process, it is necessary to thin the back of the wafer and slice it.

[0021] The realization of ultrathin wafers currently commonly employs temporary bonding and debonding technology. This involves temporarily bonding the wafer to a carrier to provide strength support, performing back-side thinning, debonding, and then directly slicing the thinned wafer. This process requires temporary bonding and debonding, utilizes specific carriers, and is complex and costly. Furthermore, due to the extremely thin wafer, direct slicing can easily lead to risks such as back-side chipping, wafer warping, and fragmentation.

[0022] Based on this, refer to Figure 1 , Figure 1 This is a flowchart illustrating a chip fabrication method provided in an embodiment of this application. The fabrication method is used to fabricate a chip using a wafer, and includes, but is not limited to, steps S110 to S150.

[0023] Step S110: A plurality of first grooves are formed on the surface of the wafer near the first orientation.

[0024] In the embodiments of this application, reference is made to Figure 2 , Figure 2 This is a schematic diagram of the state corresponding to the step of fabricating a plurality of spaced-apart first grooves on the surface of a wafer near a first position, as provided in an embodiment of this application. Figure 2 As shown, one side of wafer 10 along the thickness direction is designated as the first orientation 20, and the other side along the thickness direction is designated as the second orientation 30. The thickness direction is perpendicular to the wafer surface, and the first orientation 20 and the second orientation 30 are opposite orientations. For example, if the first orientation 20 is above, then the second orientation 30 is below. If the first orientation 20 is to the left, then the second orientation 30 is to the right. Figure 2 As shown, when wafer 10 is placed horizontally, the first orientation 20 represents the top, and the second orientation 30 represents the bottom. Therefore, the surface 11 of wafer 10 closest to the first orientation 20 is the top surface of the wafer.

[0025] It should be noted that in step S110 of this embodiment, the wafer is a wafer after a metal layer has been deposited on its surface, and the metal layer has been chemically and mechanically polished to remove excess metal and obtain a smooth surface. Therefore, further wafer slicing and packaging processes are required to prepare a single chip.

[0026] In the embodiments of this application, such as Figure 2 As shown, a plurality of first grooves 111 are formed on the surface 11 of the wafer 10 near the first orientation 20. Specifically, the surface 11 of the wafer 10 near the first orientation 20 has scribe lines that are formed at intervals. Forming the first grooves 111 on the scribe lines at intervals will not damage the circuit.

[0027] Wherein, the depth of the first groove is greater than or equal to the thickness of the wafer in the finished chip, but less than the thickness of the wafer in the step of creating the first groove on the surface of the wafer near the first position. For example... Figure 2 As shown, the depth of the first groove 111 is less than the thickness of the wafer 10 in its current state. That is, the wafer 10 is pre-cut by creating the first groove 111, but the wafer in its current state cannot be completely cut. Simultaneously, the thickness of the wafer in the finished chip needs to be determined in advance. When creating the first groove 111, the depth of the first groove 111 needs to be greater than or equal to the thickness of the wafer in the finished chip, so that pre-cutting can be performed before wafer thinning, i.e., when the wafer is relatively thick. Because the wafer is relatively thick, the risk of wafer backside chipping, wafer warping, and fragmentation can be reduced during the creation of the first groove 111.

[0028] In one embodiment of this application, the first groove is formed by cutting a wafer.

[0029] For example, the cutting width and cutting depth of the first groove 111 are determined. In a general wafer dicing process, a single-axis or dual-axis dicing machine is used to cut along the dicing tracks spaced apart on the surface 11 of the wafer 10 near the first orientation 20 to obtain a plurality of spaced first grooves 111.

[0030] Step S120: A first molding layer is formed on the side of the wafer close to the first position, and the first molding layer fills the first groove.

[0031] In the embodiments of this application, reference is made to Figure 3 , Figure 3 This is a schematic diagram showing the state corresponding to the step of fabricating the first molding compound layer on the side of the wafer closest to the first position, as provided in the embodiments of this application. Figure 3As shown, after a plurality of first grooves 111 are formed on the surface 11 of the wafer 10 near the first orientation 20, a first molding compound 13 is formed on the side of the wafer 10 near the first orientation 20, and the first molding compound 13 fills the first grooves 111.

[0032] For example, a wafer coating stage can be used to uniformly coat a molding compound, such as epoxy resin or polyimide, on the side of the wafer 10 near the first orientation 20 to completely cover the surface 11 of the wafer 10 near the first orientation 20 and fill the first groove 111, forming a first molding layer 13.

[0033] In one embodiment of this application, the first molding layer is a resin material layer.

[0034] In this embodiment, the first molding layer is made of resin material. Since the stress of the resin material matches the stress of the chip, the risk of wafer warping during polishing can be reduced when the first molding layer is used as the carrier layer for polishing.

[0035] In one embodiment of this application, such as Figure 3 As shown, a chip electrode 14 is disposed on the surface 11 of the wafer 10 near the first orientation 20. Before the step of fabricating the first molding compound 13 on the side of the wafer 10 near the first orientation 20, the fabrication method further includes: Metal bumps 15 are fabricated on the chip electrode 14 of wafer 10. Thus, after the step of fabricating metal bumps 15 on the chip electrode 14 of wafer 10, wafer 10 is a wafer with metal bumps 15.

[0036] For example, a photoresist layer, such as PI, BCB, or other photosensitive materials, is first coated on the surface of wafer 10 to form a photoresist layer. Then, a solder resist layer, such as a thermosetting solder resist, is coated to form a solder resist layer. After curing, a windowing process is performed on the surface 11 of wafer 10 near the first orientation 20 where the metal bump 15 is grown, to obtain the windowed position. Then, solder is applied to the surface 11 of wafer 10 near the first orientation 20 using printing technology. The solder composition is a tin-lead-silver alloy. The reflow soldering temperature varies slightly depending on the solder composition, with a peak temperature between 220 and 260°C (lower temperature for leaded solder and higher temperature for lead-free solder). Under the action of the solder resist, a metal bump 15 will form at the windowed position. Finally, the solder resist layer and photoresist layer are removed.

[0037] Exemplarily, in this embodiment of the application, another method for fabricating metal bumps 15 on the chip electrode 14 of wafer 10 includes: firstly coating a photoresist layer on the surface of wafer 10, such as coating PI, BCB or other photosensitive materials, to form a photoresist layer; performing a windowing process on the surface 11 of wafer 10 near the first orientation 20 where the metal bumps 15 are grown to obtain the windowed position; immersing the windowed wafer 10 in a prepared electroplating solution and electroplating it, thereby forming metal bumps 15 at the windowed position, the metal composition of which is generally copper, gold, tin, etc.; after electroplating, the photoresist layer is removed.

[0038] In the embodiments of this application, such as Figure 3 As shown, before step S120, that is, before the step of forming the first molding compound 13 on the side of wafer 10 near the first orientation 20, a metal bump 15 has already been formed on the chip electrode 14 of wafer 10. Therefore, the wafer 10 in step 1110 is a wafer with the metal bump 15. Thus, in step S120, that is, during the process of forming the first molding compound 13 on the side of wafer 10 near the first orientation 20, the molding compound needs to completely cover the metal bump 15 and be higher than the metal bump 15 by a predetermined height, such as 50 to 200 μm.

[0039] In this embodiment, by completely covering the metal protrusion 15 with the first molding layer 13 and extending it above the metal protrusion 15 by a predetermined height, the metal protrusion 15 can be effectively protected when the first molding layer 13 is used as a grinding carrier layer to perform the first grinding process on the surface 12 of the wafer 10 near the second orientation 30.

[0040] In one embodiment of this application, the step of creating metal bumps on the chip electrodes of the wafer is performed after the step of creating a plurality of spaced first grooves on the surface of the wafer near a first orientation.

[0041] In this embodiment, considering that the metal bump 15 has a certain thickness, fabricating the metal bump 15 on the chip electrode 14 of the wafer 10 would make it difficult to cut and fabricate the first groove 111. Specifically, the dicing blade might easily collide with the metal bump 15 during wafer 10 stepping, and the dicing blade needs to be lengthened to reach the same cutting depth due to the presence of the metal bump 15. Therefore, the step of fabricating the metal bump on the chip electrode of the wafer is placed before step S120 but after step S110, i.e., between steps S110 and S120. That is, after fabricating a plurality of spaced-apart first grooves 111 on the surface 11 of the wafer 10 near the first orientation 20, the metal bump 15 is then fabricated on the chip electrode 14 of the wafer 10. Thus, since the metal bump 15 has not yet been formed on the wafer 10 when pre-cutting to form the first groove 111 is performed in step S110, it facilitates the smooth progress of pre-cutting.

[0042] It should be noted that in order to fabricate the metal bumps 15 on the chip electrode 14 of the wafer 10, a base layer for the metal bumps 15 needs to be formed on the chip electrode 14 of the wafer 10 before step S110, that is, before fabricating a plurality of spaced first grooves 111 on the surface 11 of the wafer 10 near the first orientation 20.

[0043] For example, a metal layer is sputtered on wafer 10 to form an under-bump metal layer (UBM) as the base layer for the metal bump 15. The material of the under-bump metal layer is selected from copper, chromium, titanium, nickel, titanium-tungsten alloy, chromium-copper alloy, nickel-gold alloy, or a combination of the above materials. In addition to serving as the base layer for the metal bump 15, the under-bump metal layer also acts as an effective diffusion barrier layer between the wafer and the bump, improving the device's quality and reliability.

[0044] Step S130: Perform a first grinding process on the surface of the wafer near the second position to thin the wafer and expose the first groove and the first molding compound layer in the first groove on the first grinding surface formed by the first grinding process.

[0045] In this embodiment, a first molding compound 13 is formed on the side of the wafer 10 near the first orientation 20. After the first molding compound 13 fills the first groove 111, the first molding compound 13 is used as the carrier layer for grinding, and the surface 12 of the wafer 10 near the second orientation 30 is subjected to a first grinding process. (Refer to...) Figure 4 , Figure 4 This is a schematic diagram showing the state of the wafer after the first polishing process is performed on the surface near the second position, as provided in an embodiment of this application. Figure 4 As shown, by performing a first grinding process on the surface 12 of the wafer 10 near the second orientation 30, the wafer 10 can be thinned, and the first groove 111 and the first molding compound 13 within the first groove 111 are exposed on the first grinding surface 121 formed by the first grinding process of the wafer 10.

[0046] For example, in this embodiment of the application, the first molding layer 13 is used as the carrier layer for grinding. First, a grinding machine is used to mechanically grind and thin it, and then the surface stress damage layer is removed by chemical etching (HF+HNO3). Grinding is required until the first groove 111 and the first molding layer 13 in the first groove 111 are exposed on the first grinding surface 121 formed by the first grinding process of the wafer 10.

[0047] In this embodiment, the first plastic sealing layer 13 is used as the grinding carrier layer for grinding and thinning, which means that no additional carrier is needed, no material waste is generated, the cost can be reduced, and the thickness can be reduced to a thinner thickness.

[0048] Step S140: Create a second groove for the first molding compound exposed in the first groove of the first grinding surface. The depth of the second groove is greater than or equal to the thickness of the wafer after the first grinding process, and less than the total thickness of the first molding compound.

[0049] In the embodiments of this application, reference is made to Figure 5 , Figure 5 This is a schematic diagram of the state corresponding to the step of creating a second groove for the first molding compound layer exposed in the first groove of the first polishing surface provided in the embodiments of this application. Because step S130 involves performing a first polishing process on the surface 12 of the wafer 10 near the second orientation 30, the first groove 111 and the first molding compound layer 13 within the first groove 111 are exposed on the first polishing surface 121 formed by the first polishing process of the wafer 10. Therefore, by… Figure 5 As shown, a second groove 131 can be directly fabricated in the first molding compound 13 exposed in the first groove 111 of the first polishing surface 121. The depth of the second groove 131 is greater than or equal to the thickness of the wafer 10 after the first polishing process, and less than the total thickness of the first molding compound.

[0050] In this embodiment, after the first grinding process, the thickness of wafer 10 becomes very thin. Since wafer 10 was pre-cut before the first grinding process (when the wafer thickness was relatively thick), after the first grinding process, only a second groove 131 needs to be made in the first molding compound 13 exposed in the first groove 111 of the first grinding surface 121 to achieve slicing of each individual wafer. That is, after the wafer 10 is thinned by grinding, slicing of wafer 10 is no longer necessary, avoiding the risk of back-side chipping, wafer warping, and fragmentation during slicing.

[0051] In one embodiment of this application, the second groove 131 is formed by cutting a wafer.

[0052] For example, using the first molding compound 13 exposed in the first groove 111 of the first polishing surface 121 as the cutting path, a second groove 131 is cut out using a dicing machine. The depth of the second groove 131 is greater than or equal to the thickness of the wafer 10 after the first polishing process, and less than the total thickness of the first molding compound 13. This ensures the separation of individual wafer units while preventing the wafer 10 with the first molding compound 13 from being completely cut off in this step.

[0053] Step S150: Perform a second grinding process on the surface of the first molding layer near the first orientation until the wafer and the second groove are exposed on the surface of the first molding layer near the first orientation, so that the wafer is broken along the second groove to form multiple wafer units.

[0054] In the embodiments of this application, reference is made to Figure 6 , Figure 6This is a schematic diagram illustrating the state of a second grinding process performed on the surface of the first molding layer near the first orientation, as provided in an embodiment of this application. Figure 6 As shown, after the second groove 131 is made in the first groove 111 of the first molding layer 13 exposed in the first grinding surface 121, the surface of the first molding layer 13 near the first orientation 20 is subjected to a second grinding process until the wafer 10 and the second groove 131 are exposed on the surface of the first molding layer 13 near the first orientation 20, so that the wafer 10 is broken along the second groove 131 to form a plurality of wafer units 101.

[0055] It should be noted that since both the wafer 10 in step S120 and the wafer 10 after step S120 are wafers with metal bumps 15, a second grinding process is performed on the surface of the first molding compound 13 near the first orientation 20 until the wafer 10 and the second groove 131 are exposed on the surface of the first molding compound 13 near the first orientation 20. Thus, the wafer 10 is broken along the second groove 131 to form multiple wafer units 101.

[0056] For example, a blue film is adhered to the first grinding surface 121 and attached to a metal frame. A wafer polishing machine is used to polish and thin the surface of the first molding compound 13 near the first orientation 20. The polishing process is related to the polishing speed, polishing wheel type, etc. The polishing speed under the corresponding process conditions can be obtained through experiments. Based on the thickness of the first molding compound 13 and the height of the metal protrusion 15, the thickness of the first molding compound 13 to be polished off can be obtained. Dividing this value by the polishing speed gives the polishing time required. Thus, the wafer polishing machine can be controlled to polish the surface of the first molding compound 13 near the first orientation 20 within this time. During the polishing process, it is necessary to observe whether the metal protrusion 15 and the second groove 131 are exposed on the surface of the first molding compound 13 near the first orientation 20.

[0057] In this embodiment, a plurality of first grooves are formed at intervals on the surface of the wafer near the first position. A first molding compound is then formed on the side of the wafer near the first position, and the first molding compound fills the first grooves. Thus, the first molding compound can be used as a carrier to perform a first grinding process on the surface of the wafer near the second position, thereby thinning the wafer and exposing the first grooves and the first molding compound within the first grooves on the first grinding surface formed by the first grinding process. This eliminates the need for additional specific carrier wafers for grinding, reducing costs. Furthermore, grinding can be performed directly using the first molding compound as a carrier, which is simpler than traditional grinding processes that require temporary bonding and debonding. A second groove is formed in the first groove exposed on the first grinding surface, the depth of which is greater than or equal to the thickness of the wafer after the first grinding process, and less than the total thickness of the first molding compound. That is, after the wafer is thinned, the wafer is no longer sliced ​​directly. Instead, the slicing is completed by creating a second groove in the first groove of the first molding layer exposed on the first grinding surface. This can avoid the risk of back-side chipping, wafer warping and fragmentation during slicing.

[0058] In one embodiment of this application, reference is made to Figure 7 , Figure 7 This is a flowchart of the steps performed after the second grinding process is performed on the surface of the first molding layer near the first position, as provided in the embodiments of this application, including but not limited to steps S710 to S730.

[0059] Step S710: Perform a film expansion process between adjacent wafer units to form a first gap between adjacent wafer units.

[0060] In the embodiments of this application, reference is made to Figure 8 , Figure 8 This is a schematic diagram illustrating the states corresponding to the film expansion process between adjacent wafer monomers provided in an embodiment of this application. Figure 8 As shown, after the second grinding process is performed on the surface of the first molding layer 13 near the first orientation 20, a film expansion process can be performed between adjacent wafer units 101 to form a first gap 60 between adjacent wafer units 101.

[0061] For example, a wafer expansion machine is used to expand the wafer unit 101 attached to the blue film by utilizing the extensibility of the blue film attached to the first polishing surface 121, so as to meet the pitch requirements of the finished chip.

[0062] Step S720: The wafer monomers after the film expansion process are bonded so that the metal protrusions of the two wafer monomers distributed on both sides of the first gap are connected together along the bonding member.

[0063] In this embodiment of the application, after the film expansion process is performed between adjacent wafer monomers 101, the wafer monomers 101 after the film expansion process are further bonded so that the metal protrusions 15 of the two wafer monomers 101 distributed on both sides of the first gap 60 are connected together along the bonding member 17.

[0064] In one embodiment of this application, reference is made to Figure 9 , Figure 9 This is a flowchart of the steps for bonding wafer monomers after film expansion processing provided in the embodiments of this application, including but not limited to steps S910 to S930.

[0065] Step S910: A second molding layer is formed on the side of the plurality of wafer units near the second orientation and between adjacent wafer units.

[0066] In the embodiments of this application, reference is made to Figure 10 , Figure 10 This is a schematic diagram illustrating the state of fabricating a second molding compound layer on one side of multiple wafer units near the second orientation and between adjacent wafer units, as provided in an embodiment of this application. Figure 10 As shown, after performing a film expansion process between adjacent wafer units 101, a second molding compound 16 is formed on the side of the plurality of wafer units 101 near the second orientation 30 and between adjacent wafer units 101. That is, the exposed first polished surface 121 and adjacent wafer units 101 are first molded together by the second molding compound 16, which can more firmly connect the plurality of wafer units 101.

[0067] It should be noted that the materials used for the second molding layer 16 and the first molding layer 13 are different. The first molding layer 13 mainly considers whether it matches the stress of the chip, and therefore requires the selection of materials with a high degree of stress matching. However, as the outermost layer of the final chip molding, the second molding layer 16 must consider both stress and hermeticity. That is, the stress matching degree can be slightly reduced, but materials with good hermeticity must be used.

[0068] In step S920, the metal protrusions of the two wafer units distributed on both sides of the first gap are connected together by a bonding component.

[0069] In the embodiments of this application, reference is made to Figure 11 , Figure 11 This is a schematic diagram illustrating the state in which metal protrusions of two wafer monomers distributed on both sides of a first gap are connected together by a bonding component, as provided in an embodiment of this application. Figure 11 As shown, since the second molding layer 16 firmly connects multiple wafer units 101, the metal protrusions 15 of two wafer units 101 distributed on both sides of the first gap 60 can be connected together by the bonding member 17.

[0070] For example, the bonding component 17 is a pre-designed electrode sheet that matches the wafer 10. A layer of flux is sprayed on the electrode sheet and then a layer of solder is coated on it. The electrode sheet is precisely aligned with the metal protrusions 15 of the two wafer units 101 on both sides of the first gap 60, and then clamped with a jig and placed in a reflow oven for sintering and bonding.

[0071] In step S930, a third molding compound is formed on the side of the multiple wafer units near the first position. The third molding compound covers the bonding points between the bonding components and the metal protrusions, and a portion of the bonding components are exposed on the surface of the third molding compound.

[0072] In the embodiments of this application, reference is made to Figure 12 , Figure 12 This is a schematic diagram illustrating the state corresponding to the fabrication of a third molding compound layer on one side of multiple wafer units near the first orientation, as provided in an embodiment of this application. Figure 12 As shown, after the metal bumps 15 of two wafer units 101 distributed on both sides of the first gap 60 are connected together by the bonding member 17, a third molding compound 18 is formed on the side of the plurality of wafer units 101 near the first orientation 20. The third molding compound 18 covers the bonding points between the bonding member 17 and the metal bumps 15, and a portion of the bonding member 17 is exposed on the surface of the third molding compound 18.

[0073] It should be noted that the third molding layer 18 is made of the same material as the second molding layer 16. As the outermost layer of the final chip product, the third molding layer 18 must also consider both stress and hermeticity. That is, the stress matching degree can be slightly reduced, but a material with good hermeticity must be used.

[0074] In this embodiment, a multi-injection molding method is used, which not only completes the chip fabrication but also reduces material costs and meets the dual requirements of packaging stress and airtightness.

[0075] It should be noted that, in this embodiment of the application, step S720 can also be performed in the following sub-steps: The metal protrusions of two wafer units distributed on both sides of the first gap are connected together by a bonding component. A molding compound is fabricated on one side of multiple wafer units near the second orientation and the other side near the first orientation. The molding compound fills the first void and covers the bonding points of the bonding components and the metal protrusions. A portion of the bonding components are exposed on the surface of the molding compound.

[0076] In this embodiment, bonding can also be completed by bonding first and then encapsulating. However, it should be noted that in the step of connecting the metal protrusions of two wafer units distributed on both sides of the first gap together using a bonding component, multiple wafer units need to be fastened together first.

[0077] In this embodiment, the entire packaging process is completed on the wafer, which reduces the cost of the packaging frame, reduces the wafer mounting process, and greatly improves packaging efficiency.

[0078] Step S730: Cut the structure after bonding treatment along the location of the bonded parts.

[0079] In the embodiments of this application, reference is made to Figure 13 , Figure 13 This is a schematic diagram showing the state of the structure after bonding processing cut along the position of the bonded component, provided in an embodiment of this application. Figure 13 As shown, after the wafer monomer 101 after the film expansion process is bonded, so that the metal protrusions 15 of the two wafer monomers 101 distributed on both sides of the first gap 60 are connected together along the bonding member, the bonded structure is cut along the bonding member 17 to obtain multiple chip monomers.

[0080] It should be noted that before the finished product is cut, the bonded structure can be placed in an electroplating solution for electroplating, so that the exposed bonded part 17 (electrode sheet) is plated with a layer of solderable metal. After the finished product is cut, the bonded part 17 electrode sheet can also be used for pattern recognition, testing, printing, and other work.

[0081] In one embodiment of this application, reference is made to Figure 14 , Figure 14 This is a schematic diagram of the chip structure provided in an embodiment of this application. This application also proposes a chip manufactured using the fabrication method provided in any embodiment of this application. Figure 14 As shown, the chip includes: a wafer 10, chip electrodes 14, metal bumps 15, and a first molding compound 13. Wherein: A first surface 11 (i.e., the surface of the wafer near the first position) is formed at one end of the wafer 10 along the thickness direction, and a second surface 12 (i.e., the surface of the wafer near the second position) is formed at the other end of the wafer 10 along the thickness direction. A chip electrode 14 is disposed on the first surface 11, and a metal bump 15 is disposed on the side of the chip electrode 14 opposite to the wafer 10.

[0082] The first molding compound 13 covers the side surface of the wafer 10 and the first surface 11. The chip electrode 14 and the metal protrusion 15 are embedded in the first molding compound 13 on the first surface 11. The end of the metal protrusion 15 away from the chip electrode 14 is exposed on the surface of the first molding compound 13.

[0083] In this embodiment, the chip unit can be fabricated using the fabrication method provided in any embodiment of this application. During the fabrication process, the risks of back-side chipping, wafer warping, and fragmentation during wafer slicing can be avoided, thereby increasing the chip yield.

[0084] In one embodiment of this application, reference is made to Figure 15 , Figure 15 This is another schematic diagram of the chip structure provided in an embodiment of this application. Figure 15 As shown, the chip includes a wafer 10, chip electrodes 14, metal bumps 15, and a first molding compound 13, as well as a bonding member 17, a second molding compound 16, and a third molding compound 18. The bonding member 17 is connected to the metal bumps 15. The second molding compound 16 covers the second surface 12 of the wafer 10 and the first molding compound 13 on the side of the wafer 10. The third molding compound 18 is disposed on the first molding compound 13 on the first surface 11 of the wafer 10, covering the bonding points between the bonding member 17 and the metal bumps 15, with a portion of the bonding member 17 exposed on the surface of the third molding compound 18.

[0085] In this embodiment, the chip unit can also be fabricated using the method provided in any embodiment of this application. During fabrication, the risks of back-side chipping, wafer warping, and fragmentation during slicing can be avoided, thereby increasing the chip yield.

[0086] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0087] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0088] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0089] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0090] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0091] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0092] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0093] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0094] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0095] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0096] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A method for fabricating a chip, used to fabricate a chip using a wafer, characterized in that, The wafer is positioned at a first orientation along its thickness direction, and at a second orientation along the other side of its thickness direction. The method includes the following steps: A plurality of first grooves are formed at intervals on the surface of the wafer near the first orientation; A first molding compound is formed on the side of the wafer near the first orientation, and the first molding compound fills the first groove; The surface of the wafer near the second position is subjected to a first grinding process to thin the wafer and expose the first groove and the first molding layer in the first groove on the first grinding surface formed by the first grinding process. A second groove is made in the first groove of the first molding compound exposed in the first grinding surface. The depth of the second groove is greater than or equal to the thickness of the wafer after the first grinding process, and less than the total thickness of the first molding compound. A second grinding process is performed on the surface of the first molding layer near the first orientation until the wafer and the second groove are exposed on the surface of the first molding layer near the first orientation, so that the wafer is broken along the second groove to form multiple wafer units; A chip electrode is disposed on the surface of the wafer near the first orientation. Before the step of forming a first molding compound layer on the side of the wafer near the first orientation, the method further includes: Metal bumps are fabricated on the chip electrodes of the wafer; In this process, after the step of fabricating metal bumps on the chip electrodes of the wafer, all wafers are wafers with the metal bumps. In the step of performing a second grinding process on the surface of the first molding layer near the first orientation, the second grinding process is performed until the metal protrusion and the second groove are exposed on the surface of the first molding layer near the first orientation. After performing a second polishing process on the surface of the first molding layer near the first orientation, the method further includes: A film expansion process is performed between adjacent wafer units to form a first gap between them. The wafer monomers after the film expansion treatment are bonded so that the metal protrusions of the two wafer monomers distributed on both sides of the first gap are connected together along the bonding member. The structure after bonding is cut along the location of the bonded component.

2. The method according to claim 1, characterized in that, The step of creating metal bumps on the chip electrodes of the wafer is performed after the step of creating a plurality of spaced first grooves on the surface of the wafer near the first orientation.

3. The method according to claim 1, characterized in that, The wafer monomers after the film expansion treatment are subjected to bonding treatment, including: A second molding layer is formed on the side of the plurality of wafer units near the second orientation and between adjacent wafer units; The metal protrusions of the two wafer units distributed on both sides of the first gap are connected together by a bonding component; A third molding compound is formed on one side of the plurality of wafer units near the first orientation. The third molding compound covers the bonding points of the bonding components and the metal protrusions, and a portion of the bonding components are exposed on the surface of the third molding compound.

4. The method according to claim 1, characterized in that, The first molding layer includes a resin material layer.

5. The method according to claim 1, characterized in that: The first groove is formed by cutting the wafer; The second groove is formed by cutting the wafer.

6. The method according to claim 1, characterized in that, The depth of the first groove is greater than or equal to the thickness of the wafer in the finished chip, and less than the thickness of the wafer in the step of forming the first groove on the surface of the wafer near the first position.

7. A chip, manufactured by the preparation method according to any one of claims 1-6, characterized in that, The chip includes: a wafer, chip electrodes, metal bumps, and a first molding layer; The wafer has a first surface formed at one end along the thickness direction and a second surface formed at the other end along the thickness direction. The chip electrode is disposed on the first surface, and the metal protrusion is disposed on the side of the chip electrode opposite to the wafer. The first molding compound covers the side of the wafer and the first surface. The chip electrode and the metal protrusion are embedded in the first molding compound on the first surface. The end of the metal protrusion away from the chip electrode is exposed on the surface of the first molding compound.

8. The chip according to claim 7, characterized in that, The chip further includes a bonding component, a second molding compound, and a third molding compound. The bonding component is connected to the metal protrusion. The second molding compound covers the second surface of the wafer and the first molding compound on the side surface of the wafer. The third molding compound is disposed on the first molding compound on the first surface of the wafer and covers the bonding points between the bonding component and the metal protrusion. A portion of the bonding component is exposed on the surface of the third molding compound.

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