A trigger device multiplexing circuit

Abstract

An embodiment of the present specification provides a trigger device multiplexing circuit, including a trigger device, first and second resistors, a capacitor, a field effect transistor Q5, a timer chip U1, a first NOT gate N1, a second NOT gate N2, a first latch SR1 and a second latch SR2; the signal output end of the trigger device is connected to the programmable input end of the controlled chip, and is also connected to the charging input terminal of U1 through the first and second resistors connected in series, and the connection between the first and second resistors is connected to the discharge input terminal of U1; the charging input terminal is grounded through the capacitor; the output terminal of U1 is respectively connected to the power input end of the controlled chip, the input end of N2, and the setting pin of SR2, and the output end of N2 is connected to the setting pin of SR1; the signal output end is connected to the input end of N1, and the output end of N1 is connected to the reset pin of SR1; the output pin of SR1 is connected to the reset pin of SR2, the output pin of SR2 is connected to the gate of Q5, its drain is connected to the first terminal of the capacitor, and its source is grounded.

Description

Technical Field

[0001] This specification relates to the field of circuit design technology, and in particular to a trigger device multiplexing circuit. Background Art

[0002] With the development of smart terminal devices, some portable products are equipped with only one physical button for the sake of simple design and easy operation. Therefore, a circuit has emerged that uses the same button to realize the chip power on / off function and customized functions (for example, lock screen, switch screen, etc.).

[0003] In existing circuits, different functions are usually achieved by long pressing or short pressing the same button. However, in this way, the long press and short press operations may affect each other, or the previous button operation may affect the next button operation, resulting in false triggering.

[0004] Therefore, it is hoped to provide a trigger device multiplexing circuit so that long press operations and short press operations do not affect each other, thereby improving the accuracy of the trigger signal. Summary of the Invention

[0005] One of the embodiments of the present specification provides a key multiplexing circuit, including a trigger device, a first resistor, a second resistor, a capacitor, a first field effect transistor, a timer chip, a first NOT gate, a second NOT gate, a first latch, and a second latch; wherein the signal output end of the trigger device is connected to the programmable input end of the controlled chip, the signal output end is connected to the charging input terminal of the timer chip through the first resistor and the second resistor connected in series, and the connection point between the first resistor and the second resistor is connected to the discharge input terminal of the timer chip; the charging input terminal of the timer chip is connected to the first terminal of the capacitor, and the second terminal of the capacitor is grounded; the output terminal of the timer chip is connected to the first terminal of the capacitor, and the second terminal of the capacitor is grounded; The power input terminal of the controlled chip is connected; the output terminal of the timer chip is connected to the input terminal of the second NOT gate, and the output terminal of the second NOT gate is connected to the setting pin of the first latch; the output terminal of the timer chip is also connected to the setting pin of the second latch; the signal output terminal is connected to the input terminal of the first NOT gate, and the output terminal of the first NOT gate is connected to the reset pin of the first latch; the output pin of the first latch is connected to the reset pin of the second latch, and the output pin of the second latch is connected to the gate of the first field effect transistor, the drain of the first field effect transistor is connected to the first terminal of the capacitor, and the source of the first field effect transistor is grounded. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] This specification will be further described in the form of exemplary embodiments, which will be described in detail with reference to the accompanying drawings. These embodiments are not limiting, and in these embodiments, like numbers represent like structures, wherein:

[0007] Figure 1 is a structural block diagram of a trigger device multiplexing circuit according to some embodiments of this specification;

[0008] Figure 2 is a schematic diagram of the circuit structure of the third NOT gate according to some embodiments of this specification;

[0009] Figure 3 is a schematic diagram of a circuit structure of an OR gate according to some embodiments of this specification;

[0010] Figure 4 is a schematic diagram of the circuit structure of a first NOT gate according to some embodiments of this specification;

[0011] Figure 5 is a schematic diagram of the circuit structure of a second NOT gate according to some embodiments of this specification;

[0012] Figure 6 is a schematic diagram of the circuit structure of a first latch and a second latch according to some embodiments of this specification;

[0013] Figure 7 This is a waveform diagram of a button pressed in a trigger device multiplexing circuit according to some embodiments of this specification. DETAILED DESCRIPTION

[0014] To more clearly illustrate the technical solutions of the embodiments of this specification, the following briefly describes the drawings required for describing the embodiments. Obviously, the drawings described below are merely examples or embodiments of this specification. Those skilled in the art can apply this specification to other similar scenarios based on these drawings without inventive effort. Unless otherwise apparent from the context or otherwise noted, the same reference numerals in the figures represent the same structure or operation.

[0015] It should be understood that the terms "system," "device," "unit," and / or "module" used herein are a method for distinguishing different components, elements, parts, portions, or assemblies at different levels. However, if other terms can achieve the same purpose, the terms may be replaced by other expressions.

[0016] As used in this specification and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" do not refer to the singular but also include the plural. Generally speaking, the terms "comprises" and "include" only indicate the inclusion of the steps and elements specifically identified, and these steps and elements do not constitute an exclusive list. A method or apparatus may also include other steps or elements.

[0017] Figure 1 It is a structural block diagram of a trigger device multiplexing circuit according to some embodiments of this specification.

[0018] The trigger device multiplexing circuit 110 can generate at least a first signal and a second signal based on a trigger device. For example, the first signal can be a short-time trigger signal, and the second signal can be a long-time trigger signal. For more information about short-time trigger signals and long-time trigger signals, please refer to the following description. The trigger device multiplexing circuit 110 is connected to the programmable input terminal and the power input terminal of the controlled chip 120 through two output ports to output the first trigger signal and the second trigger signal respectively, wherein the first trigger signal can be used as a programmable control signal of the controlled chip 120, and the second trigger signal can be used as a power on / off control signal of the controlled chip 120, so as to control the controlled chip 120 to realize the custom function and the power on / off function respectively without affecting each other.

[0019] In some embodiments, the trigger device multiplexing circuit 110 may include a trigger device 111, a first resistor 112, a second resistor 113, a capacitor 114, a first field effect transistor 115, a timer chip 116, a first NOT gate 117, a second NOT gate 118, a first latch 119-1 and a second latch 119-2.

[0020] In some embodiments, the signal output terminal 1111 of the trigger device 111 is connected to the charging input terminal of the timer chip 116 via a first resistor 112 and a second resistor 113 connected in series. The connection point 1123 between the first resistor 112 and the second resistor 113 is connected to the discharging input terminal of the timer chip 116. The charging input terminal of the timer chip 116 is connected to the first terminal of the capacitor 114, the second terminal of the capacitor 114 is grounded, and the output terminal of the timer chip is connected to the power input terminal of the controlled chip. This connection method can enable the trigger device multiplexing circuit 110 to output a long-duration trigger signal.

[0021] The trigger device 111 is a device for triggering other devices or modules to perform certain operations, such as a button, a dial switch, a wireless remote control transceiver module, an optoelectronic device, etc. In some embodiments, the trigger device 111 is a button S1. The trigger device 111 can be set to a trigger state or a non-trigger state. When the trigger condition is met (for example, the button S1 is pressed, the dial switch is toggled into place), the trigger device is in a trigger state, generates a trigger signal, and outputs it through its signal output terminal 1111. When the trigger condition is not met, the trigger device is in a non-trigger state and does not generate a trigger signal. The trigger signal may include an edge trigger signal, a horizontal trigger signal, a pulse trigger signal, etc.

[0022] The trigger device can directly generate a short-time trigger signal. For example, when the key is short-pressed, the signal output terminal 1111 of the key outputs a short-time trigger signal. Exemplarily, if the duration of pressing the key is less than 800ms, the key action can be regarded as a short press. Accordingly, the waveform change process of the short-time trigger signal may include a change from a high voltage to a low voltage when the key is pressed, the low voltage lasts for 800ms, and the low voltage changes back to a high voltage when the key is released. In some embodiments, the signal output terminal 1111 of the trigger device 111 is directly connected to the programmable input terminal of the controlled chip 120. In this connection method, the trigger device multiplexing circuit 110 can output a short-time trigger signal. The programmable input terminal of the controlled chip 120 directly receives the short-time trigger signal generated by the trigger device 111 to realize the custom function of the controlled chip 120.

[0023] The first resistor 112 and the second resistor 113 may each include, but are not limited to, a combination of one or more of a wirewound resistor, a carbon composite resistor, a carbon film resistor, a metal film resistor, a metal oxide film resistor, etc. For example, the first resistor 112 may be a chip resistor R3 (SMD resistor) with a resistance of 20 kΩ, and the second resistor 113 may be a chip resistor R5 with a resistance of 220 kΩ.

[0024] Capacitor 114 may be a combination of one or more of a paper capacitor, a metallized paper capacitor, a ceramic capacitor, a film capacitor, an oil-impregnated paper capacitor, an aluminum electrolytic capacitor, a semi-variable capacitor, a variable capacitor, etc. For example, capacitor 114 may include a chip capacitor C4 (a multilayer ceramic capacitor) having a capacitance of 10 μF and a rated voltage of 16 V.

[0025] Timer chip 116 may include a 555 timer chip (e.g., NE555, LM555), a 556 timer chip (e.g., NE556), or the like. Timer chip 116 includes a charge input terminal and a discharge input terminal. When the voltage on the charge input terminal meets a condition (e.g., the voltage on the charge input terminal increases to a first preset voltage or decreases to a second preset voltage, as described below), a voltage reversal may occur on the output terminal of timer chip 116.

[0026] The first resistor 112 and the second resistor 113, connected in series, can be used to form a charging circuit between the signal output terminal 1111 of the trigger device 111 and the capacitor 114, so that the capacitor 114 is charged. When the capacitor 114 is charged, the voltage increases, and the voltage of the charging input terminal of the timer chip 116 increases accordingly. The charging time of the capacitor 114 depends on the resistance value of the first resistor 112, the resistance value of the second resistor 113, and the capacitance value of the capacitor 114. When the voltage of the charging input terminal of the timer chip 116 increases to a first preset voltage (for example, two-thirds of the power supply voltage), the output terminal of the timer chip 116 can undergo a first voltage reversal based on the current output voltage. For example, if the current output voltage is a high voltage, the voltage reversal can be from a high voltage to a low voltage. The first voltage reversal of the output terminal of the timer chip 116 can serve as the start of the long-duration trigger signal generated by the trigger device multiplexing circuit 110.

[0027] The second resistor 113 can also be used to form a discharge loop between the capacitor 114 and the discharge input terminal of the timer chip 116 to facilitate the discharge of the capacitor 114. The discharge time depends on the resistance of the second resistor 113 and the capacitance of the capacitor 114. When the voltage of the capacitor is reduced to a second preset voltage (for example, one-third of the power supply voltage), the output terminal of the timer chip 116 can generate a second voltage reversal based on the current output voltage. For example, after the first voltage reversal, the current output voltage is a low voltage, and the voltage reversal can be from a low voltage to a high voltage. The second voltage reversal of the output terminal of the timer chip 116 can serve as the end of the long-time trigger signal generated by the trigger device multiplexing circuit 110. A complete long-time trigger signal can be regarded as a long press of a button.

[0028] In some embodiments, the output terminal of timer chip 116 is connected to the power input terminal of controlled chip 120. Trigger device multiplexing circuit 110 outputs a long-duration trigger signal through the output terminal of timer chip 116. The power input terminal of controlled chip 120 receives the long-duration trigger signal to implement the power on / off function.

[0029] In some embodiments, the output terminal of the timer chip 116 is connected to the input terminal of the second NOT gate 118, and the output terminal of the second NOT gate 118 is connected to the setting pin of the first latch 119-1; the output terminal of the timer chip is also connected to the setting pin of the second latch 119-2; the signal output terminal 1111 is connected to the input terminal of the first NOT gate, and the output terminal of the first NOT gate is connected to the reset pin of the first latch 119-1; the output pin of the first latch 119-1 is connected to the reset pin of the second latch 119-2, and the output pin of the second latch 119-2 is connected to the gate of the first field effect transistor 115, the drain of the first field effect transistor 115 is connected to the first terminal of the capacitor 114, and the source of the first field effect transistor 115 is grounded.

[0030] When a high voltage is input to the gate of the first field-effect transistor 115, the drain and source of the first field-effect transistor 115 are conductive, thereby discharging the charge of the capacitor 114. The first field-effect transistor 115 may include at least one of a junction field-effect transistor (JFET) and an insulated gate field-effect transistor (IGFET). In some embodiments, the first field-effect transistor is an N-channel enhancement-type JFET Q5.

[0031] The first NOT gate 117 can be used to flip the trigger signal so that the first latch 119-1 is reset after the trigger device 111 is released. The first NOT gate 117 can be an NMOS logic circuit N1. The trigger signal serves as the input voltage of the first NOT gate 117, and the first NOT gate 117 outputs a flip signal of the trigger signal to the reset pin of the first latch 119-1. For example, when the key is released, the trigger signal is low voltage, and the first NOT gate 117 outputs a high voltage. For more information about the first NOT gate, see Figure 4 and related instructions.

[0032] The second NOT gate 118 can be used to input the voltage of the output terminal of the timer chip 116 and flip it, and output the flipped voltage to the set pin of the first latch 119-1. After the output terminal of the timer chip 116 undergoes the first voltage flip, the first latch 119-1 can output a high voltage on the output pin based on the voltage of its set pin and the voltage of its reset pin, thereby resetting the second latch. For example, when the voltage of the output terminal of the timer chip 116 is low, the second NOT gate 118 outputs a high voltage. The second NOT gate 118 can be an NMOS logic circuit N2. For more information about the second NOT gate 118, see Figure 5 and related instructions.

[0033] The latch can be used to temporarily store the current output state of the latch and change the output state of the latch when the condition is met. The first latch 119-1 and the second latch 119-2 can include at least one of a D (Data, input data) latch, an SR (Set / Reset, set / reset) latch, a JK (Jumper / Knob, jumper / control) latch, etc. In some embodiments, the first latch 119-1 and the second latch 119-2 are SR latch SR1 and SR latch SR2 respectively. The first latch and the second latch can have other implementation methods, see Figure 6 and related instructions.

[0034] like Figure 1As shown, since the reset pin of the first latch 119-1 is connected to the output of the first NOT gate, and the input of the first NOT gate is connected to the signal output 1111 of the trigger device 111, when the trigger device is in the non-trigger state (the non-trigger state is a low voltage), for example, the key is released after being pressed or is always in the released state, the voltage of the signal output 1111 is flipped by the first NOT gate and pulled high, then the first latch 119-1 is reset, and then the first latch 119-1 outputs a high level, thereby resetting the second latch 119-2. Therefore, in some embodiments of the present specification, by providing a first NOT gate in the trigger device multiplexing circuit 110, and connecting the signal output 1111 to the input of the first NOT gate, and connecting the output of the first NOT gate to the reset pin of the first latch 119-1, it is beneficial to restore the first latch and the second latch to their initial states, thereby avoiding the trigger device from generating an erroneous trigger signal when it is triggered next time.

[0035] like Figure 7 As shown, Figure 7 This is a waveform diagram of the button pressed in the trigger device multiplexing circuit shown in some embodiments of this specification. Among them, waveform 710 is the voltage waveform of the signal output terminal 1111 of the trigger device 111, waveform 720 is the voltage waveform of the charging input terminal of the timer chip 116, waveform 730 is the voltage waveform of the output terminal of the timer chip 116, waveform 740 is the voltage waveform of the reset pin of the first latch 119-1, waveform 750 is the voltage waveform of the setting pin of the first latch 119-1, waveform 760 is the voltage waveform of the output pin of the first latch 119-1, and waveform 770 is the voltage waveform of the output pin of the second latch 119-2; T0 is the moment when the trigger device 111 is triggered (for example, the moment when the button is pressed), T1 is the moment when the voltage of the output terminal of the timer chip 116 is reversed for the first time, and T2 is the moment when the voltage of the output terminal of the timer chip 116 is reversed for the second time. Combined Figure 1 and Figure 7Since the output terminal of the timer chip 116 is connected to the input terminal of the second NOT gate 118, the output terminal of the second NOT gate 118 is connected to the set pin of the first latch 119-1, and the signal output terminal 1111 is connected to the input terminal of the first NOT gate 117, the output terminal of the first NOT gate 117 is connected to the reset pin of the first latch 119-1, and the voltage of the output pin of the first latch 119-1 depends on the input voltage of its set pin and the input voltage of its reset pin. After the trigger device 111 is triggered (for example, at time T0 when the key S1 is pressed), the signal output terminal 1111 of the trigger device 111 outputs a high voltage, and the reset pin of the first latch 119-1 becomes a low voltage. Simultaneously, the charging input terminal of the timer chip 116 begins to charge, and the output terminal of the timer chip 116 outputs the nominal starting voltage, i.e., a high voltage. Accordingly, the set pin of the first latch 119-1 is a low voltage. Therefore, the output pin (which may be an inverting output pin) of the first latch 119-1 outputs a high voltage. Since the output pin of the first latch 119-1 is connected to the reset pin of the second latch 119-2, the second latch 119-2 is reset at this time. When the output terminal of the timer chip 116 undergoes a first voltage flip (at time T1), for example, from a high voltage to a low voltage, due to the presence of the second NOT gate 118, the set pin of the first latch 119-1 also undergoes a voltage flip, from a low voltage to a high voltage. Correspondingly, the output pin (which may be an inverted output pin) of the first latch 119-1 changes from a high voltage to a low voltage. Since the second latch 119-2 has been reset and the set pin of the second latch 119-2 is directly connected to the output terminal of the timer chip 116 (which is a low voltage at this time), the output voltage of the second latch 119-2 is consistent with the voltage of its set pin, which is a low voltage. When the output terminal of the timer chip 116 undergoes a second voltage reversal (at time T2), for example, from a low voltage to a high voltage, the voltage of the set pin of the first latch 119-1 changes from a high voltage to a low voltage. The output pin voltage of the first latch 119-1 remains unchanged and outputs a low voltage. The reset pin of the second latch 119-2 also remains at a low voltage. Since the set pin of the second latch 119-2 is consistent with the voltage of the output terminal of the timer chip 116 (which is a high voltage at this time), the output pin of the second latch 119-2 outputs a high voltage at this time. Since the output pin of the second latch 119 - 2 is connected to the gate of the first field effect transistor 115 , the first field effect transistor 115 is turned on, and the capacitor 114 can be discharged through the first field effect transistor.

[0036] From the above principle, it can be seen that when the trigger device maintains the trigger state for a long time (for example, the button is pressed and not released), after the output terminal of the timer chip 116 outputs a complete long-time trigger signal, the capacitor 114 can continue to discharge through the first field-effect transistor 115 without being charged again. That is, when the trigger device maintains the trigger state for a long time, the trigger device multiplexing circuit 110 only generates one long-time trigger signal, which can avoid the situation where the button is pressed for a long time, causing the controlled chip to be turned on and then shut down again after a while because the button is not released.

[0037] In some embodiments of the present specification, by setting a trigger device, a first resistor, a second resistor, a capacitor, a timer chip and a specific connection method between them, a short-time trigger signal and a long-time trigger signal that do not interfere with each other can be output for the controlled chip, which is conducive to controlling the controlled chip to realize custom functions and power on / off functions respectively; by setting a first field-effect transistor, a first NOT gate, a second NOT gate, a first latch and a second latch, and a specific connection method between them, when the trigger device maintains a triggered state for a long time, after the trigger device multiplexing circuit outputs a complete long-time trigger signal to the controlled chip, the capacitor can continue to discharge and no longer be charged, thereby avoiding the situation where the key is pressed for a long time, causing the controlled chip to be turned on and then turned off again after a while because the key is not released.

[0038] It should be noted that the above description of the trigger device multiplexing circuit 110 and its components and devices is for convenience only and does not limit this specification to the scope of the embodiments. It is understandable that those skilled in the art, after understanding the principles of the system, may arbitrarily combine the modules or form a subsystem to connect with other modules without deviating from the principles. In some embodiments, Figure 1 The first latch and the second latch disclosed in the present invention may be different circuit elements or devices, or may be implemented by an integrated circuit or device to realize the functions of the first latch and the second latch. Such variations are within the scope of protection of this specification.

[0039] In some embodiments, the trigger device multiplexing circuit 110 further includes a third NOT gate 210 and an OR gate 220 .

[0040] In some embodiments, the signal output terminal 1111 of the trigger device 111 is connected to the input terminal of the third NOT gate 210, the output terminal of the third NOT gate 210 is connected to the second input terminal of the OR gate 220; the first input terminal of the OR gate 220 is connected to the output pin of the second latch; and the output terminal of the OR gate 220 is connected to the gate of the first field-effect transistor 115. This connection method facilitates the timely release of charge when the trigger device multiplexing circuit 110 outputs a short-term trigger signal, and is compatible with the function of preventing false triggering caused by a long press when the trigger device multiplexing circuit 110 outputs a long-term trigger signal.

[0041] The third NOT gate 210 can be used to flip the trigger signal. The third NOT gate 210 can be implemented by a basic logic operation circuit, such as a CMOS logic circuit, a TTL logic circuit, an NMOS logic circuit, a PMOS logic circuit, etc. In some embodiments, the third NOT gate 210 is an NMOS logic circuit N3. For more information about the third NOT gate, see Figure 2 and related instructions.

[0042] OR gate 220 can be configured to output a high voltage to the gate of first field-effect transistor 115 when the trigger signal is a low voltage or the output pin of second latch 119-2 is a high voltage, thereby conducting the drain and source of first field-effect transistor 115. OR gate 220 can be implemented using a basic logic operation circuit, such as a diode logic circuit, a CMOS logic circuit, or a TTL logic circuit. In some embodiments, OR gate 220 is a diode logic circuit OR1.

[0043] The trigger signal serves as the input voltage of the third NOT gate 210, which then outputs a flip signal of the trigger signal to the OR gate 220. For example, when the key is released, the trigger signal is low, and the third NOT gate 210 outputs a high voltage to the OR gate 220. The output of the OR gate 220 then outputs a high voltage, causing conduction between the drain and source of the first field-effect transistor 115, and the capacitor 114 releases its charge through the drain and source of the first field-effect transistor 115.

[0044] When the output pin of the second latch 119 - 2 is a high voltage, the output terminal of the OR gate 220 can also output a high voltage, so that the drain and source of the first field effect transistor 115 are conductive, and the capacitor 114 releases charge through the drain and source of the first field effect transistor 115 .

[0045] In some embodiments of the present specification, a third NOT gate 210 is provided in the trigger device multiplexing circuit 110. After the trigger device is briefly triggered, for example, a key is pressed and then released, the signal output end of the trigger device outputs a low voltage, which is flipped to a high voltage through the third NOT gate, and the output end of the OR gate 220 outputs a high voltage, so that the drain and source of the first field effect transistor are conductive, which is beneficial for the timely release of the charge of the capacitor 114, and avoids the accumulation of the charge of the capacitor 114 during the process of the trigger device being briefly triggered multiple times (for example, pressing and releasing the key multiple times in succession), thereby generating an erroneous short-time trigger signal.

[0046] In some embodiments of the present disclosure, an OR gate 220 is provided in the trigger device multiplexing circuit 110. When a condition is met, the OR gate can output a high voltage, turning on the first field effect transistor, thereby facilitating the discharge of charge from the capacitor 114. The conditions for outputting a high voltage include the trigger device being in a non-triggering state, such as when a key is released, or the output pin of the second latch outputting a high voltage, such as when a key is pressed for a long time without being released, thereby outputting a complete long-duration trigger signal. This takes into account possible anomalies that may occur in both short-term and long-term triggering of the trigger device. When either condition (e.g., a short key press or a long key press without releasing) occurs, the OR gate outputs a high voltage, causing the capacitor 114 to discharge charge, thereby reducing the probability of false triggering.

[0047] It should be noted that the above description of trigger device multiplexing circuit 110 is for illustrative purposes only and does not limit the scope of application of this specification. Those skilled in the art will be able to make various modifications and changes to trigger device multiplexing circuit 110 under the guidance of this specification. However, such modifications and changes will remain within the scope of this specification.

[0048] Figure 2 2 is a schematic diagram of the circuit structure of the third NOT gate according to some embodiments of this specification.

[0049] The third NOT gate 210 is a component that flips the logic state of the input signal and then outputs it. In some embodiments, the signal output terminal 1111 of the trigger device is connected to the input terminal of the third NOT gate 210, and the output terminal of the third NOT gate 210 is connected to the gate of the first field effect transistor 115.

[0050] The third NOT gate 210 can be used to flip the voltage of the signal output terminal 1111, so that the capacitor 114 can discharge when the trigger device 111 is in the non-trigger state. For example, after the button S1 is released, the voltage of the signal output terminal 1111 can be a low voltage, that is, the third NOT gate inputs a low voltage and outputs a high voltage. Correspondingly, the gate of the first field effect transistor 115 inputs a high voltage, the drain and source of the first field effect transistor 115 are turned on, and the capacitor 114 releases the charge through the turned-on first field effect transistor 115, and the charge amount is reset to zero. When the button S1 is pressed again the next time, the capacitor 114 starts to charge again from zero, so as to avoid the accumulation of unreleased or incompletely released charge in the capacitor 114 after the last button is pressed, which shortens the duration of the trigger signal generation, so that the duration of the trigger signal generation after each press of the button S1 remains consistent.

[0051] The key multiplexing circuit 110 further includes a pull-up power supply VCC; the third NOT gate 210 includes a second field effect transistor Q1, a third resistor R2, a fourth resistor R4 and a fifth resistor R6.

[0052] The pull-up power supply VCC can be used to pull up the voltage of the pin or node connected to it to a high voltage to maintain the high voltage state. In some embodiments, the pull-up power supply can use a 3.8V power supply. In some embodiments, the pull-up power supply is connected to ground through a filter capacitor to filter power supply ripple and improve circuit stability. The filter capacitor can have a capacitance of 100nF or other values.

[0053] The second field-effect transistor Q1 can be used to implement logic level inversion. The second field-effect transistor Q1 can be an N-channel MOSFET (metal-oxide-semiconductor field-effect transistor) or a P-channel MOSFET (metal-oxide-semiconductor field-effect transistor). Exemplarily, the model of the second field-effect transistor Q1 can be YJL3400A.

[0054] The third resistor R2 can serve as a load element. The fourth resistor R4 and the fifth resistor R6 are used to divide the input voltage and limit the current. In some embodiments, the resistance of the third resistor R2, the fourth resistor R4, and the fifth resistor R6 can be 1MΩ (megaohm).

[0055] The fourth resistor R4 and the fifth resistor R6 form a series circuit, one end of which serves as the input terminal of the third NOT gate 210, and the other end of which is grounded. The fourth resistor R4 and the fifth resistor R6 are connected in series to form a voltage divider for dividing the voltage of the input signal. The larger resistor serves to limit the current, while the smaller resistor provides an effective voltage divider ratio. This allows the input signal voltage to be adjusted to the gate voltage range suitable for the field-effect transistor, ensuring correct logical operation.

[0056] One end of the third resistor R2 is connected to the pull-up power supply VCC, and the other end is connected to the drain of the second FET Q1. The drain of the second FET Q1 is the output of the third NOT gate 210. The third resistor R2 acts as a load element to absorb and distribute current, ensuring circuit stability and reliability.

[0057] The gate of the second field-effect transistor Q1 is connected to the connection point between the fourth resistor R4 and the fifth resistor R6; the source of the second field-effect transistor Q1 is grounded. When the input voltage to the gate of the second field-effect transistor Q1 is low, the source and drain of the second field-effect transistor Q1 are disconnected, and the drain output of the second field-effect transistor is pulled up to the high voltage of VCC. When the input voltage to the gate of the second field-effect transistor Q1 is high, the source and drain of the second field-effect transistor Q1 are connected, and the drain output of the second field-effect transistor is pulled down to the low voltage of ground, thereby achieving the function of inverting its input voltage.

[0058] Figure 3 is an exemplary circuit structure diagram of an OR gate according to some embodiments of this specification.

[0059] In some embodiments, the OR gate 220 includes a first diode D1, a second diode D2, and a sixth resistor R15; wherein, the anode of the first diode D1 is the first input terminal of the OR gate 220; the anode of the second diode D2 is the second input terminal of the OR gate 220; the cathode of the first diode D1 and the cathode of the second diode D2 are both connected to one end of the sixth resistor R15 and serve as the output terminal of the OR gate 220; the other end of the sixth resistor R15 is grounded.

[0060] When a high voltage is input to the anode of the first diode D1 or the anode of the second diode D2, the end of the sixth resistor R15 away from the ground is a high voltage. When a low voltage is input to the anode of the first diode D1 and the anode of the second diode D2, the end of the sixth resistor R15 away from the ground is a low voltage, thereby realizing the function of an OR gate.

[0061] The first diode D1 and the second diode D2 may include a switching diode, a Schottky diode, etc. The type of the sixth resistor R15 may be selected with reference to the first resistor, etc. For example, the resistance of the sixth resistor R15 may be 2M ohms.

[0062] Figure 4 2 is a schematic diagram of the circuit structure of a first NOT gate according to some embodiments of this specification.

[0063] The first NOT gate 117 is a component that flips the logic state of the input signal and then outputs it. In some embodiments, the signal output terminal 1111 of the trigger device 111 is connected to the input terminal of the first NOT gate 117, and the output terminal of the first NOT gate 117 is connected to the reset pin of the first latch.

[0064] The first NOT gate 117 can be used to reset the latch after the trigger device 111 is released. For example, if the voltage output by the button S1 is pulled down to a low voltage, that is, the input terminal of the first NOT gate is a low voltage, then the output terminal of the first NOT gate is a high voltage. The output terminal of the first NOT gate resets the first latch 119-1, and the first latch 119-1 then outputs a high voltage. The output terminal of the first latch 119-1 resets the second latch 119-2, so that the internal state of the latch returns to the initial state, waiting to be triggered next time.

[0065] The key multiplexing circuit 110 further includes a pull-up power supply VCC; the first NOT gate 117 includes a third field effect transistor Q14 and a seventh resistor R8.

[0066] For details on the pull-up power supply VCC, please refer to Figure 2 The function and type of the third field effect transistor Q14 can be found in Figure 2 The value of the seventh resistor R8 can be found in Figure 2 Related instructions for the third resistor R2.

[0067] The gate of the third field effect transistor Q14 is the input terminal of the first NOT gate 117; the source of the third field effect transistor Q14 is grounded; the drain of the third field effect transistor Q14 is the output terminal of the first NOT gate 117. The working principle of the third field effect transistor Q14 is similar to that of the second field effect transistor Q1, which can be seen in FIG. Figure 2 Related instructions for the second field effect transistor Q1.

[0068] The drain of the third field effect transistor Q14 is connected to the pull-up power supply VCC through the seventh resistor R8. The function of the seventh resistor R8 can be seen in Figure 2 Related instructions for the third resistor R2.

[0069] Figure 5 2 is a schematic diagram of the circuit structure of the second NOT gate according to some embodiments of this specification.

[0070] Second NOT gate 118 is a component that inverts the logic state of an input signal and then outputs it. Second NOT gate 118 is configured to input the voltage at the output terminal of timer chip 116, invert it, and output the inverted voltage to the set pin of first latch 119-1. After the first voltage inversion at the output terminal of timer chip 116 occurs, first latch 119-1 can output a high voltage at its output pin based on the voltages at its set pin and reset pin, thereby resetting the second latch.

[0071] The key multiplexing circuit 110 further includes a pull-up power supply VCC; the second NOT gate 118 includes a fourth field effect transistor Q13 and an eighth resistor R7.

[0072] For details on the pull-up power supply VCC, please refer to Figure 2 The function and type of the fourth field effect transistor Q13 can be found in Figure 2 The value of the eighth resistor R7 can be found in Figure 2 Related instructions for the third resistor R2.

[0073] The gate of the fourth field effect transistor Q13 is the input terminal of the second NOT gate 118; the source of the fourth field effect transistor Q13 is grounded; the drain of the fourth field effect transistor Q13 is the output terminal of the second NOT gate 118. The working principle of the fourth field effect transistor Q13 is the same as that of the second field effect transistor Q1, which can be seen in FIG. Figure 2 Related instructions for the second field effect transistor Q1.

[0074] The drain of the fourth field effect transistor Q13 is connected to the pull-up power supply through the eighth resistor. The function of the eighth resistor R7 can be seen in Figure 2 Related instructions for the third resistor R2.

[0075] Figure 6This is an exemplary circuit structure diagram of a dual-way trigger according to some embodiments of this specification.

[0076] In some embodiments, the first latch 119 - 1 and the second latch 119 - 2 are implemented by a dual flip-flop U2 .

[0077] The dual flip-flop U2 includes two independently operable flip-flops. For example, the dual flip-flop is a dual D (Data) flip-flop. For example, the model of the dual flip-flop U2 may be CD4013BM / TR. Pins 1Q through 1SD of the dual flip-flop belong to the first internal D flip-flop, and pins 2SD through 2Q belong to the second internal D flip-flop.

[0078] In some embodiments, the sixth pin 1SD of the dual-way trigger U2 is the setting pin of the first latch 119-1; the fourth pin 1CD of the dual-way trigger U2 is the reset pin of the first latch 119-1; the second pin 1Q# (the inverted output pin of the first internal D trigger) of the dual-way trigger U2 is the output pin of the first latch 119-1; the tenth pin 2CD of the dual-way trigger is the reset pin of the second latch 119-2; the eighth pin 2SD of the dual-way trigger is the setting pin of the second latch 119-2; the thirteenth pin 2Q of the dual-way trigger U2 is the output pin of the second latch 119-2.

[0079] When the first latch and the second latch are implemented by a dual-way flip-flop, the connection method of the first latch and the second latch pins can be referred to Figure 1 connections and related instructions.

[0080] Implementing the first latch and the second latch by a dual-flip-flop integrated circuit can simplify the hardware design and manufacturing process of the trigger device multiplexing circuit 110 and improve production efficiency.

[0081] While the basic concepts have been described above, it will be apparent to those skilled in the art that the detailed disclosure is merely illustrative and does not limit this specification. Although not explicitly stated herein, various modifications, improvements, and revisions to this specification may be made by those skilled in the art. Such modifications, improvements, and revisions are suggested in this specification and remain within the spirit and scope of the exemplary embodiments of this specification.

[0082] This specification also uses specific terms to describe the embodiments of this specification. For example, "one embodiment," "an embodiment," and / or "some embodiments" refer to a feature, structure, or characteristic associated with at least one embodiment of this specification. Therefore, it should be emphasized and noted that references to "one embodiment," "an embodiment," or "an alternative embodiment" two or more times in different locations in this specification do not necessarily refer to the same embodiment. Furthermore, certain features, structures, or characteristics of one or more embodiments of this specification may be appropriately combined.

[0083] In addition, unless expressly stated in the claims, the order of the processing elements and sequences, the use of alphanumeric characters, or the use of other names described in this specification are not intended to limit the order of the processes and methods of this specification. Although the above disclosure discusses some of the invention embodiments currently considered useful through various examples, it should be understood that such details are for illustrative purposes only, and the appended claims are not limited to the disclosed embodiments. On the contrary, the claims are intended to cover all modifications and equivalent combinations that are consistent with the spirit and scope of the embodiments of this specification. For example, although the system components described above can be implemented by hardware devices, they can also be implemented only by software solutions, such as installing the described system on an existing server or mobile device.

[0084] Similarly, it should be noted that, in order to simplify the presentation of this specification and thus facilitate understanding of one or more embodiments of the invention, the foregoing descriptions of the embodiments of this specification sometimes combine multiple features into a single embodiment, figure, or description thereof. However, this disclosure method does not imply that the subject matter of this specification requires more features than those recited in the claims. In fact, an embodiment may have fewer features than all of the features of a single disclosed embodiment.

[0085] In some embodiments, numbers are used to describe the quantity of components and attributes. It should be understood that such numbers used in the description of the embodiments are modified by the modifiers "about", "approximately" or "substantially" in some examples. Unless otherwise stated, "about", "approximately" or "substantially" indicate that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in the description and claims are approximate values, which may change according to the required characteristics of individual embodiments. In some embodiments, the numerical parameters should take into account the specified significant digits and adopt the general method of retaining digits. Although the numerical domains and parameters used to confirm the breadth of their range in some embodiments of this specification are approximate values, in specific embodiments, the settings of such numerical values ​​are as accurate as possible within the feasible range.

[0086] Each patent, patent application, patent application publication, and other materials, such as articles, books, specifications, publications, and documents, cited in this specification is hereby incorporated by reference in its entirety. This includes application history documents that are inconsistent with or conflict with the content of this specification, as well as documents (currently or subsequently attached to this specification) that limit the broadest scope of the claims of this specification. It should be noted that if the descriptions, definitions, and / or terminology used in the accompanying materials are inconsistent or conflicting with the content of this specification, the descriptions, definitions, and / or terminology used in this specification will control.

[0087] Finally, it should be understood that the embodiments described in this specification are intended only to illustrate the principles of the embodiments of this specification. Other variations may also fall within the scope of this specification. Therefore, by way of example and not limitation, alternative configurations of the embodiments of this specification may be considered consistent with the teachings of this specification. Accordingly, the embodiments of this specification are not limited to the embodiments explicitly described and illustrated in this specification.

Claims

1. A trigger device multiplexing circuit, characterized in that: It includes a trigger device, a first resistor, a second resistor, a capacitor, a first field effect transistor, a timer chip, a first NOT gate, a second NOT gate, a first latch and a second latch; wherein, The signal output terminal of the trigger device is connected to the programmable input terminal of the controlled chip. The signal output terminal is connected to the charging input terminal of the timer chip through a first resistor and a second resistor connected in series, and the connection point between the first resistor and the second resistor is connected to the discharging input terminal of the timer chip; The charging input terminal of the timer chip is connected to the first terminal of the capacitor, and the second terminal of the capacitor is grounded; The output terminal of the timer chip is connected to the power input terminal of the controlled chip; The output terminal of the timer chip is connected to the input terminal of the second NOT gate, and the output terminal of the second NOT gate is connected to the setting pin of the first latch; the output terminal of the timer chip is also connected to the setting pin of the second latch; The signal output end is connected to the input end of the first NOT gate, and the output end of the first NOT gate is connected to the reset pin of the first latch; the output pin of the first latch is connected to the reset pin of the second latch, and the output pin of the second latch is connected to the gate of the first field effect transistor, the drain of the first field effect transistor is connected to the first terminal of the capacitor, and the source of the first field effect transistor is grounded.

2. The circuit according to claim 1, wherein The circuit further includes a third NOT gate and an OR gate; wherein, The signal output end is connected to the input end of the third NOT gate, and the output end of the third NOT gate is connected to the second input end of the OR gate; The first input end of the OR gate is connected to the output pin of the second latch; The output end of the OR gate is connected to the gate of the first field effect transistor.

3. The circuit according to claim 2, characterized in that The circuit further includes a pull-up power supply; the third NOT gate includes a second field effect transistor, a third resistor, a fourth resistor and a fifth resistor; wherein, The fourth resistor and the fifth resistor form a series circuit, one end of the series circuit is the input end of the third NOT gate, and the other end of the series circuit is grounded; The gate of the second field effect transistor is connected to the connection point between the fourth resistor and the fifth resistor; The source of the second field effect transistor is grounded; One end of the third resistor is connected to the pull-up power supply, and the other end is connected to the drain of the second field effect transistor; the drain of the second field effect transistor is the output end of the third NOT gate.

4. The circuit according to claim 2, characterized in that The OR gate includes a first diode, a second diode and a sixth resistor; wherein, The anode of the first diode is the first input terminal of the OR gate; The anode of the second diode is the second input terminal of the OR gate; The cathode of the first diode and the cathode of the second diode are both connected to one end of the sixth resistor and serve as the output end of the OR gate; The other end of the sixth resistor is grounded.

5. The circuit according to claim 1, wherein: The circuit further includes a pull-up power supply; the first NOT gate includes a third field effect transistor and a seventh resistor; wherein, The gate of the third field effect transistor is the input end of the first NOT gate; The source of the third field effect transistor is grounded; The drain of the third field effect transistor is connected to the pull-up power supply through the seventh resistor; The drain of the third field effect transistor is the output end of the first NOT gate.

6. The circuit according to claim 1, wherein: The circuit further includes a pull-up power supply; the second NOT gate includes a fourth field effect transistor and an eighth resistor; wherein, The gate of the fourth field effect transistor is the input terminal of the second NOT gate; The source of the fourth field effect transistor is grounded; The drain of the fourth field effect transistor is connected to the pull-up power supply through the eighth resistor; The drain of the fourth field effect transistor is the output end of the second NOT gate.

7. The circuit according to claim 3, 5 or 6, characterized in that The pull-up power supply is connected to the ground through a filter capacitor.

8. The circuit according to claim 1, wherein: The first latch and the second latch are implemented by a dual-way flip-flop. The sixth pin of the dual-way trigger is a setting pin of the first latch; the fourth pin of the dual-way trigger is a reset pin of the first latch; the second pin of the dual-way trigger is an output pin of the first latch; The tenth pin of the dual-way trigger is the reset pin of the second latch; the eighth pin of the dual-way trigger is the setting pin of the second latch; and the thirteenth pin of the dual-way trigger is the output pin of the second latch.

9. The circuit according to claim 8, characterized in that The dual-way trigger is a dual-way D trigger.

10. The circuit according to claim 9, characterized in that The model of the dual D flip-flop is CD4013BM / TR.

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