Semiconductor device and method for manufacturing the same

Abstract

The present application relates to a semiconductor device and a manufacturing method thereof. A semiconductor device is disclosed, the semiconductor device including: a gate structure on a source structure and including conductive layers and insulating layers alternately laminated with each other; a contact plug passing through the gate structure and electrically connected to the source structure; a stressor around a sidewall of the contact plug; and a seed layer around the stressor.

Description

Technical Field

[0001] Various embodiments of this disclosure relate to an electronic device, and more specifically, to a semiconductor device and a method of manufacturing the semiconductor device. Background Technology

[0002] The integration density of semiconductor devices is primarily determined by the area occupied by a single memory cell. Recently, as the integration density of semiconductor devices forming single-layer memory cells on a substrate has reached its limit, three-dimensional semiconductor devices for stacking memory cells on a substrate have been proposed. Furthermore, various structures and manufacturing methods are being developed to improve the operational reliability of semiconductor devices with three-dimensional structures. Summary of the Invention

[0003] According to one embodiment, a semiconductor device may include: a gate structure located on a source structure, the gate structure including conductive and insulating layers alternately stacked on top of each other; a contact plug passing through the gate structure and electrically connected to the source structure; a stress source surrounding a sidewall of the contact plug, the stress source including compressive stress; and a seed layer surrounding the stress source.

[0004] According to one embodiment, a semiconductor device may include: a gate structure including conductive and insulating layers alternately stacked on top of each other, the gate structure including tensile stress; a contact plug passing through the gate structure; a stress source surrounding the sidewall of the contact plug, the stress source including compressive stress; and a seed layer surrounding the stress source.

[0005] According to one embodiment, a method of manufacturing a semiconductor device may include: forming a laminate on a source structure; forming a first opening through the laminate and exposing the source structure; forming a seed layer in the first opening; forming a stress source including compressive stress by expanding the seed layer; and forming a contact plug in the stress source.

[0006] According to one embodiment, a method of manufacturing a semiconductor device may include: forming a laminate comprising alternating layers of a first material layer and a second material layer; forming a first opening through the laminate; replacing the first material layer with a third material layer having tensile stress through the first opening; forming a seed layer in the first opening; forming a stress source including compressive stress by oxidizing the seed layer; and forming a contact plug in the stress source. Attached Figure Description

[0007] Figure 1A , Figure 1B and Figure 1C This is a diagram illustrating the structure of a semiconductor device according to one embodiment.

[0008] Figure 2A , Figure 2B and Figure 2C This is a cross-sectional view showing the structure of a semiconductor device according to one embodiment.

[0009] Figure 3A , Figure 3B and Figure 3C This is a cross-sectional view showing the structure of a semiconductor device incorporating a stress source according to one embodiment.

[0010] Figure 4 This is a flowchart illustrating a method for manufacturing a semiconductor device according to one embodiment.

[0011] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Figure 5F and Figure 5G This is a diagram illustrating a method for manufacturing a semiconductor device according to one embodiment. Detailed Implementation

[0012] Various embodiments according to the technical spirit of this disclosure are described below with reference to the accompanying drawings. It should be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, the element or layer may be directly on, directly connected to, or directly coupled to the other element or layer, or there may be intermediate elements or layers. Conversely, when an element or layer is referred to as being "directly" on, directly connected to, or directly coupled to another element or layer, there are no intermediate elements or layers. The same reference numerals always denote the same elements.

[0013] Figures 1A to 1C This is a diagram illustrating the structure of a semiconductor device according to one embodiment.

[0014] Reference Figure 1A The semiconductor device may include a first wafer structure WF1. The first wafer structure WF1 may include a substrate 10 and a first layer 11. The first layer 11 may be located on the front surface FS of the substrate 10. The first layer 11 may shrink during its formation process. The first layer 11 may have tensile stress, which may cause tensile stress in the substrate 10. The substrate 10 may be bent, causing its rear surface RS to bulge, and may cause warping of the first wafer structure WF1.

[0015] Reference Figure 1BThe semiconductor device may include a second wafer structure WF2. The second wafer structure WF2 may include a substrate 10 and a second layer 12. The second layer 12 may be located on the front surface FS of the substrate 10. The second layer 12 may expand during its formation process. The second layer 12 may have compressive stress, which may cause compressive stress on the substrate 10. The substrate 10 may be bent, causing its front surface FS to bulge, and may cause warping of the second wafer structure WF2.

[0016] Reference Figure 1C The semiconductor device may include a third wafer structure WF3. The third wafer structure WF3 may include a substrate 10, a first layer 11, and a second layer 12. The first layer 11 and the second layer 12 may be located on the front surface of the substrate 10. The first layer 11 may have tensile stress, and the second layer 12 may have compressive stress. Since both the first layer 11 and the second layer 12 are formed on the front surface of the substrate 10, the tensile stress caused by the first layer 11 can be offset by the compressive stress of the second layer 12. Therefore, in one embodiment, warpage of the third wafer structure WF3 can be minimized or prevented.

[0017] Figures 2A to 2C This is a cross-sectional view showing the structure of a semiconductor device according to one embodiment. Detailed descriptions of content repeated above are omitted below.

[0018] Reference Figure 2A The semiconductor device may have a wafer structure including structures formed on the front or rear surface of the substrate 20. The semiconductor device may include a gate structure (GST) and a source contact structure (SCT). The semiconductor device may also include the substrate 20, a source structure 28, a contact plug 26, a stress source 25, a seed layer 24, an insulating spacer 23, or a combination thereof.

[0019] Source structure 28 may be located on the front surface of substrate 20. Source structure 28 may include a conductive material such as polysilicon or metal. In one embodiment, source structure 28 may be a conductive layer located between substrate 20 and gate structure GST. Substructures such as peripheral circuitry may be located between source structure 28 and substrate 20. In one embodiment, source structure 28 may be a portion of substrate 20. Source structure 28 may be an impurity region in substrate 20.

[0020] The gate structure GST can be located on the front surface of the substrate 20 and can be located on the source structure 28. The gate structure GST may include conductive layers 21 and insulating layers 22 alternately stacked on top of each other. The conductive layer 21 may be a word line, bit line, or select line. The conductive layer 21 may include polysilicon, tungsten, molybdenum, or metal. The insulating layer 22 may be used to insulate the stacked conductive layers from each other. The insulating layer 22 may include insulating materials such as oxides, nitrides, or air gaps.

[0021] The gate structure GST can have tensile stress. The conductive layer 21 can shrink in volume during its formation process, and the conductive layer 21 can have tensile stress. For reference, structures with tensile stress are not limited to the gate structure GST, and various structures included in a semiconductor device can each have tensile stress.

[0022] The source contact structure SCT can pass through the gate structure GST and be electrically connected to the source structure 28. The source contact structure SCT may include a contact plug 26 and a stress source 25. The source contact structure SCT may also include a seed layer 24, an insulating spacer 23, or a combination thereof.

[0023] Contact plug 26 may extend through the gate structure GST. Contact plug 26 may extend to and be electrically connected to the source structure 28. Contact plug 26 may have a single-layer or multi-layer structure. Apertures V may be included in contact plug 26. Contact plug 26 may include a conductive material such as polysilicon, tungsten, molybdenum, or a metal, or a combination thereof.

[0024] Stress source 25 may be formed on the front surface of substrate 20 and surrounding the sidewalls of contact plug 26. Stress source 25 may be used to control wafer warpage. Stress source 25 may have compressive stress and reduce or counteract tensile stress in the wafer structure.

[0025] Seed layer 24 may surround stress source 25. Seed layer 24 may be retained after serving as a seed for forming stress source 25. In one embodiment, seed layer 24 may surround the sidewalls of stress source 25 and the bottom surface BT of contact plug 26. Contact plug 26 may be electrically connected to source structure 28 via seed layer 24.

[0026] Stress source 25 can be formed by oxidizing seed layer 24, and volume expansion occurs during the oxidation process. The compressive stress of stress source 25 can be caused by the volume expansion during its formation. Seed layer 24 can include a material that expands in volume upon oxidation. In one embodiment, seed layer 24 can include silicon, and stress source 25 can include silicon oxide. In one embodiment, seed layer 24 can include polycrystalline silicon, silicon nitride, silicon oxynitride, or a combination thereof. The magnitude of the compressive stress of stress source 25 can be determined based on the thickness T of stress source 25. When the thickness T is large, the compressive stress can be large; when the thickness T is small, the compressive stress can be small.

[0027] The insulating spacer 23 may surround the seed layer 24. In one embodiment, the insulating spacer 23 may surround the sidewall of the seed layer 24. The insulating spacer 23 may include protrusions projecting toward the conductive layer. The insulating spacer 23 may insulate the seed layer 24 and the conductive layer 21 from each other. The insulating spacer 23 may include an insulating material such as an oxide or a nitride.

[0028] Reference Figure 2B The semiconductor device may include a gate structure GST, a contact plug 26A, a stress source 25, a seed layer 24A, a substrate 20, a source structure 28, an insulating spacer 23, or a combination thereof. The seed layer 24A may surround the sidewall of the stress source 25. The contact plug 26A may pass through the seed layer 24A to be directly connected to the source structure 28.

[0029] Reference Figure 2C The semiconductor device may include a gate structure GST, a contact plug 26A, a stress source 25A, a substrate 20, a source structure 28, an insulating spacer 23, or a combination thereof. The semiconductor device may not include a seed layer. Alternatively, the seed layer may be partially retained between the stress source 25A and the gate structure GST, or between the contact plug 26A and the source structure 28.

[0030] According to the structure described above, stress source 25 or 25A can be used to adjust the warpage of the semiconductor device. Even if a structure causing tensile stress (such as a gate structure GST) is formed on the front surface of the substrate 20, stress source 25 or 25A with compressive stress can be formed on the front surface of the substrate 20 to counteract the tensile stress of the semiconductor device. Furthermore, stress source 25 or 25A can be formed in the form of a spacer surrounding the sidewall of contact plug 26 or 26A, thereby efficiently positioning stress source 25 or 25A within the gate structure GST. Therefore, in one embodiment, warpage of the semiconductor device can be minimized or prevented.

[0031] Figures 3A to 3C This is a cross-sectional view showing the structure of a semiconductor device employing a stress source according to one embodiment. Detailed descriptions of content repeated above are omitted below.

[0032] Reference Figure 3A The semiconductor device may include a cell array CA and peripheral circuitry PC. The semiconductor device may include a substrate 30, a gate structure GST, a source contact structure SCT, a through-structure PS, a first interconnect IC1, a second interconnect IC2, a first interlayer insulating layer IL1, a second interlayer insulating layer IL2, or a combination thereof. The peripheral circuitry PC may be located below the cell array CA.

[0033] The cell array CA may include stacked memory cells. The cell array CA may include a gate structure GST and a source contact structure SCT, and may also include a source structure 38 or a through-type structure PS. The gate structure GST may include conductive layers 31 and insulating layers 32 stacked alternately on top of each other. The conductive layer 31 may be a word line, bit line, or select line. The conductive layer 31 may include a conductive material such as polysilicon, tungsten, or molybdenum.

[0034] The source contact structure SCT may include a contact plug 36 and a stress source 35 having compressive stress surrounding the contact plug 36 and having a sidewall. The source contact structure SCT may also include a seed layer or an insulating spacer. The source contact structure SCT may have the same characteristics as a reference. Figures 2A to 2C The described implementation methods have essentially the same or similar structures.

[0035] The through-structure PS can pass through the gate structure GST and extend to the source structure 38. The memory cell can be located at the intersection of the through-structure PS and the conductive layer 31.

[0036] In one embodiment, the through-structure PS can be a channel structure CH. The channel structure CH may include a channel layer 7 passing through the gate structure GST, and may also include a memory layer 8 surrounding the outer wall of the channel layer 7 or an insulating core 9 in the channel layer 7. The memory layer 8 may include a tunneling layer, a data storage layer, a barrier layer, or a combination thereof. The channel structure CH can be connected to the source structure 38 through the gate structure GST. The channel layer 7 can be directly connected to the source structure 38, or connected to the source structure 38 through an epitaxially grown semiconductor pattern.

[0037] In one embodiment, the through-structure PS can be an electrode structure. The electrode structure may include an electrode layer extending through the gate structure GST, and may also include a memory layer surrounding the outer or inner walls of the electrode layer. The memory layer may include a variable resistance material.

[0038] The first interlayer insulating layer IL1 may be located above the gate structure GST, and the first interconnect IC1 may be located within the first interlayer insulating layer IL1. The first interconnect IC1 may include a contact plug 5 and wiring 6. The first interconnect IC1 may be electrically connected to the through structure PS, the source contact structure SCT, and the gate structure GST.

[0039] The peripheral circuitry PC used to drive the cell array CA may include transistors TR, capacitors, and resistors. The substrate 30 may include an isolation layer 4, which may define an active region. The transistor TR may be located in the active region and includes a gate 1, a gate insulating layer 2, and a junction 3. The gate 1 may be located on the substrate 30, and the gate insulating layer 2 may be located between the gate 1 and the substrate 30. The junction 3 may be located in the substrate 30 on both sides of the gate 1.

[0040] The second interlayer insulating layer IL2 may be located between the substrate 30 and the source structure 38, and the second interconnect IC2 may be located within the second interlayer insulating layer IL2. The second interconnect IC2 may include contact plugs 5 and wiring 6, and is electrically connected to the peripheral circuit PC.

[0041] Reference Figure 3B The semiconductor device may include a cell array CA and peripheral circuitry PC. The semiconductor device may include a substrate 30, a gate structure GST, a source contact structure SCT, a through-structure PS, a first interconnect IC1, a second interconnect IC2, an interlayer insulating layer IL, or a combination thereof. The cell array CA and the peripheral circuitry PC may be adjacent to each other in a horizontal direction on the substrate 30.

[0042] Reference Figure 3C The semiconductor device may include a unit chip C_CHIP and a peripheral circuit chip P_CHIP. The unit chip C_CHIP may include a cell array CA. The cell array CA may include a first substrate 30A, a gate structure GST, a source contact structure SCT, a through structure PS, a first interconnect IC1, a first interlayer insulating layer IL1, a first bonding pad BP1, or a combination thereof. The peripheral circuit chip P_CHIP may include a second substrate 30B, a peripheral circuit PC, a second interconnect IC2, a second interlayer insulating layer IL2, a second bonding pad BP2, or a combination thereof. The peripheral circuit chip P_CHIP and the unit chip C_CHIP can be electrically connected to each other by bonding the first bonding pad BP1 and the second bonding pad BP2.

[0043] According to the structure described above, the semiconductor device may include a stress source 35 with compressive stress. Therefore, in one embodiment, tensile stress caused by various structures included in the semiconductor device can be offset by the stress source 35. Thus, in one embodiment, warping of the semiconductor device can be minimized or prevented.

[0044] Figure 4 This is a flowchart illustrating a method for manufacturing a semiconductor device according to one embodiment.

[0045] First, a test wafer can be fabricated in step S410. The test wafer can be a wafer structure including a substrate and a laminate formed on the substrate. The test wafer can have the same characteristics as described above. Figures 2A to 2C or Figures 3A to 3C The described implementation has a similar structure, but may not include stress sources. Because the test wafer does not include stress sources, tensile stress in the stacked layers may cause wafer warping during the manufacturing process of the test wafer.

[0046] Subsequently, the warpage of the test wafer can be measured in step S420. A warpage measuring device can be used to measure the bending direction, bending area, and degree of bending of the test wafer. In one embodiment, since the warpage of the wafer structure is measured, the magnitude of the tensile stress caused during the manufacture of the test wafer can be examined.

[0047] Subsequently, the compressive stress and target thickness of the stress source can be calculated in step S430. In one embodiment, a stress source can be implemented to improve the warpage of the test wafer. In one embodiment, when wafer warpage is caused by tensile stress, warpage can be improved by using a stress source with compressive stress. In one embodiment, when wafer warpage is caused by compressive stress, warpage can be improved by using a stress source with tensile stress.

[0048] In one embodiment, since the stress source has compressive stress and is included within the wafer structure, the tensile stress of the wafer structure can be offset. Therefore, in one embodiment, the location, shape, and size of the stress source can be configured to have compressive stress capable of minimizing or offsetting the tensile stress of the wafer structure. The compressive stress of the stress source can be proportional to the thickness of the stress source. In one embodiment, the target thickness of the stress source can be set according to the magnitude of the compressive stress required to improve wafer warpage.

[0049] A stress source can be formed by oxidizing a seed layer, and it can exhibit compressive stress as its volume expands during its formation process. When the oxidation amount is large, the degree of volume expansion is large, and the compressive stress of the stress source is also large. When the oxidation amount is small, the degree of volume expansion is small, and the compressive stress of the stress source is also small. Therefore, considering the target thickness of the stress source and the amount of volume increase when the seed layer is oxidized, the conditions for forming the stress source can be determined. The material of the seed layer, the thickness of the seed layer, the oxidation amount of the seed layer, and the formulation of the oxidation process can be set.

[0050] Subsequently, a semiconductor device can be manufactured in step S440. The semiconductor device may have a structure substantially the same as or similar to that of the test wafer, but may also include a stress source. The stress source can be formed based on the target thickness and location of the stress source calculated according to the measurement results of the warpage of the test wafer, the material of the seed layer, the thickness of the seed layer, the amount of oxidation of the seed layer, and the formulation of the oxidation process.

[0051] According to the manufacturing method described above, the target thickness of the stress source can be calculated based on the measurement results of the warpage of the test wafer, and a semiconductor device including a stress source having the target thickness can be manufactured. Therefore, in one embodiment, warpage of the semiconductor device can be minimized or prevented.

[0052] Figures 5A to 5GThis is a diagram illustrating a method for manufacturing a semiconductor device according to one embodiment.

[0053] Reference Figure 5A A source structure 50 can be formed. In one embodiment, the source structure 50 may include a conductive layer located on a substrate and comprising polysilicon, tungsten, and metal. The source structure 50 may also be an impurity region included in the substrate.

[0054] Subsequently, a stack ST can be formed on the source structure 50. The stack ST may include a first material layer 51 and a second material layer 52 alternately stacked on top of each other. The first material layer 51 may be used to form word lines, bit lines, and select lines, while the second material layer 52 may be used to form an insulating layer. The first material layer 51 may include a material with high etch selectivity relative to the second material layer 52. For example, the first material layer 51 may include a sacrificial material such as a nitride, while the second material layer 52 may include an insulating material such as an oxide. As another example, the first material layer 51 may include a conductive material such as polysilicon, tungsten, or molybdenum, while the second material layer 52 may include an insulating material such as an oxide.

[0055] Reference Figure 5B A first opening OP1 can be formed through the laminate ST. The first opening OP1 can expose the source structure 50. For reference, although not shown in the figure, a through structure through the laminate ST can be formed before the first opening OP1 is formed.

[0056] Subsequently, the first material layer 51 can be replaced with a third material layer 61 through the first opening OP1. In one embodiment, the first material layer 51 is removed through the first opening OP1 to form a second opening OP2. Subsequently, third material layers 61 are formed in the second opening OP2. After depositing the third material to fill the second opening OP2, some of the third material layers formed in the first opening OP1 can be etched into the third material layers 61 to form third material layers 61 that are separated from each other. Depending on the etching method, each of the third material layers 61 may have a circular sidewall R or a flat sidewall F.

[0057] The third material layer 61 may include a conductive material such as a metal. Replacing the first material layer 51 with the third material layer 61 may cause tensile stress due to the shrinkage of the third material layer 61. The third material layer 61 may shrink and have tensile stress during its formation process. For reference, when the first material layer 51 includes a conductive material, a siliconization process may also be performed instead of replacing the first material layer 51 with the third material layer 61.

[0058] Therefore, a gate structure (GST) comprising alternating layers of conductive and insulating layers can be formed. The gate structure (GST) can have a large aspect ratio and exhibit tensile stress.

[0059] Subsequently, a spacer layer 53 may be formed in the first opening OP1. The spacer layer 53 may be formed conformally along the contours of the first opening OP1 and the gate structure GST. The spacer layer 53 may be formed along the inner surface of the first opening OP1 and along the top surface of the gate structure GST. The spacer layer 53 may include an insulating material such as an oxide or a nitride.

[0060] Reference Figure 5C Spacer 53A can be formed. In one embodiment, spacer layer 53 can be etched on the front surface of spacer layer 53, and a portion of spacer layer 53 formed on the top surface of gate structure GST and a portion of spacer layer 53 formed on the bottom surface of first opening OP1 can be removed. Therefore, source structure 50 can be exposed on the bottom surface of first opening OP1, and spacer 53A can be formed on the inner wall of first opening OP1.

[0061] Reference Figure 5D A seed layer 54 can be formed in the first opening OP1. The seed layer 54 can be formed conformally along the contours of the first opening OP1 and the gate structure GST. The seed layer 54 can be formed along the inner surface of the first opening OP1 and along the top surface of the gate structure GST. The material, thickness, etc., of the seed layer 54 can be determined based on measurements of the warpage of the test wafer. In one embodiment, the seed layer 54 may include a material that expands in volume upon oxidation. The seed layer 54 may include silicon.

[0062] Reference Figure 5E A stress source layer 55 with compressive stress can be formed. The stress source layer 55 can be formed by expanding the seed layer 54. In one embodiment, the stress source layer 55 can be formed by oxidizing the seed layer 54. The surface of the seed layer 54 can be oxidized using an oxidation process. Because the silicon contained in the seed layer 54 is oxidized, the volume of the seed layer 54 may expand, and compressive stress may be induced due to this volume expansion. The target thickness of the stress source layer 55, the formulation of the oxidation process, etc., can be determined based on measurements of the warpage of the test wafer.

[0063] When the stress source layer 55 is formed, the seed layer 54 can be oxidized to a partial or full thickness. The oxidation thickness of the seed layer 54 can vary depending on the region. Therefore, the thickness of the remaining seed layer 54A can be uniform or varied. Alternatively, the seed layer 54A can be partially retained.

[0064] Reference Figure 5FStress source 55A can be formed. In one embodiment, stress source layer 55 can be etched on the front surface of stress source layer 55 to form stress source 55A. Therefore, a portion of stress source layer 55 formed on the bottom surface of the first opening OP1 or a portion of stress source layer 55 formed on the top surface of gate structure GST can be removed, and stress source 55A can be formed on the inner wall of the first opening OP1.

[0065] When etching the stress source layer 55, the seed layer 54A can be etched. A portion of the seed layer 54A formed on the bottom surface of the first opening OP1 or a portion of the seed layer 54A formed on the top surface of the gate structure GST can be removed. Because the seed layer 54A is etched, the source structure 50 can be exposed through the bottom surface of the first opening OP1. Alternatively, the seed layer 54A can remain on the bottom surface of the first opening OP1.

[0066] Reference Figure 5G A contact plug 56 can be formed in the first opening OP1. The contact plug 56 may include an aperture V. In one embodiment, after forming a conductive layer to fill the first opening OP1, the conductive layer can be planarized until the top surface of the gate structure GST is exposed, thereby forming the contact plug 56. During the planarization of the conductive layer, the seed layer 54A retained on the top surface of the gate structure GST can be removed together.

[0067] According to the manufacturing method described above, a stress source 55A with compressive stress can be formed on the sidewall of the contact plug 56. Since the stress source 55A is formed with a target thickness calculated based on the warpage of the test wafer, warpage of the semiconductor device can be minimized or prevented in one embodiment. Furthermore, after measuring the warpage of the semiconductor device including the stress source 55A, in one embodiment, the target thickness of the stress source 55A can be corrected based on the measurement results. Therefore, in one embodiment, warpage of the subsequently manufactured semiconductor device can be corrected.

[0068] One embodiment of this disclosure relates to a semiconductor device having a stable structure and improved properties, and a method for manufacturing the same.

[0069] According to one embodiment of this disclosure, a semiconductor device with a stable structure and improved reliability can be provided.

[0070] While this disclosure has been illustrated and described with reference to specific embodiments, the disclosed embodiments are provided for illustrative purposes and are not intended to be limiting. Furthermore, it should be noted that those skilled in the art will recognize from this disclosure that it can be implemented in various ways through substitutions, modifications, and variations falling within the scope of the appended claims.

[0071] Cross-reference of related applications

[0072] This application claims priority to Korean Patent Application No. 10-2022-0059089, filed on May 13, 2022, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, the semiconductor device comprising: A gate structure located on a source structure, the gate structure comprising alternating conductive layers and insulating layers; A contact plug passing through the gate structure and electrically connected to the source structure; A stress source surrounding the sidewall of the contact plug, the stress source including compressive stress; as well as A seed layer surrounding the stress source.

2. The semiconductor device according to claim 1, wherein, The seed layer comprises a material that expands in volume upon oxidation.

3. The semiconductor device according to claim 1, in, The seed layer comprises silicon, and The stress source includes silicon oxide.

4. The semiconductor device according to claim 1, wherein, The seed layer comprises polysilicon, silicon nitride, silicon oxynitride, or a combination thereof.

5. The semiconductor device according to claim 1, wherein, The seed layer surrounds the sidewall of the stress source.

6. The semiconductor device according to claim 1, wherein, The seed layer surrounds the sidewalls of the stress source and the bottom surface of the contact plug.

7. The semiconductor device of claim 1, further comprising an insulating spacer surrounding the seed layer.

8. The semiconductor device according to claim 1, wherein, The contact plug is directly connected to the source structure.

9. The semiconductor device according to claim 1, wherein, The contact plug is electrically connected to the source structure through the seed layer.

10. The semiconductor device according to claim 1, wherein, The tensile stress in the semiconductor device is offset by the compressive stress from the stress source.

11. A semiconductor device, the semiconductor device comprising: A gate structure comprising alternating layers of conductive and insulating materials, the gate structure including tensile stress; A contact plug that passes through the gate structure; A stress source surrounding the sidewall of the contact plug, the stress source including compressive stress; as well as A seed layer surrounding the stress source.

12. The semiconductor device according to claim 11, wherein, The seed layer comprises a material that expands in volume upon oxidation.

13. The semiconductor device according to claim 11, in, The seed layer comprises silicon, and The stress source includes silicon oxide.

14. A method for manufacturing a semiconductor device, the method comprising the following steps: A stacked structure is formed on the source electrode structure; A first opening is formed through the stack and exposes the source structure; A seed layer is formed in the first opening; A stress source including compressive stress is formed by expanding the seed layer; as well as A contact plug is formed in the stress source.

15. The manufacturing method according to claim 14, wherein, The step of forming the stress source includes oxidizing the seed layer to form the stress source.

16. The manufacturing method according to claim 14, wherein, The steps for forming the laminate include the following: Forming alternating layers of first and second materials; and The first material layer is replaced with a third material layer that has tensile stress.

17. The manufacturing method according to claim 14, further comprising the following step: An insulating spacer is formed in the first opening before the stress source is formed.

18. The manufacturing method according to claim 14, wherein, The seed layer comprises a material that expands in volume upon oxidation.

19. The manufacturing method according to claim 14, in, The seed layer comprises silicon, and The stress source includes silicon oxide.

20. The manufacturing method according to claim 14, further comprising the following step: Forming test wafers; Measure the warpage of the test wafer; as well as Calculate the target thickness of the stress source used to counteract the warping of the test wafer.

21. The manufacturing method according to claim 14, further comprising the following step: The warpage of the semiconductor device, including the stress source, is measured. as well as The target thickness of the stress source is corrected based on the measurement results of the warpage of the semiconductor device.

22. A method for manufacturing a semiconductor device, the method comprising the following steps: Forming a laminate comprising alternating layers of first and second materials; Forming a first opening through the stacked body; The first material layer is replaced by a third material layer with tensile stress through the first opening; A seed layer is formed in the first opening; By oxidizing the seed layer, a stress source including compressive stress is formed; as well as A contact plug is formed in the stress source.

23. The manufacturing method according to claim 22, wherein, The step of replacing the first material layer with a third material layer causes tensile stress due to the shrinkage of the third material layer.

24. The manufacturing method according to claim 22, further comprising the following step: An insulating spacer is formed in the first opening before the stress source is formed.

25. The manufacturing method according to claim 22, wherein, The seed layer comprises a material that expands in volume upon oxidation.

26. The manufacturing method according to claim 22, in, The seed layer comprises silicon, and The stress source includes silicon oxide.

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