Charge domain in-memory computing circuit based on sparse-tracked adc and computing method thereof

Abstract

The application discloses a charge domain in-memory computing circuit based on a sparse tracking ADC and a computing method thereof, and belongs to the technical field of integrated circuits. The circuit comprises a plurality of column in-memory computing unit arrays, each column is repeatedly arranged by a plurality of in-memory computing subunits, and the in-memory computing units repeatedly arranged on the column share one sparse tracking ADC. After external input feature data is processed by a locally sparse word line driving unit, the data is input into a local skip computing unit to perform a multiplication operation and accumulate voltage in a capacitor. The capacitors in the local skip computing units in multiple columns are connected in parallel to realize accumulation through charge sharing, and then the output result is obtained through quantization by the sparse tracking ADC. An external shift addition unit performs shift addition on the outputs of the four ADCs, and combines and outputs a multi-bit computing result. The application has small influence by process, voltage and temperature, high computing speed and high accuracy, breaks through the bottleneck of in-memory computing processing of sparse network data operation, and improves energy efficiency.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a charge domain in-memory calculation circuit and calculation method based on a sparse tracking ADC. Background Technology

[0002] In the traditional von Neumann architecture, the central processing unit (CPU) and memory are separate, transmitting data between them through a bandwidth-limited interface. With the continuous development of integrated circuit design technology and manufacturing processes, processor performance has significantly improved. However, memory bandwidth remains limited, exacerbating the problems of high data transmission latency and high energy consumption. Memory performance restricts further improvements in overall system performance, a phenomenon known as the von Neumann architecture's "memory wall problem." Furthermore, the rapid development of artificial intelligence technology has drastically increased the computational load on processors. For traditional von Neumann processors, a significant amount of energy and time is consumed in data transmission, often making it difficult for them to meet the computational power and energy efficiency requirements of neural networks.

[0003] Computing-in-Memory (CIM) is a feasible approach to solving the memory wall problem. In a compute-in-memory architecture, the memory retains both storage and read / write functions while also supporting common logical OR multiply-accumulate operations found in neural networks. Transferring the results of CIM between the processor and memory reduces the amount of data transferred between them, mitigating the impact of low memory bandwidth on overall system throughput. It also reduces energy consumption for data transfer, improving system energy efficiency.

[0004] Static Random Access Memory (SRAM) is a type of volatile memory that offers advantages such as CMOS process compatibility, fast access speed, low static power consumption, and high durability, making it a common memory for in-memory computing. Currently, SRAM-CIM can be categorized into time-domain, analog-domain, and digital-domain computing based on the computation method.

[0005] The mainstream approach to time-domain computation typically uses inverter chains to implement delays. Input and weight values ​​control the length of the delay, which is then accumulated through the inverter chain and quantized into a digital domain result by a Time-to-Digital Converter (TDC). Time-domain computation uses the length of the delay to characterize the computation result, overcoming the limitations of operating voltage on computational accuracy in the analog domain. However, in-memory time-domain computation is severely affected by process technology, voltage, and temperature (PVT). If the linearity and matching of the delay units are poor, the result accumulated through the delay chain is difficult to quantize correctly by the TDC. Furthermore, TDCs have large area overhead and require high frequency and stability of the reference clock. Some TDC designs introduce internal delay chains or phase-locked loops to reduce the influence of on-chip clocks, further increasing the area and power consumption of the TDC.

[0006] Digital domain computation involves only digital logic during computation, resulting in high precision and accuracy. However, the adders used in the accumulation process suffer from high power consumption and area overhead. Digital logic computation can only perform single-bit multiplication or addition in a single operation, exhibiting low parallelism. Multiplication requires numerous logic circuits and interconnections, leading to difficult layout routing and high area overhead.

[0007] Analog-domain computing converts input data and stored weights from the digital domain into analog quantities such as voltage and current for calculation. After the calculation, the result is then quantized back to the digital domain. As the precision of in-memory computing increases, the signal margin of analog signals is further compressed due to the upper limit of the circuit's operating voltage. This places extremely high demands on the accuracy of analog-to-digital conversion. However, high-precision analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) introduce significant latency and power consumption overhead, reducing the system's computing power-to-energy ratio. Therefore, for analog-domain in-memory computing, high precision and high computing power-to-energy ratio are mutually restrictive. Summary of the Invention

[0008] This invention provides a charge domain in-memory calculation circuit and its calculation method based on a sparse tracking ADC. By utilizing a sparse control module and a sparse tracking ADC, the calculation and quantization of sparse matrix multiplication can be well realized, and the sparsity can be used to achieve efficient calculation in most cases.

[0009] A first aspect of the present invention provides a charge domain in-memory calculation circuit based on a sparse tracking ADC, comprising:

[0010] The system consists of a local input control module composed of local input control units, a sparsely configured local word line drive module composed of sparsely configured local word line drive units, a sparse tracking ADC module with shared counting, read / write ports, timing control, in-memory control, a digital adder tree and shifter module, and 64 in-memory units arranged repeatedly in rows.

[0011] Each memory cell consists of 64 memory cells arranged in a column. Each memory cell includes four 6T-SRAM memory cells and one local selection calculation unit. The SRAM memory cells are used to store the weight data required for calculation.

[0012] Each memory-based computing unit is followed by a sparse tracking ADC module to quantize the calculation result of each column. That is, 64 memory-based computing units that are repeatedly arranged in columns share one sparse tracking ADC module. The output results of the four columns corresponding to the four sparse tracking ADC modules are processed by the digital adder tree and shifter module to complete one operation. The externally input feature data is processed by the sparsely configured local word line driving unit and then input into the local skip selection computing unit of the memory-based computing unit to perform a multiplication operation with the weight data and accumulate the voltage in the capacitor. The capacitors in the multiple column-oriented local skip selection computing units are connected in parallel to achieve accumulation through charge sharing. The output result is then quantized by the sparse tracking ADC module. The digital adder tree and shifter module shift and add the outputs of the four sparse tracking ADC modules to combine and output a multi-bit calculation result.

[0013] In one embodiment of the present invention, the memory operator unit includes four 6T-SRAM memory cells, a local bit line (LBL), a complementary local bit line (LBLB), a word line (WL), a horizontal word line (HWL), a global bit line (GBL), a complementary global bit line (GBLB), a third NMOS transistor (N3), and a fourth NMOS transistor (N4); the weighted storage nodes of the 6T-SRAM memory cells are all connected to the local bit lines (LBL), and the complementary weighted storage nodes of the 6T-SRAM memory cells are connected to the complementary local bit lines (LBLB); wherein, the third The drain of the third NMOS transistor (N3) is connected to the local bit line (LBL), the source is connected to the global bit line (GBL), and the gate is connected to the lateral word line (HWL); the drain of the fourth NMOS transistor (N4) is connected to the complementary local bit line (LBLB), the source is connected to the complementary global bit line (GBLB), and the gate is connected to the lateral word line (HWL); the 64 memory operators arranged in columns share the same global bit line (GBL) and complementary global bit line (GBLB); the 6T-SRAM memory cells in each row of the 64 memory operators arranged in rows share a word line (WL).

[0014] In one embodiment of the present invention, the local jump selection calculation unit (LJCC) includes an input signal line (VIN), a jump selection signal line (JUMP), a complementary jump selection signal line (JUMPB), a local bit line (LBL), a complementary local bit line (LBLB), a fifth NMOS transistor (N5), a first transmission gate (S1), a second transmission gate (S2), a capacitor (C), and an accumulation line (MBL). The input terminal of the first transmission gate (S1) is connected to the input signal line (VIN), the output terminal of the first transmission gate (S1) is connected to the drain of the fifth NMOS transistor (N5) and the upper plate of the capacitor (C), the control terminal of the first transmission gate (S1) is connected to the local bit line (LBL) signal line, and the complementary control terminal of the first transmission gate (S1) is connected to the complementary local bit line (LBLB) signal line. The source of the fifth NMOS transistor (N5) is connected to the common terminal (VSS), the drain of the fifth NMOS transistor (N5) is connected to the output of the first transmission gate (S1) and the upper plate of the capacitor (C), and the gate of the fifth NMOS transistor (N5) is connected to the complementary local bit line (LBLB) signal line; the upper plate of the capacitor (C) is connected to the output of the first transmission gate (S1) and the drain of the fifth NMOS transistor (N5), and the lower plate is connected to the input of the second transmission gate (S2); the input of the second transmission gate S2 is connected to the lower plate of the capacitor (C), the output of the second transmission gate (S2) is connected to the accumulation line (MBL), the control terminal of the second transmission gate (S2) is connected to the jump selection signal line (JUMP) signal line, and the complementary control terminal of the second transmission gate (S2) is connected to the complementary jump selection signal line (JUMPB).

[0015] In one embodiment of the present invention, the local input control unit comprises a 2-to-4 decoder and transmission gates S3, S4, S5, and S6. The input of the 2-to-4 decoder is a 2-bit binary digital signal. The input terminals of transmission gates S3, S4, S5, and S6 are four different external input voltages: VDIN0, VDIN1, VDIN2, and VDIN3, respectively. The output of the decoder and its inverse signal are connected to the control terminals of the transmission gates. When the decoder input is 00, transmission gate S3 is open, and transmission gates S4, S5, and S6 are connected. Input gate S5 and transmission gate S6 are closed; when the decoder input is 01, transmission gate S4 is open, and transmission gates S3, S5, and S6 are closed; when the decoder input is 10, transmission gate S5 is open, and transmission gates S3, S4, and S6 are closed; when the decoder input is 11, transmission gate S6 is open, and transmission gates S3, S4, and S5 are closed. This converts the 2-bit input digital signal into the corresponding analog voltage signal VDIN input, which is then connected to the input signal line (VIN) of the Local Jump Selection Calculation Unit (LJCC).

[0016] In one embodiment of the present invention, the sparsely configured local word line driving unit determines the number of local skip selection calculation units to be turned on based on the sparsity of the input features. When the input feature value is 1, the corresponding word line is driven to generate the corresponding skip selection signal and the complementary skip selection signal, and the corresponding memory calculation unit participates in the calculation. When the input feature value is 0, the word line is not driven and the corresponding memory calculation unit is turned off.

[0017] In one embodiment of the present invention, the sparse tracking ADC module includes a shared module and a multiplexed module. The shared module includes a sparse tracking compensation unit, a reference voltage generator, a shared counter, and a total shutdown module after calculation. 64 multiplexed modules share one shared module. The sparse tracking compensation unit consists of four capacitors, which are matched with different total capacitances based on input characteristics to determine the output range of the signal line (VDAC) to match the actual accumulation line (MBL) voltage swing. The reference voltage generator generates a reference voltage based on the counter count. The multiplexed module includes a comparator, a pulse generation circuit, a latch module, and a column shutdown module. Each memory unit corresponds to one multiplexed module, for a total of 64 multiplexed modules. First, a comparator is used to compare the reference voltage output by the shared module with the accumulation line (MBL) voltage. When the reference voltage is greater than the accumulation line (MBL) voltage, a pulse signal is generated, and the current counter value is latched as the output result of the sparse tracking ADC module. At the same time, the pulse signal is input to the column shutdown module to generate a column completion signal (column_finish). After all columns have completed the comparison, the total shutdown module in the shared module generates an ADC shutdown signal (finish_all) to shut down all sparse tracking ADC modules. The sparse tracking ADC module obtains a 5-bit data output (ADC_OUTn), which represents the quantization result of the multiplication results accumulated on the same column.

[0018] In one embodiment of the present invention, the digital adder and shifter module performs a shift and add operation on the four 5-bit sparse tracking ADC output results (ADC_OUTn) of each memory unit. The shift and add operation is essentially a signed multiplication operation. The calculation result needs to be extended with a corresponding sign bit. The specific extension method depends on whether the multiplicand and multiplier are signed numbers. The digital adder and shifter module performs a 1-bit unsigned number and a 4-bit signed number multiplication operation on the sparse tracking ADC output result. The corresponding sign bit extension operation is to fill the highest bit of the last addend, invert the highest bit, and add one. Finally, a 9-bit data output calculation result (QOUTn[8:0]) is obtained, which is represented by the result of multiplying and adding the 2-bit input and 4-bit weight of 64 channels. The memory calculation circuit has a total of 64 memory units, and each time 16 9-bit output results are obtained.

[0019] In one embodiment of the present invention, multiple local skip selection calculation units arranged repeatedly in rows correspond to one local input control unit and one sparsely configured local word line driving module; the outputs of 64 local skip selection calculation units arranged repeatedly in columns are connected to the same accumulation line (MBL); the connection relationship between the local skip selection calculation unit and the sparse tracking ADC is as follows: the accumulation line (MBL) of the local skip selection calculation unit is connected to the input of the sparse tracking ADC, and the analog-to-digital conversion is performed to quantize the result into 5 bits; the connection relationship between the sparse tracking ADC and the digital adder and shifter module is as follows: the four 5-bit calculation results corresponding to the four sparse tracking ADCs are connected to the input of one digital adder and shifter module to obtain one 9-bit output data (QOUTn[8:0]); or it is configured to complete the operation of 13-bit output data in two cycles, the first cycle outputs multiple 9-bit data, and the second cycle shifts and adds every two 9-bit data to obtain a 13-bit output data QOUT[12:0].

[0020] A second aspect of the present invention provides a calculation method for a charge domain in-memory calculation circuit based on a sparse tracking ADC, comprising the following steps:

[0021] When the computation cycle of the memory unit begins, the horizontal word line (HWL) is first set to a low level. At the same time, the corresponding word line (WL) is opened according to the sparse configuration of the local word line driver module, and the corresponding jump selection signal (JUMP) and complementary jump selection signal (JUMPB) are generated.

[0022] When the sparsely configured local word line driver module does not select a memory cell, the memory cell does not work and does not participate in the calculation process;

[0023] When the sparsely configured local word line module selects a memory cell, the data stored in the 6T-SRAM memory cell is read onto the local bit line (LBL) and the complementary local bit line (LBLB). When the value stored in the SRAM is 0, the complementary local bit line (LBLB) signal is 1, the fifth NMOS transistor (N5) in the local skip-selection calculation unit is turned on, and the upper plate of the capacitor is grounded. When the value stored in the SRAM is 1, the complementary local bit line (LBLB) signal is 0, the fifth NMOS transistor (N5) in the local skip-selection calculation unit is turned off, and the local bit line (LBL) is... When the signal is 1, the first transmission gate (S1) of the local skip selection calculation unit is opened, so that the corresponding VIN voltage is transmitted to the upper plate of the capacitor. The skip selection signal (JUMP) and the complementary skip selection signal (JUMPB) open the transmission gate, so that the lower plates of the capacitors of the corresponding multiple local skip selection calculation units are connected and participate in the calculation process of capacitive coupling and charge sharing. The analog voltage generated by the multiplication and addition of multiple memory units is quantized by the sparse tracking ADC to produce a 5-bit result. The entire memory circuit realizes the shift and addition of the quantization results of the four sparse tracking ADCs through the digital adder tree and shifter module to obtain the final result.

[0024] In one embodiment of the present invention, each local skip selection calculation unit of the in-memory computing circuit calculates 1 bit weight multiplied by 2 bits of input signal, and each in-memory unit corresponds to one local input control unit; each column of the in-memory array is connected to a sparse tracking ADC to quantize and obtain a 5-bit binary result; the output signal of the entire in-memory computing circuit is the QOUT of the digital adder tree and shifter module. <n>The binary result.

[0025] This invention provides a charge-domain in-memory computation circuit and method based on a sparse tracking ADC, enabling high-speed, high-precision, and high-accuracy computation. In this circuit, the product of the input and weights determines the analog voltage, and the ADC circuit quantizes the computation result. Compared to ordinary analog domain computation, it overcomes the bottleneck of in-memory computation in handling sparse network data, while also improving energy efficiency. Compared to the digital domain, this circuit utilizes capacitive coupling and charge sharing to achieve multiplication and accumulation operations, reducing the number of transistors in the arithmetic unit and enabling multiple operations in one cycle. Compared to ordinary analog domain ADC modules, this invention, using a sparse control module and a sparse tracking ADC, can better achieve the computation and quantization of sparse matrix multiplication, and leverages sparsity to achieve efficient computation in most cases.

[0026] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0027] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0028] Figure 1 This is a structural diagram of a charge domain in-memory computing circuit based on a sparse tracking ADC according to an embodiment of the present invention;

[0029] Figure 2 This is a schematic diagram of the structure of the in-memory operator unit of the charge domain in-memory computing circuit based on a sparse tracking ADC provided in an embodiment of the present invention.

[0030] Figure 3 This is a schematic diagram of the sparse tracking ADC structure of the charge domain in-memory computing circuit based on the sparse tracking ADC provided in an embodiment of the present invention.

[0031] Figure 4 This is a schematic diagram of the working waveform of the charge domain in-memory calculation circuit based on a sparse tracking ADC provided in an embodiment of the present invention;

[0032] Figure reference numerals: Local bit line LBL, complementary local bit line LBLB, global bit line GBL, complementary global bit line GBLB, horizontal word line HWL, word line WL, jump selection signal line JUMP, complementary jump selection signal line JUMPB, external input signal line VIN, power supply VDD, common terminal VSS; first NMOS transistor N1, second NMOS transistor N2, third NMOS transistor N3, fourth NMOS transistor N4, fifth NMOS transistor N5, first inverter INV1, second inverter INV2, first transmission gate S1, second transmission gate S2, capacitor C, capacitor C0, capacitor C1, capacitor C2, capacitor Cm, capacitor CT0, capacitor CT1, capacitor CT2, capacitor CT3, capacitor CT4, transmission gate CPC[0], transmission gate CPC[1], transmission gate CPC[2]. Detailed Implementation

[0033] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0034] Figure 1 This is a structural diagram of a charge domain in-memory computing circuit based on a sparse tracking ADC, according to an embodiment of the present invention.

[0035] like Figure 1 As shown, the charge domain in-memory computing circuit based on sparse tracking ADC includes: a local input control module composed of local input control units, a sparsely configured local word line driving module composed of sparsely configured local word line driving units, a sparse tracking ADC module with shared counting, a read / write port, timing control, in-memory control, a digital adder tree and a shifter module, and 64 in-memory units arranged repeatedly in rows;

[0036] Each memory cell consists of 64 memory cells arranged in a column. Each memory cell includes four 6T-SRAM memory cells and one local selection calculation unit. The SRAM memory cells are used to store the weight data required for calculation.

[0037] Each memory-based computing unit is followed by a sparse tracking ADC module to quantize the calculation results of each column. That is, 64 memory-based computing units that are repeatedly arranged in columns share one sparse tracking ADC module. The output results of the four columns corresponding to the four sparse tracking ADC modules are processed by a digital adder tree and a shifter module to complete one operation. The externally input feature data is processed by the sparsely configured local word line driving unit and then input into the local skip selection computing unit of the memory-based computing unit to perform a multiplication operation with the weight data and accumulate the voltage in the capacitor. The capacitors in the multiple column-oriented local skip selection computing units are connected in parallel to achieve accumulation through charge sharing. The output results are then quantized by the sparse tracking ADC module. The digital adder tree and shifter module shift and add the outputs of the four sparse tracking ADC modules to combine and output a multi-bit calculation result.

[0038] like Figure 1 As shown, the in-memory computing circuit includes a Local Input Control Unit (LVICU), a sparsely configured Local Word Line Drive Unit (LDRV), a sparse tracking ADC module with shared counting, read / write ports, timing control, in-memory control, a digital adder tree and shifter module (DAS), and 64 in-memory units arranged repeatedly in rows. Each in-memory unit consists of 64 in-memory sub-units arranged repeatedly in columns. Each in-memory sub-unit includes four 6T-SRAM memory cells and one Local Jump Select Computation Unit (LJCC). Each in-memory unit is followed by a sparse tracking ADC to quantize the calculation result of each column. The output results of the four ADCs corresponding to the four columns are processed by the digital adder tree and shifter module (DAS) to complete one operation.

[0039] like Figure 2 As shown, the SRAM memory cell array includes four 6T-SRAM memory cells, a local bit line (LBL), a complementary local bit line (LBLB), a word line (WL), a horizontal word line (HWL), a global bit line (GBL), and a complementary global bit line (GBLB). The weighted storage nodes of the 6T-SRAM memory cells are all connected to the local bit lines (LBL), and the complementary weighted storage nodes of the SRAM memory cells are connected to the complementary local bit lines (LBLB). The drain of the first NMOS transistor (N1) is connected to the local bit line. (LBL), source connected to global bit line (GBL), gate connected to lateral word line (HWL); the drain of the second NMOS transistor (N2) is connected to complementary local bit line (LBLB), source connected to complementary global bit line (GBLB), gate connected to lateral word line (HWL); 64 memory operators arranged repeatedly in columns share the same global bit line (GBL) and complementary global bit line (GBLB); 6T-SRAM memory cells in each row of the 64 memory operators arranged repeatedly in rows share a word line (WL).

[0040] Furthermore, the 6T-SRAM memory cell includes: a first NMOS transistor (N1), a second NMOS transistor (N2), a first inverter (INV1), and a second inverter (INV2). The source of the first NMOS transistor (N1) is connected to the local bit line (LBL), the gate is connected to the word line (WL), and the drain is connected to the input of the first inverter (INV1) and the output of the second inverter (INV2), respectively. The source of the second NMOS transistor (N2) is connected to the complementary local bit line (LBLB), the gate is connected to the word line (WL), and the drain is connected to the output of the first inverter (INV1) and the input of the second inverter (INV2), respectively.

[0041] Furthermore, the first inverter INV1 includes: a first PMOS transistor (P1) and a first NMOS transistor (N1). The source of the first PMOS transistor (P1) is connected to the power supply (VDD), the drain is connected to the output terminal (OUT), and the gate is connected to the input terminal (IN); the source of the first NMOS transistor (N1) is connected to the common terminal (VSS), the drain is connected to the output terminal (OUT), and the gate is connected to the input terminal (IN).

[0042] The Local Selection Calculation Unit (LJCC) includes: an input signal line (VIN), a selection signal line (JUMP), a complementary selection signal line (JUMPB), a local bit line (LBL), a complementary local bit line (LBLB), an accumulation line (MBL), a fifth NMOS transistor (N5), a first transmission gate (S1), a second transmission gate (S2), and a capacitor (C). The input terminal of the first transmission gate (S1) is connected to the input signal line (VIN), the output terminal is connected to the drain of the fifth NMOS transistor (N5) and the upper plate of the capacitor (C), the control terminal is connected to the local bit line (LBL) signal line, and the complementary control terminal is connected to the complementary local bit line (L...). The source of the fifth NMOS transistor (N5) is connected to the common terminal (VSS), the drain is connected to the output of the first transmission gate (S1) and the upper plate of the capacitor (C), and the gate is connected to the complementary local bit line (LBLB) signal line; the upper plate of the capacitor (C) is connected to the output of the first transmission gate (S1) and the drain of the fifth NMOS transistor (N5), and the lower plate is connected to the input of the second transmission gate (S2); the input of the second transmission gate (S2) is connected to the lower plate of the capacitor (C), the output is connected to the accumulation line (MBL), the control terminal is connected to the jump selection signal line (JUMP), and the complementary control terminal is connected to the complementary jump selection signal line (JUMPB).

[0043] The Local Input Control Unit (LVICU) mainly consists of a 2-to-4 decoder and four transmission gates (S3, S4, S5, and S6). The 2-to-4 decoder takes a 2-bit binary digital signal as input. The inputs of transmission gates S3, S4, S5, and S6 are VDIN0, VDIN1, VDIN2, and VDIN3, respectively, representing four different external input voltages. The decoder's output and its inverse signal are connected to the control terminals of the transmission gates. When the decoder input is 00, transmission gate S3 is open, and the other three transmission gates are closed; when the decoder input is 01, transmission gate S4 is open, and the other three transmission gates are closed; when the decoder input is 10, transmission gate S5 is open, and the other three transmission gates are closed; when the decoder input is 11, transmission gate S6 is open, and the other three transmission gates are closed. In this way, the 2-bit input digital signal is converted into the corresponding analog voltage signal VDIN, which is then connected to the input signal line (VIN) of the Local Jump Selection Calculation Unit (LJCC).

[0044] The sparsely configured local word line driving units determine the number of local jump selection computation units (LJCCs) to be activated based on the sparsity of the input features. When the input feature value is 1, the corresponding word line is driven, simultaneously generating the corresponding jump selection signal (JUMP) and complementary jump selection signal (JUMPB), and the corresponding memory-based computation unit participates in the computation. When the input feature value is 0, the word line is not driven, and the corresponding memory-based computation unit is turned off, thereby saving energy consumption.

[0045] like Figure 3 As shown, the sparse tracking ADC with shared counting includes a shared module and multiplexed modules. The shared module includes a sparse tracking compensation unit (CAP) for sparse tracking, a reference voltage generator (CDAC), a shared counter, and a total shutdown module after calculation. 64 multiplexed modules share one shared module. The sparse tracking compensation unit (CAP) consists of four capacitors, and different total capacitances are matched according to the input characteristics to determine the output range of the signal line (VDAC) to match the actual accumulation line (MBL) voltage swing. The reference voltage generator (CDAC) generates a reference voltage based on the counter count. The multiplexed modules include comparators, pulse generation circuits, latch modules, and column shutdown modules. Each memory unit corresponds to one multiplexed module, for a total of 64 multiplexed modules. First, a comparator compares the reference voltage output from the shared module with the accumulation line (MBL) voltage. Once the reference voltage exceeds the MBL voltage, a pulse signal is generated, latching the counter value at that moment; this value is the ADC output. Simultaneously, the pulse signal is input to the column shutdown module, generating a column-finish signal. After all columns have completed the comparison, the overall shutdown module in the shared module generates an ADC shutdown signal (finish_all) to turn off all ADCs, thus saving significant power consumption when the overall quantization result is small. Finally, the sparse tracking ADC outputs a 5-bit data, representing the quantized result of the sum of multiplication results from the same column.

[0046] In the shared module, the sparse tracking compensation unit (CAP) includes: capacitors C0, C1, C2, and Cm; transmission gates CPC[0], CPC[1], and CPC[2]; and signal line VDAC. The capacitance values ​​of capacitors C0, C1, C2, and Cm are all the same, and their two ends are connected to VSS and signal line VDAC, respectively. Transmission gates CPC[0], CPC[1], and CPC[2] are connected to signal line VDAC, which are used to control the on / off state between capacitors C0, C1, and C2 and signal line VDAC, respectively. The reference voltage generator (CDAC) includes: capacitors CT0, CT1, CT2, CT3, and CT4; outputs of digital counters Count[0], Count[1], Count[2], Count[3], and Count[4]; and signal line VDAC. The capacitance values ​​of capacitors CT0, CT1, CT2, CT3, and CT4 decrease proportionally, and their upper and lower plates are connected to Count[0], Count[1], Count[2], Count[3], Count[4], and signal line VDAC, respectively. The change in the counter output value causes different voltage divisions in the capacitors, thus generating different reference voltages.

[0047] The Digital Adder and Shifter (DAS) module shifts and adds the outputs (ADC_OUTn) of the four sparse tracking ADCs corresponding to the four memory units, thus adding four 5-bit data. This process is essentially a signed multiplication operation, and the result needs to be extended with a sign bit. The specific extension method depends on whether the multiplicand and multiplier are signed numbers. The DAS module performs a 1-bit unsigned multiplication and a 4-bit signed multiplication on the ADC output. The corresponding sign bit extension operation is to pad the last addend with the highest bit, invert the highest bit, and add one, finally obtaining a 9-bit data output result (QOUTn[8:0]) with a sign bit. This result represents the addition of a 2-bit input and a 4-bit weight from a 64-channel multiplication.

[0048] In the memory-based computing circuit, multiple SRAM memory sub-units arranged repeatedly in rows share one local input control unit and one sparsely configured local word line driver module; the outputs of the local jump selection calculation units (LJCCs) of 64 SRAM memory sub-units arranged repeatedly in columns are connected to the same accumulation line (MBL); the connection relationship between the SRAM memory sub-units and the sparse tracking ADC is that the local jump selection calculation unit (LJCC) of each memory sub-unit selected by the sparsely configured local word line driver module in the same column participates in the multiplication operation to generate VOUT[n], and all VOUTs are connected to the same accumulation line (MBL) to complete the accumulation in the analog domain. Then it is connected to the input of the sparse tracking ADC, and the analog-to-digital conversion is quantized into a 5-bit calculation result; the connection relationship between the sparse tracking ADC and the digital adder and shifter module (DAS) is as follows: the four 5-bit calculation results corresponding to the four sparse tracking ADCs are connected to the input of one digital adder and shifter module to obtain a 9-bit output data (QOUTn[8:0]); or it can be configured to complete the operation of 13-bit output data in two cycles. In the first cycle, multiple 9-bit data are output, and in the second cycle, the shift and addition of every two 9-bit data are processed to obtain a 13-bit output data (QOUT[12:0]).

[0049] The analog domain in-memory computation method based on the above computing circuit includes the following steps: when the computation cycle of the in-memory unit begins, the horizontal word line (HWL) is first set to a low level, and at the same time, the corresponding word line (WL) is opened according to the sparsely configured local word line driving module, and the corresponding jump selection signal (JUMP) and complementary jump selection signal (JUMPB) are generated. When the local word line driver module does not select the memory-based computing unit, the memory-based computing unit does not work and does not participate in the calculation process. When the local word line module selects the memory-based computing unit, the data stored in the 6T-SRAM memory cell is read onto the local bit line (LBL) and the complementary local bit line (LBLB). When the value stored in the SRAM is 0, the complementary local bit line (LBLB) signal line is 1, the fifth NMOS transistor (N5) in the local jump-selection computing unit (LJCC) is turned on, and the upper plate of the capacitor is grounded. When the value stored in the SRAM is 1, the complementary local bit line (LBLB) signal is 0, the fifth NMOS transistor (N5) in the local jump-selection computing unit (LJCC) is turned off, the local bit line (LBL) signal is 1, and the first transmission gate of the local jump-selection computing unit (LJCC) is opened, so that the voltage of the corresponding input signal line (VIN) is transmitted to the upper plate of the capacitor. The jump selection signal (JUMP) and the complementary jump selection signal (JUMPB) open the transmission gate, connecting the lower plates of the capacitors of the corresponding multiple column-oriented local jump selection computation units (LJCCs), which then participate in the calculation process of capacitive coupling and charge sharing. The analog voltage generated by the multiplication and addition of multiple memory units is quantized by a sparse tracking ADC to produce a 5-bit result. The entire memory circuit uses a digital adder tree and a shifter module to shift and add the quantized results of the four sparse tracking ADCs to obtain the final result (QOUTn[8:0]).

[0050] Each Local Jump-Selection Computation Unit (LJCC) in the in-memory computing circuit can calculate 1 bit weight multiplied by 2 bits of input signal, and each in-memory unit corresponds to one local input control unit; each column of the in-memory array is connected to a sparse tracking ADC to quantize and obtain a 5-bit binary result; the output signal of the entire in-memory computing circuit is the QOUT of the digital adder tree and shifter module. <n>The binary result.

[0051] Figure 4 This demonstrates a working waveform of this embodiment. When the computation cycle of the storage unit begins, if the input element in the sparse matrix is ​​0, then each module is not enabled; if the input element in the sparse matrix is ​​1, the word line (WL) and jump selection signal (JUMP) are enabled, and the weight data stored in the SRAM memory cell is read onto the local bit line (LBL) and complementary bit line (LBLB), and input to the local jump selection computation unit (LJCC) to participate in the multiplication operation to generate VOUT[n], that is, to perform one operation.

[0052] This invention proposes a charge-domain in-memory computation circuit and method based on a sparse tracking ADC. In this circuit, the product of the input and weights determines the analog voltage, and the ADC circuit quantizes the computation result. Compared with ordinary analog domain computation, this overcomes the bottleneck of in-memory computation in processing sparse network data, while improving energy efficiency. Compared with the digital domain, this circuit utilizes capacitive coupling and charge sharing to achieve multiplication and accumulation operations, reducing the number of transistors in the arithmetic unit and enabling multiple operations in one cycle. Furthermore, compared to ordinary analog domain ADC modules, this invention utilizes a sparse control module and a sparse tracking ADC to better achieve the calculation and quantization processing of sparse matrix multiplication, leveraging sparsity to achieve efficient computation in most cases: the sparse tracking ADC can match different total capacitances according to the input sparsity to determine the output range of the signal line (VDAC) to match the voltage swing of the actual accumulation line (MBL), thereby improving the signal margin under high sparsity conditions; the total shutdown module of the shared module in the sparse tracking ADC can immediately generate an ADC shutdown signal (finish_all) to shut down all ADCs after all columns have been compared, thereby significantly accelerating the quantization speed and saving a lot of power consumption; and each memory unit is connected to a sparse tracking ADC, which can flexibly realize multi-bit reconstruction.

[0053] In the description of this specification, the references to "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0054] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "N" means at least two, such as two, three, etc., unless otherwise explicitly specified.< / n> < / n>

Claims

1. A charge domain in-memory computing circuit based on a sparse tracking ADC, characterized in that, include: The system consists of a local input control module composed of local input control units, a sparsely configured local word line drive module composed of sparsely configured local word line drive units, a sparse tracking ADC module with shared counting, read / write ports, timing control, in-memory control, a digital adder tree and shifter module, and 64 in-memory units arranged repeatedly in rows. Each memory cell consists of 64 memory cells arranged in a column. Each memory cell includes four 6T-SRAM storage cells and one local selection calculation cell. The SRAM storage cells are used to store the weight data required for calculation. Each memory-based computing unit is followed by a sparse tracking ADC module to quantize the calculation result of each column. That is, 64 memory-based computing units that are repeatedly arranged in columns share one sparse tracking ADC module. The output results of the four columns corresponding to the four sparse tracking ADC modules are processed by the digital adder tree and shifter module to complete one operation. The externally input feature data is processed by the sparsely configured local word line driving unit and then input into the local skip selection computing unit of the memory-based computing unit to perform a multiplication operation with the weight data and accumulate the voltage in the capacitor. The capacitors in the multiple column-oriented local skip selection computing units are connected in parallel to achieve accumulation through charge sharing. The output result is then quantized by the sparse tracking ADC module. The digital adder tree and shifter module shift and add the outputs of the four sparse tracking ADC modules to combine and output a multi-bit calculation result. The sparse tracking ADC module includes a shared module and multiplexed modules. The shared module includes a sparse tracking compensation unit, a reference voltage generator, a shared counter, and a total shutdown module after calculation. 64 multiplexed modules share one shared module. The sparse tracking compensation unit consists of four capacitors, which are matched with different total capacitors based on input characteristics to determine the output range of the signal line (VDAC) to match the actual accumulation line (MBL) voltage swing. The reference voltage generator produces a reference voltage based on the counter count. The multiplexed modules include a comparator, a pulse generation circuit, a latch module, and a column shutdown module. Each memory unit corresponds to one multiplexed module, for a total of 64 multiplexed modules. Firstly... A comparator is used to compare the reference voltage output by the shared module with the accumulation line (MBL) voltage. When the reference voltage is greater than the accumulation line (MBL) voltage, a pulse signal is generated, and the current counter value is latched as the output result of the sparse tracking ADC module. At the same time, the pulse signal is input to the column shutdown module to generate a column completion signal (column_finish). After all columns have completed the comparison, the total shutdown module in the shared module generates an ADC shutdown signal (finish_all) to shut down all sparse tracking ADC modules. The sparse tracking ADC module obtains a 5-bit data output (ADC_OUTn), which represents the quantized result of the multiplication results accumulated on the same column.

2. The charge domain in-memory calculation circuit based on a sparse tracking ADC according to claim 1, characterized in that, The in-memory unit includes four 6T-SRAM memory cells, a local bit line (LBL), a complementary local bit line (LBLB), a word line (WL), a horizontal word line (HWL), a global bit line (GBL), a complementary global bit line (GBLB), a third NMOS transistor (N3), and a fourth NMOS transistor (N4). The weighted storage nodes of each 6T-SRAM memory cell are connected to the local bit lines (LBL), and the complementary weighted storage nodes of each 6T-SRAM memory cell are connected to the complementary local bit lines (LBLB). The third NMOS transistor... (N3) Drain connected to local bit line (LBL), source connected to global bit line (GBL), gate connected to lateral word line (HWL); fourth NMOS transistor (N4) drain connected to complementary local bit line (LBLB), source connected to complementary global bit line (GBLB), gate connected to lateral word line (HWL); 64 memory operators arranged repeatedly in columns share the same global bit line (GBL) and complementary global bit line (GBLB); 6T-SRAM memory cells in each row of the 64 memory operators arranged repeatedly in rows share a word line (WL).

3. The charge domain in-memory calculation circuit based on a sparse tracking ADC according to claim 1, characterized in that, The Local Selection Calculation Unit (LJCC) includes an input signal line (VIN), a selection signal line (JUMP), a complementary selection signal line (JUMPB), a local bit line (LBL), a complementary local bit line (LBLB), a fifth NMOS transistor (N5), a first transmission gate (S1), a second transmission gate (S2), a capacitor (C), and an accumulation line (MBL). The input terminal of the first transmission gate (S1) is connected to the input signal line (VIN), the output terminal of the first transmission gate (S1) is connected to the drain of the fifth NMOS transistor (N5) and the upper plate of the capacitor (C), the control terminal of the first transmission gate (S1) is connected to the local bit line (LBL) signal line, and the complementary control terminal of the first transmission gate (S1) is connected to the complementary local bit line (LBLB) signal line. The source of the S-channel MOSFET (N5) is connected to the common terminal (VSS). The drain of the fifth NMOS transistor (N5) is connected to the output of the first transmission gate (S1) and the upper plate of the capacitor (C). The gate of the fifth NMOS transistor (N5) is connected to the complementary local bit line (LBLB) signal line. The upper plate of the capacitor (C) is connected to the output of the first transmission gate (S1) and the drain of the fifth NMOS transistor (N5). The lower plate is connected to the input of the second transmission gate (S2). The input of the second transmission gate (S2) is connected to the lower plate of the capacitor (C). The output of the second transmission gate (S2) is connected to the accumulation line (MBL). The control terminal of the second transmission gate (S2) is connected to the jump selection signal line (JUMP) signal line. The complementary control terminal of the second transmission gate (S2) is connected to the complementary jump selection signal line (JUMPB).

4. The charge domain in-memory calculation circuit based on a sparse tracking ADC according to claim 1, characterized in that, The local input control unit consists of a 2-to-4 decoder and transmission gates S3, S4, S5, and S6. The input of the 2-to-4 decoder is a 2-bit binary digital signal. The input terminals of transmission gates S3, S4, S5, and S6 are four different external input voltages: VDIN0, VDIN1, VDIN2, and VDIN3, respectively. The output of the decoder and its inverse signal are connected to the control terminals of the transmission gates. When the decoder input is 00, transmission gate S3 is open, and transmission gates S4, S5, and S6 are closed; when the decoder input is 01, transmission gate S4 is open, and transmission gates S3, S5, and S6 are closed. When the decoder input is 10, transmission gate S5 is open, and transmission gates S3, S4, and S6 are closed. When the decoder input is 11, transmission gate S6 is open, and transmission gates S3, S4, and S5 are closed. This converts the 2-bit input digital signal into the corresponding analog voltage signal VDIN, which is then connected to the input signal line (VIN) of the Local Jump Selection Calculation Unit (LJCC).

5. The charge domain in-memory calculation circuit based on a sparse tracking ADC according to claim 1, characterized in that, The sparsely configured local word line driving unit determines the number of local skip selection calculation units to be turned on based on the sparsity of the input features. When the input feature value is 1, the corresponding word line is driven to generate the corresponding skip selection signal and complementary skip selection signal, and the corresponding memory-based calculation unit participates in the calculation. When the input feature value is 0, the word line is not driven and the corresponding memory-based calculation unit is turned off.

6. The charge domain in-memory calculation circuit based on a sparse tracking ADC according to claim 1, characterized in that, The digital adder and shifter module performs a shift and add operation on the four 5-bit sparse tracking ADC outputs (ADC_OUTn) of each memory unit. The shift and add operation is essentially a signed multiplication operation. The calculation result needs to be extended with a corresponding sign bit. The specific extension method depends on whether the multiplicand and multiplier are signed numbers. The digital adder and shifter module performs a 1-bit unsigned number and a 4-bit signed number multiplication operation on the sparse tracking ADC output. The corresponding sign bit extension operation is to fill the highest bit of the last addend, invert the highest bit, and add one. Finally, a 9-bit data output calculation result (QOUTn[8:0]) is obtained, which is represented by the result of multiplying and adding the 2-bit input and 4-bit weight of the 64-channel. The memory calculation circuit has a total of 64 memory units, and each time 16 9-bit output results are obtained.

7. The charge domain in-memory calculation circuit based on a sparse tracking ADC according to claim 1, characterized in that, Multiple local skip selection calculation units arranged repeatedly in rows correspond to one local input control unit and one sparsely configured local word line driver module; the outputs of 64 local skip selection calculation units arranged repeatedly in columns are connected to the same accumulation line (MBL); the connection relationship between the local skip selection calculation unit and the sparse tracking ADC is as follows: the accumulation line (MBL) of the local skip selection calculation unit is connected to the input of the sparse tracking ADC, and the analog-to-digital conversion is performed to quantize the result into 5 bits; The connection relationship between the sparse tracking ADC and the digital adder and shifter module is as follows: the four 5-bit calculation results corresponding to the four sparse tracking ADCs are connected to the input of one digital adder and shifter module to obtain one 9-bit output data (QOUTn[8:0]); or it can be configured to complete the operation of 13-bit output data in two cycles. In the first cycle, multiple 9-bit data are output, and in the second cycle, the shift and addition of every two 9-bit data are processed to obtain a 13-bit output data QOUT[12:0].

8. A calculation method for a charge domain in-memory computing circuit based on a sparse tracking ADC, executed on the computing circuit according to any one of claims 1 to 7, characterized in that, Includes the following steps: When the computation cycle of the memory unit begins, the horizontal word line (HWL) is first set to low level, and the corresponding word line (WL) is opened according to the sparse configuration of the local word line driver module, and the corresponding jump selection signal (JUMP) and complementary jump selection signal (JUMPB) are generated. When the sparsely configured local word line driver module does not select a memory cell, the memory cell does not work and does not participate in the calculation process; When the sparsely configured local word line module selects the in-memory computing unit, the data stored in the 6T-SRAM memory cell is read onto the local bit line (LBL) and the complementary local bit line (LBLB). When the value stored in the SRAM is 0, the complementary local bit line (LBLB) signal is 1, the fifth NMOS transistor (N5) in the local skip-select computing unit is turned on, and the upper plate of the capacitor is grounded. When the value stored in the SRAM is 1, the complementary local bit line (LBLB) signal is 0, the fifth NMOS transistor (N5) in the local skip-select computing unit is turned off, and the local bit line (LBL) is... When the signal is 1, the first transmission gate (S1) of the local skip selection calculation unit is opened, so that the corresponding VIN voltage is transmitted to the upper plate of the capacitor. The skip selection signal (JUMP) and the complementary skip selection signal (JUMPB) open the transmission gate to connect the lower plates of the capacitors of the corresponding multiple local skip selection calculation units, so that they can participate in the calculation process of capacitive coupling and charge sharing. The analog voltage generated by the multiplication and addition of multiple memory units is quantized by the sparse tracking ADC to produce a 5-bit result. The entire memory circuit realizes the shifting and addition of the quantization results of the four sparse tracking ADCs through the digital adder tree and shifter module to obtain the final result.

9. The calculation method for the charge domain in-memory calculation circuit based on sparse tracking ADC according to claim 8, characterized in that, Each local skip-selection computation unit of the in-memory computing circuit calculates a 1-bit weight multiplied by a 2-bit input signal, and each in-memory unit corresponds to a local input control unit; each column of the in-memory array is connected to a sparse tracking ADC to quantize and obtain a 5-bit binary result; the output signal of the entire in-memory computing circuit is the QOUT of the digital adder tree and shifter module. <n> The binary result.< / n>

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