A BAM neural network circuit based on reverse complementary memristor synaptic array

Abstract

The present application provides a BAM neural network circuit based on an inverse complementary memristive synaptic array, comprising: the BAM neural network circuit being a two-layer neural network circuit, the two-layer neural network circuit including two neural network circuits, the neural network circuit including: an input module circuit, a memristive synaptic circuit, and an activation module circuit; the input module circuit being electrically connected to the memristive synaptic circuit, and the memristive synaptic circuit being electrically connected to the activation module circuit. A reverse complementary memristive synaptic array is constructed using the input module circuit and the memristive synaptic circuit. The reverse complementary memristive synaptic array can implement parallel weight programming, thus achieving parallel weight programming and parallel computing for a bidirectional associative memory neural network circuit.

Description

Technical Field

[0001] The present application relates to the field of neural network circuits, and in particular to a BAM neural network circuit based on an inverse complementary memristor synaptic array. Background Art

[0002] In today's information age, computing power drives the development of modern society in many ways. However, the existing von Neumann architecture, with its independent computing and serial processing, limits computer efficiency. With the continued exploration of the brain's workings, the emergence of brain-inspired neural systems holds the promise of breaking through the von Neumann architecture.

[0003] Associative memory, a high-level cognitive function of biological neural networks, is crucial in the research of brain-inspired computing. Progress in neural network hardware implementation based on traditional electronic components has been slow over the past few decades due to a lack of a solution to integrate storage and computing, and to combine synaptic modulation with memory. The emergence of a new circuit device, the memristor, offers hope for the hardware implementation of neural networks.

[0004] In the research on bidirectional associative memory neural network circuits, conventional BAM neural network circuits cannot implement parallel weight programming while meeting the requirements of large-scale integration, which limits the speed of neural network operations. Neural network circuits must be able to meet the requirements of parallel computing and parallel programming to maximize the advantages of hardware implementation. Summary of the Invention

[0005] The purpose of this application is to solve the technical problem that conventional BAM neural network circuits cannot achieve parallel weight programming, which limits the speed of neural network operations, and to provide a BAM neural network circuit based on an inverse complementary memristor synaptic array.

[0006] The above-mentioned purpose of this application is achieved through the following technical solutions:

[0007] The BAM neural network circuit is composed of two neural network circuits with the same structure, denoted as an x-layer neural network circuit and a y-layer neural network circuit; the BAM neural network circuit has m inputs and m outputs;

[0008] The x-layer neural network circuit and the y-layer neural network circuit respectively include:

[0009] 2m 2 memristors M1, M2, M3, M4, ... M2m 2 ;

[0010] m 2 PMOS tubes Q1, Q2, Q3, Q4, ... Qm 2 ;

[0011] 8m resistors R1, R2, R3, R4, ... R8m;

[0012] 2m operational amplifiers U1, U2, U3, U4, ... U2m;

[0013] 2m diodes D1, D2, D3, D4, ... D2m and 2m multipliers A1, A2, A3, A4, ... A2m;

[0014] The x-layer neural network circuit includes: m PMOS tubes: Qx1, Qx2, Qx3, ..., Qxm, an input module circuit, a memristor synapse circuit, and an activation module circuit;

[0015] The y-layer neural network circuit includes: m PMOS tubes: Qy1, Qy2, Qy3, ... Qym, the input module circuit, the memristor synapse circuit and the activation module circuit;

[0016] The input module circuit includes: a feature vector input control module and an input mode selection module;

[0017] The m feature vector inputs x1, x2, x3, ... xm of the feature vector input control module of the x-layer neural network circuit are connected to the memristor synapse circuit of the x-layer neural network circuit through the S poles of the corresponding PMOS tubes Qx1, Qx2, Qx3, ... Qxm;

[0018] The m feature vector inputs y1, y2, y3, ... ym of the feature vector input control module of the y-layer neural network circuit are connected to the memristor synapse circuit of the y-layer neural network circuit through the S poles of the corresponding PMOS tubes Qy1, Qy2, Qy3, ... Qym;

[0019] The memristive synapse circuit is composed of m memristive neuron circuits; the memristive neuron circuits have the same structure, and the first memristive neuron circuit of the memristive synapse circuit includes: 2i memristors M1, M2, ..., M2i, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, and a first operational amplifier U1;

[0020] The positive ends of the i memristors M1, M3, ..., M2i-1 of the first memristor neuron circuit are connected to the voltage input end, and the reverse ends are connected to the first resistor R1 and the third resistor R3;

[0021] The reverse ends of the i memristors M2, M4, ..., M2i of the first memristor neuron circuit are connected to the voltage input end, and the forward ends are connected to the second resistor R2 and the fourth resistor R4;

[0022] The other end of the first resistor R1 and the other end of the second resistor R2 are grounded;

[0023] The other end of the third resistor R3 and one end of the fifth resistor R5 are connected to the positive input terminal of the first operational amplifier U1, and the other end of the fifth resistor R5 is grounded;

[0024] The other end of the fourth resistor R4 and one end of the sixth resistor R6 are connected to the inverting input terminal of the first operational amplifier U1, and the other end of the sixth resistor R6 is connected to the output terminal of the first operational amplifier U1;

[0025] The input terminals Vin_1, ... Vin_i of the m adjacent memristor neuron circuits corresponding to the i-th row of the single-layer neural network circuit are connected through PMOS transistors, the S pole of the PMOS transistor is connected to the voltage input of the corresponding row of the memristor neuron circuit on the left, and the D pole is connected to the voltage input terminal of the corresponding row of the memristor neuron circuit on the right;

[0026] The activation module circuit is composed of m sub-activation module circuits, each of which has the same sub-activation module circuit structure. The first sub-activation module circuit of the activation module circuit includes: a first diode D1, a second diode D2, a first multiplier A1, a second multiplier A2, a seventh resistor R7, an eighth resistor R8, and a second operational amplifier U2;

[0027] The positive electrode of the first diode D1 is connected to the input end of the first sub-activation module circuit, and the negative electrode is connected to the voltage power supply;

[0028] The cathode of the second diode D2 is connected to the input end of the first sub-activation module circuit, and the anode is connected to the voltage power supply;

[0029] The X terminal and the Y terminal of the first multiplier A1 are connected to the input terminal of the first sub-activation module circuit, and the output terminal is connected to the X terminal of the second multiplier A2;

[0030] The Y terminal of the second multiplier A2 is connected to the input terminal of the first sub-activation module circuit, and the output terminal is connected to one end of the seventh resistor R7;

[0031] The other end of the seventh resistor R7 and one end of the eighth resistor R8 are connected to the positive input terminal of the second operational amplifier U2, and the other end of the eighth resistor R8 is connected to the output terminal of the second operational amplifier U2;

[0032] The inverting input terminal of the second operational amplifier U2 is connected to the input terminal of the first sub-activation module circuit;

[0033] The m output ends of the m memristive neuron circuits of the memristive synaptic circuit of the neural network circuit are respectively connected to the m input ends of the m sub-activation module circuits of the neural network circuit;

[0034] The m output ends of the activation module circuit of the x-layer neural network circuit are connected to the m PMOS tubes of the y-layer neural network circuit; the m output ends of the activation module circuit of the y-layer neural network circuit are connected to the S poles of the m PMOS tubes Qx1, Qx2, Qx3, ... Qxm of the x-layer neural network circuit.

[0035] Optionally, the input mode selection module of the neural network circuit is configured by m 2 -m PMOS tubes control input mode, m 2 -m PMOS tubes with S pole connected to input and D pole connected to output;

[0036] The m 2 -m PMOS tubes with the same control voltage V control ;

[0037] If m 2 When the voltage of the G terminals of the m PMOS tubes is 0V, the input module circuit is in calculation mode;

[0038] If m 2 When the voltage of the G terminals of the m PMOS tubes is 1V, the input module circuit is in programming mode.

[0039] Optionally, the model of the operational amplifier in the BAM neural network circuit is TL082.

[0040] Optionally, the diode model in the BAM neural network circuit is SS26.

[0041] Optionally, the multipliers in the BAM neural network circuit are all four-elephant multipliers.

[0042] Optionally, the memristors in the BAM neural network circuit are all voltage threshold memristors.

[0043] The beneficial effects of the technical solution provided by this application are:

[0044] An inverse complementary memristive synaptic array is constructed through input module circuits, memristive synaptic circuits and activation module circuits. The inverse complementary memristive synaptic array can realize parallel weight programming, realize parallel weight programming and parallel computing of bidirectional associative memory neural network circuits, and further bring into play the advantages of hardware implementation of BAM neural network. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The present application will be further described below with reference to the accompanying drawings and embodiments, in which:

[0046] Figure 1 Schematic diagram of a BAM neural network circuit based on a reverse complementary memristor synaptic array in an embodiment of the present application;

[0047] Figure 2 This is a memristive neuron circuit diagram of a BAM neural network circuit based on a reverse complementary memristive synaptic array in an embodiment of the present application;

[0048] Figure 3 This is a circuit diagram of an activation module of a BAM neural network circuit based on a reverse complementary memristor synaptic array in an embodiment of the present application;

[0049] Figure 4 1 is a diagram showing the change process of the input signal of the BAM neural network circuit based on the reverse complementary memristor synaptic array in an embodiment of the present application;

[0050] Figure 5 1 is a graph showing a change trend of an input signal of a BAM neural network circuit based on a reverse complementary memristor synaptic array in an embodiment of the present application;

[0051] Figure 6 It is an associative memory diagram of a BAM neural network circuit based on a reverse complementary memristor synaptic array in an embodiment of the present application. DETAILED DESCRIPTION

[0052] In order to have a clearer understanding of the technical features, purposes and effects of this application, the specific implementation methods of this application are now described in detail with reference to the accompanying drawings.

[0053] An embodiment of the present application provides a BAM neural network circuit based on a reverse complementary memristor synaptic array.

[0054] Please refer to Figure 1 , Figure 1 This is a schematic diagram of a BAM neural network circuit based on a reverse complementary memristor synaptic array in an embodiment of the present application. Figure 2 , Figure 2 This is a memristive neuron circuit based on a BAM neural network circuit of a reverse complementary memristive synaptic array in the embodiment of the present application. Please refer to Figure 3 , Figure 3This is an activation module circuit of a BAM neural network circuit based on a reverse complementary memristor synaptic array in an embodiment of the present application. It includes:

[0055] The BAM neural network circuit is composed of two neural network circuits with the same structure, denoted as an x-layer neural network circuit and a y-layer neural network circuit; the BAM neural network circuit has m inputs and m outputs;

[0056] The x-layer neural network circuit and the y-layer neural network circuit respectively include:

[0057] 2m 2 memristors M1, M2, M3, M4, ... M2m 2 ;

[0058] m 2 PMOS tubes Q1, Q2, Q3, Q4, ... Qm 2 ;

[0059] 8m resistors R1, R2, R3, R4, ... R8m;

[0060] 2m operational amplifiers U1, U2, U3, U4, ... U2m;

[0061] 2m diodes D1, D2, D3, D4, ... D2m and 2m multipliers A1, A2, A3, A4, ... A2m;

[0062] The x-layer neural network circuit includes: m PMOS tubes: Qx1, Qx2, Qx3, ..., Qxm, an input module circuit, a memristor synapse circuit, and an activation module circuit;

[0063] The y-layer neural network circuit includes: m PMOS tubes: Qy1, Qy2, Qy3, ... Qym, the input module circuit, the memristor synapse circuit and the activation module circuit;

[0064] The input module circuit includes: a feature vector input control module and an input mode selection module;

[0065] The m feature vector inputs x1, x2, x3, ... xm of the feature vector input control module of the x-layer neural network circuit are connected to the memristor synapse circuit of the x-layer neural network circuit through the S poles of the corresponding PMOS tubes Qx1, Qx2, Qx3, ... Qxm;

[0066] The m feature vector inputs y1, y2, y3, ... ym of the feature vector input control module of the y-layer neural network circuit are connected to the memristor synapse circuit of the y-layer neural network circuit through the S poles of the corresponding PMOS tubes Qy1, Qy2, Qy3, ... Qym;

[0067] The memristive synapse circuit is composed of m memristive neuron circuits; the memristive neuron circuits have the same structure, and the first memristive neuron circuit of the memristive synapse circuit includes: 2i memristors M1, M2, ..., M2i, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, and a first operational amplifier U1;

[0068] The positive ends of the i memristors M1, M3, ..., M2i-1 of the first memristor neuron circuit are connected to the voltage input end, and the reverse ends are connected to the first resistor R1 and the third resistor R3;

[0069] The reverse ends of the i memristors M2, M4, ..., M2i of the first memristor neuron circuit are connected to the voltage input end, and the forward ends are connected to the second resistor R2 and the fourth resistor R4;

[0070] The other end of the first resistor R1 and the other end of the second resistor R2 are grounded;

[0071] The other end of the third resistor R3 and one end of the fifth resistor R5 are connected to the positive input terminal of the first operational amplifier U1, and the other end of the fifth resistor R5 is grounded;

[0072] The other end of the fourth resistor R4 and one end of the sixth resistor R6 are connected to the inverting input terminal of the first operational amplifier U1, and the other end of the sixth resistor R6 is connected to the output terminal of the first operational amplifier U1;

[0073] The input terminals Vin_1, ... Vin_i of the m adjacent memristor neuron circuits corresponding to the i-th row of the single-layer neural network circuit are connected through PMOS transistors, the S pole of the PMOS transistor is connected to the voltage input of the corresponding row of the memristor neuron circuit on the left, and the D pole is connected to the voltage input terminal of the corresponding row of the memristor neuron circuit on the right;

[0074] The activation module circuit is composed of m sub-activation module circuits, each of which has the same sub-activation module circuit structure. The first sub-activation module circuit of the activation module circuit includes: a first diode D1, a second diode D2, a first multiplier A1, a second multiplier A2, a seventh resistor R7, an eighth resistor R8, and a second operational amplifier U2;

[0075] The positive electrode of the first diode D1 is connected to the input end of the first sub-activation module circuit, and the negative electrode is connected to the voltage power supply;

[0076] The cathode of the second diode D2 is connected to the input end of the first sub-activation module circuit, and the anode is connected to the voltage power supply;

[0077] The X terminal and the Y terminal of the first multiplier A1 are connected to the input terminal of the first sub-activation module circuit, and the output terminal is connected to the X terminal of the second multiplier A2;

[0078] The Y terminal of the second multiplier A2 is connected to the input terminal of the first sub-activation module circuit, and the output terminal is connected to one end of the seventh resistor R7;

[0079] The other end of the seventh resistor R7 and one end of the eighth resistor R8 are connected to the positive input terminal of the second operational amplifier U2, and the other end of the eighth resistor R8 is connected to the output terminal of the second operational amplifier U2;

[0080] The inverting input terminal of the second operational amplifier U2 is connected to the input terminal of the first sub-activation module circuit;

[0081] The m output ends of the m memristive neuron circuits of the memristive synaptic circuit of the neural network circuit are respectively connected to the m input ends of the m sub-activation module circuits of the neural network circuit;

[0082] The m output ends of the activation module circuit of the x-layer neural network circuit are connected to the m PMOS tubes of the y-layer neural network circuit; the m output ends of the activation module circuit of the y-layer neural network circuit are connected to the S poles of the m PMOS tubes Qx1, Qx2, Qx3, ... Qxm of the x-layer neural network circuit.

[0083] The input mode selection module of the neural network circuit is m 2 -m PMOS tubes control input mode, m 2 -m PMOS tubes with S pole connected to input and D pole connected to output;

[0084] The m 2 -m PMOS tubes with the same control voltage V control ;

[0085] If m 2 When the voltage of the G terminals of the m PMOS tubes is 0V, the input module circuit is in calculation mode;

[0086] If m 2 When the voltage of the G terminals of the m PMOS tubes is 1V, the input module circuit is in programming mode.

[0087] The operational amplifier in the BAM neural network circuit is of model TL082.

[0088] The diode model in the BAM neural network circuit is SS26.

[0089] The multipliers in the BAM neural network circuit are all four-elephant multipliers.

[0090] The memristors in the BAM neural network circuit are all voltage threshold memristors.

[0091] Specifically, the working principle of the BAM neural network circuit of this application is as follows:

[0092] Input module circuit: When the characteristic vector input control voltage Vctrlx of the x-layer neural network circuit is low and the characteristic vector input control voltage Vctrly of the y-layer neural network circuit is high, Qx1, Qx2, Qx3, ... Qxm are in the on state, and Qy1, Qy2, Qy3, ... Qym are in the off state. At this time, it is the x-layer characteristic vector input of the BAM neural network circuit; when the characteristic vector input control voltage Vctrlx of the x-layer neural network circuit is high and the characteristic vector input control voltage Vctrly of the y-layer neural network circuit is low, Qx1, Qx2, Qx3, ... Qxm are in the off state, and Qy1, Qy2, Qy3, ... Qym are in the on state. At this time, it is the y-layer characteristic vector input of the BAM neural network circuit. When the control voltage Vcontrol is low, Q1, Q2, ... Qm(m-1) are in the on state. At this time, refer to Figure 2 , the common end of each row of reverse-connected memristors in each memristor neuron circuit is connected; when the control voltage Vcontrol is high, Q1, Q2, ..., Qm(m-1) are in the disconnected state, and the common end of each row of reverse-connected memristors in each memristor neuron circuit is disconnected, as shown in FIG. Figure 2 As shown, the common terminal of the reverse-connected memristors becomes the programming input for the synaptic weight.

[0093] Memristor synaptic circuit: Each layer of the memristor synaptic circuit is composed of m interconnected memristor neuron circuits. When there is a voltage input, the memristors M1, M2, M3, M4, ... M2i, M2i-1 are connected in reverse, so they show symmetrical and opposite resistance changes. Then, the current sum of each branch is converted into voltage through resistors R1 and R2. Resistors R3, R4, R5, R6 and operational amplifiers form a subtractor, which subtracts the voltages of nodes A and B as the output. Because all memristors are the same and resistors R1 and R2 have the same resistance value, the voltage change trends of nodes A and B are symmetrical and opposite as the voltage input memristor resistance changes, so that each synapse can achieve a weight range of positive and negative zero. The specific principle derivation refers to the following formula:

[0094] V A=(I1+I3+…I 2n-1 )·R1 (1)

[0095] V B =(I2+I4+…I 2n )·R2 (2)

[0096]

[0097]

[0098] Substituting equations (3) and (4) into equations (1) and (2), they can be rewritten as:

[0099]

[0100]

[0101] And because R1=R2、R3=R4、R5=R5, so

[0102]

[0103]

[0104]

[0105]

[0106] Specifically, the memristive neuron circuit realizes the sum of the product of synaptic input and synaptic weight. Therefore, the memristive synaptic circuit of each layer, connected by the input ends of the same row of m memristive neuron circuits, can realize the product of the input vector and the weight matrix. Let the weight matrix of the x layer be W and the weight matrix of the y layer be V. Then the output signal of the memristive synaptic circuit of the x layer is W*x, and the output signal of the memristive synaptic circuit of the y layer is V*y.

[0107] Please refer to Figure 4 , Figure 4 This is a diagram of the input signal change process of the BAM neural network circuit based on the reverse complementary memristor synaptic array in an embodiment of the present application.

[0108] Please refer to Figure 5 , Figure 5 This is a graph showing the input signal variation trend of a BAM neural network circuit based on a reverse complementary memristor synaptic array in an embodiment of the present application.

[0109] Figure 4 Describes the waveform of the input signal, the change process of synaptic weight, and M 2n-1 (t) and M 2n (t) changes. In fact, it can be seen from formula (10) that the synaptic weight Wn The positive and negative relationship between M 2n-1 With M 2n When M 2n-1 <M 2n The weight is positive, when M 2i-1 >M 2i The weight is negative, when M 2n-1 =M 2n By changing the input signal, positive, negative and zero weights can be achieved. Figure 5 Describes the changing trend of synaptic weights when positive and negative voltage inputs are applied.

[0110] Activation module circuit: Two reverse-parallel diodes are connected to upper and lower voltage limits through current-limiting resistors to achieve voltage limiting. The upper and lower voltage limits are 0.5V and -0.5V, respectively, limiting the input of the activation module to -0.5V to 0.5V. The X-end and Y-end of the first multiplier A1 are connected to the signal input end of the circuit, and the input signal is squared to obtain the first output signal; the first output signal and the input signal are multiplied by the second multiplier A2 to obtain the second output signal by the cube of the input signal; the second output signal is connected to the non-inverting input end of the operational amplifier through the seventh resistor R7 and then to the output end of the operational amplifier through the eighth resistor R8. The inverting input end of the operational amplifier is connected to the input signal, thereby obtaining a function of the first power of the input signal minus the cube of the input signal. R8 / R7 is the coefficient of the cubic term, and (R7+R8) / R7 is the coefficient of the linear term. The mathematical model of the activation function f(x) is shown in formula (12). x is the input variable of the activation function, corresponding to the input voltage of the activation module circuit. It is an important transfer parameter. When δ is between 0 and 0.5, the network presents a monotonic steady state.

[0111]

[0112]

[0113] In this application, operational amplifiers U1, U2, U3, U4, ... U2m are all TL082 operational amplifiers; A1, A2, A3, A4, ... A2m are all AD633 four-quadrant multipliers; memristors M1, M2, M3, M4, ... M2m are all AD633 four-quadrant multipliers. 2A voltage threshold memristor is selected, with the starting resistance of M1, M3, ..., M2i-1 being 2 kΩ, and the starting resistance of M2, M4, ..., M2i being 4 kΩ; the resistance of resistors R1, R2, R9, R10, ..., R8m-7, R8m-6 being 50 Ω; the resistance of resistors R3, R4, R11, R12, ..., R8m-5, R8m-4 being 1 kΩ; the resistance of resistors R5, R6, R13, R14, ..., R8m-3, R8m-2 being 100 kΩ; and the model of diodes D1, D2, D3, D4, ..., D2m being SS26.

[0114] Specifically, by Figure 4 、 Figure 5 It can be seen that the BAM neural network circuit based on the reverse complementary memristor synaptic array of this application has the characteristics of parallel programming and can realize the synchronous programming of synaptic weights. This application built a two-layer 15×15 neural network circuit in Pspice for MATLAB simulation experiments, took the voltage value corresponding to the image vector as the input of the neural network circuit, and converted the neuron output voltage vector of the two layers of the neural network into an image in MATLAB. Please refer to Figure 6 , Figure 6 It is an associative memory diagram of a BAM neural network circuit based on a reverse complementary memristor synaptic array in an embodiment of the present application.

[0115] The above are only preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A BAM neural network circuit based on a reverse complementary memristor synaptic array, characterized in that: The BAM neural network circuit is composed of two neural network circuits with the same structure, denoted as an x-layer neural network circuit and a y-layer neural network circuit; the BAM neural network circuit has m inputs and m outputs; The x-layer neural network circuit and the y-layer neural network circuit respectively include: 2m 2 memristors M1, M2, M3, M4, ... M2m 2 ; m 2 PMOS tubes Q1, Q2, Q3, Q4, ... Qm 2 ; 8m resistors R1, R2, R3, R4, ... R8m; 2m operational amplifiers U1, U2, U3, U4, ... U2m; 2m diodes D1, D2, D3, D4, ... D2m and 2m multipliers A1, A2, A3, A4, ... A2m; The x-layer neural network circuit includes: m PMOS tubes: Qx1, Qx2, Qx3, ..., Qxm, an input module circuit, a memristor synapse circuit, and an activation module circuit; The y-layer neural network circuit includes: m PMOS tubes: Qy1, Qy2, Qy3, ... Qym, the input module circuit, the memristor synapse circuit and the activation module circuit; The input module circuit includes: a feature vector input control module and an input mode selection module; The m feature vector inputs x1, x2, x3, ... xm of the feature vector input control module of the x-layer neural network circuit are connected to the memristor synapse circuit of the x-layer neural network circuit through the S poles of the corresponding PMOS tubes Qx1, Qx2, Qx3, ... Qxm; The m feature vector inputs y1, y2, y3, ... ym of the feature vector input control module of the y-layer neural network circuit are connected to the memristor synapse circuit of the y-layer neural network circuit through the S poles of the corresponding PMOS tubes Qy1, Qy2, Qy3, ... Qym; The memristive synapse circuit is composed of m memristive neuron circuits; the memristive neuron circuits have the same structure, and the first memristive neuron circuit of the memristive synapse circuit includes: 2i memristors M1, M2, ..., M2i, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, and a first operational amplifier U1; The positive ends of the i memristors M1, M3, ..., M2i-1 of the first memristor neuron circuit are connected to the voltage input end, and the reverse ends are connected to the first resistor R1 and the third resistor R3; The reverse ends of the i memristors M2, M4, ..., M2i of the first memristor neuron circuit are connected to the voltage input end, and the forward ends are connected to the second resistor R2 and the fourth resistor R4; The other end of the first resistor R1 and the other end of the second resistor R2 are grounded; The other end of the third resistor R3 and one end of the fifth resistor R5 are connected to the positive input terminal of the first operational amplifier U1, and the other end of the fifth resistor R5 is grounded; The other end of the fourth resistor R4 and one end of the sixth resistor R6 are connected to the inverting input terminal of the first operational amplifier U1, and the other end of the sixth resistor R6 is connected to the output terminal of the first operational amplifier U1; The input terminals Vin_1, ... Vin_i of the m adjacent memristor neuron circuits corresponding to row i of the single-layer neural network circuit are connected through PMOS transistors. The S-pole of the PMOS transistor is connected to the voltage input terminal of the corresponding row of the memristor neuron circuit on the left, and the D-pole is connected to the voltage input terminal of the corresponding row of the memristor neuron circuit on the right. The activation module circuit is composed of m sub-activation module circuits, each of which has the same structure. The first sub-activation module circuit of the activation module circuit includes: a first diode D1, a second diode D2, a first multiplier A1, a second multiplier A2, a seventh resistor R7, an eighth resistor R8, and a second operational amplifier U2; The anode of the first diode D1 is connected to the input end of the first sub-activation module circuit, and the cathode is connected to the voltage power supply; The cathode of the second diode D2 is connected to the input end of the first sub-activation module circuit, and the anode is connected to the voltage power supply; The X terminal and the Y terminal of the first multiplier A1 are connected to the input terminal of the first sub-activation module circuit, and the output terminal is connected to the X terminal of the second multiplier A2; The Y terminal of the second multiplier A2 is connected to the input terminal of the first sub-activation module circuit, and the output terminal is connected to one end of the seventh resistor R7; The other end of the seventh resistor R7 and one end of the eighth resistor R8 are connected to the positive input terminal of the second operational amplifier U2, and the other end of the eighth resistor R8 is connected to the output terminal of the second operational amplifier U2; The inverting input terminal of the second operational amplifier U2 is connected to the input terminal of the first sub-activation module circuit; The m output ends of the m memristive neuron circuits of the memristive synaptic circuit of the neural network circuit are respectively connected to the m input ends of the m sub-activation module circuits of the neural network circuit; The m output ends of the activation module circuit of the x-layer neural network circuit are connected to the m PMOS tubes of the y-layer neural network circuit; the m output ends of the activation module circuit of the y-layer neural network circuit are connected to the S poles of the m PMOS tubes Qx1, Qx2, Qx3, ... Qxm of the x-layer neural network circuit.

2. A BAM neural network circuit based on a reverse complementary memristor synaptic array as claimed in claim 1, characterized in that: The input mode selection module of the neural network circuit is m 2 -m PMOS tubes control input mode, m 2 -m PMOS tubes with S pole connected to input and D pole connected to output; The m 2 -m PMOS tubes with the same control voltage V control ; If m 2 When the voltage of the G terminals of the m PMOS tubes is 0V, the input module circuit is in calculation mode; If m 2 When the voltage of the G terminals of the m PMOS tubes is 1V, the input module circuit is in programming mode.

3. A BAM neural network circuit based on a reverse complementary memristor synaptic array as claimed in claim 1, characterized in that: The operational amplifier in the BAM neural network circuit is of model TL082.

4. A BAM neural network circuit based on a reverse complementary memristor synaptic array as claimed in claim 1, characterized in that: The diode model in the BAM neural network circuit is SS26.

5. A BAM neural network circuit based on a reverse complementary memristor synaptic array as claimed in claim 1, characterized in that: The multipliers in the BAM neural network circuit are all four-elephant multipliers.

6. A BAM neural network circuit based on an inverse complementary memristor synaptic array as claimed in claim 1, characterized in that: The memristors in the BAM neural network circuit are all voltage threshold memristors.

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