Drive system, transceiver and transceiving communication system

Abstract

The application discloses a driving system, a transceiver and a transceiving communication system. The driving system comprises a first bias current circuit, a first driving circuit, a second driving circuit and a second bias current circuit which are connected. According to the driving system, the transceiver and the transceiving communication system, the current multiplexing principle is adopted, so that two driving circuits share one bias current, and the power consumption of the driving circuit is reduced. When the transceiver sends data to the upper and lower transceivers, the power consumption of the driving circuit can be halved compared with the traditional technical scheme, the overall power consumption of the transceiver is greatly reduced, the current flowing through the cable is reduced, and more transceivers can be cascaded in the whole link system.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of signal transmission, and in particular to a driving system, a transceiver and a transceiving communication system. BACKGROUND

[0002] In a transceiver, a master controls a plurality of slaves, in order to reduce the number of ports of the master and the number of cables for signal transmission, a connection mode in the form of daisy chain is usually adopted to build the system. As shown in FIG. 1, each device in the system is connected in series, each device can only transmit data to the adjacent device, so the data and control signals sent by the master to the slaves are transmitted through the serial link. Meanwhile, the data signals uploaded by the slaves to the master are also transmitted through the serial link. This data transmission mode has obvious advantages when there are many slaves, not only can the number of ports and cables be greatly reduced, but also the slaves can be powered through the cables, so the slaves no longer need local power supply, thereby reducing the number of power supply devices in the system. Figure 1 When the power is transmitted through the cable, due to the large number of slaves, the current to be transmitted on the cable is usually large, the resistance on the cable will cause the power voltage of the slaves to drop gradually, thereby limiting the number of cascades, and the heat on the cable will also be serious, which will adversely affect the reliability of the device, so reducing the power consumption of each slave is helpful to increase the number of cascades.

[0003] In the daisy chain system, each slave needs to communicate with its superior and inferior devices, so there are two transceiver modules TRX, if each transceiver module TRX needs to consume current I, when the two transceiver modules TRX work at the same time, the consumed current is 2I. In the slave, the power consumption of the transceiver module TRX accounts for a large proportion, so if the power consumption of the transceiver module TRX can be reduced, the power consumption of the entire transceiver can be greatly reduced.

[0004]

[0005] Figure 2 is Figure 1 ​The structure block diagram of a single device, wherein the on chip regulator is a voltage stabilizing circuit, which is used to convert the power supply voltage outside the chip into the power supply inside the chip, so as to avoid the influence of the excessive ripple of the power supply outside the chip on the internal circuit of the chip. The data circuit is a data processing unit, which is used to generate the data to be sent and process the received data. The driver is used to send the data to the front-stage device and the rear-stage device, and the receiver is used to receive the data sent by the front-stage device and the rear-stage device. Generally, the current consumed by the driver is much greater than that consumed by the receiver, so as long as the current consumed by the driver is reduced, the power consumption of the transceiver circuit in the device can be greatly reduced.

[0006] The information disclosed in this section is only intended to increase the understanding of the overall background of the present application and should not be considered as acknowledging or implying in any form that the information constitutes the prior art known to those skilled in the art. SUMMARY

[0007] The purpose of the present application is to provide a driving system, a transceiver and a transceiving communication system, which can greatly reduce the current consumed by the driver, so as to reduce the power consumption of the whole system.

[0008] To achieve the above-mentioned purpose, the embodiment of the present application provides a driving system, comprising: a first bias current circuit, a first driving circuit, a second driving circuit and a second bias current circuit.

[0009] The first bias current circuit is used to provide a first bias current.

[0010] The first driving circuit has a first current input end for receiving the first bias current, a first current output end for outputting the first bias current and a first output end and a second output end for outputting a first differential signal.

[0011] The second driving circuit has a second current input end connected with the first current output end of the first driving circuit to form a connection node for receiving the first bias current, a second current output end for outputting the first bias current and a third output end and a fourth output end for outputting a second differential signal.

[0012] The second bias current circuit is used to provide a second bias current same as the first bias current, and the second current output end of the second driving circuit is connected with the second bias current circuit.

[0013] In one or more embodiments of the present application, the driving system further comprises an adjusting unit connected with the connection node, and the adjusting unit is used to generate an adjusting current to adjust the bias current of the first driving circuit and / or the second driving circuit.

[0014] In one or more embodiments of the present application, the regulating unit comprises a first shunt regulator and a second shunt regulator, the first shunt regulator being connected to the connection node to generate a first regulating current, and the second shunt regulator being connected to the connection node to generate a second regulating current.

[0015] In one or more embodiments of the present application, the first driving circuit comprises a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a first resistor, a second resistor, and a first common-mode signal generating circuit.

[0016] The source of the first switch tube is connected to the source of the second switch tube to form a first current input end, the drain of the first switch tube is connected to the drain of the third switch tube, the drain of the second switch tube is connected to the drain of the fourth switch tube, the source of the third switch tube is connected to the source of the fourth switch tube to form a first current output end, the first end of the first resistor is connected to the drain of the second switch tube to form a first output end, the second end of the first resistor is connected to the first end of the second resistor and the first common-mode signal generating circuit, and the second end of the second resistor is connected to the drain of the first switch tube to form a second output end.

[0017] In one or more embodiments of the present application, the first common-mode signal generating circuit comprises a first transconductance amplifier, the first transconductance amplifier having a first input end, a second input end, and a fifth output end, the first input end and the fifth output end of the first transconductance amplifier being connected, the second input end of the first transconductance amplifier being used to receive a reference voltage, and the fifth output end of the first transconductance amplifier being used to output a first common-mode signal.

[0018] In one or more embodiments of the present application, the second driving circuit comprises a fifth switch tube, a sixth switch tube, a seventh switch tube, an eighth switch tube, a third resistor, a fourth resistor, and a second common-mode signal generating circuit.

[0019] The source of the fifth switch tube is connected to the source of the sixth switch tube to form a second current input end, the drain of the fifth switch tube is connected to the drain of the seventh switch tube, the drain of the sixth switch tube is connected to the drain of the eighth switch tube, the source of the seventh switch tube is connected to the source of the eighth switch tube to form a second current output end, the first end of the third resistor is connected to the drain of the sixth switch tube to form a third output end, the second end of the third resistor is connected to the first end of the fourth resistor and the second common-mode signal generating circuit, and the second end of the fourth resistor is connected to the drain of the fifth switch tube to form a fourth output end.

[0020] In one or more embodiments of the present application, the second common mode signal generation circuit includes a second trans-impedance amplifier having a third input terminal, a fourth input terminal and a sixth output terminal, the third input terminal and the sixth output terminal of the second trans-impedance amplifier are connected, the fourth input terminal of the second trans-impedance amplifier is configured to receive a reference voltage, and the sixth output terminal of the second trans-impedance amplifier is configured to output the second common mode signal.

[0021] In one or more embodiments of the present application, the first bias current circuit includes a first bias current source transistor, a source of the first bias current source transistor is connected to a power supply voltage, and a drain of the first bias current source transistor is connected to the first current input terminal of the first drive circuit.

[0022] In one or more embodiments of the present application, the second bias current circuit includes a second bias current source transistor, a source of the second bias current source transistor is connected to a ground voltage, and a drain of the second bias current source transistor is connected to the second current output terminal of the second drive circuit.

[0023] In one or more embodiments of the present application, the drive system further includes a bias voltage control module configured to provide a bias voltage to the first bias current circuit, the second bias current circuit and / or the adjustment unit.

[0024] The present application discloses a drive system, comprising:

[0025] a bias current circuit configured to provide a bias current;

[0026] a first drive circuit having a first current input terminal configured to receive the bias current, a first current output terminal configured to output the bias current, and a first output terminal and a second output terminal configured to output a first differential signal; and

[0027] a second drive circuit having a second current input terminal connected to the first current output terminal of the first drive circuit to form a connection node to receive the bias current, a second current output terminal configured to output the bias current, and a third output terminal and a fourth output terminal configured to output a second differential signal.

[0028] In one or more embodiments of the present application, the drive system further includes an adjustment unit connected to the first current input terminal of the first drive circuit, the connection node, and the second current output terminal of the second drive circuit, the adjustment unit configured to generate an adjustment current to adjust the bias current of the first drive circuit and / or the second drive circuit.

[0029] In one or more embodiments of the present application, the adjusting unit comprises a first parallel regulator and a second parallel regulator, the first parallel regulator is connected with the connecting node and the first current input end to generate a first adjusting current, and the second parallel regulator is connected with the connecting node and the second current output end to generate a second adjusting current.

[0030] In one or more embodiments of the present application, the driving system further comprises a bias voltage control module, which is used to provide a bias voltage for the bias current circuit and / or the adjusting unit.

[0031] In one or more embodiments of the present application, the bias current circuit comprises a bias current source tube, the source of the bias current source tube is connected with a ground voltage, and the drain of the bias current source tube is connected with the second current output end of the second driving circuit.

[0032] In one or more embodiments of the present application, the first driving circuit comprises a fifth resistor, a sixth resistor, a ninth switch tube and a tenth switch tube; the first end of the fifth resistor is connected with the first end of the sixth resistor to form a first current input end, the second end of the fifth resistor is connected with the drain of the ninth switch tube to form a first output end, the second end of the sixth resistor is connected with the drain of the tenth switch tube to form a second output end, and the source of the ninth switch tube is connected with the source of the tenth switch tube to form a first current output end.

[0033] In one or more embodiments of the present application, the second driving circuit comprises a seventh resistor, an eighth resistor, an eleventh switch tube and a twelfth switch tube; the first end of the seventh resistor is connected with the first end of the eighth resistor to form a second current input end, the second end of the seventh resistor is connected with the drain of the eleventh switch tube to form a third output end, the second end of the eighth resistor is connected with the drain of the twelfth switch tube to form a fourth output end, and the source of the eleventh switch tube is connected with the source of the twelfth switch tube to form a second current output end.

[0034] The present application further discloses a transceiver, comprising a data processing unit, a receiver and the driving system, the receiver is used to receive data and send the data to the data processing unit, the data processing unit is used to process the data sent by the receiver and generate data to be sent to the driving system, and the driving system is used to send the data sent by the data processing unit.

[0035] The present application further discloses a transceiver communication system, comprising a plurality of transceivers connected in a daisy chain form.

[0036] Compared with the prior art, the driving system, the transceiver and the transceiving communication system according to the embodiments of the present application, by adopting the principle of current multiplexing, make two driving circuits in the transceiver share one bias current, so as to realize reducing the power consumption of the driving circuit in the transceiver; when the transceiver simultaneously sends data to the upper-level and lower-level transceivers, the power consumption of the driving circuit can be halved compared with the scheme in the prior art, greatly reducing the overall power consumption of the transceiver, so as to reduce the current flowing through the cable, and make more transceivers be cascaded in the whole link system. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 is a system diagram of the transceiving communication system of the prior art.

[0038] Figure 2 is a circuit diagram of the transceiver of the prior art.

[0039] Figure 3 is a circuit principle diagram of the driving circuit in the driving system according to the first embodiment of the present application.

[0040] Figure 4 is a circuit principle diagram of the first common-mode signal generating circuit according to the present application.

[0041] Figure 5 is a circuit principle diagram of the second common-mode signal generating circuit according to the present application.

[0042] Figure 6 is a circuit principle diagram of the driving system according to the first embodiment of the present application when only the second driving circuit works.

[0043] Figure 7 is a circuit diagram of the transceiver according to the present application.

[0044] Figure 8 is a circuit principle diagram of the driving system according to the second embodiment of the present application.

[0045] Figure 9 is a circuit principle diagram of the driving system according to the second embodiment of the present application when only the second driving circuit works. DETAILED DESCRIPTION

[0046] The specific embodiments of the present application are described in detail below with reference to the accompanying drawings, but it should be understood that the protection scope of the present application is not limited by the specific embodiments.

[0047] Unless otherwise clearly indicated, in the entire specification and claims, the term "comprise" or its variants such as "comprises" or "comprising" and the like will be understood to encompass the stated elements or components, but not to exclude the presence of other elements or components.

[0048] The terms "coupled," "connected," or "linked" in this specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrical conduction medium, which may have parasitic inductance or capacitance. Indirect connections may also include connections made through other active or passive devices to achieve the same or similar functional purpose, such as connections through switches, follower circuits, or other circuits or components. Furthermore, in this invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship, quantity, or order between these technical features.

[0049] Example 1

[0050] like Figure 3 As shown, a drive system includes: a first bias current circuit 10, a first drive circuit 20, a second drive circuit 30, a second bias current circuit 40, an adjustment unit 50, and a bias voltage control module 60.

[0051] The first bias current circuit 10 is connected to the power supply voltage Vdd and is used to provide the first bias current.

[0052] The first driving circuit 20 has a first current input terminal, a first current output terminal, a first output terminal DP1, and a second output terminal DN1. The first current input terminal of the first driving circuit 20 is connected to the first bias current circuit 10 to receive a first bias current, and the first output terminal DP1 and the second output terminal DN1 of the first driving circuit 20 are used to output a first differential signal based on the first bias current.

[0053] The second driving circuit 30 has a second current input terminal, a second current output terminal, a third output terminal DP2, and a fourth output terminal DN2. The second current input terminal of the second driving circuit 30 is connected to the first current output terminal of the first driving circuit 20 to receive the first bias current Idrv and form a connection node. The second current output terminal of the second driving circuit 30 is connected to the second bias current circuit 40. The third output terminal DP2 and the fourth output terminal DN2 of the second driving circuit 30 are used to output a second differential signal based on the second bias current.

[0054] The second bias current circuit 40 is also connected to the ground voltage. The second bias current circuit 40 is used to provide a second bias current equal to the first bias current.

[0055] The adjustment unit 50 is connected to the connection node. The adjustment unit 50 is used to generate an adjustment current to adjust the bias current of the first drive circuit 20 and / or the second drive circuit 30, so that the bias current flowing through the second drive circuit 30 is equal to the bias current flowing through the first drive circuit 20.

[0056] The first bias current circuit 10, the second bias current circuit 40, and the adjustment unit 50 are all connected to the bias voltage control module 60. The bias voltage control module 60 provides bias voltages to the first bias current circuit 10, the second bias current circuit 40, and the adjustment unit 50 respectively, so that the first bias current circuit 10 and the second bias current circuit 40 generate equal bias currents, and the adjustment unit 50 generates an adjustment current.

[0057] like Figure 3 As shown, the first bias current circuit 10 includes a first bias current source transistor Mbp. The source of the first bias current source transistor Mbp is connected to the power supply voltage Vdd. The drain of the first bias current source transistor Mbp is connected to the first current input terminal of the first drive circuit 20. The gate of the first bias current source transistor Mbp is connected to the bias voltage control module 60 to receive the bias voltage generated by the bias voltage control module 60.

[0058] The first driving circuit 20 includes a first switching transistor M1, a second switching transistor M2, a third switching transistor M3, a fourth switching transistor M4, a first resistor R1, a second resistor R2, and a first common-mode signal generation circuit Vcm1.

[0059] The source of the first switch M1 is connected to the source of the second switch M2 to form a first current input terminal connected to the drain of the first bias current source Mbp. The drain of the first switch M1 is connected to the drain of the third switch M3, and the drain of the second switch M2 is connected to the drain of the fourth switch M4. The source of the third switch M3 is connected to the source of the fourth switch M4 to form a first current output terminal. The first end of the first resistor R1 is connected to the drain of the second switch M2 to form a first output terminal DP1. The second end of the first resistor R1 is connected to the first end of the second resistor R2 and the first common-mode signal generation circuit Vcm1. The second end of the second resistor R2 is connected to the drain of the first switch M1 to form a second output terminal DN1. The first output terminal DP1 and the second output terminal DN1 constitute a differential port. In this embodiment, the first switch M1 and the fourth switch M4 are turned on simultaneously, or the second switch M2 and the third switch M3 are turned on simultaneously. The first differential signal is output from the first output terminal DP1 and the second output terminal DN1 by alternating their on / off states.

[0060] like Figure 4 and Figure 3As shown, the first common-mode signal generation circuit Vcm1 includes a first transconductance amplifier OTA1. The first transconductance amplifier OTA1 has a first input terminal, a second input terminal, and a fifth output terminal Output1. In one embodiment, the first input terminal is a negative input terminal (-), and the second input terminal is a positive input terminal (+). The first input terminal and the fifth output terminal of the first transconductance amplifier OTA1 are connected. The second input terminal of the first transconductance amplifier OTA1 is used to receive a reference voltage Vcm, which is typically 1.2V. The fifth output terminal Output1 of the first transconductance amplifier OTA1 is connected to the second terminal of the first resistor R1 and the first terminal of the second resistor R2 to output a variable current to provide common-mode feedback, thereby generating a first common-mode signal equal to the reference voltage Vcm.

[0061] like Figure 3 As shown, the second driving circuit 30 includes a fifth switch M5, a sixth switch M6, a seventh switch M7, an eighth switch M8, a third resistor R3, a fourth resistor R4, and a second common-mode signal generation circuit Vcm2.

[0062] The source of the fifth switch M5 is connected to the source of the sixth switch M6 to form a second current input terminal connected to the first current output terminal. The first current output terminal and the second current input terminal are connected to form a connection node. The drain of the fifth switch M5 is connected to the drain of the seventh switch M7, the drain of the sixth switch M6 is connected to the drain of the eighth switch M8, and the source of the seventh switch M7 is connected to the source of the eighth switch M8 to form a second current output terminal. The first end of the third resistor R3 is connected to the drain of the sixth switch M6 to form the third output terminal DP2. The second end of the third resistor R3 is connected to the second common-mode signal generation circuit Vcm2 and the first end of the fourth resistor R4. The second end of the fourth resistor R4 is connected to the drain of the fifth switch M5 to form the fourth output terminal DN2. The third output terminal DP2 and the fourth output terminal DN2 are used to output the second differential signal. In this embodiment, by simultaneously turning on the fifth switch M5 and the eighth switch M8, or simultaneously turning on the sixth switch M6 and the seventh switch M7, the second differential signal is output at the third output terminal DP2 and the fourth output terminal DN2 in an alternating manner.

[0063] like Figure 5 and Figure 3As shown, the second common-mode signal generation circuit Vcm2 includes a second transconductance amplifier OTA2, which has a third input terminal, a fourth input terminal, and a sixth output terminal Output2. In one embodiment, the third input terminal is a negative input terminal (-), and the fourth input terminal is a positive input terminal (+). The third input terminal and the sixth output terminal Output2 of the second transconductance amplifier OTA2 are connected. The fourth input terminal of the second transconductance amplifier OTA2 is used to receive a reference voltage Vcm, which is typically 1.2V. The sixth output terminal Output2 of the second transconductance amplifier OTA2 is connected to the second terminal of the third resistor R3 and the first terminal of the fourth resistor R4 to output a variable current to provide common-mode feedback, thereby generating a second common-mode signal equal to the reference voltage Vcm.

[0064] like Figure 3 As shown, the second bias current circuit 40 includes a second bias current source transistor Mbn. The source of the second bias current source transistor Mbn is connected to ground voltage, the drain of the second bias current source transistor Mbn is connected to the second current output terminal of the second drive circuit 30, and the gate of the second bias current source transistor Mbn is connected to the bias voltage control module 60 to receive the bias voltage generated by the bias voltage control module 60.

[0065] In this embodiment, the bias voltage generated by the bias voltage control module 60 causes the first bias current source transistor Mbp and the second bias current source transistor Mbn to generate the same bias current.

[0066] like Figure 3As shown, the regulating unit 50 includes a first parallel regulator 1 and a second parallel regulator 2. The first parallel regulator 1 and the second parallel regulator 2 can adjust the output regulating current according to the changes in the load driven by the first drive circuit 20 and the second drive circuit 30. The first terminal of the first parallel regulator 1 is connected to the power supply voltage Vdd, and the second terminal of the first parallel regulator 1 is connected to a connection node to generate a first regulating current. The first terminal of the second parallel regulator 2 is connected to a connection node to generate a second regulating current, and the second terminal of the second parallel regulator 2 is connected to ground. The first parallel regulator 1 and the second parallel regulator 2 are both connected to the bias voltage control module 60. The bias voltage provided by the bias voltage control module 60 is used to detect the current consumed by the load, thereby adjusting the current output by the first parallel regulator 1 and the second parallel regulator 2. The bias voltage control module 60 is usually composed of two parts: a current detection circuit and a current output circuit.

[0067] like Figure 3 As shown, the first drive circuit 20 and the second drive circuit 30 operate simultaneously. If the first parallel regulator Shunt regulator 1 and the second parallel regulator Shunt regulator 2 are also turned on, then, under the premise that the second bias current flowing through the second drive circuit 30 is equal to the first bias current flowing through the first drive circuit 20, the first regulating current generated by the first parallel regulator Shunt regulator 1 and the second regulating current generated by the second parallel regulator Shunt regulator 2 also need to be equal. At this time, both the first regulating current and the second regulating current are Ishunt, where Ishunt is the minimum current required to ensure the normal operation of the first parallel regulator Shunt regulator 1 and the second parallel regulator Shunt regulator 2. Both the first bias current and the second bias current are Idrv, where Idrv is the current required by the drive circuit to generate the corresponding output signal. The first regulating current and the first bias current flow into the connection node, and the second regulating current and the second bias current flow out of the connection node. Therefore, the bias voltage generated by the bias voltage control module 60 can cause the first parallel regulator Shunt regulator 1 and the second parallel regulator Shunt regulator 2 to generate regulating currents of the same magnitude but opposite flow directions.

[0068] The present invention adopts the principle of current reuse, which reuses the bias current flowing through the first driving circuit 20, so that the first driving circuit 20 and the second driving circuit 30 can share a bias current, thereby halving the power consumption when the two driving circuits work at the same time.

[0069] When the first drive circuit 20 and the second drive circuit 30 operate simultaneously, the bias voltage control module 60 controls the first bias current source transistor Mbp to generate a first bias current, and the bias voltage control module 60 controls the second bias current source transistor Mbn to generate a second bias current. Both the first bias current and the second bias current are Idrv. The first parallel regulator Shuntregulator1 generates a first regulating current, and the second parallel regulator Shuntregulator2 generates a second regulating current (the first parallel regulator Shuntregulator1 and the second parallel regulator Shuntregulator2 may also not operate). Both the first regulating current and the second regulating current are Ishunt. At this time, the first / second regulating current is much smaller than the first / second bias current. The first common-mode signal generation circuit Vcm1 is used to output the first common-mode signal that generates the first differential signal, and the second common-mode signal generation circuit Vcm2 is used to output the second common-mode signal that generates the second differential signal. The power consumption of the two common-mode signal generation circuits is also much smaller than the power consumption of the two drive circuits. In this way, the two driving circuits can not only transmit data simultaneously, but also consume only one bias current to drive the corresponding two load resistors. This is equivalent to halving the bias current consumption under the same signal swing, which means that the overall system power consumption is halved.

[0070] like Figure 6As shown, when only the second drive circuit 30 needs to operate normally, the switching transistors M1 to M4 in the first drive circuit 20 are all turned off, the current generated by the first bias current source Mbp is 0, and the first output terminal DP1 and the second output terminal DN1 remain in a high-impedance state. The second drive circuit 30 performs data transmission normally. At this time, the second bias current source Mbn generates a second bias current, Idrv, and the second parallel regulator Shunt regulator 2 generates a second regulating current, Ishunt. The first parallel regulator Shunt regulator 1 can generate a first regulating current according to the load adjustment. When the second bias current is Idrv, the difference between the first regulating current generated by the first parallel regulator Shunt regulator 1 and the second regulating current generated by the second parallel regulator Shunt regulator 2 must be equal to the second bias current, thereby ensuring that the bias current flowing into the second drive circuit 30 is Idrv. The second common-mode signal generation circuit Vcm2 then outputs a second common-mode signal that generates a second differential signal. Conversely, when the first drive circuit 20 is transmitting data normally and the second drive circuit 30 is not working, the first regulating current generated by the first parallel regulator 1 and the second regulating current generated by the second parallel regulator 2 can be matched to ensure the normal operation of the first drive circuit 20.

[0071] Therefore, whether the two drive circuits work simultaneously or one of the drive circuits works alone, the power consumption of the drive circuit is always the product of Idrv and the power supply voltage Vdd. This is equivalent to halving the power consumption when the two drive circuits work simultaneously, thereby reducing the power consumption of the entire system and allowing more transceivers to be cascaded in the entire link.

[0072] The present invention also discloses a transceiver, such as Figure 7 As shown, the system includes a data processing unit, receivers, and the aforementioned drive system. In one embodiment, two receivers are provided, one for receiving data sent from the upstream transceiver and the other for receiving data sent from the downstream transceiver, and then transmitting the data to the data processing unit. The data processing unit processes the data sent from each receiver and generates the data to be transmitted to the drive system. The drive system transmits the data sent from the data processing unit to the receivers of the upstream transceiver and / or the receivers of the downstream transceiver.

[0073] The transceiver also includes a voltage regulator circuit, which converts the external power supply into the internal power supply voltage to provide power to the data processing unit, receiver, and the aforementioned drive system, preventing excessive ripple from the external power supply from affecting the transceiver's internal circuitry. The voltage regulator circuit can also be placed externally to achieve the same function.

[0074] The present invention also discloses a transceiver communication system, comprising multiple transceivers connected in a daisy chain as described above.

[0075] Example 2

[0076] like Figure 8 As shown, in this embodiment, a bias current circuit 40 is provided.

[0077] like Figure 8 As shown, the first driving circuit 20 includes a fifth resistor R5, a sixth resistor R6, a ninth switch M9, and a tenth switch M10. The first end of the fifth resistor R5 is connected to the first end of the sixth resistor R6 to form a first current input terminal. The second end of the fifth resistor R5 is connected to the drain of the ninth switch M9 to form a first output terminal DP3. The second end of the sixth resistor R6 is connected to the drain of the tenth switch M10 to form a second output terminal DN3. The source of the ninth switch M9 is connected to the source of the tenth switch M10 to form a first current output terminal. By alternately turning on the ninth switch M9 and the tenth switch M10, a first differential signal is output at the first output terminal DP3 and the second output terminal DN3.

[0078] The second driving circuit 30 includes a seventh resistor R7, an eighth resistor R8, an eleventh switch M11, and a twelfth switch M12. The first end of the seventh resistor R7 is connected to the first end of the eighth resistor R8 to form a second current input terminal, which is connected to the first current output terminal to form a connection node. The second end of the seventh resistor R7 is connected to the drain of the eleventh switch M11 to form a third output terminal DP4. The second end of the eighth resistor R8 is connected to the drain of the twelfth switch M12 to form a fourth output terminal DN4. The sources of the eleventh switch M11 and the twelfth switch M12 are connected to form a second current output terminal. By alternately turning on the eleventh switch M11 and the twelfth switch M12, a second differential signal is output at the third output terminal DP4 and the fourth output terminal DN4.

[0079] The drive system also includes an adjustment unit 50, which is connected to the first current input terminal and connection node of the first drive circuit 20 and the second current output terminal of the drive circuit 30. The adjustment unit 50 is used to generate an adjustment current to adjust the bias current of the first drive circuit 20 and / or the second drive circuit 30.

[0080] Specifically, the regulating unit 50 includes a first parallel regulator 3 and a second parallel regulator 4. The first parallel regulator 3 is connected to the connection node and the first current input terminal to generate a first regulating current, and the second parallel regulator 4 is connected to the connection node and the second current output terminal to generate a second regulating current.

[0081] The drive system also includes a bias voltage control module 60, which provides a bias voltage to the bias current circuit 40 and the regulation unit 50. The first parallel regulator 3 and the second parallel regulator 4 generate corresponding regulating currents based on the bias voltage provided by the bias voltage control module 60.

[0082] The bias current circuit 40 includes a bias current source transistor Mbn. The drain of the bias current source transistor Mbn is connected to the second current output terminal of the second driving circuit 30. The source of the bias current source transistor Mbn is connected to the ground voltage. The gate of the bias current source transistor Mbn is connected to the bias voltage control module 60. The bias current source transistor Mbn generates a bias current based on the bias voltage generated by the bias voltage control module 60.

[0083] like Figure 9 As shown, when both the first drive circuit 20 and the second drive circuit 30 are working, and the bias currents flowing through the first drive circuit 20 and the second drive circuit 30 are equal, the regulating currents generated by the first parallel regulator Shunt regulator 3 and the second parallel regulator Shunt regulator 4 are equal and are both Ishunt. Ishunt is the minimum current to ensure the normal operation of the first parallel regulator Shunt regulator 3 and the second parallel regulator Shunt regulator 4. Furthermore, the regulating current Ishunt generated by the second parallel regulator Shunt regulator 4 plus the bias current Idrv flowing through the second drive circuit 30 is equal to the bias current generated by the bias current source tube Mbn (i.e., Ishunt + Idrv). Idrv is the current required by the second drive circuit 30 to generate the corresponding output signal, thereby ensuring that the bias currents flowing through the first drive circuit 20 and the second drive circuit 30 are equal and are both Idrv.

[0084] like Figure 9As shown, when only the second drive circuit 30 is working, the regulating current generated by the first parallel regulator 3 is Ishunt + Idrv, and the regulating current generated by the second parallel regulator 4 is Ishunt. This ensures that the bias current flowing through the second drive circuit 30 is Idrv, that is, the bias current flowing through the second drive circuit 30 is equal to the regulating current generated by the first parallel regulator 3 minus the regulating current generated by the second parallel regulator 4. At this time, the bias current generated by the bias current source transistor Mbn is Ishunt + Idrv. Conversely, when the first drive circuit 20 is working and the second drive circuit 30 is not working, the first regulating current generated by the first parallel regulator 3 is matched with the second regulating current generated by the second parallel regulator 4, which also ensures that the bias current flowing through the first drive circuit 20 is Idrv, allowing the first drive circuit 20 to operate normally.

[0085] In this embodiment, the bias current source transistor Mbn serves as a constant current source. The first parallel regulator 3 and the second parallel regulator 4 adjust the output regulating current according to the working state of the first driving circuit 20 and the second driving circuit 30, so that when the first driving circuit 20 and the second driving circuit 30 are working simultaneously or when any one of the driving circuits is working, a constant bias current can be guaranteed to drive the first driving circuit 20 and / or the second driving circuit 30 to work normally.

[0086] The foregoing description of specific exemplary embodiments of the invention is for illustrative and explanatory purposes. These descriptions are not intended to limit the invention to the precise forms disclosed, and it will be apparent that many changes and variations can be made in accordance with the foregoing teachings; the invention can be implemented in other forms, structures, arrangements, proportions, and with other components, materials, and parts. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application, thereby enabling those skilled in the art to implement and utilize various different exemplary embodiments and various different choices and modifications of the invention without departing from the scope and spirit of the invention. The scope of the invention is intended to be defined by the claims and their equivalents.

Claims

1. A drive system, characterized in that, include: The first bias current circuit is used to provide the first bias current; The first driving circuit has a first current input terminal for receiving a first bias current, a first current output terminal for outputting the first bias current, and a first output terminal and a second output terminal for outputting a first differential signal. The second driving circuit has a second current input terminal connected to the first current output terminal of the first driving circuit to form a connection node to receive the first bias current, a second current output terminal outputting the first bias current, and a third and fourth output terminals outputting the second differential signal. as well as The second bias current circuit is used to provide a second bias current that is the same as the first bias current, and the second current output terminal of the second drive circuit is connected to the second bias current circuit.

2. The drive system as described in claim 1, characterized in that, The drive system further includes an adjustment unit connected to the connection node, the adjustment unit being used to generate an adjustment current to adjust the bias current of the first drive circuit and / or the second drive circuit.

3. The drive system as described in claim 2, characterized in that, The regulating unit includes a first parallel regulator and a second parallel regulator. The first parallel regulator is connected to a connection node to generate a first regulating current, and the second parallel regulator is connected to a connection node to generate a second regulating current.

4. The drive system as described in claim 1, characterized in that, The first driving circuit includes a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a first resistor, a second resistor, and a first common-mode signal generation circuit; The source of the first switch is connected to the source of the second switch to form a first current input terminal. The drain of the first switch is connected to the drain of the third switch. The drain of the second switch is connected to the drain of the fourth switch. The source of the third switch is connected to the source of the fourth switch to form a first current output terminal. The first end of the first resistor is connected to the drain of the second switch to form a first output terminal. The second end of the first resistor is connected to the first end of the second resistor and the first common-mode signal generation circuit. The second end of the second resistor is connected to the drain of the first switch to form a second output terminal.

5. The drive system as described in claim 4, characterized in that, The first common-mode signal generation circuit includes a first transconductance amplifier, which has a first input terminal, a second input terminal, and a fifth output terminal. The first input terminal and the fifth output terminal of the first transconductance amplifier are connected. The second input terminal of the first transconductance amplifier is used to receive a reference voltage, and the fifth output terminal of the first transconductance amplifier is used to output a first common-mode signal.

6. The drive system as described in claim 1, characterized in that, The second driving circuit includes a fifth switch, a sixth switch, a seventh switch, an eighth switch, a third resistor, a fourth resistor, and a second common-mode signal generation circuit; The source of the fifth switch is connected to the source of the sixth switch to form a second current input terminal. The drain of the fifth switch is connected to the drain of the seventh switch. The drain of the sixth switch is connected to the drain of the eighth switch. The source of the seventh switch is connected to the source of the eighth switch to form a second current output terminal. The first end of the third resistor is connected to the drain of the sixth switch to form a third output terminal. The second end of the third resistor is connected to the second common-mode signal generation circuit and the first end of the fourth resistor. The second end of the fourth resistor is connected to the drain of the fifth switch to form a fourth output terminal.

7. The drive system as described in claim 6, characterized in that, The second common-mode signal generation circuit includes a second transconductance amplifier, which has a third input terminal, a fourth input terminal, and a sixth output terminal. The third input terminal and the sixth output terminal of the second transconductance amplifier are connected. The fourth input terminal of the second transconductance amplifier is used to receive a reference voltage, and the sixth output terminal of the second transconductance amplifier is used to output a second common-mode signal.

8. The drive system as described in claim 1, characterized in that, The first bias current circuit includes a first bias current source transistor, the source of which is connected to the power supply voltage, and the drain of which is connected to the first current input terminal of the first drive circuit.

9. The drive system as described in claim 1, characterized in that, The second bias current circuit includes a second bias current source transistor, the source of which is connected to ground voltage, and the drain of which is connected to the second current output terminal of the second drive circuit.

10. The drive system as described in claim 2, characterized in that, The drive system further includes a bias voltage control module, which is used to provide bias voltage to the first bias current circuit, the second bias current circuit and / or the adjustment unit.

11. A drive system, characterized in that, include: Bias current circuit, used to provide bias current; The first driving circuit has a first current input terminal for receiving bias current, a first current output terminal for outputting bias current, and a first output terminal and a second output terminal for outputting a first differential signal. as well as The second driving circuit has a second current input terminal connected to the first current output terminal of the first driving circuit to form a connection node for receiving bias current, a second current output terminal for outputting bias current, and a third and fourth output terminals for outputting a second differential signal.

12. The drive system as described in claim 11, characterized in that, The drive system further includes an adjustment unit, which is connected to the first current input terminal and connection node of the first drive circuit and the second current output terminal of the second drive circuit. The adjustment unit is used to generate an adjustment current to adjust the bias current of the first drive circuit and / or the second drive circuit.

13. The drive system as described in claim 12, characterized in that, The regulating unit includes a first parallel regulator and a second parallel regulator. The first parallel regulator is connected to a connection node and a first current input terminal to generate a first regulating current, and the second parallel regulator is connected to a connection node and a second current output terminal to generate a second regulating current.

14. The drive system as described in claim 12, characterized in that, The drive system also includes a bias voltage control module, which is used to provide a bias voltage to the bias current circuit and / or the adjustment unit.

15. The drive system as described in claim 11, characterized in that, The bias current circuit includes a bias current source transistor, the source of which is connected to ground voltage, and the drain of which is connected to the second current output terminal of the second drive circuit.

16. The drive system as described in claim 11, characterized in that, The first driving circuit includes a fifth resistor, a sixth resistor, a ninth switch, and a tenth switch; the first end of the fifth resistor is connected to the first end of the sixth resistor to form a first current input terminal, the second end of the fifth resistor is connected to the drain of the ninth switch to form a first output terminal, the second end of the sixth resistor is connected to the drain of the tenth switch to form a second output terminal, and the source of the ninth switch is connected to the source of the tenth switch to form a first current output terminal.

17. The drive system as claimed in claim 11, characterized in that, The second driving circuit includes a seventh resistor, an eighth resistor, an eleventh switch, and a twelfth switch; the first end of the seventh resistor is connected to the first end of the eighth resistor to form a second current input terminal, the second end of the seventh resistor is connected to the drain of the eleventh switch to form a third output terminal, the second end of the eighth resistor is connected to the drain of the twelfth switch to form a fourth output terminal, and the source of the eleventh switch is connected to the source of the twelfth switch to form a second current output terminal.

18. A transceiver, characterized in that, include: The data processing unit, the receiver, and the drive system as described in any one of claims 1 to 17, wherein the receiver is used to receive data and send the data to the data processing unit, the data processing unit is used to process the data sent by the receiver and generate data to be sent to the drive system, and the drive system is used to send the data sent by the data processing unit.

19. A transceiver communication system, characterized in that, It includes multiple transceivers as described in claim 18, connected in a daisy chain.

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