Array substrate and display panel thereof

Abstract

The present application provides an array substrate and a display panel thereof. The array substrate is used for a liquid crystal display panel, comprising a first substrate having a plurality of sub-pixel regions arranged in an array; a driving circuit layer, arranged on one side of the first substrate, comprising a plurality of sub-pixels; each sub-pixel is arranged corresponding to a sub-pixel region; a supporting layer, arranged on a side of the driving circuit layer away from the first substrate; the supporting layer comprises a plurality of annular retaining walls, and the plurality of annular retaining walls are arranged one-to-one corresponding to the plurality of sub-pixel regions; the annular retaining walls are arranged at the boundary of the sub-pixel region and around the sub-pixels; the annular retaining walls are configured to prevent color crosstalk between two adjacent sub-pixels. The array substrate is used to prevent color crosstalk between two adjacent sub-pixels by arranging annular retaining walls at the boundary of the plurality of sub-pixel regions and around the sub-pixels, thereby increasing the color differentiation of the pixels, thereby greatly improving the display quality of the display panel.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate and a display panel thereof. Background Art

[0002] With the improvement of science and technology and living standards, people have an increasing demand for fast-response displays and high-end flexible electronic devices. The research and development of liquid crystal devices with faster response times has always been a hot topic and focus of researchers. The response speed of traditional nematic liquid crystals is generally in the millisecond level, and the reduction in response time has reached a bottleneck.

[0003] In recent years, as people have conducted in-depth research on ferroelectric liquid crystals, they have found that ferroelectric liquid crystals have characteristics such as response time reaching microseconds, low driving voltage, excellent photoelectric and nonlinear optical effects, etc. The response time of ferroelectric liquid crystals is one thousand times faster than that of color filters, greatly reducing energy consumption by nearly 70%. Ferroelectric liquid crystals have broad application prospects in the field of liquid crystal display panels. Among them, spiral-shaped ferroelectric liquid crystals do not require R / G / B three primary color filter film layers, and full-color display can be achieved by adjusting the timing, so they have received special attention.

[0004] However, in a display panel using ferroelectric liquid crystal, cross-color phenomenon is prone to occur at the edge of pixels, thereby affecting the image quality of the display panel. Summary of the invention

[0005] The present application provides an array substrate and a display panel thereof, which mainly solve the problem in the prior art that pixel edges of the display panel are prone to cross-color phenomenon, thereby causing a significant loss in image quality presented by the display panel.

[0006] In order to solve the above technical problems, a technical solution adopted in the present application is to provide an array substrate for a liquid crystal display panel, comprising:

[0007] A first substrate having a plurality of sub-pixel regions arranged in an array;

[0008] A driving circuit layer is arranged on one side of the first substrate, and includes a plurality of sub-pixels; each of the sub-pixels is arranged corresponding to one of the sub-pixel regions;

[0009] A supporting layer, disposed on a side of the driving circuit layer away from the first substrate;

[0010] The support layer includes a plurality of annular retaining walls, and the plurality of annular retaining walls are arranged in one-to-one correspondence with the plurality of sub-pixel areas; the annular retaining walls are arranged at the boundaries of the sub-pixel areas and are arranged around the sub-pixels; the annular retaining walls are configured to prevent color crosstalk between two adjacent sub-pixels.

[0011] In a specific embodiment, the annular retaining wall corresponding to two adjacent sub-pixel regions has a common side wall, and the common side wall has a first gap connecting the two adjacent sub-pixel regions.

[0012] In a specific implementation, the height of the annular retaining wall is 1.2-1.5 um.

[0013] In a specific embodiment, the sub-pixel region includes a main light-transmitting region and an auxiliary light-transmitting region that are spaced apart, and an opaque region between the main light-transmitting region and the auxiliary light-transmitting region; the sub-pixel includes:

[0014] A main pixel electrode, located in the main light-transmitting area;

[0015] A secondary pixel electrode, located in the secondary light-transmitting area;

[0016] A first thin film transistor, located in the opaque area and electrically connected to the main pixel electrode;

[0017] The second thin film transistor is located in the opaque area and is electrically connected to the auxiliary pixel electrode.

[0018] In a specific embodiment, the array substrate further includes:

[0019] A light shielding layer, arranged on a side of the driving circuit layer away from the first substrate, comprising a plurality of sub-light shielding layers;

[0020] Wherein, the sub-light-shielding layer is arranged in the annular retaining wall, and one sub-light-shielding layer is arranged in each light-proof area.

[0021] In a specific embodiment, the annular retaining wall includes a first side wall and a second side wall arranged opposite to each other along a first direction, and a third side wall and a fourth side wall arranged opposite to each other along a second direction; the main light-transmitting area, the light-impermeable area and the auxiliary light-transmitting area are arranged in sequence along the first direction, and the second direction intersects with the first direction; wherein,

[0022] There is a gap between the sub-light shielding layer and the third side wall; and / or,

[0023] There is a gap between the sub-light shielding layer and the fourth side wall; and / or,

[0024] The sub-light-shielding layer has a second gap connecting the main light-transmitting area and the auxiliary light-transmitting area.

[0025] In a specific implementation manner, the width of the gap is 0.5um-1.5um; or the thickness of the sub-light-shielding layer is smaller than the height of the annular retaining wall.

[0026] In order to solve the above technical problems, another technical solution adopted by the present application is to provide a display panel, including:

[0027] A first substrate; the first substrate is any of the array substrates mentioned above;

[0028] A second substrate is disposed on a side of the support layer away from the first substrate;

[0029] The liquid crystal layer comprises a plurality of liquid crystal units; each of the liquid crystal units is correspondingly arranged in one of the annular retaining walls; the liquid crystal layer comprises a liquid crystal material capable of achieving color filtering.

[0030] In a specific embodiment, the liquid crystal layer includes a ferroelectric liquid crystal material; and / or

[0031] The second substrate only includes a second substrate, a common electrode layer and an alignment layer; and / or

[0032] The second base plate abuts against an end of the annular retaining wall away from the first substrate.

[0033] In a specific embodiment, the liquid crystal layer includes a ferroelectric liquid crystal material; the annular retaining wall corresponding to two adjacent sub-pixel regions has a common side wall, the common side wall has a first notch connecting the two adjacent sub-pixel regions, and the second substrate is provided with a convex strip, and the convex strip is embedded in the first notch;

[0034] Preferably, the height of the convex strip is smaller than the height of the first notch;

[0035] More preferably, the end of the convex strip away from the second substrate is spaced apart from the driving circuit layer of the first substrate, and one end of the annular retaining wall away from the driving circuit layer is in contact with the second substrate.

[0036] The present application provides an array substrate and a display panel thereof. The array substrate is used for a liquid crystal display panel, and includes a first substrate, a driving circuit layer, and a supporting layer. The supporting layer includes a plurality of annular retaining walls, and the plurality of annular retaining walls are arranged in a one-to-one correspondence with a plurality of sub-pixel areas. The array substrate provided by the present application is provided with annular retaining walls at the boundaries of the plurality of sub-pixel areas and around the sub-pixels to prevent the color crosstalk between two adjacent sub-pixels, thereby greatly improving the display quality of the display panel; in addition, the annular retaining walls arranged in this way also play a supporting role for other substrates arranged on the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0038] Figure 1 A top view of the array substrate provided in the first embodiment of the present application;

[0039] Figure 2 for Figure 1 Section view along line AA;

[0040] Figure 3 A top view of a first substrate of an array substrate provided in the first embodiment of the present application;

[0041] Figure 4 A schematic diagram of the specific structure of a driving circuit layer provided in one embodiment of the present application;

[0042] Figure 5 A top view of an array substrate provided in the second embodiment of the present application;

[0043] Figure 6 A top view of an array substrate provided in the third embodiment of the present application;

[0044] Figure 7 For Figure 6 A top view of oppositely disposed substrates;

[0045] Figure 8 for Figure 6 The array substrate and Figure 7 The partial cross-sectional schematic diagram after the substrates are aligned and boxed is shown;

[0046] Figure 9a A top view of an array substrate provided in a fourth embodiment of the present application;

[0047] Figure 9b for Figure 9a Sectional view along line BB;

[0048] Fig.10a A top view of an array substrate provided in a fifth embodiment of the present application;

[0049] Fig.10b for Fig.10a Sectional view along line CC;

[0050] Fig.11 A schematic diagram of the structure of a display panel provided in one embodiment of the present application;

[0051] Fig.12A flow chart of a method for preparing an array substrate provided in one embodiment of the present application;

[0052] Fig.13a A top view of the structure of step S1 in the array substrate preparation method provided in this application;

[0053] Fig.13b for Fig.13a Sectional view along line DD;

[0054] Fig.13c A top view of the first substrate in step S1 of the array substrate preparation method provided in the present application;

[0055] Fig.14 For Fig.13b A structural diagram of step S2 is performed based on the above;

[0056] Fig.15 For Fig.14 The structural diagram of step S3 is performed based on .

[0057] Description of Figure Numbers:

[0058] 1-first substrate; 101-sub-pixel area; 1011-main light-transmitting area; 1012-auxiliary light-transmitting area; 1013-opaque area; 2-driving circuit layer; 201-sub-pixel; 2011-main pixel electrode; 2012-auxiliary pixel electrode; 202-gate metal layer; 203-first insulating layer; 204-semiconductor layer; 205-source and drain metal layer; 206-second insulating layer; 207-pixel electrode layer; 208-alignment layer; 209-flat layer; 3-support layer; 301-annular retaining wall; 3011-first side wall; 3012-second side wall; 3013-third side wall; 3014-fourth side wall; 4-light shielding layer; 401-sub-light shielding layer; 10-array substrate; 20-first substrate; 30-second substrate; 40-liquid crystal layer; 4001-liquid crystal unit; 50-opposite substrate; 501-convex strip; 100-display panel; a-first notch; b-second notch; X-first direction; Y-second direction; G-spacer photoresist. DETAILED DESCRIPTION

[0059] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0060] In the following description, for the purpose of explanation rather than limitation, specific details such as specific system structures, interfaces, and technologies are provided to facilitate a thorough understanding of the present application.

[0061] The terms "first", "second", "third" in this application are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first", "second", "third" can expressly or implicitly include at least one of the features. In the description of this application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In the embodiments of this application, all directional indications (such as up, down, left, right, front, back...) are only used to explain the relative position relationship, movement, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication also changes accordingly. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the steps or units listed, but optionally also includes steps or units that are not listed, or optionally also includes other steps or units inherent to these processes, methods, products or devices.

[0062] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0063] In recent years, as people have conducted in-depth research on ferroelectric liquid crystals, they have found that ferroelectric liquid crystals have characteristics such as response time reaching the microsecond level, low driving voltage, and excellent photoelectric and nonlinear optical effects. The response time of ferroelectric liquid crystals is one thousand times faster than that of color filter layers, greatly reducing energy consumption by nearly 70%. Ferroelectric liquid crystals have broad application prospects in the field of liquid crystal display panels. Ferroelectric liquid crystals have broad application prospects in the field of liquid crystal display panels. Among them, spiral-shaped ferroelectric liquid crystals do not require R / G / B primary color filter film layers, and full-color display can be achieved by adjusting the timing, so they have received special attention. However, in display panels using ferroelectric liquid crystals, cross-color phenomenon is prone to occur at the edges of pixels, which affects the image quality of the display panel.

[0064] The inventor of this application has found that the existing liquid crystal display panel wants to achieve full-color display mainly by setting a color filter layer on the color filter substrate or preparing the color film layer on the array substrate. The black matrix pixels of the existing liquid crystal display panel correspond to the pixels of the color filter layer to reduce the cross-color phenomenon; the existing liquid crystal display panel sets spacer columns between the pixels on the color filter substrate to provide a stable box thickness. Compared with the traditional liquid crystal display preparation technology; the ferroelectric liquid crystal display panel does not need to set a color filter layer to achieve full-color display, and can achieve full-color display by adjusting the timing. However, using the traditional film layer design, the sub-pixel edge of the array substrate of the ferroelectric liquid crystal display panel has a serious cross-color phenomenon because there is no specific film layer to separate the sub-pixels from each other, thereby affecting the image quality of the display panel.

[0065] The present application provides an array substrate and a display panel thereof. The liquid crystal layer material of the present application is ferroelectric liquid crystal, and setting a baffle on a color film substrate cannot prevent the cross-color phenomenon. Therefore, the present application provides a solution of setting a baffle on the array substrate. By setting an annular baffle at the boundary of multiple sub-pixel areas and around the sub-pixels, it is used to prevent the cross-color between two adjacent sub-pixels, thereby greatly improving the display quality of the display panel.

[0066] The present application is described in detail below with reference to the accompanying drawings and embodiments.

[0067] See also Figure 1 , Figure 2 and Figure 3 , Figure 1 A top view of the array substrate provided in the first embodiment of the present application; Figure 2 for Figure 1 Section view along line AA; Figure 3 A top view of the first substrate of the array substrate provided in the first embodiment of the present application.

[0068] See also Figure 1 , Figure 2 and Figure 3 The present application provides an array substrate 10, which is used in a liquid crystal display panel to display images and information. The array substrate 10 includes a first substrate 1, a driving circuit layer 2 and a supporting layer 3.

[0069] Specifically, the first substrate 1 has a plurality of sub-pixel regions 101 arranged in an array. The plurality of sub-pixel regions 101 are arranged in a two-dimensional array. The first substrate 1 may be a glass substrate, or a substrate of other types such as a ceramic substrate. In this embodiment, the sub-pixel region 101 includes a main light-transmitting region 1011 and an auxiliary light-transmitting region 1012 arranged at intervals, and an opaque region 1013 located between the main light-transmitting region 1011 and the auxiliary light-transmitting region 1012; the main light-transmitting region 1011 and the auxiliary light-transmitting region 1012 are used to set the sub-pixel 201. The shape and size of the sub-pixel region 101, the main light-transmitting region 1011 and the auxiliary light-transmitting region 1012 are not limited and can be selected as needed. In this embodiment, the sub-pixel region 101, the main light-transmitting region 1011 and the auxiliary light-transmitting region 1012 are all rectangular, and the area of ​​the main light-transmitting region 1011 is greater than the area of ​​the auxiliary light-transmitting region 1012. The driving circuit layer 2 is arranged on one side of the first substrate 1, and the driving circuit layer 2 includes a plurality of sub-pixels 201. Each sub-pixel 201 of the driving circuit layer 2 is arranged corresponding to a sub-pixel area 101. Specifically, the sub-pixel 201 includes a main pixel electrode 2011, an auxiliary pixel electrode 2012, a first thin film transistor (not shown) and a second thin film transistor (not shown). The main pixel electrode 2011 is located in the main light-transmitting area 1011; the auxiliary pixel electrode 2012 is located in the auxiliary light-transmitting area 1012; the first thin film transistor is located in the opaque area 1013 and is electrically connected to the main pixel electrode 2011; the second thin film transistor is located in the opaque area 1013 and is electrically connected to the auxiliary pixel electrode 2012. In a specific embodiment, the sub-pixel 201 can be a sub-pixel 201 that emits red light, a sub-pixel 201 that emits blue light, or a sub-pixel 201 that emits green light, and the present application does not make specific limitations on this. Specifically, in the present embodiment, a plurality of sub-pixels 201 are arranged in sequence, and the sub-pixels 201 in the same row form a plurality of pixel units (not marked in the figure); each pixel unit includes three different sub-pixels 201, namely, a sub-pixel 201 that can emit red light, a sub-pixel 201 that can emit blue light, and a sub-pixel 201 that can emit green light, and the sub-pixels 201 in the same column have the same color.

[0070] In one embodiment, by connecting a leakage thin film transistor and a second thin film transistor to cause the second thin film transistor to leak a portion of the voltage, different voltages are output by the first thin film transistor and the second thin film transistor, thereby achieving different voltages obtained by the main pixel electrode 2011 and the auxiliary pixel electrode 2012, so that the main light-transmitting area 1011 and the auxiliary light-transmitting area 1012 cooperate to achieve a wider viewing angle display effect.

[0071] Continue reading Figure 1 , Figure 2 and Figure 3The support layer 3 is arranged on the side of the driving circuit layer 2 away from the first substrate 1. The support layer 3 includes a plurality of annular retaining walls 301, and the plurality of annular retaining walls 301 are arranged one by one corresponding to the plurality of sub-pixel areas 101. Specifically, the annular retaining walls 301 are arranged at the boundary of the sub-pixel area 101 and are arranged around the sub-pixel 201. Such annular retaining walls 301 can be used to prevent cross-color from occurring between two adjacent sub-pixels 201.

[0072] See also Figure 3 , the annular retaining wall 301 corresponding to two adjacent sub-pixel areas 101 has a common side wall (not shown). In this way, two adjacent sub-pixels 201 share part of the annular retaining wall 301, which can save the material of the annular retaining wall 301, thereby simplifying the process and saving the cost of preparation. In a specific embodiment, the annular retaining wall 301 is opaque. The array substrate 10 of the present application is provided with an annular retaining wall 301, and the annular retaining wall 301 is opaque. Fig.11 The support layer 3 includes a plurality of annular retaining walls 301 . The annular retaining walls 301 play the same light shielding role as the black matrix on the array substrate 10 , thereby preventing cross-color from occurring between two adjacent sub-pixels 201 .

[0073] Specifically, the material of the annular retaining wall 301 is black opaque material.

[0074] Specifically, the height of the annular retaining wall 301 is 1.2um-1.5um. For example, the height of the annular retaining wall 301 can be 1.2um, 1.25um, 1.3um, 1.35um, 1.4um, 1.45um, or 1.5um.

[0075] See also Figure 4 , Figure 4A schematic diagram of the specific structure of the driving circuit layer provided in an embodiment of the present application. In a specific embodiment, the driving circuit layer 2 specifically includes a gate metal layer 202, a first insulating layer 203, a semiconductor layer 204, a source-drain metal layer 205, a second insulating layer 206, a pixel electrode layer 207 and an alignment layer 208. Among them, the gate metal layer 202 is arranged on a side surface of the first substrate 1. The first insulating layer 203 is arranged on a side of the gate metal layer 202 away from the first substrate 1, and the first insulating layer 203 covers the gate metal layer 202, and the first insulating layer 203 can play a passivation effect. The semiconductor layer 204 is arranged on a side of the first insulating layer 203 away from the first substrate 1. The source-drain metal layer 205 is arranged on a side of the first insulating layer 203 away from the first substrate 1. The second insulating layer 206 is arranged on a side of the first insulating layer 203 away from the first substrate 1, further playing a passivation effect, and the second insulating layer 206 covers the semiconductor layer 204 and the source-drain metal layer 205. The driving circuit layer 2 further includes a planar layer 209, which is disposed on a side of the second insulating layer 206 away from the first substrate 1; the pixel electrode layer 207 is disposed on a side of the planar layer 209 away from the first substrate 1; wherein the annular retaining wall 301 is disposed on a side of the planar layer 209 away from the first substrate 1, and is disposed around the pixel electrode of the corresponding sub-pixel 201, so as to prevent cross-color from occurring between adjacent sub-pixels 201. The alignment layer 208 is disposed on a side of the pixel electrode layer 207 away from the first substrate 1, and covers the pixel electrode of the pixel electrode layer 207, and the alignment layer 208 is used to align the liquid crystal layer 40 (see below). Fig.11 ) for orientation.

[0076] Specifically, the thickness of the alignment layer 208 is 30 nm-50 nm.

[0077] See also Figure 5 , Figure 5 A top view of an array substrate provided in the second embodiment of the present application. The structure of the array substrate 10 of this embodiment is substantially the same as that of the array substrate 10 in the first embodiment, except that a first notch a is provided on the common side wall of the annular retaining wall 301 corresponding to two adjacent sub-pixel regions 101, which connects the two adjacent sub-pixel regions 101. The first notch a can be used to allow the liquid alignment layer material to flow in the adjacent sub-pixel regions 101 during the preparation of the alignment layer 208, so that the liquid alignment layer material flows evenly to each sub-pixel region 101. It can be understood that the first notch a can be provided on the common side wall of adjacent sub-pixel regions 101 in each row or column; it can also be provided on both the common side wall of adjacent sub-pixel regions 101 in each row and the common side wall of adjacent sub-pixel regions 101 in each column; regardless of how it is provided, the function of the first notch a is to allow the alignment layer 208 to be evenly spread in the sub-pixel region 101.

[0078] It is understandable that, considering that setting the first notch a on the common side wall of adjacent sub-pixel areas 101 will cause light transmission, resulting in cross-color between adjacent sub-pixels 201 of different colors; in order to prevent cross-color between adjacent sub-pixels 201 of different colors, preferably, the colors of sub-pixels 201 in the same column are the same, and the first notch a is only set on the common side wall of sub-pixels 201 of the same color in the same column.

[0079] It is understandable that the first gap a provided in the second embodiment can make the liquid alignment layer material flow evenly to each sub-pixel area 101. However, on the one hand, the existence of the first gap a may cause cross-color between adjacent sub-pixel areas 101; on the other hand, if the first gap a is too narrow, it will affect the flow rate of the liquid alignment layer material, and if the first gap a is too wide, it will more easily cause cross-color. Therefore, the present application proposes a new solution as follows:

[0080] See also Figure 6 , Figure 7 and Figure 8 , Figure 6 A top view of an array substrate provided in the third embodiment of the present application. Figure 7 For Figure 6 A top view of opposing substrates disposed opposite to each other. Figure 8 for Figure 6 The array substrate and Figure 7 The schematic partial cross-sectional view of the counter substrate after being assembled is shown. The structure of the array substrate 10 of this embodiment is basically the same as that of the array substrate 10 in the second embodiment, except that in this embodiment, a first notch a having a larger width than the first notch a in the second embodiment is provided on the longer common sidewall of the adjacent annular retaining wall 301, so that the liquid alignment layer material flows more smoothly between the two adjacent sub-pixel areas 101 defined by the adjacent annular retaining wall 301 of the array substrate 10, and the overall uniformity of the formed alignment layer is better. In addition, in order to prevent the light from being transmitted between the two adjacent sub-pixel areas 101 caused by the first notch a, a convex strip 501 is further provided on the counter substrate 50; wherein the position of the convex strip 501 corresponds to the position of the first notch a. After the array substrate 10 and the counter substrate 50 are assembled, the convex strip 501 is embedded in the first notch a to form a closed annular retaining wall 301. For example, the height of the first notch a is equal to the height of the annular retaining wall 301, and the width of the first notch a is greater than 1 micron, and preferably the width of the first notch a is greater than 5 microns.

[0081] Specifically, the sub-pixel region 101 is rectangular, and the common sidewall of the annular retaining wall 301 corresponding to the long sides of two adjacent sub-pixel regions 101 has a first notch a connecting the two adjacent sub-pixel regions 101, and multiple first notches a of the sub-pixel regions 101 in the same row are located in the same row, that is, the projections in the row direction overlap. It can be understood that a portion of the annular retaining wall 301 is disposed on the array substrate 10, and another portion is disposed on the counter substrate 50, so that the liquid alignment layer material of the array substrate 10 and the liquid alignment layer material of the counter substrate 50 can both diffuse more smoothly.

[0082] Preferably, the height of the convex strip 501 is slightly smaller than the height of the first notch a. The problem of light leakage caused by the inability to fit the partial annular retaining wall 301 and the opposite substrate 50 due to the uneven thickness of the partial annular retaining wall 301 and the convex strip 501 can be avoided; this is because the backlight will emit colored light only after passing through the ferroelectric liquid crystal, and the inability to fit the partial annular retaining wall 301 and the opposite substrate 50 will form a gap, thereby causing light leakage. In a specific embodiment, the end of the convex strip 501 away from the opposite substrate 50 is spaced from the drive circuit layer 2 of the array substrate 10, and the end of the annular retaining wall 301 away from the drive circuit layer 2 of the array substrate 10 is both fitted with the opposite substrate 50, ensuring that the annular retaining wall 301 and the convex strip 501 form a closed retaining wall on the side close to the opposite substrate 50, so that the light leakage phenomenon can be effectively prevented, and the light leakage problem caused by the gap between the end of the convex strip 501 away from the opposite substrate 50 and the drive circuit layer 2 of the array substrate 10 is very small and can be almost ignored.

[0083] See also Figure 9a and Figure 9b , Figure 9a A top view of an array substrate provided in the fourth embodiment of the present application. Figure 9b for Figure 9a Cross-sectional view along line BB. The structure of the array substrate 10 of the fourth embodiment is basically the same as the structure of the array substrate 10 in the first embodiment or the second embodiment, except that the array substrate 10 provided in this embodiment further includes a light shielding layer 4. The light shielding layer 4 is arranged on the side of the driving circuit layer 2 away from the first substrate 1, and the light shielding layer 4 includes a plurality of sub-light shielding layers 401; wherein the sub-light shielding layers 401 are arranged in the annular retaining wall 301, and each light-proof area 1013 is provided with a sub-light shielding layer 401. In a specific embodiment, the light shielding layer 4 is a black material layer.

[0084] Specifically, the thickness of the sub-light shielding layer 401 is less than the height of the annular retaining wall 301. The existence of the sub-light shielding layer 401 is used to further shield the light, prevent the external light from affecting the thin film transistor; and prevent the backlight from affecting the liquid crystal in the thin film transistor area, thereby reducing the possibility of uneven display brightness; in addition, the thickness of the sub-light shielding layer 401 is less than the height of the annular retaining wall 301, so as to allow the light of the pixel to be more evenly filled in the sub-pixel area 101.

[0085] In this embodiment, the thickness of the sub-light shielding layer 401 is 500-800 nm.

[0086] Continue reading Figure 9a and Figure 9b In this embodiment, the annular retaining wall 301 includes a first side wall 3011 and a second side wall 3012 arranged opposite to each other along a first direction X, and a third side wall 3013 and a fourth side wall 3014 arranged opposite to each other along a second direction Y. Among them, the main light-transmitting area 1011, the opaque area 1013 and the auxiliary light-transmitting area 1012 are arranged in sequence along the first direction X; the second direction Y is arranged to cross the first direction X. In a specific embodiment, the first direction X and the second direction Y are perpendicular, the first direction X is the column direction of the array formed by the plurality of sub-pixel areas 101, and the second direction Y is the row direction of the array formed by the plurality of sub-pixel areas 101. Specifically, this embodiment is described by assuming that the first direction X and the second direction Y are perpendicular.

[0087] Further reading Figure 9a and Figure 9b , there is a gap W between the sub-light shielding layer 401 and the third side wall 3013; and / or, there is a gap W between the sub-light shielding layer 401 and the fourth side wall 3014. It can be understood that the gap W between the sub-light shielding layer 401 and the third side wall 3013, and the gap W between the sub-light shielding layer 401 and the fourth side wall 3014 are both conducive to the liquid alignment layer material flowing and evenly spreading in the main light-transmitting area 1011 and the auxiliary light-transmitting area 1012 in the sub-pixel area 101 during the preparation of the alignment layer 208, so as to form an alignment layer 208 with uniform thickness.

[0088] See also Fig.10a and Fig.10b , Fig.10a A top view of an array substrate provided in the fifth embodiment of the present application. Fig.10b for Fig.10aCross-sectional view along line CC. The structure of the array substrate 10 of the fifth embodiment of the present application is basically the same as the structure of the array substrate 10 in the fourth embodiment, except that the light shielding layer 4 of the array substrate 10 provided in this embodiment also includes a second notch b. Specifically, the sub-light shielding layer 401 has a second notch b connecting the main light-transmitting area 1011 and the auxiliary light-transmitting area 1012. The provision of the second notch b is also conducive to the flow and uniform expansion of the liquid alignment layer material in the main light-transmitting area 1011 and the auxiliary light-transmitting area 1012 in the sub-pixel area 101 during the preparation of the alignment layer 208, so as to form an alignment layer 208 with uniform thickness.

[0089] In a specific embodiment, there may be gaps W between the sub-light-shielding layer 401 and the third side wall 3013 and the fourth side wall 3014, which is not specifically limited in this application. The sub-light-shielding layer 401 may be a continuous black material layer, or a black material layer having a second gap b connecting the main light-transmitting area 1011 and the auxiliary light-transmitting area 1012, which is not specifically limited in this application. Specifically, the third embodiment mainly takes the gap W between the sub-light-shielding layer 401 and the third side wall 3013 as an example; the fourth embodiment mainly takes the gap W between the sub-light-shielding layer 401 and the third side wall 3013, and the gap W between the sub-light-shielding layer 401 and the fourth side wall 3014 as an example.

[0090] Specifically, the width of the gap W is 0.5um-1.5um. For example, the width of the gap W can be 0.5um, 0.75um, 1.0um, 1.25um, or 1.5um.

[0091]

[0092] Table 1

[0093] See also Fig.11 , Fig.11 A schematic diagram of the structure of a display panel provided in one embodiment of the present application. The present application also provides a display panel 100, comprising a first substrate 20, a second substrate 30 and a liquid crystal layer 40. The first substrate 20 is the array substrate 10 provided in any of the above embodiments. The specific structure and function of the array substrate 10 can be found in the relevant description of the array substrate 10 provided in the above embodiments, which will not be repeated here. Specifically, the present application takes the array substrate 10 provided in the third embodiment as an example for explanation.

[0094] The second substrate 30 is arranged on the side of the support layer 3 away from the first substrate 1. The second substrate 30 only includes a second substrate (not shown), a common electrode layer (not shown) and an alignment layer (not shown). Compared with the prior art, the second substrate 30 of the display panel 100 provided in the present application does not include a color filter layer and a black matrix. The second substrate 30 is also abutted against one end of the annular retaining wall 301 away from the first substrate 1. The annular retaining wall 301 also plays a role in supporting the second substrate 30. In addition, in the present embodiment, the annular retaining wall 301 can also prevent the occurrence of cross-color between two adjacent sub-pixels 201, which greatly improves the display quality of the display panel 100.

[0095] Further reading Fig.11 The liquid crystal layer 40 includes a plurality of liquid crystal units 4001, each of which is disposed on a corresponding annular retaining wall 301 (see Figure 3 ). The liquid crystal layer 40 includes a liquid crystal material capable of color filtering. Specifically, the liquid crystal layer 40 includes a ferroelectric liquid crystal material. The display panel 100 using ferroelectric liquid crystal does not require a color filter layer, and full-color display can be achieved by adjusting the timing.

[0096] It can be understood that in the display panel 100 , by disposing the light shielding layer 4 in the annular retaining wall 301 to further shield light, the black matrix in the second substrate 30 is omitted, thereby making the thickness of the display panel 100 thinner.

[0097] The display panel 100 provided in the present application is provided with a support layer 3, and the support layer 3 includes a plurality of annular retaining walls 301, and the second substrate 30 is abutted against one end of the annular retaining wall 301 away from the first substrate 1, so that the annular retaining wall 301 can support the second substrate 30. In addition, the annular retaining wall 301 can also prevent the occurrence of cross-color between two adjacent sub-pixels 201, thereby greatly improving the display quality of the display panel 100.

[0098] See also Fig.12 , Fig.12 Flow chart of a method for preparing an array substrate provided in one embodiment of the present application. It is understandable that the present application provides different array substrate 10 structures in the above embodiments. For the convenience of detailed description, the following preparation method mainly uses the first embodiment, i.e. Figure 1 , Figure 2 and Figure 3 The preparation method of the provided array substrate 10 is described below.

[0099] The present application also provides a method for preparing an array substrate, comprising the following steps:

[0100] Step S1: Disposing a driving circuit layer on one side of a first substrate.

[0101] For details, see Fig.13a and Fig.13b , Fig.13a A top view of the structure of step S1 in the array substrate preparation method provided in this application; Fig.13b for Fig.13a Sectional view along line DD;

[0102] Fig.13c A top view of the first substrate of step S1 in the array substrate preparation method provided in the present application. The first substrate 1 has a plurality of sub-pixel regions 101 arranged in an array. The sub-pixel region 101 includes a main light-transmitting region 1011 and an auxiliary light-transmitting region 1012 arranged at intervals, and an opaque region 1013 located between the main light-transmitting region 1011 and the auxiliary light-transmitting region 1012; the main light-transmitting region 1011 and the auxiliary light-transmitting region 1012 are used to set sub-pixels 201. The driving circuit layer 2 is arranged on one side of the first substrate 1, and the driving circuit layer 2 includes a plurality of sub-pixels 201, and each sub-pixel 201 is arranged corresponding to a sub-pixel region 101. The sub-pixel 201 includes a main pixel electrode 2011, an auxiliary pixel electrode 2012, a first thin film transistor, and a second thin film transistor. Among them, the main pixel electrode 2011 is located in the main light-transmitting area 1011; the auxiliary pixel electrode 2012 is located in the auxiliary light-transmitting area 1012; the first thin film transistor is located in the opaque area 1013 and is electrically connected to the main pixel electrode 2011; the second thin film transistor is located in the opaque area 1013 and is electrically connected to the auxiliary pixel electrode 2012. In a specific embodiment, the sub-pixel 201 can be a sub-pixel 201 that emits red light, a sub-pixel 201 that emits blue light, or a sub-pixel 201 that emits green light, and the present application does not make specific limitations on this. Specifically in this embodiment, the sub-pixels 201 are arranged in sequence, mainly taking three different sub-pixels 201 including a sub-pixel 201 that can emit red light, a sub-pixel 201 that can emit blue light, and a sub-pixel 201 that can emit green light as an example.

[0103] Step S2: a spacer photoresist is disposed on a side of the driving circuit layer away from the first substrate, and the spacer photoresist is baked and cooled at a preset temperature.

[0104] For details, see Fig.14 , Fig.14 For Fig.13b A certain amount of spacer photoresist G is coated on the side of the driving circuit layer 2 away from the first substrate 1, and is baked at a preset temperature for a preset time and then cooled to room temperature, for example, it can be pre-baked at 100-150°C for 90-100s.

[0105] Step S3: exposing, developing, baking and cooling the spacer photoresist under a patterning process to obtain a supporting layer.

[0106] For details, see Fig.15 , Fig.15 For Fig.14 The structural diagram of step S3 is based on the above. Wherein, exposure is performed under a photomask. Specifically, 35-45 mj / cm 2 Expose. After exposure, use KOH developer to perform spray development to obtain a patterned spacer photoresist (not shown). Specifically, 0.035-0.045% KOH developer can be used for spray development, and finally the patterned spacer photoresist is baked at 200-250°C for about half an hour, and the support layer 3 is obtained after cooling. Specifically, the height of the support layer 3 is 1.2um-1.5um. The support layer 3 includes a plurality of annular retaining walls 301, and the plurality of annular retaining walls 301 are arranged in a one-to-one correspondence with the plurality of sub-pixel areas 101. Specifically, the annular retaining wall 301 is arranged at the boundary of the sub-pixel area 101 and is arranged around the sub-pixel 201. The annular retaining wall 301 arranged in this way can be used to prevent cross-color from occurring between two adjacent sub-pixels 201.

[0107] The array substrate 10 provided in the first embodiment can be formed through the above preparation steps. The annular retaining wall 301 is provided, and the annular retaining wall 301 is opaque, which can prevent the occurrence of cross-color between two adjacent sub-pixels 201, thereby greatly improving the display quality of the display panel 100.

[0108] It will be apparent to those skilled in the art that the present application is not limited to the details of the exemplary embodiments described above, and that the present application can be implemented in other specific forms without departing from the spirit or essential features of the present application. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the present application is defined by the appended claims rather than the above description, and it is intended that all changes within the meaning and scope of the equivalent elements of the claims be included in the present application. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0109] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A display panel, characterized in that: include a first substrate; The first substrate comprises: A first substrate having a plurality of sub-pixel regions arranged in an array; A driving circuit layer is arranged on one side of the first substrate, and includes a plurality of sub-pixels; each of the sub-pixels is arranged corresponding to one of the sub-pixel regions; A support layer is arranged on a side of the driving circuit layer away from the first substrate; the support layer comprises a plurality of annular retaining walls, and the plurality of annular retaining walls are arranged one-to-one with the plurality of sub-pixel areas; the annular retaining walls are arranged at the boundary of the sub-pixel area and surround the sub-pixel; the annular retaining walls are configured to prevent color crosstalk between two adjacent sub-pixels; A second substrate is disposed on a side of the support layer away from the first substrate; The liquid crystal layer comprises a plurality of liquid crystal units; each of the liquid crystal units is correspondingly arranged in one of the annular retaining walls; the liquid crystal layer comprises a ferroelectric liquid crystal material capable of achieving color filtering; The annular retaining wall corresponding to two adjacent sub-pixel areas has a common side wall, the common side wall has a first notch connecting the two adjacent sub-pixel areas, and a convex strip is arranged on the second substrate, and the convex strip is embedded in the first notch.

2. The display panel according to claim 1, characterized in that: The second base plate abuts against an end of the annular retaining wall away from the first substrate.

3. The display panel according to claim 1, characterized in that: The height of the convex strip is smaller than the height of the first notch.

4. The display panel according to claim 3, characterized in that: The end of the convex strip away from the second substrate is spaced apart from the driving circuit layer of the first substrate, and one end of the annular retaining wall away from the driving circuit layer is in contact with the second substrate.

5. The display panel according to claim 1, characterized in that: The height of the annular retaining wall is 1.2-1.5um.

6. The display panel according to claim 1, characterized in that: The sub-pixel region includes a main light-transmitting region and an auxiliary light-transmitting region that are spaced apart, and an opaque region between the main light-transmitting region and the auxiliary light-transmitting region; the sub-pixel includes: A main pixel electrode, located in the main light-transmitting area; A secondary pixel electrode, located in the secondary light-transmitting area; A first thin film transistor, located in the opaque area and electrically connected to the main pixel electrode; The second thin film transistor is located in the opaque area and is electrically connected to the auxiliary pixel electrode.

7. The display panel according to claim 6, characterized in that: The array substrate further includes: A light shielding layer, arranged on a side of the driving circuit layer away from the first substrate, comprising a plurality of sub-light shielding layers; Wherein, the sub-light-shielding layer is arranged in the annular retaining wall, and one sub-light-shielding layer is arranged in each light-proof area.

8. The display panel according to claim 7, characterized in that: The annular retaining wall comprises a first side wall and a second side wall arranged opposite to each other along a first direction, and a third side wall and a fourth side wall arranged opposite to each other along a second direction; the main light-transmitting area, the light-impermeable area and the auxiliary light-transmitting area are arranged in sequence along the first direction, and the second direction intersects the first direction; wherein, There is a gap between the sub-light shielding layer and the third side wall; and / or, There is a gap between the sub-light shielding layer and the fourth side wall; and / or, The sub-light-shielding layer has a second gap connecting the main light-transmitting area and the auxiliary light-transmitting area.

9. The display panel according to claim 6, characterized in that: The width of the gap is 0.5um-1.5um.

10. The display panel according to claim 6, characterized in that: The thickness of the sub-light-shielding layer is smaller than the height of the annular retaining wall.

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