A method, apparatus, storage medium, and electronic device for mapping qubits.

Abstract

This invention discloses a qubit mapping method, apparatus, storage medium, and electronic device, applied in the field of quantum computing technology. The method includes: constructing a quadratic unconstrained binary optimization model for qubit mapping based on the coupling relationship between logical qubits and the topological relationship between physical qubits, where logical qubits are qubits in a quantum circuit and physical qubits are qubits in a quantum chip, with the quantum circuit running on the quantum chip; solving for the qubit mapping scheme that minimizes the quadratic unconstrained binary optimization model; and mapping logical qubits to physical qubits based on this mapping scheme. By using the quadratic unconstrained binary optimization model, the optimal mapping method for each qubit is obtained in a shorter time, effectively reducing the number of SWAP gates required for qubit mapping, reducing circuit depth, and improving execution speed and overall fidelity.

Description

Technical Field

[0001] This invention belongs to the field of quantum computing technology, and in particular to a quantum bit mapping method, apparatus, storage medium and electronic device. Background Technology

[0002] A quantum computer is a physical device that performs high-speed mathematical and logical operations, stores and processes quantum information, following the laws of quantum mechanics. It requires qubits (qubits) as its basic units, and a truly practical quantum computer must have millions of qubits to solve practical problems. A quantum circuit, also known as a quantum logic circuit, represents a circuit that operates on qubits in an abstract sense. Quantum algorithms, described by quantum circuit models, can manipulate a quantum computer to process input states and output specific measurements. Quantum computers, when running quantum algorithms, possess a significantly higher efficiency in processing mathematical problems than ordinary computers, thus becoming a key technology under research.

[0003] Current quantum computers have hardware limitations and do not satisfy the requirement of fully connected qubits (i.e., any two qubits are connected). Due to this limitation, two-qubit quantum operations can only be performed on a pair of connected qubits. In contrast, quantum circuits are hardware-independent. When constructing quantum circuit models to implement quantum algorithms, quantum logic gates can be implemented on any two logical qubits.

[0004] Therefore, when mapping logical qubits to physical qubits, the quantum states of the two qubits involved need to be exchanged using SWAP gates, allowing the quantum logic gates in the quantum circuit to be executed. Different qubit mapping schemes require different numbers of SWAP gates, thus affecting the computational accuracy and fidelity of the quantum circuit. Therefore, reducing the number of SWAP gates required for qubit mapping, thereby reducing the depth of the quantum circuit, is a problem that needs to be solved. Summary of the Invention

[0005] The purpose of this invention is to provide a quantum bit mapping method, apparatus, storage medium, and electronic device, thereby reducing the number of SWAP gates required for quantum bit mapping and reducing the quantum circuit depth.

[0006] One embodiment of the present invention provides a quantum bit mapping method, the method comprising:

[0007] Based on the coupling relationship between logical qubits and the topological relationship between physical qubits, a quadratic unconstrained binary optimization model for qubit mapping is constructed. The logical qubits are qubits in quantum circuits, the physical qubits are qubits in quantum chips, and the quantum circuits operate on the quantum chips.

[0008] The qubit mapping scheme when the quadratic unconstrained binary optimization model reaches its minimum value is obtained by solving the problem, and the logical qubit is mapped to the physical qubit based on the mapping scheme.

[0009] Optionally, the construction of a quadratic unconstrained binary optimization model for qubit mapping based on the coupling relationship between logical qubits and the topological relationship between physical qubits includes:

[0010] Based on the coupling relationship between the logical qubits and the topological relationship between the physical qubits, a secondary allocation model for qubit mapping is constructed;

[0011] Determine the constraints of the quadratic allocation model of the qubit mapping, and transform the constraints into quadratic penalty terms;

[0012] By adding the quadratic penalty term to the quadratic allocation model, a quadratic unconstrained binary optimization model for the qubit mapping is obtained.

[0013] Optionally, the construction of a secondary allocation model for qubit mapping based on the coupling relationship between the logical qubits and the topological relationship between the physical qubits includes:

[0014] Based on the coupling relationship between the logical qubits, the coupling strength matrix of the logical qubits is determined, and the elements in the coupling strength matrix represent the number of two-qubit gates between the corresponding logical qubits;

[0015] Based on the topological relationship between the physical qubits, a distance matrix for the physical qubits is determined, where each element in the distance matrix represents the shortest distance between the corresponding physical qubits to establish an interaction path.

[0016] The target matrix is ​​obtained by calculating the direct product of the coupling strength matrix and the distance matrix;

[0017] The elements in the target matrix are used as coefficients for each qubit mapping method. The minimum value of the quadratic objective function of the qubit mapping is calculated, which is used as the quadratic allocation model of the qubit mapping.

[0018] Optionally, before constructing the secondary allocation model of the qubit mapping based on the coupling relationship between the logical qubits and the topological relationship between the physical qubits, the method further includes:

[0019] The multi-qubit gate in the input quantum circuit is converted into a single-qubit gate and / or a two-qubit gate.

[0020] Optionally, before constructing the quadratic unconstrained binary optimization model of the qubit mapping based on the coupling relationship between logical qubits and the topological relationship between physical qubits, the method further includes:

[0021] Physical qubits in the quantum chip with a computational error rate lower than a preset error rate are identified, and physical qubits with a coherence time lower than a first threshold or a quantum gate operation fidelity lower than a second threshold, along with their adjacent physical qubits, are used as the boundaries of a qubit concentration region. The physical qubits included in the qubit concentration region are used to map logical qubits in the quantum circuit.

[0022] Optionally, the method further includes:

[0023] The physical qubits in the target region of the quantum chip are determined. The number of physical qubits is not less than the number of logical qubits in the quantum circuit, and is less than or equal to the number of physical qubits in other regions of the quantum chip.

[0024] Optionally, the solution for obtaining the qubit mapping scheme when the quadratic unconstrained binary optimization model reaches its minimum includes:

[0025] The minimum value of the quadratic unconstrained binary optimization model is calculated, and the qubit mapping scheme when the quadratic unconstrained binary optimization model reaches its minimum value is determined. The minimum value is obtained by annealing computer or quantum computing virtual machine.

[0026] Optionally, after mapping the logical qubit to the physical qubit based on the mapping scheme, the method further includes:

[0027] According to the execution order of the two-qubit gates in the quantum circuit, it is determined in turn whether the set of physical qubits mapped by the logical qubits acted by each two-qubit gate is connected.

[0028] If they are not connected, a SWAP gate operation is performed between the set of physical qubits to swap the quantum state of one physical qubit to the target physical qubit, and the target physical qubit is connected to the other physical qubit.

[0029] The operation of the dual-qubit gate instruction is performed on the target physical qubit and another physical qubit;

[0030] The target physical qubit and the quantum state of one of the physical qubits are exchanged through a SWAP gate.

[0031] Another embodiment of the present invention provides a quantum bit mapping device, the device comprising:

[0032] The model building module is used to construct a quadratic unconstrained binary optimization model of qubit mapping based on the coupling relationship between logical qubits and the topological relationship between physical qubits. The logical qubits are qubits in quantum circuits, the physical qubits are qubits in quantum chips, and the quantum circuits run on the quantum chips.

[0033] The qubit mapping module is used to solve for the qubit mapping scheme when the quadratic unconstrained binary optimization model reaches its minimum value, and to map the logical qubits to the physical qubits based on the mapping scheme.

[0034] Another embodiment of the present invention provides a storage medium storing a computer program, wherein the computer program is configured to execute the method described in any of the preceding claims when running.

[0035] Another embodiment of the present invention provides an electronic device including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the method described in any of the preceding claims.

[0036] Compared with existing technologies, the present invention provides a quantum bit mapping method, apparatus, storage medium, and electronic device that can construct a quadratic unconstrained binary optimization model for quantum bit mapping based on the coupling relationship between logical quantum bits and the topological relationship between physical quantum bits. The logical quantum bits are quantum bits in a quantum circuit, and the physical quantum bits are quantum bits in a quantum chip. The quantum circuit operates on the quantum chip. Then, the quantum bit mapping scheme when the quadratic unconstrained binary optimization model reaches its minimum value can be solved, and the logical quantum bits can be mapped to the physical quantum bits based on the mapping scheme.

[0037] This qubit mapping method comprehensively considers the coupling relationship between logical qubits and the topological relationship between physical qubits. Through a quadratic unconstrained binary optimization model, the optimal mapping method for each qubit can be obtained in a short time, thus obtaining the mapping scheme of logical qubits in the entire quantum circuit. This effectively reduces the number of SWAP gates required for qubit mapping, reduces the circuit depth, and improves the execution speed and overall fidelity. Attached Figure Description

[0038] Figure 1 A network block diagram of a quantum bit mapping system provided in an embodiment of the present invention;

[0039] Figure 2 A flowchart illustrating a quantum bit mapping method provided in an embodiment of the present invention;

[0040] Figure 3 A schematic diagram of a quantum circuit provided for an embodiment of the present invention;

[0041] Figure 4 This is a schematic diagram of the structure of a quantum bit mapping device provided in an embodiment of the present invention;

[0042] Figure 5 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0043] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0044] Figure 1 This is a network block diagram of a qubit mapping system provided in an embodiment of the present invention. The qubit mapping system may include a network 110, a server 120, a wireless device 130, a client 140, a storage 150, a classical computing unit 160, a quantum computing unit 170, and may also include additional memory, a classical processor, a quantum processor, and other devices not shown.

[0045] Network 110 is a medium used to provide communication links between various devices and computers connected together within a quantum bit mapping system, including but not limited to the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof. The connection method can be wired, wireless communication links, or fiber optic cables.

[0046] Server 120, wireless device 130, and client 140 are conventional data processing systems that may contain data and application programs or software tools that perform conventional computational processes. Client 140 may be a personal computer or a network computer, so the data may also be provided by server 120. Wireless device 130 may be a smartphone, tablet, laptop, smart wearable device, etc. Storage unit 150 may include database 151, which can be configured to store data such as qubit parameters, quantum logic gate parameters, quantum circuits, and quantum programs.

[0047] The classical computing unit 160 (quantum computing unit 170) may include a classical processor 161 (quantum processor 171) for processing classical data (quantum data) and a memory 162 (memory 172) for storing classical data (quantum data). The classical data (quantum data) may be a boot file, an operating system image, and an application program 163 (application program 173). The application program 163 (application program 173) may be used to implement a quantum algorithm compiled by the quantum bit mapping method provided in the embodiments of the present invention.

[0048] Any data or information stored or generated in the classical computing unit 160 (quantum computing unit 170) can also be configured to be stored or generated in another classical (quantum) processing system in a similar manner, and any application executed therein can also be configured to be executed in another classical (quantum) processing system in a similar manner.

[0049] It should be noted that a true quantum computer has a hybrid structure, which includes at least... Figure 1 The system consists of two main parts: the classical computing unit 160, which is responsible for performing classical calculations and control; and the quantum computing unit 170, which is responsible for running quantum programs to achieve quantum computing.

[0050] The aforementioned classical computing unit 160 and quantum computing unit 170 can be integrated into a single device or distributed across two different devices. For example, a first device including the classical computing unit 160 runs a classical computer operating system, providing quantum application development tools and services, as well as the storage and network services required for quantum applications. Users develop quantum programs using the quantum application development tools and services on the second device, and send these quantum programs to a second device including the quantum computing unit 170 via the network services. The second device runs a quantum computer operating system, which parses and compiles the quantum program's code into instructions that the quantum processor 170 can recognize and execute. The quantum processor 170 then implements the quantum algorithm corresponding to the quantum program based on these instructions.

[0051] The computing units of the classic processor 161 within the classic computing unit 160 are based on CMOS transistors on a silicon chip. These computing units are not limited by time or coherence; that is, they are available at any time without time constraints. Furthermore, the number of such computing units in a silicon chip is sufficient; currently, a single classic processor 161 contains tens of thousands of computing units. Given this sufficient number of computing units and the fixed selectable computing logic of the CMOS transistors (e.g., AND logic), computational performance is achieved by combining a large number of CMOS transistors with a limited set of logic functions during operation.

[0052] In the quantum computing unit 170, the basic computing unit of the quantum processor 171 is the qubit. The input of a qubit is limited by coherence and coherence time; that is, a qubit is limited by its available usage time and is not always readily available. Making full use of qubits within their available usage time is a key challenge in quantum computing. Furthermore, the number of qubits in a quantum computer is one of the representative indicators of its performance. Each qubit performs computational functions through on-demand configured logical functions. Given the limited number of qubits and the diverse logical functions available in quantum computing, such as Hadamard gates (H gates), Pauli-X gates (X gates), Pauli-Y gates (Y gates), Pauli-Z gates (Z gates), X gates, RY gates, RZ gates, CNOT gates, CR gates, iSWAP gates, Tofoli gates, etc., quantum computing requires combining a limited number of qubits with diverse logical function combinations to achieve computational effects.

[0053] Based on these differences, the design of classical logic functions applied to CMOS transistors and the design of quantum logic functions applied to qubits are significantly and fundamentally different. The design of classical logic functions applied to CMOS transistors does not need to consider the individuality of CMOS transistors. For example, the representation of a CMOS transistor in a silicon chip is its individual identifier, location, and usable time of each CMOS transistor. Therefore, classical algorithms composed of classical logic functions only express the operational relationship of the algorithm, not the algorithm's dependence on individual CMOS transistors.

[0054] Quantum logic functions applied to qubits need to consider the individuality of each qubit, such as its position within the quantum chip, its relationship with surrounding qubits, and the duration of its usable time. Therefore, quantum algorithms composed of quantum logic functions not only express the computational relationships within the algorithm but also its dependence on the individual qubits.

[0055] For example:

[0056] Quantum Algorithm 1: H1, H2, CNOT(1,3), H3, CNOT(2,3);

[0057] Quantum Algorithm 2: H1, H2, CNOT(1,2), H3, CNOT(2,3);

[0058] Where 1 / 2 / 3 represent three sequentially connected qubits Q1, Q2, Q3 or interconnected qubits Q1, Q2, Q3, respectively;

[0059] An exemplary explanation of how quantum algorithms are affected by the coherence time of qubits is as follows:

[0060] Define the execution time of a single-qubit gate as t, and the execution time of a two-qubit gate acting on adjacent qubits as 2t; then:

[0061] When Q1, Q2, and Q3 are interconnected, the computation of Quantum Algorithm 1 requires 6t, which is divided into 4 time periods. The duration of each time period is t, 2t, t, and 2t, respectively. The operations performed in each time period are: H1, H2; CNOT(1,3); H3; CNOT(2,3);

[0062] The computation of Quantum Algorithm 2 requires 5t, which is divided into 3 time periods. The duration of each time period is t, 2t, and 2t respectively. The operations performed in each time period are: H1, H2, H3; CNOT(1,2); CNOT(2,3);

[0063] When Q1, Q2, and Q3 are connected sequentially, Quantum Algorithm 1 needs to be equivalent to: H1, H2; swap(1,2), CNOT(2,3), swap(1,2); H3; CNOT(2,3). The computation of the equivalent Quantum Algorithm 1 requires 10t, divided into 4 time periods, with each time period requiring durations of t, 6t, t, and 2t respectively. The operations performed in each time period are: H1, H2; swap(1,2), CNOT(2,3), swap(1,2); H3; CNOT(2,3).

[0064] A quantum chip can include qubits and channels for controlling them. Quantum logic gates are implemented using analog signals. Different combinations of analog signals are applied to the qubits through these channels, thereby creating quantum circuits with different functions to process data. Therefore, the design of quantum logic functions in the qubits (including the design of whether qubits are used and the design of the efficiency of each qubit) is crucial for improving the computational performance of quantum computers and requires special design. This is the unique characteristic of quantum algorithms based on quantum logic functions, and it is fundamentally and significantly different from classical algorithms based on classical logic functions. The aforementioned design considerations for qubits are technical problems that ordinary computing devices do not need to consider or address.

[0065] This invention proposes a quantum bit mapping method, apparatus, storage medium, and electronic device, aiming to reduce the number of SWAP gates required for quantum bit mapping and reduce the quantum circuit depth.

[0066] See Figure 2 , Figure 2 A quantum bit mapping method provided in this embodiment of the invention includes the following steps:

[0067] Step 201: Based on the coupling relationship between logical qubits and the topological relationship between physical qubits, construct a quadratic unconstrained binary optimization model for qubit mapping;

[0068] Wherein, the logical qubit is a qubit in a quantum circuit, the physical qubit is a qubit in a quantum chip, and the quantum circuit operates on the quantum chip.

[0069] Specifically, in this embodiment of the invention, the qubit mapping is a mapping from logical qubits to physical qubits. Due to hardware limitations in current quantum computers, fully connected qubits are not guaranteed; full connectivity means that any two physical qubits are connected. Because of these qubit connectivity limitations, two-qubit quantum operations in a quantum chip can only be performed on a pair of connected physical qubits. Quantum circuits, however, are hardware-independent; when constructing a quantum circuit model to implement quantum algorithms, quantum logic gates can be implemented on any two logical qubits.

[0070] In order for quantum circuits to run on quantum chips, when mapping logical qubits to physical qubits, it is usually necessary to exchange the quantum states of the two qubits they operate on using SWAP gates, so that the quantum logic gates in the quantum circuit can be executed. Therefore, the mapping of qubits cannot be arbitrary, but requires a certain strategy. A good mapping strategy can reduce the error rate of quantum program execution and speed up the execution of quantum programs.

[0071] To obtain the optimal qubit mapping scheme, the coupling relationship between logical qubits in the quantum circuit must first be considered. This coupling relationship represents the interaction frequency of quantum logic gate operations between any two logical qubits. However, quantum chips are limited by manufacturing processes and suffer from single-gate errors, double-gate errors, testing errors, crosstalk errors, etc. Considering the cumulative effect of these errors, the higher the interaction frequency between logical qubits, the more they need to be mapped to closer neighboring physical qubits during mapping. This reduces problems such as increased circuit fidelity and computational error rate caused by frequent swap operations.

[0072] Similarly, the topological relationships between physical qubits in a quantum chip must also be considered. In most current quantum chips, the topological relationships of the physical qubits are fixed after manufacturing. For example, if the physical qubits in a superconducting quantum chip are coupled in a near-neighbor manner, then when performing a two-qubit gate operation between two non-adjacent physical qubits, a SWAP gate operation is required to exchange the quantum states of the physical qubits. This topological relationship can represent the number of SWAP gates required to perform a two-qubit gate operation between any two physical qubits. In the entire quantum circuit mapping process, the fewer SWAP gates inserted, the lower the circuit depth, and the higher the execution speed and overall fidelity.

[0073] The method provided in this invention aims to comprehensively consider the influence of the coupling relationship between logical qubits and the topological relationship between physical qubits on qubit mapping, find the optimal qubit mapping scheme, and thus complete the qubit mapping, enabling the quantum circuit to run on a quantum chip. Therefore, based on the aforementioned coupling relationship between logical qubits and the topological relationship between physical qubits, a quadratic unconstrained binary optimization (QUBO) model for qubit mapping can be constructed, and the optimal solution can be obtained through this QUBO model.

[0074] The QUBO model is currently the most widely used optimization model in the field of quantum computing, capable of solving a wide variety of combinatorial optimization problems. The QUBO model is defined as follows:

[0075] max / min y=x t Qx

[0076] Here, x is a column vector consisting of binary variables (0,1). t Q is the transpose of vector x, a row vector consisting of binary variables (0,1), and Q is a symmetric or upper triangular matrix.

[0077] In specific application scenarios, the QUBO model can obtain the optimal solution to the combinatorial optimization problem by solving for the maximum or minimum value of the product of the vector and matrix mentioned above. In the scheme provided by the embodiments of the present invention, mapping a logical qubit to a physical qubit can be defined as "1" in a binary variable, and correspondingly, not mapping a logical qubit to a physical qubit can be defined as "0" in a binary variable. Then, the variable x can be composed of multiple binary variables (0,1), each binary variable representing the mapping method of each qubit, thereby obtaining a complete qubit mapping scheme.

[0078] Therefore, based on the coupling relationship between qubits and the topological relationship between physical qubits, the Q matrix in the QUBO model can be constructed so that the Q matrix can simultaneously reflect the interaction frequency of the quantum logic gate operation of the logical qubits and the influence of the number of SWAP gates that need to be inserted when the physical qubits perform two-qubit gate operations on the qubit mapping scheme. Then, by solving the binary variable x when the QUBO model reaches its minimum value, the optimal qubit mapping scheme can be obtained.

[0079] As one embodiment of the present invention, the above-described quadratic unconstrained binary optimization model for qubit mapping based on the coupling relationship between logical qubits and the topological relationship between physical qubits may include the following steps:

[0080] Step 301: Based on the coupling relationship between the logical qubits and the topological relationship between the physical qubits, construct a secondary allocation model for qubit mapping.

[0081] The Quadratic Assignment Problem (QAP) aims to assign a set of facilities to a set of locations in order to minimize the total assignment cost. The assignment cost for each pair of facilities is a function of the flow between the facilities and the distance between the facility locations.

[0082] Similar to the device point allocation problem, qubit mapping can be understood as assigning logical qubits to physical qubits. The number of physical qubits must be no less than the number of logical qubits, and the position of each physical qubit is unique and definite. Accordingly, the mapping cost for each pair of logical qubits is a function of the coupling relationship between the logical qubits and the topological relationship between the physical qubits.

[0083] For example, there exist logical qubits i,j∈{1,2,…,n} and physical qubits u,b∈{1,2,…,N}, satisfying N≥n, C ij This represents the coupling relationship between logical qubits i and j. This represents the mapping of logical bit i to physical quantum bit. superior, This represents the mapping of logical bit j to physical quantum bit. Above, at this time Let the topological relationship between physical qubits u and v be represented, then the mapping cost of the qubit mapping can be expressed as:

[0084]

[0085] Therefore, by comprehensively considering the mapping cost of each pair of logical qubits, a secondary allocation model for qubit mapping can be constructed. It is understandable that the mapping cost in this secondary allocation model is positively correlated with the elements of the Q-matrix in the QUBO model.

[0086] As one embodiment of the present invention, the above-described secondary allocation model for qubit mapping based on the coupling relationship between the logical qubits and the topological relationship between the physical qubits may include the following steps:

[0087] Step 401: Based on the coupling relationship between the logical qubits, determine the coupling strength matrix of the logical qubits, where the elements in the coupling strength matrix represent the number of two-qubit gates between the corresponding logical qubits.

[0088] Specifically, a quantum circuit includes logical qubits and quantum logic gates. Quantum logic gates can be classified into single-qubit gates, two-qubit gates, and three-qubit gates. In one implementation, a three-qubit gate can be transformed into a combination of multiple two-qubit gates and / or single-qubit gates. In this case, the quantum logic gates in the quantum circuit only include single-qubit and two-qubit gates. A single-qubit gate operates on a single qubit. After being mapped to a physical qubit, performing an operation on a single qubit does not require interaction with other physical qubits. Only operations corresponding to two-qubit gates require interaction between two physical qubits. Therefore, the number of two-qubit gates in a quantum circuit can reflect the coupling relationship between logical qubits.

[0089] By analyzing the coupling relationships between logical qubits in a quantum circuit, a coupling strength matrix H of the following form can be established, where each element represents the number of two-qubit gates between the corresponding logical qubits:

[0090]

[0091] For example, "8" in the matrix indicates that 8 two-qubit gates operate between the first and second logical qubits in this quantum circuit; similarly, "15" indicates that 15 two-qubit gates operate between the first and third logical qubits. Clearly, this coupling strength matrix is ​​a symmetric matrix.

[0092] As one embodiment of the present invention, before constructing the secondary allocation model of qubit mapping based on the coupling relationship between the logical qubits and the topological relationship between the physical qubits, the method may further include:

[0093] The multi-qubit gate in the input quantum circuit is converted into a single-qubit gate and / or a two-qubit gate.

[0094] Specifically, users can input quantum circuits through electronic devices connected to a quantum computer. The connection can be wired or wireless, and the electronic device can be a classical computer, cloud computing platform, etc., without specific limitations. Users can build quantum circuits through a graphical user interface (GUI) and input them into the electronic device. When building quantum circuits, users can add quantum logic gates to any two logical qubits without considering the topological relationship between the corresponding physical qubits.

[0095] Furthermore, this electronic device can perform quantum gate optimization on the input quantum circuit, transforming multi-qubit gates into combinations of single-qubit and / or two-qubit gates. In one embodiment, the electronic device can also correct errors in the quantum circuit; it can merge, cancel, or eliminate quantum logic gates, for example, merging two consecutive Hadamard gates into a single Rz gate; it can also rearrange the order of quantum logic gates, etc., without specific limitations.

[0096] For example, the transformed quantum circuit can be like Figure 3 As shown, the quantum circuit includes four logical qubits, q1, q2, q3, and q4, and also includes five two-qubit gates. By analyzing the number of two-qubit gates between the logical qubits in the quantum circuit, the following coupling strength matrix can be established:

[0097]

[0098] Step 402: Based on the topological relationship between the physical qubits, determine the distance matrix of the physical qubits, where the elements in the distance matrix represent the shortest distance between the corresponding physical qubits to establish an interaction path.

[0099] Specifically, on the quantum chip on which this quantum circuit operates, when two physical qubits in one group are connected, the corresponding element in the distance matrix can be represented as "0", which indicates that the two physical qubits are connected; when a group of physical qubits are not connected, the aforementioned shortest distance can be the minimum number of SWAP gates required to establish an interaction path between the two physical qubits.

[0100] By analyzing the topological relationships between physical qubits in a quantum chip, a distance matrix D of the following form can be established, where each element represents the minimum number of SWAP gates required to establish an interaction path between the corresponding physical qubits:

[0101]

[0102] Clearly, this distance matrix is ​​also a symmetric matrix.

[0103] For example, if the topology of a physical qubit in a quantum chip is a one-dimensional linear structure containing six physical qubits, then at least four SWAP gate operations are required to establish an interaction path between the two qubits. Therefore, the corresponding element in the distance matrix could be "4". Similarly, in other topologies of physical qubits, there may be multiple paths between two physical qubits to establish an interaction path. In this case, the path with the fewest SWAP gates can be chosen as the quantum state exchange path in subsequent quantum computing. The number of SWAP gates in this path is the element in the aforementioned distance matrix.

[0104] Step 403: Calculate the direct product of the coupling strength matrix and the distance matrix to obtain the target matrix.

[0105] Specifically, the target matrix is ​​the matrix obtained by performing a direct product operation on the coupling strength matrix and the distance matrix. For example, this operation can be represented based on the coupling strength matrix H and the distance matrix D mentioned above as follows:

[0106]

[0107] Each element in the target matrix is ​​obtained by multiplying the elements in the coupling strength matrix H and the distance matrix D, which can comprehensively consider the influence of the coupling relationship between logical qubits and the topological relationship between physical qubits on the qubit mapping.

[0108] Step 404: Use the elements in the target matrix as coefficients for each qubit mapping method, calculate the minimum value of the quadratic objective function of the qubit mapping, and use it as the quadratic allocation model of the qubit mapping.

[0109] Specifically, the mapping method from each logical qubit to a physical qubit can be defined, and a binary variable x can be introduced. iu and x jv In the quadratic allocation model of qubit mapping, the aforementioned binary variable x iu and x jv The value of x is either 0 or 1. iu This represents the mapping of logical bit i to physical quantum bit u, x. jv Let logical bit j be mapped to physical qubit v. Then, in this qubit mapping scheme, when logical bit i is mapped to physical qubit u, x... iu=1, otherwise 0; similarly, when logical bit j is mapped to physical quantum bit v, x jv =1, otherwise 0.

[0110] For example, in the process of mapping 3 logical qubits to 3 physical qubits as described above, the qubit mapping scheme in the quadratic allocation problem of qubit mapping is (x 11 x 12 x 13 x 21 x 22 x 23 x 31 x 32 x 33 ), where x 11 This indicates that the first logical qubit is mapped to the first physical qubit, x. 12 This indicates that the first logical qubit is mapped to the second physical qubit, and so on, x 33 This indicates that the third logical qubit is mapped to the third physical qubit.

[0111] To more conveniently label the variables in the above qubit mapping scheme, the above qubit mapping scheme (x) can be labeled. 11 x 12 x 13 x 21 x 22 x 23 x 31 x 32 x 33 ) are relabeled as (x1, x2, x3, x4, x5, x6, x7, x8, x9).

[0112] Furthermore, the elements in the objective matrix can be used as coefficients for each qubit mapping method, and the minimum value of the quadratic objective function of the qubit mapping can be calculated as follows:

[0113] min x0=80x1x5+150x1x6+32x1x8+60x1x9+80x2x4+130x2x6+60x2x7+52x2x9+150x3x4+130x3x5+60x3x7+52x3x8+48x4x8+90x4x9+78x5x9+78x6x8

[0114] Using the above polynomial as a quadratic allocation model for qubit mapping, by solving for the minimum value of this polynomial, we can obtain the value of each variable x. iu The value in binary form of the variable is used to determine the mapping method from each logical qubit to the physical qubit in the qubit mapping scheme by judging whether the value of the variable is 0 or 1.

[0115] Step 302: Determine the constraints of the quadratic allocation model of the qubit mapping, and transform the constraints into quadratic penalty terms.

[0116] Specifically, in the above-mentioned quadratic allocation model of qubit mapping, the variables are subject to real constraints. This means that during the qubit mapping process, each logical qubit can only be mapped to one physical qubit; correspondingly, each physical qubit can only be mapped to one logical qubit. This real constraint can be expressed in binary variable equation form as follows:

[0117] x1 + x2 + x3 = 1

[0118] x4 + x5 + x6 = 1

[0119] x7 + x8 + x9 = 1

[0120] x1 + x4 + x7 = 1

[0121] x² + x⁵ + x⁸ = 1

[0122] x³ + x⁶ + x⁹ = 1

[0123] The QUBO model is an unconstrained optimization model, meaning that when creating a QUBO model, all the aforementioned constraints must be fully added to the Q matrix. As is known to those skilled in the art, the quadratic penalties for certain types of constraints are known, allowing a given constrained problem to be added to the QUBO model. For example, the quadratic penalties for some common constraints are shown in the table below:

[0124] Classical constraints Corresponding secondary punishment x+y≤1 P(xy) x+y≥1 P(1-x-y+xy) x+y=1 P(1-x-y+2xy) x≤y P(x-xy) <![CDATA[x1+x2+x3≤1]]> <![CDATA[P(x1x2+x1x3+x2x3)]]> x = y P(x+y-2xy)

[0125] It is important to note that all variables in the table are binary, and P is a positive scalar penalty value. This value must be chosen large enough to ensure that the penalty term can be used to represent classical constraints. In practical applications, the value of P is usually easy to specify when building a QUBO model, so no specific limitation is made in this embodiment of the invention.

[0126] Specifically, the classical constraint x1+x2+x3=1 can be transformed into a quadratic penalty term P(x1+x2+x3-1). 2 Similarly, the transformation of all the above real constraints can be completed to obtain the following quadratic penalty term:

[0127] P(x1+x2+x3-1) 2

[0128] P(x⁴ + x⁵ + x⁶ - 1) 2

[0129] P(x7+x8+x9-1) 2

[0130] P(x1+x4+x7-1) 2

[0131] P(x² + x⁵ + x⁸ - 1) 2

[0132] P(x³ + x⁶ + x⁹ - 1) 2

[0133] Step 303: Add the quadratic penalty term to the quadratic allocation model to obtain the quadratic unconstrained binary optimization model of the qubit mapping.

[0134] Specifically, in the process of mapping 3 logical qubits to 3 physical qubits, the aforementioned quadratic penalty term can be added to the quadratic allocation model, that is, all quadratic penalty terms can be added to the aforementioned polynomial x0, resulting in a polynomial of the following form:

[0135] min y=80x1x5+150x1x6+32x1x8+60x1x9+80x2x4+130x2x6+60x2x7+52x2x9+150x3 x4+130x3x5+60x3x7+52x3x8+48x4x8+90x4x9+78x5x9+78x6x8+P(x1+x2+x3-1) 2 +P(x4+x5+x6-1) 2 +P(x7+x8+x9-1) 2 +P(x1+x4+x7-1) 2 +P(x2+x5+x8-1) 2 +P(x3+x6+x9-1) 2

[0136] At this point, we can choose a penalty value P = 200 to transform the above quadratic allocation problem into a QUBO problem, where the additional constant is 1200. This yields the quadratic unconstrained binary optimization model for qubit mapping as follows:

[0137] min y = x t Qx

[0138] In the QUBO model, the variable x is in binary form, specifically as follows:

[0139] x=(x1,x2,x3,x4,x5,x6,x7,x8,x9)

[0140] The Q matrix has a size of 9×9, specifically:

[0141]

[0142] As one embodiment of the present invention, before constructing the quadratic unconstrained binary optimization model of qubit mapping based on the coupling relationship between logical qubits and the topological relationship between physical qubits, the above method may further include:

[0143] Physical qubits in the quantum chip with a computational error rate lower than a preset error rate are identified, and physical qubits with a coherence time lower than a first threshold or a quantum gate operation fidelity lower than a second threshold, along with their adjacent physical qubits, are used as the boundaries of a qubit concentration region. The physical qubits included in the qubit concentration region are used to map logical qubits in the quantum circuit.

[0144] Specifically, to improve the fidelity and computational accuracy of the quantum circuit, it is necessary to select high-performance physical qubits from the quantum chip as target mapping bits for the logical qubits in the quantum circuit. In one implementation, a quantum algorithm can be pre-set, and all physical qubits in the quantum chip can be controlled to repeatedly execute the quantum algorithm for a preset number of times. After each execution of the quantum algorithm, the state of each physical qubit can be measured and compared with the theoretical calculation result to obtain the computational error rate of each physical qubit. Then, physical qubits with a computational error rate not higher than the preset error rate can be eliminated; these eliminated physical qubits do not participate in subsequent qubit mapping and quantum computation processes.

[0145] Furthermore, a first threshold can be preset for the coherence time of physical qubits, and a second threshold can be preset for the fidelity of quantum gate operations. From physical qubits with a computational error rate lower than the preset error rate, physical qubits with a coherence time lower than the first threshold or a quantum gate operation fidelity lower than the second threshold can be selected. Since the performance of these physical qubits is not optimal, they can be omitted in the qubit mapping and quantum computing processes. Moreover, based on the topological structure between the physical qubits included in the quantum chip, the physical qubits adjacent to the aforementioned physical qubits can be determined, thus defining the aforementioned physical qubits and their adjacent physical qubits as the boundaries of the qubit concentration region.

[0146] Based on these boundaries, multiple qubit concentration regions can be divided in the quantum chip. The physical qubits included in the qubit concentration regions are used to map the logical qubits in the quantum circuit, while the physical qubits included in these boundaries are not used for subsequent qubit mapping and quantum computing processes. When exchanging the quantum states of physical qubits through SWAP gates, it is also possible to bypass the physical qubits on these boundaries.

[0147] As one embodiment of the present invention, the method may further include:

[0148] The physical qubits in the target region of the quantum chip are determined. The number of physical qubits is not less than the number of logical qubits in the quantum circuit, and is less than or equal to the number of physical qubits in other regions of the quantum chip.

[0149] Specifically, the quantum chip has been divided into multiple concentrated qubit regions using the method described above. The physical qubits within these regions exhibit excellent performance, long coherence times, and high quantum gate operation fidelity, making them suitable for qubit mapping and subsequent quantum computing. However, the number of physical qubits in each region varies. To ensure proper qubit mapping without wasting excessive physical qubits, a target region can first be defined within these regions. This target region should contain a number of physical qubits no less than the number of logical qubits in the quantum circuit, and less than or equal to the number of physical qubits in other regions of the quantum chip.

[0150] Furthermore, multiple neighboring physical qubits can be selected within the target region to map the logical qubits in the quantum circuit. This allows for a further reduction in the number of SWAP gates, and consequently, the depth of the quantum circuit, while satisfying qubit mapping requirements and avoiding waste of physical qubits.

[0151] Step 202: Solve for the qubit mapping scheme when the quadratic unconstrained binary optimization model reaches its minimum value, and map the logical qubit to the physical qubit based on the mapping scheme.

[0152] Specifically, the minimum value of the QUBO model can be solved in various ways, and the binary variable x when the QUBO model reaches its minimum value can be determined. By analyzing the binary numbers included in the variable x, the mapping method of each quantum bit can be obtained, and thus the quantum bit mapping scheme can be determined.

[0153] For example, in the QUBO model that maps 3 logical qubits to 3 physical qubits, the minimum value of the QUBO model can be solved. When x1 = x5 = x9 = 1 and all other variables are 0, y = -982, which is the minimum value. The corresponding qubit mapping scheme is: the first qubit is mapped to the first physical qubit; the second qubit is mapped to the second physical qubit; and the third qubit is mapped to the third physical qubit.

[0154] Therefore, based on this qubit mapping scheme, each logical qubit can be mapped to its corresponding physical qubit.

[0155] As one embodiment of the present invention, the quantum bit mapping scheme obtained by solving the above-mentioned quadratic unconstrained binary optimization model to obtain the minimum value can include:

[0156] Calculate the minimum value of the quadratic unconstrained binary optimization model, and determine the qubit mapping scheme when the quadratic unconstrained binary optimization model reaches its minimum value;

[0157] The minimum value is calculated using an annealing computer or a quantum computing virtual machine.

[0158] Specifically, an annealing computer is a computational method based on simulated annealing, used to solve optimization problems. Simulated annealing runs on classical computers and obtains approximate optimal solutions to combinatorial optimization problems by randomly generating initial solutions and performing multiple iterative optimizations. A quantum computing virtual machine is a software tool that simulates quantum computing operations. It can simulate qubits, quantum gate operations, quantum measurements, and even quantum error correction and noise simulation. Given the current immaturity and limited availability of quantum computing hardware, quantum computing virtual machines play a crucial role in the verification and development of quantum algorithms.

[0159] Solving the QUBO model, a classic combinatorial optimization problem, is computationally challenging when the size of the binary variable x to be solved is very large. Common solution methods for the QUBO model include Quadratic Programming (QP), Sequential Quadratic Programming (SQP), and the conjugate gradient method. Among these, QP and SQP methods solve the original convex optimization problem step by step through a series of quadratic programming problems. Their main idea is to transform the original problem into a series of quadratic programming problems, and then iteratively solve these quadratic programming problems to gradually approach the optimal solution of the original problem.

[0160] The conjugate gradient method is an iterative algorithm for solving systems of linear equations, applicable to specific unconstrained optimization problems. As a direct search method, it does not require calculating matrix inverses, thus enabling it to handle large-scale problems. It is commonly used to solve quadratic unconstrained bivariate optimization problems, and its execution steps typically include:

[0161] Initialize vector x0 and residual r0;

[0162] Calculate the search direction d in step i. i Calculate the search direction matrix D in the i-th step. i Calculate the search direction vector x in the i-th step. i ;

[0163] Update solution vector Update the residual Where α is the step size in the pre-set search direction;

[0164] Determine if the convergence condition is met. If it is, output the result; otherwise, continue iterating.

[0165] Understandably, as the scale of the QUBO model increases, the computational difficulty also gradually increases, requiring more time to perform calculations to ensure the accuracy of the results. The methods for solving the QUBO model described above are diverse; the use of an annealing computer or a quantum computing virtual machine is merely an example. Similarly, the methods for solving this type of problem are constantly being updated and optimized.

[0166] As one embodiment of the present invention, after mapping the logical qubit to the physical qubit based on the mapping scheme, the method may further include the following steps:

[0167] Step 501: Determine in sequence whether the set of physical qubits mapped by the logical qubits acted by each two-qubit gate in the quantum circuit is connected, according to the execution order of the two-qubit gates in the quantum circuit.

[0168] Specifically, after mapping logical qubits to physical qubits based on the solved mapping scheme, the operations corresponding to the qubit gates can be performed on the physical qubits according to the execution order of the qubit gates in the quantum circuit. The quantum logic gates in the quantum circuit optimized by quantum gates include only single-qubit gates and two-qubit gates. Since the physical qubits selected for qubit mapping all have excellent performance, the fidelity of quantum gate operations is high, and good computational performance and accuracy are achieved when performing operations indicated by single-qubit gates or two-qubit gates.

[0169] A single-qubit gate operates on only a single qubit and does not require the physical qubits to be interconnected. Therefore, the operation indicated by the single-qubit gate can be directly executed on a single physical qubit. In contrast, the physical qubits operating under a two-qubit gate must satisfy the condition of interconnection. Therefore, it is necessary to sequentially determine whether the set of physical qubits mapped to the logical qubits operating under each two-qubit gate is interconnected, according to the execution order of the two-qubit gates in the quantum circuit.

[0170] Step 502: If not connected, perform a SWAP gate operation between the set of physical qubits to swap the quantum state of one physical qubit to the target physical qubit, and the target physical qubit is connected to the other physical qubit.

[0171] Step 503: Perform the operation of the dual-qubit gate instruction on the target physical qubit and another physical qubit.

[0172] Specifically, if the set of physical qubits mapped by the logical qubits of the two-qubit gate are not connected, then the quantum state of one of the physical qubits needs to be swapped to the physical qubit adjacent to the other physical qubit through the SWAP gate operation. The adjacent physical qubit is connected to the other physical qubit.

[0173] In one implementation, when selecting a suitable path to swap the quantum state of one physical qubit to a physical qubit adjacent to another physical qubit, it is necessary to select the path that uses the fewest SWAP gates and that does not pass through the boundary of the qubit concentration region. This reduces the depth of the quantum circuit while ensuring computational accuracy, thereby improving execution speed and overall fidelity.

[0174] Since the target physical qubit is adjacent to and connected to another physical qubit, two-qubit gate instruction operations can be performed on both the target physical qubit and the other physical qubit. For example, in a superconducting quantum computer, the physical qubits are of Josephson junction structure. The quantum chip can include physical qubits and channels for controlling the physical qubits. Two-qubit gates are implemented using analog signals, and different combinations of analog signals are applied to the combined physical qubits through the channels controlling the physical qubits.

[0175] Correspondingly, if the set of physical qubits mapped by the logical qubits of the two-qubit gate are connected, the operation indicated by the two-qubit gate can be directly performed on the set of physical qubits.

[0176] Step 504: Exchange the quantum state of the target physical qubit and one of the physical qubits through a SWAP gate.

[0177] After executing the two-qubit gate instruction operation, the quantum states of the target physical qubit and the other physical qubit are quantum entangled. At this point, it is necessary to swap the quantum state of the target physical qubit with that of one of the aforementioned physical qubits. This can be done using a SWAP gate, following the reverse path of the SWAP operation described above, to swap the quantum states of the target physical qubit and the other physical qubit, thus completing the two-qubit gate operation on this set of physical qubits. Based on the above steps, the operations indicated by the single-qubit gate and the two-qubit gate in this quantum circuit can be executed separately, thereby running the quantum circuit and measuring the computational results.

[0178] In this embodiment, a QUBO model for qubit mapping is first constructed based on the coupling relationship between logical qubits and the topological relationship between physical qubits. Solving this QUBO model yields the optimal qubit mapping scheme, which is then used to map the logical qubits in the quantum circuit to the physical qubits in the quantum chip. Furthermore, following the execution order of the quantum logic gates in the quantum circuit, single-qubit gates and two-qubit gates are applied to the corresponding physical qubits to run the quantum circuit and obtain the computational results. This scheme effectively reduces the number of SWAP gates required for qubit mapping, decreases the circuit depth, and improves execution speed and overall fidelity.

[0179] See Figure 4 , Figure 4 A quantum bit mapping device is provided as an embodiment of the present invention, the device comprising:

[0180] The model building module 401 is used to construct a quadratic unconstrained binary optimization model of qubit mapping based on the coupling relationship between logical qubits and the topological relationship between physical qubits. The logical qubits are qubits in quantum circuits, the physical qubits are qubits in quantum chips, and the quantum circuits run on the quantum chips.

[0181] The qubit mapping module 402 is used to solve for the qubit mapping scheme when the quadratic unconstrained binary optimization model reaches its minimum value, and to map the logical qubit to the physical qubit based on the mapping scheme.

[0182] The specific functions and effects of the qubit mapping device can be explained by referring to other embodiments in this specification, and will not be repeated here. Each module in the qubit mapping device can be implemented entirely or partially through software, hardware, or a combination thereof. Each module can be embedded in or independent of the processor in a computer device in hardware form, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0183] Please see Figure 5 This specification also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor, when executing the computer program, implements the quantum bit mapping method of any of the above embodiments. Please refer to... Figure 5 The computer device can be a classical computer or a quantum computer.

[0184] This specification also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a computer, causes the computer to perform the quantum bit mapping method in any of the above embodiments.

[0185] This specification also provides a computer program product containing instructions that, when executed by a computer, cause the computer to perform the qubit mapping method in any of the above embodiments.

[0186] It is understood that the specific examples in this specification are only intended to help those skilled in the art better understand the implementation methods described herein, and are not intended to limit the scope of the invention.

[0187] It is understood that in the various embodiments of this specification, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not limit the implementation process of the embodiments of this specification in any way.

[0188] It is understood that the various implementation methods described in this specification can be implemented individually or in combination, and the implementation methods in this specification are not limited in this respect.

[0189] Unless otherwise stated, all technical and scientific terms used in the embodiments of this specification have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of this specification. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this specification and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0190] It is understood that the processor in the embodiments of this specification can be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method embodiments can be completed by integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this specification. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this specification can be directly implemented by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above methods.

[0191] It is understood that the memory in the embodiments of this specification may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM). It should be noted that the memory in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0192] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this specification.

[0193] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the aforementioned method implementations, and will not be repeated here.

[0194] In the several embodiments provided in this specification, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0195] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0196] In addition, the functional units in the various embodiments of this specification can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0197] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of this specification, in essence, or the parts that contribute to the prior art, or parts of the technical solutions, can be embodied in the form of software products. These computer software products are stored in a storage medium and include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this specification. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0198] The above description is merely a specific embodiment of this specification, but the scope of protection of this invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this specification should be included within the scope of protection of this specification. Therefore, the scope of protection of this invention should be determined by the scope of the claims.

Claims

1. A quantum bit mapping method, characterized in that, The method includes: Identify physical qubits in the quantum chip whose computational error rate is lower than a preset error rate, and from these physical qubits, select physical qubits whose coherence time is lower than a first threshold or whose quantum gate operation fidelity is lower than a second threshold, along with their adjacent physical qubits, as the boundaries of the qubit concentration regions. Divide the quantum chip into multiple qubit concentration regions based on these boundaries. Physical qubits in a target region of the quantum chip are determined in multiple qubit concentration regions. These physical qubits are used to map logical qubits in the quantum circuit. The number of physical qubits in the target region is not less than the number of logical qubits in the quantum circuit, and is less than or equal to the number of physical qubits in other regions of the quantum chip. Based on the coupling relationship between logical qubits, a coupling strength matrix for the logical qubits is determined. This coupling strength matrix is ​​a symmetric matrix, and its elements represent the number of two-qubit gates between the corresponding logical qubits. Based on the topological relationship between the physical qubits, a distance matrix for the physical qubits is determined. This distance matrix is ​​also a symmetric matrix, and its elements represent the shortest distance for establishing interaction paths between the corresponding physical qubits. The direct product of the coupling strength matrix and the distance matrix is ​​calculated to obtain the target matrix. The elements of the target matrix are used as coefficients for the mapping method of each qubit. The minimum value of the quadratic objective function of the qubit mapping is calculated as the quadratic allocation model for the qubit mapping. The logical qubits are qubits in a quantum circuit, and the physical qubits are qubits in a quantum chip. The quantum circuit operates on the quantum chip. The solution obtains the qubit mapping scheme when the quadratic unconstrained binary optimization model reaches its minimum value, and maps the logical qubit to the physical qubit based on the mapping scheme. The quadratic unconstrained binary optimization model includes a quadratic allocation model.

2. The method as described in claim 1, characterized in that, The method for constructing the quadratic unconstrained binary optimization model includes: Based on the coupling relationship between the logical qubits and the topological relationship between the physical qubits, a secondary allocation model for qubit mapping is constructed; Determine the constraints of the quadratic allocation model of the qubit mapping, and transform the constraints into quadratic penalty terms; By adding the quadratic penalty term to the quadratic allocation model, a quadratic unconstrained binary optimization model for the qubit mapping is obtained.

3. The method as described in claim 1, characterized in that, Before constructing the secondary allocation model of the qubit mapping based on the coupling relationship between the logical qubits and the topological relationship between the physical qubits, the method further includes: The multi-qubit gate in the input quantum circuit is converted into a single-qubit gate and / or a two-qubit gate.

4. The method as described in claim 1, characterized in that: The solution yields the qubit mapping scheme when the quadratic unconstrained binary optimization model reaches its minimum value, including: The minimum value of the quadratic unconstrained binary optimization model is calculated, and the qubit mapping scheme when the quadratic unconstrained binary optimization model reaches its minimum value is determined. The minimum value is obtained by annealing computer or quantum computing virtual machine.

5. The method as described in claim 1, characterized in that, After mapping the logical qubit to the physical qubit based on the mapping scheme, the method further includes: According to the execution order of the two-qubit gates in the quantum circuit, it is determined in turn whether the set of physical qubits mapped by the logical qubits acted by each two-qubit gate is connected. If they are not connected, a SWAP gate operation is performed between the set of physical qubits to swap the quantum state of one physical qubit to the target physical qubit, and the target physical qubit is connected to the other physical qubit. The operation of the dual-qubit gate instruction is performed on the target physical qubit and another physical qubit; The target physical qubit and the quantum state of one of the physical qubits are exchanged through a SWAP gate.

6. A quantum bit mapping device, characterized in that, The device includes: The first determining module is used to determine the physical qubits in the quantum chip whose computational error rate is lower than a preset error rate, and from the physical qubits whose computational error rate is lower than the preset error rate, the physical qubits whose coherence time is lower than a first threshold or whose quantum gate operation fidelity is lower than a second threshold, and their adjacent physical qubits, are used as the boundaries of the qubit concentration regions. Based on the boundaries, multiple qubit concentration regions are divided in the quantum chip, and the physical qubits included in the qubit concentration regions are used to map the logical qubits in the quantum circuit. The first determining module is used to determine the physical qubits of a target region in the quantum chip among multiple qubit concentration regions. The physical qubits are used to map the logical qubits in the quantum circuit. The number of physical qubits in the target region is not less than the number of logical qubits in the quantum circuit, and is less than or equal to the number of physical qubits in other regions of the quantum chip. The model building module is used to determine the coupling strength matrix of the logical qubits based on the coupling relationship between them. The coupling strength matrix is ​​a symmetric matrix, and its elements represent the number of two-qubit gates between the corresponding logical qubits. Based on the topological relationship between the physical qubits, the module determines the distance matrix of the physical qubits. The distance matrix is ​​a symmetric matrix, and its elements represent the shortest distance for establishing an interaction path between the corresponding physical qubits. The module calculates the direct product of the coupling strength matrix and the distance matrix to obtain the target matrix. The elements in the target matrix are used as coefficients for the mapping method of each qubit, and the minimum value of the quadratic objective function of the qubit mapping is calculated as the quadratic allocation model of the qubit mapping. The qubit mapping module is used to solve for the qubit mapping scheme when the quadratic unconstrained binary optimization model reaches its minimum value, and to map the logical qubits to the physical qubits based on the mapping scheme. The quadratic unconstrained binary optimization model includes a quadratic allocation model.

7. A storage medium, characterized in that, The storage medium stores a computer program, wherein the computer program is configured to execute the method described in any one of claims 1 to 5 when it is run.

8. An electronic device comprising a memory and a processor, characterized in that, The memory stores a computer program, and the processor is configured to run the computer program to perform the method as described in any one of claims 1 to 5.

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