Pre-sense core node amplification in sense amplifier

Abstract

Embodiments of the present application relate to pre-sense gut node amplification in sense amplifiers. A memory device includes a plurality of memory cells configured to store data. The memory device also includes a plurality of digit lines each configured to carry data to and from a respective memory cell. The memory device further includes a plurality of sense amplifiers each selectively coupled to a respective digit line and including first and second NMOS transistors and first and second gut nodes coupled to the first and second NMOS transistors, respectively. Each sense amplifier is configured to perform threshold compensation on the first and second NMOS transistors by storing respective voltages at the first and second gut nodes proportional to respective threshold voltages of the first and second NMOS transistors. The sense amplifier also amplifies a differential voltage between the first and second gut nodes by charging the first gut node and discharging the second gut node based at least in part on a respective charge of the digit line.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to memory devices. More specifically, the embodiments of this disclosure relate to monitoring the operation of memory devices. Background Technology

[0002] Typically, a computing system may include electronic devices that transmit information via electrical signals during operation. For example, a computing system may include a processor communicatively coupled to a memory device, such as a dynamic random access memory (DRAM) device, a ferroelectric random access memory (FeRAM) device, another type of random access memory (RAM) device, and / or a hybrid device of more than one type of RAM. In this way, for example, the processor may communicate with the memory device to retrieve executable instructions, retrieve data to be processed by the processor, and / or store data output from the processor.

[0003] Memory devices utilize sense amplifiers used by the memory device during read operations. Specifically, the read circuitry of the memory device uses a sense amplifier to receive low-voltage (e.g., low-differential) signals and amplify small voltage differences so that the memory device can properly interpret the data. However, some embodiments of the sense amplifier consume excessive resources (e.g., power and / or area). Furthermore, some sense amplifiers may not amplify low voltages sufficiently or too slowly.

[0004] The embodiments disclosed herein may address one or more of the problems set forth above. Summary of the Invention

[0005] A memory device is described. The memory device may include: a plurality of memory cells configured to store data; a plurality of digital lines, each configured to carry data to and from a corresponding memory cell among the plurality of memory cells; and a plurality of sense amplifiers, each selectively coupled to a corresponding digital line among the plurality of digital lines, and including a first NMOS transistor and a second NMOS transistor, and a first core node and a second core node respectively coupled to the first NMOS transistor and the second NMOS transistor. Each sense amplifier is configured to: charge a first core node with a first voltage; charge a second core node with a second voltage; amplify a differential voltage between a first core node and a second core node by charging the first core node and discharging the second core node, at least partially based on the corresponding charge from the plurality of digital lines; and transmit the amplified differential voltage as a differential signal to the corresponding digital line among the plurality of digital lines. The first voltage at least partially compensates for threshold voltage fluctuations of the first NMOS transistor caused by process, voltage, or temperature fluctuations and is proportional to the threshold voltage of the first NMOS transistor, and the second voltage at least partially compensates for threshold voltage fluctuations of the second NMOS transistor caused by process, voltage, or temperature fluctuations and is proportional to the threshold voltage of the second NMOS transistor.

[0006] A memory device is described. The memory device may include: one or more memory cells configured to store data; a pair of digital lines coupled to the one or more memory cells; and a sense amplifier coupled to the pair of digital lines. The sense amplifier may include: a cross-coupled transistor coupled to a power supply voltage; a first core node coupled to a first transistor of the cross-coupled transistor, wherein the first core node corresponds to a first digital line of the pair of digital lines; a second core node coupled to a second transistor of the cross-coupled transistor, wherein the second core node corresponds to a second digital line of the pair of digital lines; a third transistor coupled to the first core node, wherein the gate of the third transistor is coupled to the second digital line; a fourth transistor coupled to the core node, wherein the gate of the fourth transistor is coupled to the first digital line; a first isolation transistor coupled between the first digital line and the first core node to selectively decouple the first digital line from the first core node when amplifying the voltage difference between the first core node and the second core node; and a second isolation transistor coupled between the second digital line and the second core node to selectively decouple the second digital line from the second core node when amplifying the voltage difference between the first core node and the second core node.

[0007] Describe a method. The method may include: configuring a first diode-configured transistor of a sense amplifier for a memory device using a first compensation transistor to couple the gate terminal and source terminal of the first transistor together, thereby charging a first core node with a first voltage proportional to a first threshold voltage of the first transistor; configuring a second diode-configured transistor of the sense amplifier using a second compensation transistor to couple the gate terminal and source terminal of the second transistor together, thereby charging a second core node with a second voltage proportional to a second threshold voltage of the second transistor; disconnecting the gate terminal of the first transistor from the source terminal using the first compensation transistor; disconnecting the gate terminal of the second transistor from the source terminal using the second compensation transistor; amplifying the voltage difference between the first core node and the second core node using the sense amplifier by: charging a first digital line with a logic high value from a memory cell, discharging the second core node using the charging of the first digital line, and charging the first core node using the discharging of the second core node, wherein the first digital line is configured to transmit data to and receive data from the sense amplifier via the first core node; and transmitting the amplified voltage difference between the first core node and the second core node as a differential signal on the digital line. Attached Figure Description

[0008] Figure 1 A simplified block diagram illustrating certain features of a memory device with a sense amplifier according to embodiments of the present disclosure;

[0009] Figure 2 According to embodiments of this disclosure Figure 1 Circuit diagram of an embodiment of the sensing amplifier;

[0010] Figure 3 According to embodiments of this disclosure Figure 1 Circuit diagram of an alternative embodiment of the sense amplifier;

[0011] Figure 4 For the first stage of sensing amplification according to embodiments of this disclosure Figure 3 Circuit diagram of an embodiment of the sensing amplifier;

[0012] Figure 5 For the second stage of sensing amplification according to embodiments of this disclosure Figure 3 Circuit diagram of an embodiment of the sensing amplifier;

[0013] Figure 6 For the third stage of sensing amplification according to embodiments of this disclosure Figure 3 Circuit diagram of an embodiment of the sensing amplifier;

[0014] Figure 7 For the fourth stage of sensing amplification according to embodiments of this disclosure Figure 3 Circuit diagram of an embodiment of the sensing amplifier;

[0015] Figure 8 For the fifth stage of sensing amplification according to embodiments of this disclosure Figure 3 Circuit diagram of an embodiment of the sensing amplifier;

[0016] Figure 9 According to embodiments of this disclosure Figure 3 The graph shows the operation of the sense amplifier, which involves controlling the n-channel gating using a single control signal; and

[0017] Figure 10 According to embodiments of this disclosure Figure 3 The graph shows the operation of the sensing amplifier, which involves using multiple control signals to control the n-channel gating. Detailed Implementation

[0018] One or more specific embodiments will be described below. To provide a concise description of these embodiments, not all features of the actual implementation are described in the specification. It should be understood that, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developer's specific goals, such as complying with system-related and business-related constraints, which can vary from one implementation to another. Furthermore, it should be understood that such development work can be complex and time-consuming, but these are routine tasks in design, construction, and manufacturing for those of ordinary skill in the art who benefit from this disclosure.

[0019] As previously discussed, the read circuitry of a memory device utilizes a sense amplifier to receive low-voltage (e.g., low-differential) signals and amplify small voltage differences so that the memory device can properly interpret data. However, some embodiments of the sense amplifier consume excessive resources (e.g., power and / or area). Therefore, as taught herein, the sense amplifier can be modified to directly use the array voltage (VARY) without generating a local voltage (ACT). Furthermore, with the aforementioned local voltage, the sense amplifier can operate using a lower voltage. Additionally, eliminating the circuitry used to generate the local voltage can reduce size, cost, and / or power consumption. Moreover, some sense amplifiers may not amplify low voltages sufficiently or too slowly. Therefore, to increase amplification in the sense amplifier, the sense amplifier can utilize core node pre-amplification to increase the accuracy of reading data from the digital line. Furthermore, by using amplification to increase fidelity, the length of the digital line can be increased to a distance unsuitable for use in the absence of differential voltage pre-sensing amplification.

[0020] Now turn to the various diagrams, Figure 1 A simplified block diagram illustrating certain characteristics of the memory device 10. Specifically, Figure 1 The block diagram is a functional block diagram illustrating certain functionalities of the memory device 10. According to one embodiment, the memory device 10 may be a fifth-generation dual data rate synchronous dynamic random access memory (DDR5 SDRAM) device. Various features of DDR5 SDRAM allow for reduced power consumption, greater bandwidth, and greater storage capacity compared to previous generations of DDR SDRAM.

[0021] Memory device 10 may include a plurality of memory banks 12. For example, the memory banks 12 may be DDR5 SDRAM memory banks. The memory banks 12 may be disposed on one or more chips (e.g., SDRAM chips) arranged on a dual in-line memory module (DIMM). As will be understood, each DIMM may include a plurality of SDRAM memory chips (e.g., ×8 or ×16 memory chips). Each SDRAM memory chip may include one or more memory banks 12. Memory device 10 represents a portion of a single memory chip (e.g., an SDRAM chip) having a plurality of memory banks 12. For DDR5, the memory banks 12 may be further arranged to form memory bank groups. For example, for 8 gigabyte (Gb) DDR5 SDRAM, the memory chip may include 16 memory banks 12, arranged in 8 memory bank groups, each memory bank group containing 2 memory banks. For example, a 16Gb DDR5 SDRAM may contain 32 memory banks 12 arranged in 8 bank groups, each bank group containing 4 memory banks. Depending on the application and design of the entire system, various other configurations, organization, and sizes of the memory banks 12 on the memory device 10 may be utilized.

[0022] The memory bank 12 and / or memory bank control block 22 include a sense amplifier 13. As previously mentioned, the sense amplifier 13 is used by the memory device 10 during a read operation. Specifically, the read circuitry of the memory device 10 utilizes the sense amplifier 13 to receive low-voltage (e.g., low-differential) signals from the memory cells of the memory bank 12 and amplify small voltage differences so that the memory device 10 can properly interpret the data.

[0023] The memory device 10 may include a command interface 14 and an input / output (I / O) interface 16. The command interface 14 is configured to provide a number of signals (e.g., signal 15) from an external (e.g., a host) device (not shown), such as a processor or controller. The processor or controller may provide various signals 15 to the memory device 10 to facilitate the transfer and reception of data to be written to or read from the memory device 10.

[0024] As will be understood, command interface 14 may include several circuits, such as clock input circuitry 18 and command address input circuitry 20, for example, to ensure proper handling of signal 15. Command interface 14 may receive one or more clock signals from an external device. Typically, dual data rate (DDR) memory utilizes a differential pair of system clock signals: a true clock signal Clk_t and an inverted clock signal Clk_b. The positive clock edge of DDR refers to the point where the rising true clock signal Clk_t crosses the falling inverted clock signal Clk_c, while the negative clock edge indicates the transition of the falling true clock signal Clk_t and the rising of the inverted clock signal Clk_c. Commands (e.g., read commands, write commands, etc.) are typically entered on the positive edge of the clock signal, and data is transmitted or received on both the positive and negative clock edges.

[0025] Clock input circuit 18 receives a true clock signal Clk_t and an inverted clock signal Clk_c, and generates an internal clock signal CLK. The internal clock signal CLK is supplied to an internal clock generator, such as a delay-locked loop (DLL) circuit 30. The DLL circuit 30 generates a phase-controlled internal clock signal LCLK based on the received internal clock signal CLK. The phase-controlled internal clock signal LCLK is supplied to, for example, an I / O interface 16, and used as a timing signal for determining the output timing of data reads. In some embodiments, clock input circuit 18 may include circuitry that splits the clock signal into multiple (e.g., four) phases. Clock input circuit 18 may also include phase detection circuitry that detects which phase receives the first pulse when pulse sets occur too frequently, allowing clock input circuit 18 to reset between pulse sets.

[0026] The internal clock signal / phase CLK can also be provided to various other components within the memory device 10 and can be used to generate various additional internal clock signals. For example, the internal clock signal CLK can be provided to the command decoder 32. The command decoder 32 can receive command signals from the command bus 34 and can decode the command signals to provide various internal commands. For example, the command decoder 32 can provide command signals to the DLL circuit 30 via the bus 36 to coordinate the generation of the phase control internal clock signal LCLK. For example, the phase control internal clock signal LCLK can be used to time data via the I / O interface 16.

[0027] Furthermore, the command decoder 32 can decode commands such as read commands, write commands, mode register set commands, activation commands, etc., and provides access to the specific memory bank 12 corresponding to the command via bus path 40. As will be understood, the memory device 10 may include various other decoders, such as row decoders and column decoders, to facilitate access to the memory bank 12. In one embodiment, each memory bank 12 includes a memory bank control block 22, which provides the necessary decoding (e.g., row decoders and column decoders) and other features (such as timing control and data control) to facilitate the execution of commands entering and leaving the memory bank 12.

[0028] Memory device 10 performs operations such as read and write commands based on command / address signals received from an external device, such as a processor. In one embodiment, the command / address bus may be a 14-bit bus for accommodating command / address signals CA<13:0>. The command / address signals are timed to command interface 14 using clock signals (Clk_t and Clk_c). The command interface may include command address input circuitry 20, configured to receive and transmit commands via, for example, command decoder 32, to provide access to memory bank 12. Additionally, command interface 14 may receive a chip select signal CS_n. The CS_n signal enables memory device 10 to process commands input on the CA<13:0> bus. Access to a specific memory bank 12 within memory device 10 is encoded as a command on the CA<13:0> bus.

[0029] Additionally, command interface 14 can be configured to receive several other command signals. For example, a command / address (CA_ODT) signal on the die termination can be provided to facilitate proper impedance matching within memory device 10. For example, a reset command RESET_n can be used during power-on to reset command interface 14, status registers, state machines, etc. Command interface 14 can also receive a command / address inversion (CAI) signal, which can be provided to invert the state of command / address signals CA<13:0> on the command / address bus, for example, depending on the command / address routing of a particular memory device 10. A mirror (MIR) signal can also be provided to facilitate mirroring functionality. Based on the configuration of multiple memory devices in a particular application, the MIR signal can be used to multiplex the signal so that it can be interchanged to implement a particular route of signal to memory device 10. Various signals can also be provided to facilitate testing of memory device 10, such as a test enable (TEN) signal. For example, the TEN signal can be used to put memory device 10 into test mode for connectivity testing.

[0030] Command interface 14 can also be used to provide an alarm signal ALERT_n to the system processor or controller in response to certain detectable errors. For example, the alarm signal ALERT_n can be transmitted from memory device 10 in the event of a cyclic redundancy check (CRC) error. Other alarm signals may also be generated. Furthermore, the bus and pins used for transmitting the alarm signal ALERT_n from memory device 10 can be used as input pins during certain operations, such as connectivity test modes performed using the TEN signal as described above.

[0031] By transmitting and receiving data signals 44 via I / O interface 16, data can be sent to and from memory device 10 using the command and timing signals discussed above. More specifically, data can be sent to or retrieved from memory bank 12 via data path 46, which includes multiple bidirectional data buses. Data I / O signals, commonly referred to as DQ signals, are typically transmitted and received in one or more bidirectional data buses. For some memory devices, such as DDR5 SDRAM memory devices, I / O signals can be divided into upper and lower bytes. For example, for a ×16 memory device, I / O signals can be divided into upper and lower I / O signals corresponding to upper and lower bytes of, for example, data signals (e.g., DQ<15:8> and DQ<7:0>).

[0032] To allow for higher data rates within memory device 10, some memory devices, such as DDR memory devices, may utilize data strobe signals, commonly referred to as DQS signals. The DQS signals are driven by an external processor or controller transmitting data (e.g., for write commands) or by memory device 10 itself (e.g., for read commands). For read commands, the DQS signals are effectively additional data output (DQ) signals with a predetermined pattern. For write commands, the DQS signals are used as clock signals to capture the corresponding input data. Similar to clock signals (Clk_t and Clk_c), differential pairs (DQS_t and DQS_c) of DQS signals can be provided as data strobe signals to provide differential pair signaling during read and write operations. For some memory devices, such as DDR5 SDRAM memory devices, the differential pairs of DQS signals can be divided into upper and lower data strobe signals (e.g., UDQS_t and UDQS_c; LDQS_t and LDQS_c), corresponding to, for example, the upper and lower bytes of data sent to and from memory device 10.

[0033] An impedance (ZQ) calibration signal can also be provided to memory device 10 via I / O interface 16. The ZQ calibration signal can be provided to a reference pin and used to tune the output driver and ODT values ​​by adjusting the pull-up and pull-down resistors of memory device 10 over changes in process, voltage, and temperature (PVT) values. Because PVT characteristics can affect the ZQ resistor value, the ZQ calibration signal can be provided to the ZQ reference pin to adjust the resistance, thereby calibrating the input impedance to a known value. As will be understood, a precision resistor is typically coupled between the ZQ pin on memory device 10 and GND / VSS external to memory device 10. This resistor acts as a reference for adjusting the drive strength of the internal ODT and I / O pins.

[0034] Additionally, a loopback data signal LBDQ and a loopback strobe signal LBDQS can be provided to memory device 10 via I / O interface 16. The loopback data signal and loopback strobe signal can be used during testing or debugging phases to set memory device 10 into a mode where signals loop back through memory device 10 via the same pin. For example, the loopback signal can be used to set memory device 10 to test the data output (DQ) of memory device 10. The loopback may include both LBDQ and LBDQS or possibly only the data pin. This is typically intended for monitoring data captured by memory device 10 at I / O interface 16. LBDQ can indicate data operations of a target memory device (such as memory device 10) and can therefore be analyzed to monitor (e.g., debug and / or perform diagnostics on it) the data operations of the target memory device. Additionally, LBDQS can indicate strobe operations (e.g., timing of data operations) of a target memory device (such as memory device 10) and can therefore be analyzed to monitor (e.g., debug and / or perform diagnostics on it) the strobe operations of the target memory device.

[0035] As will be understood, various other components, such as power supply circuitry (for receiving external VDD and VSS signals), mode registers (for defining various modes of programmable operation and configuration), read / write amplifiers (for amplifying signals during read / write operations), and temperature sensors (for sensing the temperature of memory device 10), may also be incorporated into memory device 10. Therefore, it should be understood that only... Figure 1 The block diagram is provided to highlight certain functional features of the memory device 10 to facilitate a detailed description thereafter. Furthermore, while the memory device 10 is described for the foregoing as a DDR5 device, the memory device 10 may be any suitable device (e.g., dual data rate type 4 DRAM (DDR4), ferroelectric RAM device, or a combination of different types of memory devices).

[0036] Figure 2 For feasible Figure 1A circuit diagram of the sensing amplifier 50 in an embodiment of the sensing amplifier 13. Although only a single sensing amplifier 50 is shown, multiple sensing amplifiers 13 are included in a memory device 10 that can share at least some control signals and / or power supply voltages.

[0037] As described, the sense amplifier 50 receives an array voltage (VARY) 52. The sense amplifier 50 also includes a transistor 54, which receives a control signal 56 at its gate to control the generation of an activation signal (ACT) 58, which is a local voltage. ACT 58 activates the sense amplifier 50 by providing an operating voltage to the sense amplifier 50.

[0038] The sense amplifier 50 also receives an isolation signal (ISO) 60. The sense amplifier 50 includes transistors 61 and 62, which use ISO 60 to couple the internal circuitry of the sense amplifier 50 and decouple it from corresponding digital lines 65 and 64. Digital line 65 indicates data in a memory cell as a "Bit Line True" (BLT) signal, while digital line 64 can conversely serve as a complementary "Bit Line / Error" (BLB) signal.

[0039] The sense amplifier 50 also includes a cross-coupled p-channel metal-oxide-semiconductor device (CCP) 66. Core nodes 68 and 70 are each coupled to a first terminal (e.g., gate) of a corresponding one of the P-channel MOSFETs of CCP 66 and a second terminal (e.g., drain) of the other corresponding P-channel MOSFET of CCP 66.

[0040] The sense amplifier 50 further includes a transistor 72 for equalizing the voltages of core nodes 68 and 70 based on an equalization signal (EQ) 74. Specifically, when asserting EQ 74, core node 68 can be discharged / charged to a line precharge voltage (VBLP) 76. ISO 60 controls the coupling of core node 68 to digital line 65 and the decoupling of core node 68 from said digital line via transistor 61. Similarly, ISO 60 controls the coupling of core node 70 to digital line 64 and the decoupling of core node 70 from said digital line via transistor 62.

[0041] The sense amplifier 50 further includes n-channel MOSFET (NMOS) transistors 78, 80, 82, and 84. Both n-channel transistors 78 and 82 receive a Local Bit Line Compensation Enable (lblcp) 86 at their respective gates. Another terminal (e.g., source) of NMOS transistor 78 is coupled to digital line 64, while another terminal (e.g., source) of NMOS transistor 82 is coupled to digital line 65. A third terminal of NMOS transistor 78 is coupled to a terminal (e.g., source) of NMOS transistor 88, and a third terminal of NMOS transistor 82 is coupled to a terminal (e.g., source) of NMOS transistor 84. The gate of NMOS transistor 80 is coupled to digital line 64, and the gate of NMOS transistor 84 is coupled to digital line 65. The third terminals of transistors 80 and 84 are coupled to an n-channel strobe (NCS) 87. The sense amplifier 50 receives an n-channel sense amplifier signal (NSA) 88 to control transistor 90, which selectively couples to NCS 87 and decouples it from ground.

[0042] The illustrated embodiment of sense amplifier 50 senses and amplifies low-voltage data, but sense amplifier 50 may have some drawbacks. Specifically, there may be problems with the local generation of ACT 58 from VARY 52. Although VARY 52 can be a well-regulated voltage, during low-voltage operation, there may be a voltage drop across transistor 54 (and any other circuitry), which can cause ACT 58 to fluctuate inappropriately. For example, VARY may be regulated from VDD and can be as low as 0.8V for LPDRAM during active cycling. This low voltage can correspond to a voltage drop across transistor 54 that can be as high as 0.1V, resulting in an ACT level as low as 0.7V, which can significantly reduce active cycling operation. Such voltage drops during low-voltage operation can be avoided by eliminating the local generation of ACT 58. Furthermore, the limited amplification in sense amplifier 50 limits the length of digital lines 64 and 65 and / or results in relatively high noise levels.

[0043] To address the problem with sensing amplifier 50, an alternative embodiment of sensing amplifier 13 can be used. For example, Figure 3 A sense amplifier 100 is shown that can be used to replace at least one of the sense amplifiers 50 as a memory device 10. The sense amplifier 100 is similar to the sense amplifier 50 except that the sense amplifier 100 is configured differently (i.e., it does not locally generate ACT 58 and does not connect the core node 68 to VBLP 76 via transistor 72).

[0044] Instead of locally generating ACT 58, sense amplifier 100 directly utilizes VARY 52 and completely omits transistor 54. This direct reliance on VARY 52, rather than relying on ACT 58 via transistor 54, enables the array to operate at low voltages. This capability allows memory device 10 to operate with lower power consumption and / or achieve a robust design with increased reliability, provided the array and peripheral power supplies are scaled proportionally. The use of VARY 52 can further increase row activity time (tRAS) and / or write recovery time (tWR) timing. Furthermore, the removal of transistor 54 allows for a reduction in the size of sense amplifier 100 compared to sense amplifier 50.

[0045] Furthermore, different mechanisms used to utilize the sensing amplifier 100 can further reduce noise on digital lines 64 and 65. This allows the digital lines to be longer at the processing nodes where differential voltage pre-sensing amplification exists in the sensing amplifier 100.

[0046] Figure 4 This is a circuit diagram of the sense amplifier 100 in its first stage. This first stage occurs during the pre-charge phase of the previous cycle. As illustrated, ISO 60 disables / de-asserts, causing transistor 62 to act as an open switch disconnecting digital line 64 and core node 70. The disabled state of ISO 60 also causes transistor 61 to act as an open switch to disconnect digital line 65 from core node 68. Assertion EQ 74 causes transistor 72 to act as a closed switch connecting core nodes 68 and 70 together to equalize their voltages. During this stage, lblcp 86 and NSA 88 can also be disabled / de-asserted.

[0047] Figure 5This is a circuit diagram of the sense amplifier 100 in the second stage, immediately following the first stage. The second stage corresponds to the low-threshold voltage compensation stage where the core nodes are balanced. This stage begins with the assertion of lblcp 86 together with NSA 88. The assertion of EQ 74 is also de-asserted at the beginning of the second stage to decouple core nodes 68 and 70 from each other. The assertion of lblcp 86 couples core node 68 to the two terminals (e.g., gate and source) of NMOS transistor 80. This connection is achieved because the assertion of lblcp 86 causes NMOS transistor 78 to act as a closed switch between the two terminals of NMOS transistor 80. Similarly, the assertion of lblcp 86 couples core node 70 to the two terminals (e.g., gate and source) of NMOS transistor 84. This connection is achieved because the assertion of lblcp 86 causes NMOS transistor 82 to act as a closed switch between the two terminals of NMOS transistor 84. Furthermore, transistor 90, which acts as a closed switch by attribution to the assertion of NSA 88, grounds the connection of the third terminal (e.g., drain) of NMOS transistors 80 and 84. Due to these connections, transistors 80 and 84 act as diodes to enable threshold voltage compensation using the charge from the core nodes 68 and 70 of the previous cycle, setting the charge at core nodes 68 and 70 to the threshold voltage of the respective transistors 80 and 84.

[0048] Figure 6 This is a circuit diagram of the sense amplifier 100 in the third stage following the second stage. The third stage corresponds to the high (or low) memory cell being discharged to the corresponding digital line (e.g., digital line 64 or digital line 65). This stage includes deassertion of lblcp 86 and NSA 88, causing transistors 78, 82, and 88 to act as open switches. When the active word line is part of this stage, this causes the high (or low) memory cell to be discharged to the corresponding location. For example, the memory cell can charge the corresponding digital line 65. For example, discharging the memory cell can charge digital line 65 from an intermediate level (e.g., 0.5V) to a level higher than the intermediate level (e.g., 30-50mV higher) or a level lower than the intermediate level (e.g., 30-50mV lower). If digital line 65 is pulled high, then core node 70 is pulled low via NMOS transistor 84. Core nodes 68 and 70 are also charged. Furthermore, since EQ 74 is activated at its position in the third stage, core nodes 68 and 70 are then charged to similar values ​​above VBLP, which helps to balance 1 and 0 tolerance sensing during subsequent stages.

[0049] Figure 7This is a circuit diagram of the sense amplifier 100 in the fourth stage following the third stage. The fourth stage enables the sense amplifier 100 to function in a differential voltage amplifier configuration. Assertion EQ 74 is also de-asserted during the fourth stage. The fourth stage also corresponds to NSA 88 being asserted so that transistor 90 functions like a closed switch. When NSA 88 is asserted, the terminals (e.g., drains) of transistors 80 and 84 are coupled to ground via transistor 90. Due to the charge in digital line 65, NMOS transistor 84 releases charge from core node 70, thereby pulling down the voltage of core node 70, while simultaneously amplifying the voltage of core node 68 by enabling the transfer of the PMOS across core node 68 and VARY 52. Therefore, the voltage difference between core nodes 68 and 70 is amplified during the fourth stage. By increasing this voltage difference, when reasserting ISO 60, a higher voltage Δ exists between digital lines 64 and 65 when writing data from core nodes 68 and 70 to digital lines 65 and 64, as... Figure 8 The fifth stage is shown in the document.

[0050] In some embodiments, the sensing amplifier 100 can be used to perform soft sensing, wherein the connection of transistors 80 and 84 to ground can be performed incrementally. This soft sensing can be performed by using different transistors with different control signals to control the strength and timing of the coupling of transistors 80 and 84 to ground in a fourth stage. For example, transistor 90 may be only a portion of the total device width, and transistors 80 and 84 are relatively weakly connected to ground as a soft gating in the first part of sensing, while another transistor 124 provides additional gating strength in a second part using another NSA 122. Thus, based on the size of transistors 90 and 124, the first part can provide a first portion (e.g., 50%) of the total gating strength, while another part (e.g., a sixth stage) provides the remaining portion (e.g., 50%) of the total gating strength. However, any number of transistors can be used to provide gating strength. In other words, the gating strength can be interleaved into any suitable number (e.g., 1, 2, 3, 4, 5, 6 or more) of sub-parts by utilizing a certain number of transistors. Furthermore, although these transistors are described as generally having the same size as each other, some embodiments of the memory device 10 may have at least two of such transistors having different sizes, resulting in different ratios between the percentages of total gating strength (e.g., 30% in the first part and 70% in the second part).

[0051] Figure 9 To showcase Figures 4 to 8The timing diagram 130 shows the operation phases of the sense amplifier 100. As explained, the diagram 120 includes lines 132, 134, 136, 138, 140, 142, 144, 146, 148, 150, and 152. Line 132 corresponds to ISO 60. Line 134 corresponds to 1blcp 86. Line 136 corresponds to EQ 74. Line 138 corresponds to NSA 88, and line 140 corresponds to NSA 122. Line 142 corresponds to a word line corresponding to the sense amplifier 100. Line 144 corresponds to a high memory cell being read using the sense amplifier 100. Line 146 corresponds to core node 68, and line 148 corresponds to core node 70. Line 150 corresponds to digital line 65, and line 152 corresponds to digital line 64.

[0052] As previously discussed, the first stage 154 originates from a previous cycle with pre-charge. As explained, in the first stage 154, ISO 60, NSA 88, NSA 122, and the word line are low, while lblcp 86 and EQ 74 are high. In the second stage 156, EQ 74 remains asserted, while lblcp 86 is deasserted, and NSA 88 and NSA 122 are asserted. As previously discussed, this configuration causes the sense amplifier 100 to initiate VTC compensation as previously discussed.

[0053] In phase 3, 158, lblcp 86, NSA 88, and NSA 122 are deasserted while the word line is asserted. As previously discussed, this configuration causes digital line 65 to be charged from the high memory cell when the signal is generated. Core nodes 68 and 70 are also charged after assertion EQ 74 (line 136) causes equalization of core nodes 68 and 70.

[0054] In stage 4, 160, assertion EQ 74 is deasserted, and both NSA 88 and NSA 122 are asserted using CCP 66 and transistors 78, 80, 82, and 84 in the differential amplifier configuration. This releases the charge on core node 70 (line 148) while amplifying the charge on core node 68 (line 146). This increase in the voltage difference between core nodes 68 and 70 increases the decoding fidelity of data from memory cells.

[0055] At the end / inside of phase 4 160, ISO 60 is re-asserted, thereby coupling core node 68 to digital line 65 and core node 70 to digital line 64. NSA 88 and NSA 122 are also asserted to configure sense amplifier 100 as a latch to latch the value of phase 5 162.

[0056] As previously mentioned, in some embodiments, NSA 88 and NSA 122 may be asserted at different times in the fourth phase 160. For example, except that the graph 170 has a period 172 between the assertions of NSA 88 and NSA 122 to perform soft sensing, Figure 10 Display graph 170, which is the same as graph 130.

[0057] Return to Figure 9 The fifth stage 162 is used to transfer differential data stored in core nodes 68 and 70 to the corresponding digital lines 65 and 64. This transfer is asserted to be at least partially based on ISO 60.

[0058] While this disclosure allows for various modifications and alternatives, specific embodiments have been shown by way of example in the drawings and described in detail herein. However, it should be understood that this disclosure is not intended to be limited to the specific forms disclosed. In fact, this disclosure is intended to cover all modifications, equivalents, and alternatives that fall within the spirit and scope of this disclosure as defined by the appended claims.

[0059] The technical references presented and asserted herein are applied to tangible objects and specific examples of practical nature that demonstrably improve the technical field of the invention and are therefore not abstract, intangible, or purely theoretical. Furthermore, if any claim appended to this specification contains one or more elements expressed as “component for performing a function…” or “step for performing a function…”, such elements are expected to be interpreted in accordance with 35U.SC112(f). However, for any claim containing elements specified in any other manner, such elements are not expected to be interpreted in accordance with 35U.SC112(f).

Claims

1. A memory device comprising: Multiple memory units configured to store data; Multiple digital lines, each configured to carry data to and from a corresponding memory cell in the plurality of memory cells; and A plurality of sense amplifiers, each selectively coupled to a corresponding digital line among the plurality of digital lines, and including a first NMOS transistor and a second NMOS transistor, and a first core node and a second core node respectively coupled to the first NMOS transistor and the second NMOS transistor, wherein each sense amplifier is configured to: The first core node is charged with a first voltage, which at least partially compensates for the threshold voltage fluctuation of the first NMOS transistor caused by process, voltage or temperature fluctuations and is proportional to the threshold voltage of the first NMOS transistor. The second core node is charged with a second voltage, which at least partially compensates for the threshold voltage fluctuations of the second NMOS transistor caused by process, voltage, or temperature fluctuations and is proportional to the threshold voltage of the second NMOS transistor. The differential voltage between the first core node and the second core node is amplified by charging the first core node and discharging the second core node based at least in part on the corresponding charges from the plurality of digital lines. and The amplified differential voltage is sent as a differential signal to the corresponding digital line among the plurality of digital lines.

2. The memory device of claim 1, wherein the plurality of digital lines comprises a plurality of complementary pairs of the respective digital lines.

3. The memory device of claim 2, wherein each of each of the plurality of complementary pairs of the respective digital lines is coupled to a respective memory cell storing complementary data.

4. The memory device of claim 1, wherein the sensing amplifier includes a first digital line of the plurality of digital lines corresponding to the first core node, and a second digital line of the plurality of digital lines corresponding to the second core node.

5. The memory device of claim 4, wherein the sense amplifier includes an equalization transistor configured to equalize the first core node and the second core node before amplifying the differential voltage.

6. The memory device of claim 5, wherein the balancing of the first core node and the second core node includes receiving a logic voltage from a respective memory cell among the plurality of memory cells to charge the first digital line, which causes the second core node to discharge, wherein the discharge of the second core node causes the first core node to be charged using a power supply voltage, wherein the balancing is performed via the balancing transistor after the first core node is charged.

7. The memory device of claim 6, wherein the sense amplifier includes a cross-coupled PMOS transistor, and wherein the charging of the first core node is performed via the cross-coupled PMOS transistor using the discharging of the second core node to charge the first core node.

8. The memory device of claim 7, wherein the charging of the first core node in the differential amplification is performed via the cross-coupled PMOS transistor, wherein the equalization transistor decouples the first core node and the second core node and the second NMOS transistor discharges the second core node.

9. The memory device of claim 1, wherein the memory device operates under low-voltage operation during the charging of the first voltage, the charging of the second voltage, the amplification of the differential voltage, and the transmission of the amplified differential voltage to the respective digital line.

10. The memory device of claim 1, wherein the first NMOS transistor and the second NMOS transistor are coupled to a plurality of transistors between the first NMOS transistor and the second NMOS transistor and ground.

11. The memory device of claim 10, wherein at least two of the plurality of transistors switch at different times.

12. A memory device comprising: One or more memory units configured to store data; A pair of digital lines coupled to the one or more memory cells; and A sensing amplifier coupled to the pair of digital lines, and comprising: A cross-coupled transistor that is coupled to the power supply voltage; A first core node, which is coupled to a first transistor of the cross-coupled transistor, wherein the first core node corresponds to a first digital line of the pair of digital lines; The second core node is coupled to the second transistor of the cross-coupled transistor, wherein the second core node corresponds to the second digital line of the pair of digital lines; A third transistor is coupled to the first core node, wherein the gate of the third transistor is coupled to the second digital line; A fourth transistor, coupled to the second core node, wherein the gate of the fourth transistor is coupled to the first digital line; A first isolation transistor, coupled between the first digital line and the first core node, selectively decouples the first digital line from the first core node when amplifying the voltage difference between the first core node and the second core node; and A second isolation transistor, coupled between the second digital line and the second core node, selectively decouples the second digital line from the second core node when amplifying the voltage difference between the first core node and the second core node.

13. The memory device of claim 12, wherein the first transistor and the second transistor comprise a PMOS transistor.

14. The memory device of claim 12, wherein the first digital line is configured to be charged using a logic high value stored in a cell of the one or more memory cells.

15. The memory device of claim 14, wherein the fourth transistor is configured to use the charge of the first digital line to discharge the voltage stored in the second core node.

16. The memory device of claim 15, wherein the first transistor is configured to amplify the voltage of the first core node using the discharge voltage of the second core node, thereby amplifying the differential voltage between the first core node and the second core node.

17. The memory device of claim 12, wherein the sensing amplifier comprises: A first compensation transistor is coupled between the gate and source of the third transistor to charge the first core node with a first voltage proportional to the threshold voltage of the third transistor during a threshold voltage compensation phase. and A second compensation transistor, coupled between the gate and source of the fourth transistor, charges the second core node with a second voltage proportional to the threshold voltage of the fourth transistor during the threshold voltage compensation phase.

18. A method comprising: The first compensation transistor is used to configure the first transistor of the sense amplifier for the memory device in a first diode configuration to couple the gate terminal and the source terminal of the first transistor together, thereby charging the first core node with a first voltage proportional to the first threshold voltage of the first transistor. The second compensation transistor is used to configure the second transistor of the sense amplifier in a second diode configuration to couple the gate terminal and source terminal of the second transistor together, thereby charging the second core node with a second voltage proportional to the second threshold voltage of the second transistor; The first compensation transistor is used to disconnect the gate terminal of the first transistor from the source terminal; The gate terminal of the second transistor is disconnected from the source terminal using the second compensation transistor; Using the sensing amplifier, the voltage difference between the first core node and the second core node is amplified by the following operation: The first digital line is charged with a logic high value from the memory cell. The first digital line is configured to send data to the sensing amplifier and receive data from the sensing amplifier via the first core node; The second core node is discharged using the charging of the first digital line. and The first core node is charged using the discharge from the second core node. and The amplified voltage difference between the first core node and the second core node is transmitted as a differential signal through a pair of digital lines.

19. The method of claim 18, wherein control signals are used to perform configuring the first transistor configured as the first diode, configuring the second transistor configured as the second diode, disconnecting the gate terminal of the first transistor from the source terminal, and disconnecting the gate terminal of the first and second transistors from the source terminal to control the first compensation transistor and the second compensation transistor in series.

20. The method of claim 18, wherein charging the first core node using the discharge of the second core node is performed by connecting the second core node to the gate terminal of the PMOS transistor, and The other two terminals of the PMOS transistor are coupled to the voltage supply and the first core node, respectively.

21. The method of claim 18, further comprising equalizing the first core node and the second core node before amplifying the voltage difference caused by the voltage difference between the first digital line and a second digital line complementary to the first digital line.

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