Testable design circuit and read-write path decoupling circuit for sram

Abstract

The application discloses a testable design circuit of SRAM, and a write path circuit detection mode of a fault diagnosis logic control module, wherein the write path circuit is in a conducting state, a write data bit selector is in a selection state, a read data bit selector is in a non-selection state, a read path circuit is in a conducting state, and a storage unit is in a selection state; in a read path circuit detection mode, the write path circuit is in a non-conducting state, the write data bit selector is in the selection state, the read data bit selector is in the non-selection state, the read path circuit is in the conducting state, and the storage unit is in a non-selection state, and a bit line signal end is connected with a test signal output by a signal generation circuit. The application can improve the judgment ability and efficiency of functional failure faults existing in the write path circuit and the read path circuit in the fault diagnosis process. The application further discloses a read-write path decoupling circuit of SRAM, which can realize double-port output by using a single-port storage unit.

Description

Technical Field

[0001] This invention relates to a semiconductor integrated circuit, and more particularly to a design-testable circuit (DFT) for static random access memory (SRAM). The invention also relates to a decoupling circuit for the read / write paths of SRAM. Background Technology

[0002] Static random access memory (SRAM) is not only an indispensable component of CPU chips, but also a widely used test vehicle during advanced process development due to its high density characteristics.

[0003] like Figure 1 The diagram shows the layout of an existing SRAM; the existing SRAM includes a memory cell area 101 and an external control circuit area 102. The memory cell area 101 has an array structure composed of multiple memory cells, making it easy to locate when a fault occurs in the memory cell area 101.

[0004] The external control circuit area 102 contains input / output (IO) circuits and bit line (BL) circuits. If a fault occurs in the external control circuit area 102, the fault location in the external control circuit area 102 is difficult because the layout in the external control circuit area 102 is relatively irregular and lacks effective testability design, and the probability of successful fault diagnosis is greatly reduced.

[0005] like Figure 2 As shown, is Figure 1 An enlarged view of a unit structure of the external control circuit area 102; the external control circuit area 102 includes a read and write latch 103, a write drive circuit 104, a sensitive amplifier 105, a read and write data bit selector 106, a head circuit 107, a tail circuit 108, and a precharge circuit 109. Figure 2 In this circuit, the read and write latch 103 is also referred to as Read / Write DataLatch, the write driver circuit 104 is referred to as Write Driver, the sensitive amplifier 105 is referred to as S / A, the read and write data bit selector 106 is referred to as R / W MUX, the header circuit 107 is referred to as Header, the footer circuit 108 is referred to as Footer, and the pre-charge circuit 109 is referred to as Pre-Charge.

[0006] like Figure 3A The image shown is an SEM image 201 of the second via layer of the external control circuit region of an existing SRAM. In SEM image 201, V2 represents the second via layer, and 0.5kV and 5.0keV represent the electron beam energies.

[0007] like Figure 3BThe image shown is an SEM image 202 of the first via layer of the external control circuit region of an existing SRAM. In SEM image 202, V1 represents the first via layer, and 0.5kV and 5.0keV represent the electron beam energies.

[0008] like Figure 3C The image shown is an SEM image 203 of the zeroth via layer and the zeroth metal layer of the external control circuit region of an existing SRAM. In the SEM image 203, V0 represents the zeroth via layer, M0 represents the zeroth metal layer, and 0.5kV and 10.0keV represent the electron beam energies.

[0009] No obvious abnormalities can be detected from SEM images 201 to 203, therefore the SEM images are not able to locate the fault in the external control circuit area 102.

[0010] like Figure 4 The diagram shown is a circuit diagram of the write path circuit and read path circuit of an existing SRAM; the read path circuit includes: a sensitive amplifier 306, a read buffer 307, and a read latch 308;

[0011] The input terminal of the sensitive amplifier 306 is connected to the bit line signal terminal, the output terminal of the sensitive amplifier 306 is connected to the input terminal of the read buffer 307, the output terminal of the read buffer 307 is connected to the input terminal of the read latch 308, and the output terminal of the read latch 308 outputs a read signal.

[0012] The enable signal connected to the enable terminal of the sensitive amplifier 306 is the SAE signal; the SAEN signal is the inverted signal of the SAE signal. Figure 4 In this context, the sensitive amplifier 306 is referred to as Sense AMP., the SAEN signal is represented by / SAE, and the SAE signal is directly represented by SAE.

[0013] The enable signals connected to the enable terminal of the read buffer 307 are the SAE signal and the SAEN signal; Figure 4 In this context, the read buffer 307 is represented as a Read Buffer.

[0014] The enable signal connected to the enable terminal of the read latch 308 is either an SAE signal or a SAEN signal; Figure 4 In this context, the read latch 308 is represented as a Data Latch.

[0015] The write path circuit includes: a write selector 303, a write drive circuit 304, and a write latch (not shown).

[0016] The output end of the write drive circuit 304 is connected to the input end of the write selector 303, and the output end of the write selector 303 is the output end of the write path circuit. Figure 4 In the embodiment, the write selector 303 is denoted as Write Select.

[0017] The input end of the write drive circuit 304 is connected to the output end of the write latch, and a pair of mutually inverse data DATA and / DATA are input to the input end of the write drive circuit 304.

[0018] The input end of the write latch is connected to a write signal; Figure 4 In the embodiment, the write drive circuit 304 is denoted as Write Driver.

[0019] The enable end of the write selector 303 is connected to an enable signal WE, and the WEN signal is the inverse signal of the WE signal. Figure 4 In the embodiment, the WEN signal is denoted as / WE. The WE signal is obtained by inverting the WEN signal through an inverter.

[0020] The enable end of the write drive circuit 304 is connected to an enable signal WEN.

[0021] The storage unit area includes a plurality of storage units (bit cells) 301 to form a storage unit array (Cell Array). One storage unit stores one bit of data and is called a bit cell. The address of the storage unit 301 in the storage array needs to be determined through a word line and a bit line, Figure 4 In the embodiment, the word line of the storage unit 301 is WL0, and the bit line is BL0 and / BL0. Generally, WL0 indicates that the storage unit 301 is located in the first row, and BL0 and / BL0 indicate that the storage unit is located in the first column.

[0022] Figure 4 In the embodiment, the storage unit 301 is of a 6T structure, and the storage unit 301 is connected to a pair of bit lines BL0 and / BL0.

[0023] Generally, a pre-charge circuit 309 is also provided, and the control end of the pre-charge circuit 309 is controlled by a PRE signal, which is used to charge the bit line before reading and writing.

[0024] The working mode of the SRAM includes a write mode and a read mode.

[0025] In the write mode, the signals WE and WEN enable and turn on the write selector 303, the write drive circuit 304, and the write latch, and the output end of the write selector 303 writes data into the selected storage unit 301 through the write data bit selector 302.Figure 4 In the write mode, the address signal YW0 enables the write data bit selector 302 corresponding to the memory cell 301 in the first column, and the data is written into the selected memory cell 301. In the write mode, the SAE signal and the SAEN signal disable the sense amplifier 306, the read buffer 307 and the read latch 308, and the address signal YR0 also disables the read data bit selector 305 corresponding to the memory cell 301 in the first column. Figure 4 As shown in the figure, the last write path is shown as a mark 310.

[0026] In the read mode, the SAE signal and the SAEN signal enable the sense amplifier 306, the read buffer 307 and the read latch 308, and the address signal YR0 also enables the read data bit selector 305 corresponding to the memory cell 301 in the first column. Figure 4 In the read mode, the signal WE and the WEN disable the write selector 303, the write drive circuit 304 and the write latch, and the address signal YW0 also disables the write data bit selector 302 corresponding to the memory cell 301 in the first column. Figure 4 As shown in the figure, the last read path is shown as a mark 311.

[0027] As shown in the write path 310 and the read path 311, when the function failure of the existing SRAM is caused by the external control circuit, if the positioning range is to be reduced, the most basic work is to confirm whether the function failure is caused by the read path circuit or the write path circuit. However, this will increase the complexity of test programming and the time of artificial judgment, and further delay the fault diagnosis time. Figure 4 SUMMARY

[0028] The technical problem to be solved by the present application is to provide a testable design circuit of SRAM, which can improve the judgment ability and efficiency of the function failure fault in the write path circuit and the read path circuit in the fault diagnosis process. To this end, the present application also provides a read-write path decoupling circuit of SRAM, which can realize double-port output by using single-port memory cells, thereby improving the storage density of the SRAM with double-port function.

[0029] To solve the above technical problem, the testable design circuit of SRAM provided by the present application comprises a memory cell area and an external control circuit area.

[0030] ​The memory cell array is formed in the memory cell region.

[0031] The external control circuit region includes a write path circuit and a read path circuit.

[0032] The output end of the write path circuit and the input end of the read path circuit are connected to a bit line signal end, which is connected to the corresponding bit line through a write data bit selector and connected to the corresponding bit line through a read data bit selector.

[0033] The DFT circuit includes a fault diagnosis logic control module.

[0034] The fault diagnosis logic control module is used to control a fault diagnosis mode in a fault diagnosis process, and the fault diagnosis mode includes a write path circuit detection mode, in which the write path circuit is in an on state, the write data bit selector is in a selection state, the read data bit selector is in a non-selection state, the read path circuit is in an on state, and the memory cell is in a selection state; the write path circuit realizes writing to the memory cell, and the read path circuit realizes reading of the bit line signal end and thereby realizes detection of the write path circuit.

[0035] The fault diagnosis mode further includes a read path circuit detection mode.

[0036] In the read path circuit detection mode, the write path circuit is in a non-on state, the write data bit selector is in a selection state, the read data bit selector is in a non-selection state, the read path circuit is in an on state, and the memory cell is in a non-selection state; the bit line signal end is connected to a test signal output by a signal generation circuit, and the read path circuit realizes reading of the test signal and thereby realizes detection of the read path circuit.

[0037] Further improvement is that the read path circuit includes a sense amplifier, a read buffer, and a read latch.

[0038] The input end of the sense amplifier is connected to the bit line signal end, the output end of the sense amplifier is connected to the input end of the read buffer, the output end of the read buffer is connected to the input end of the read latch, and the output end of the read latch outputs a read signal.

[0039] The enable signal connected to the enable end of the sense amplifier is an SAE signal or an SAEN signal; the SAEN signal is an inverse signal of the SAE signal.

[0040] The enable signal connected to the enable end of the read buffer is an SAE signal or an SAEN signal.

[0041] The enable signal connected to the enable end of the read latch is an SAE signal or an SAEN signal.

[0042] The fault diagnosis logic control module comprises a DFT signal generation module, which is configured to form a DFT signal.

[0043] In the fault diagnosis detection, the DFT signal is provided to the SAE signal.

[0044] The write path circuit comprises a write selector, a write drive circuit and a write latch.

[0045] The output end of the write drive circuit is connected to the input end of the write selector, the output end of the write selector serves as the output end of the write path circuit, the input end of the write drive circuit is connected to the output end of the write latch, and the input end of the write latch is connected to a write signal.

[0046] The enable signal connected to the enable end of the write selector is a WE signal or a WEN signal, and the WEN signal is an inverse signal of the WE signal.

[0047] The enable signal connected to the enable end of the write drive circuit is a WE signal or a WEN signal, and the WEN signal is an inverse signal of the WE signal.

[0048] Further improvement is that, in the write path circuit detection mode, the DFT signal enables the sensitive amplifier, the read buffer and the read latch.

[0049] The WE signal or the WEN signal enables the write selector, the write drive circuit and the write latch.

[0050] Further improvement is that, the working mode of the SRAM comprises a write mode and a read mode.

[0051] In the write mode, the write path circuit is in a conductive state, the write data bit selector is in a selected state, the read data bit selector is in a non-selected state, the read path circuit is in a non-conductive state, and the storage unit is in a selected state.

[0052] In the read mode, the write path circuit is in a non-conductive state, the write data bit selector is in a non-selected state, the read data bit selector is in a selected state, the read path circuit is in a conductive state, and the storage unit is in a selected state.

[0053] The external control circuit area further comprises a tracking circuit, the tracking circuit comprises a tracking unit, the tracking unit has the same structure as the storage unit, the tracking unit is connected with a tracking bit line, and the tracking bit line provides a tracking bit line signal.

[0054] In the write mode, the SAE signal is provided by the tracking bit line signal and disables the sense amplifier, the read buffer and the read latch.

[0055] Further improvement is that the SAE signal is obtained by logically combining the tracking bit line signal and the DFT signal by the first logic circuit.

[0056] The write path circuit detection mode is obtained by adding the DFT signal to the write mode; in the write mode, the DFT signal is not added, and the first logic circuit takes the SAE signal as the tracking bit line signal; in the write path circuit detection mode, the DFT signal is added, the first logic circuit takes the SAE signal as the DFT signal, and the DFT signal changes the write mode to the write path circuit detection mode.

[0057] Further improvement is that when the SAE signal is high, the sense amplifier, the read buffer and the read latch are all enabled.

[0058] The first logic circuit is a first OR gate.

[0059] Further improvement is that in the write mode, a write address signal is added to the selection end of the write data bit selector to make the write data bit selector in a selection state.

[0060] In the read mode, a read address signal is added to the selection end of the read data bit selector to make the read data bit selector in a selection state.

[0061] Further improvement is that in the read path circuit detection mode, the DFT signal is added to the selection end of the read data bit selector to make the read data bit selector in a non-selection state.

[0062] The test signal is obtained from the tracking bit line signal.

[0063] Further improvement is that the bit line connected with each storage unit comprises a non-inverted bit line and an inverted bit line.

[0064] The bit line signal end comprises a non-inverted bit line signal end and an inverted bit line signal end.

[0065] The tracking bit line includes a non-inverted tracking bit line and an inverted tracking bit line, and the tracking bit line signal includes a non-inverted tracking bit line signal and an inverted tracking bit line signal.

[0066] The signal generating circuit adopts the tracking circuit, and the test signal is obtained from the inverted tracking bit line signal.

[0067] Further improvement is that the signal of the selection end of the read data bit selector is obtained by logical combination of the read address signal and the DFT signal by the second logic circuit.

[0068] The inverted tracking bit line signal is input to the input end of the third logic circuit, and the output end of the third logic circuit outputs the test signal under the control of the control signal.

[0069] The read path circuit detection mode is based on the read mode, and the storage unit is in a non-selection state and the DFT signal and the control signal of the third logic circuit are added.

[0070] In the read mode, the DFT signal and the control signal of the third logic circuit are not added, the second logic circuit makes the signal of the selection end of the read data bit selector be the read address signal, and the third logic circuit makes the test signal not output to the bit line signal end; in the read path circuit detection mode, the DFT signal and the control signal of the third logic circuit are added, the second logic circuit makes the signal of the selection end of the read data bit selector be the DFT signal, and the third logic circuit makes the test signal output to the bit line signal end.

[0071] Further improvement is that the read data bit selector is in a selection state when the signal of the selection end of the read data bit selector is low, and the read data bit selector is in a non-selection state when the signal of the selection end of the read data bit selector is high.

[0072] The second logic circuit is a first NOR gate.

[0073] Further improvement is that the third logic circuit includes a first transmission gate and a second transmission gate.

[0074] The input end of the first transmission gate is connected to the inverted tracking bit line signal, and the output end of the first transmission gate is connected to the non-inverted bit line signal end.

[0075] The input end of the second transmission gate is connected to the inverted tracking bit line signal, and the output end of the second transmission gate is connected to the inverted bit line signal end.

[0076] The control signal of the third logic circuit includes a first selection signal and a second selection signal which are inversely connected to each other.

[0077] The non-inverting control terminal of the first transmission gate and the inverting control terminal of the second transmission gate are connected to the first selection signal.

[0078] The inverting control terminal of the first transmission gate and the non-inverting control terminal of the second transmission gate are connected to the second selection signal.

[0079] To solve the above technical problems, the SRAM read-write path decoupling circuit provided by the application comprises a storage unit area and an external control circuit area.

[0080] The storage unit area is formed with a storage unit array arranged by a plurality of storage units, and the storage units in the same column are connected to the same bit line.

[0081] The external control circuit area comprises a write path circuit and a read path circuit.

[0082] The output end of the write path circuit and the input end of the read path circuit are both connected to a bit line signal end, the bit line signal end is connected to the corresponding bit line through a write data bit selector, and the bit line signal end is connected to the corresponding bit line through a read data bit selector.

[0083] Each storage unit adopts a 1RW single-port structure.

[0084] The read-write path decoupling circuit is used to realize a read-write mode in the working process of the SRAM, in which the write path circuit is in a conduction state, the write data bit selector is in a selection state, the read data bit selector is in a non-selection state, the read path circuit is in a conduction state, and the storage unit is in a selection state; the write path circuit realizes writing to the storage unit and makes the input end of the write path circuit as a write port, the read path circuit realizes reading to the bit line signal end and makes the output end of the read path circuit as a read port, so that the storage unit with the 1RW single-port structure realizes the function of a double-port, thereby improving the storage density.

[0085] Further improvement is that the read path circuit comprises a sense amplifier, a read buffer and a read latch.

[0086] The input end of the sense amplifier is connected to the bit line signal end, the output end of the sense amplifier is connected to the input end of the read buffer, the output end of the read buffer is connected to the input end of the read latch, and the output end of the read latch outputs a read signal.

[0087] The enable signal connected to the enable end of the sense amplifier is an SAE signal or an SAEN signal; the SAEN signal is an inverting signal of the SAE signal.

[0088] The enable signal connected to the enable end of the read buffer is an SAE signal or an SAEN signal.

[0089] The enable signal connected to the enable end of the read latch is an SAE signal or an SAEN signal.

[0090] The write path circuit comprises a write selector, a write drive circuit and a write latch.

[0091] The output end of the write drive circuit is connected to the input end of the write selector, the output end of the write selector is the output end of the write path circuit, the input end of the write drive circuit is connected to the output end of the write latch, and the input end of the write latch is connected to a write signal.

[0092] The enable signal connected to the enable end of the write selector is a WE signal or a WEN signal, and the WEN signal is an inverse signal of the WE signal.

[0093] The enable signal connected to the enable end of the write drive circuit is a WE signal or a WEN signal, and the WEN signal is an inverse signal of the WE signal.

[0094] The read-write path decoupling circuit comprises a fourth logic circuit, and in the read-write mode, the fourth logic circuit provides a read-write control signal to the SAE signal.

[0095] Further improvement is that the fourth logic circuit comprises a first OR gate, a D flip-flop and a second OR gate.

[0096] The first input end of the second OR gate is connected to a write clock signal, the second input end is connected to a read clock signal, and the output end of the second OR gate is connected to the reset end of the D flip-flop.

[0097] The clock end of the D flip-flop is connected to an address change detection signal, and the D end is connected to an operating voltage.

[0098] The first input end of the first OR gate is connected to the Q end of the D flip-flop, the second input end of the first OR gate is connected to a tracking bit line signal, and the output end of the first OR gate outputs the SAE signal.

[0099] The fault diagnosis logic control module of the testability design circuit of the SRAM of the application can set a control fault diagnosis mode in the fault diagnosis process, wherein the write path circuit detection mode can turn on the read path circuit under the condition of writing the storage unit through the write path circuit, so that the detection of the write path circuit can be realized through the reading of the read path circuit; and the read path circuit detection mode can turn off the reading of the storage unit under the condition of turning on the read path circuit and change to read the set test signal, so that the detection of the read path circuit can be realized, and the judgment ability and efficiency of the functional failure fault occurring in the write path circuit and the read path circuit can be improved in the fault diagnosis process.

[0100] The read-write path decoupling circuit of the SRAM of the application can realize the read-write mode by changing the write path circuit detection mode of the testability design circuit, can realize the writing operation and the reading operation of the storage unit with the 1RW single-port structure in the same read-write cycle, and makes the storage unit with the 1RW single-port structure realize the function of the double-port, so that the storage density of the SRAM with the double-port function can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0101] The application will be further described in detail below in combination with the drawings and specific embodiments:

[0102] Figure 1 is the layout of the existing SRAM;

[0103] Figure 2 is Figure 1 is an enlarged view of a unit structure of the external control circuit area in the application;

[0104] Figure 3A is the SEM photo of the second via layer of the external control circuit area of the existing SRAM;

[0105] Figure 3B is the SEM photo of the first via layer of the external control circuit area of the existing SRAM;

[0106] Figure 3C is the SEM photo of the zeroth via layer and the zeroth metal layer of the external control circuit area of the existing SRAM;

[0107] Figure 4 is the circuit diagram of the write path circuit and the read path circuit of the existing SRAM;

[0108] Figure 5A is the circuit diagram of the testability design circuit of the SRAM of the embodiment of the application in the write path circuit detection mode;

[0109] Figure 5Bis a circuit diagram of the testability design circuit of the SRAM of the embodiment of the present application in the read path circuit detection mode;

[0110] Figure 6A is a circuit diagram of the testability design circuit of the SRAM of the preferred embodiment of the present application in the write path circuit detection mode;

[0111] Figure 6B is a circuit diagram of the testability design circuit of the SRAM of the preferred embodiment of the present application in the read path circuit detection mode;

[0112] Figure 7A is a circuit diagram of the 1RW 6T memory cell of the SRAM of the embodiment of the present application;

[0113] Figure 7B is a circuit diagram of the 1R1W 8T memory cell of the prior art SRAM;

[0114] Figure 7C is Figure 7B is a circuit diagram of the write path and the read path of the 1R1W 8T memory cell of the prior art SRAM shown in

[0115] Figure 7D is Figure 7B is a signal change over time diagram of the 1R1W 8T memory cell of the prior art SRAM in three read-write cycles shown in

[0116] Figure 8 is a circuit diagram of the read-write path decoupling circuit of the SRAM of the embodiment of the present application. DETAILED DESCRIPTION

[0117] As shown in Figure 5A is a circuit diagram of the testability design circuit of the SRAM of the embodiment of the present application in the write path circuit detection mode; As shown in Figure 5B is a circuit diagram of the testability design circuit of the SRAM of the embodiment of the present application in the read path circuit detection mode; In the testability design circuit of the SRAM of the embodiment of the present application, the SRAM comprises a memory cell region and an external control circuit region.

[0118] As shown in Figure 5A The memory cell region is formed with a memory cell array 401 arranged by a plurality of memory cells, and the memory cells in the same column are connected to the same bit line. In the embodiment of the present application, the memory cell is connected with a pair of mutually opposite bit lines BL and / BL. The memory cell is selected by a word line and a bit line. Figure 5A In the embodiment of the present application, the memory cell array 401 is also represented as Cell Array, and the structure of the memory cell in the memory cell array 401 is not shown separately.

[0119] The structure of the storage unit in the embodiment of the application adopts a 1RW 6T storage unit as shown in the figure Figure 7A The 1 in 1RW represents one port, R represents reading, W represents writing, 1RW represents reading and writing simultaneously using one port, and 6T represents that six transistors are included in one of the storage units, and the six transistors are a first selection transistor 501, a second selection transistor 502, a first pull-up transistor 503, a second pull-up transistor 504, a first pull-down transistor 505, and a second pull-down transistor 506. The gate of the first selection transistor 501 and the gate of the second selection transistor 502 are connected to a word line WL, the drain of the first selection transistor 501 is connected to a bit line BL, and the drain of the second selection transistor 502 is connected to the bit line BL. Figure 7A In the figure, the first selection transistor 501 is also denoted by PG1, the second selection transistor 502 is also denoted by PG2, the first pull-up transistor 503 is also denoted by PU1, the second pull-up transistor 504 is also denoted by PU2, the first pull-down transistor 505 is also denoted by PD1, and the second pull-down transistor 506 is also denoted by PD2.

[0120] The external control circuit region includes a write path circuit and a read path circuit.

[0121] The output end of the write path circuit and the input end of the read path circuit are both connected to a bit line signal end, the bit line signal end is connected to the corresponding bit line through a write data bit selector 402, and the bit line signal end is connected to the corresponding bit line through a read data bit selector 405. As shown in FIG. 5, in the embodiment of the application, the write data bit selector 402 is composed of two NMOS transistors, and the read data bit selector 405 is composed of two PMOS transistors.

[0122] The design-for-testability circuit includes a fault diagnosis logic control module.

[0123] The fault diagnosis logic control module is used to control a fault diagnosis mode in a fault diagnosis process.

[0124] As shown in the figure Figure 5A The fault diagnosis mode includes a write path circuit detection mode, in which the write path circuit is in an on state, the write data bit selector 402 is in a selection state, the read data bit selector 405 is in a non-selection state, the read path circuit is in an on state, and the storage unit is in a selection state; the write path circuit realizes writing to the storage unit, the read path circuit realizes reading of the bit line signal end and thereby realizes detection of the write path circuit. Figure 5A In the figure, the read data bit selector 405 in the non-selection state is also denoted by Deselect.

[0125] As shown in Figure 5B The read path circuit detection mode further includes that the write path circuit is in a non-conductive state, the write data bit selector 402 is in a selection state, the read data bit selector 405 is in a non-selection state, the read path circuit is in a conductive state, and the storage unit is in a non-selection state, the bit line signal end is connected to the test signal output by the signal generation circuit 507, the read path circuit realizes reading of the test signal and thereby realizes detection of the read path circuit. Figure 5B In the read path circuit detection mode, the signal generation circuit 507 is also represented as Signal Generation.

[0126] In the embodiment of the present application, the read path circuit includes a sense amplifier 406, a read buffer 407, and a read latch 408.

[0127] The input end of the sense amplifier 406 is connected to the bit line signal end, the output end of the sense amplifier 406 is connected to the input end of the read buffer 407, the output end of the read buffer 407 is connected to the input end of the read latch 408, and the output end of the read latch 408 outputs a read signal.

[0128] The enable signal connected to the enable end of the sense amplifier 406 is an SAE signal or an SAEN signal; the SAEN signal is an inverse signal of the SAE signal.

[0129] The enable signal connected to the enable end of the read buffer 407 is an SAE signal or an SAEN signal. Figure 5A As shown, the read buffer 407 is composed of an inverter with an enable end.

[0130] The enable signal connected to the enable end of the read latch 408 is an SAE signal or an SAEN signal. Figure 5A As shown, the read latch 408 is formed by interlocking an inverter with an enable end and an inverter without an enable end.

[0131] The fault diagnosis logic control module includes a DFT signal generation module, and the DFT signal generation module is used to form a DFT signal.

[0132] In the fault diagnosis detection, the DFT signal is provided to the SAE signal.

[0133] In the embodiment of the present application, the write path circuit includes a write selector 403, a write drive circuit 404, and a write latch (not shown).

[0134] The output terminal of the write driver circuit 404 is connected to the input terminal of the write selector 403. The output terminal of the write selector 403 serves as the output terminal of the write path circuit. The input terminal of the write driver circuit 404 is connected to the output terminal of the write latch. The input terminal of the write latch is connected to the write signal.

[0135] The enable signal connected to the enable terminal of the write selector 403 is either the WE signal or the WEN signal, where the WEN signal is the inverted version of the WE signal. Figure 5A As shown, the write selector 403 consists of a pair of NMOS transistors.

[0136] The enable signal connected to the enable terminal of the write drive circuit 404 is either the WE signal or the WEN signal, where the WEN signal is the inverted signal of the WE signal.

[0137] In this embodiment of the invention, in the write path circuit detection mode, the DFT signal enables the sensitive amplifier 406, the read buffer 407, and the read latch 408.

[0138] The WE signal or the WEN signal enables the write selector 403, the write drive circuit 404, and the write latch.

[0139] The SRAM operates in two modes: write mode and read mode.

[0140] like Figure 5A As shown, in the write mode, the write path circuit is in the ON state, the write data bit selector 402 is in the OFF state, the read data bit selector 405 is in the OFF state, the read path circuit is in the OFF state, and the memory cell is in the OFF state. The OFF state of the read path circuit is also the sensitive amplifier 406, the read buffer 407, and the read latch 408.

[0141] Comparing the write path circuit detection mode and the write mode, the difference is that the read path circuit is in the on state in the write path circuit detection mode. Therefore, the write path circuit detection mode can be obtained by enabling the sensitive amplifier 406, the read buffer 407, and the read latch 408 based on the write mode. Figure 5ADisable means non-enabled, Enable means enabled, and Disable→Enable means switching the circuits in the dashed box 501 and the dashed box 502 from non-enabled to enabled, which visually shows the switching from the write mode to the write path circuit detection mode. The dashed box 501 has the sense amplifier 406, and the dashed box 502 has the read buffer 407 and the read latch 408. In the write path circuit detection mode, two conduction paths are included, which are a first conduction path 503 and a second conduction path 504 represented by dashed lines with arrows. The first conduction path 503 includes a write path; and the second conduction path 504 is a read path that directly reads from the bit line signal end. The second conduction path 504 does not read the memory cell through the read data bit selector 405, but can still read the written data by reading the bit line signal end. Figure 5A In the write path circuit detection mode, the sense amplifier 406 is in a non-enabled state, and the read buffer 407 and the read latch 408 are in an enabled state. The sense amplifier 406 is represented by Sense AMP., and it can be seen that, in the write mode, the originally closed sense amplifier 406, the read buffer 407, and the read latch 408 are opened, so that data can be read out while writing data, and thus whether the write path is normal can be detected.

[0142] In the read mode, the write path circuit is in a non-conduction state, the write data bit selector 402 is in a non-selection state, the read data bit selector 405 is in a selection state, the read path circuit is in a conduction state, and the memory cell is in a selection state. The write path circuit being in a non-conduction state means that the write selector 403, the write drive circuit 404, and the write latch are non-enabled, that is Figure 5B The circuits in the area represented by the dashed box 506 in the read mode are in a Disable state, and the circuits in the dashed box 506 include the write selector 403, the write drive circuit 404, and the write latch. Compared with the read mode, in the read path circuit detection mode, the circuits in the area represented by the dashed box 505 are switched from a selection state to a non-selection state while keeping the circuits in the area represented by the dashed box 506 in a Disable state, Figure 5BIn the figure, the Select→Deselect indicates that the selection state is switched to the non-selection state, wherein the Select indicates the selection state. The circuit in the dashed box 506 includes the memory cell in the memory array 401 and the read data bit selector 405, so that even if the write data bit selector 402 is in the selection state, the data in the memory cell will not be read out, and the read path is the second conduction path 504 shown by the arrowed dashed line; the read data is the test signal output by the signal generation circuit 507, and since the test signal is a known signal preset in advance, the test signal can be read to determine whether the read path is correct.

[0143] As shown in the figure, the testability design circuit of the SRAM of the preferred embodiment of the present application is in the write path circuit detection mode. Figure 6A As shown in the figure, the testability design circuit of the SRAM of the preferred embodiment of the present application is in the write path circuit detection mode. Figure 5A As shown in the figure, the testability design circuit of the SRAM of the preferred embodiment of the present application is in the write path circuit detection mode. Figure 6A As shown in the figure, the testability design circuit of the SRAM of the preferred embodiment of the present application is in the write path circuit detection mode. Figure 6A In the figure, a selected memory cell 401a is shown, and the memory cell 401a is in the selection state in the write path circuit detection mode. Figure 5A The address of the memory cell 401a in the memory array 401 needs to be determined by the word line and the bit line. Figure 6A In the figure, the word line of the memory cell 401a is WL0, and the bit line is BL0 and / BL0. Generally, WL0 indicates that the memory cell 401a is located in the first row, and BL0 and / BL0 indicate that the memory cell is located in the first column. Figure 6A In the figure, the memory cell 401a adopts the 1RW 6T memory cell shown in the figure. Figure 7A In the figure, the memory cell 401a adopts the 1RW 6T memory cell shown in the figure.

[0144] The pre-charge circuit 409 connected with the bit line and used for pre-charging the bit line is provided, and the control end of the pre-charge circuit 409 is controlled by the PRE signal, which is used for charging the bit line before reading and writing.

[0145] The write data bit selector 402 is in the selection state by turning on the two NMOS tubes of the write data bit selector 402 through the write address signal YW0.

[0146] Figure 6A In the figure, the SAEN signal is represented by / SAE, and the SAE signal is directly represented by SAE.

[0147] The enable signal connected with the enable end of the sense amplifier 406 is the SAE signal.

[0148] The enable signal connected with the enable end of the read buffer 407 is the SAE signal and the SAEN signal.

[0149] The enable signal connected to the enable end of the read latch 408 is the SAE signal or the SAEN signal.

[0150] The WEN signal is represented by / WE. The WE signal (not shown) is obtained by inverting the WEN signal through an inverter.

[0151] The data input into the input end of the write drive circuit 404 is a pair of mutually inverted data DATA and / DATA.

[0152] As shown in Figure 6B The external control circuit area further includes a tracking circuit 413, which includes a tracking unit 415. The tracking unit 415 has the same structure as the storage unit, and is connected to a tracking bit line, which provides a tracking bit line signal. Figure 6B In the tracking unit 415, the tracking bit line is represented by Tracking BL, and there are a pair of two in total.

[0153] As shown in Figure 6A In the write mode, the SAE signal is provided by the tracking bit line signal and disables the sense amplifier 406, the read buffer 407 and the read latch 408. Figure 6A In the tracking unit 415, the tracking bit line signal provided to the SAE signal is represented by Trk BL alone.

[0154] The SAE signal is obtained by logically combining the tracking bit line signal and the DFT signal through the first logic circuit 410. The write path circuit detection mode is obtained by adding the DFT signal to the write mode; in the write mode, the DFT signal is not added, and the first logic circuit 410 takes the SAE signal as the tracking bit line signal; in the write path circuit detection mode, the DFT signal is added, and the first logic circuit 410 takes the SAE signal as the DFT signal, and the DFT signal changes the write mode to the write path circuit detection mode.

[0155] The SAE signal enables the sense amplifier 406, the read buffer 407 and the read latch 408 when it is at a high level. The first logic circuit 410 is a first OR gate. In other embodiments, the first logic circuit 410 can also be composed of other circuits that can achieve the same logic.

[0156] As shown in Figure 6BAs shown, in the read mode, the read address signal YR0 is input to the selection terminal of the read data bit selector 405 to make the read data bit selector 405 in the selected state.

[0157] In the detection mode of the read path circuit, the DFT signal is input to the selection terminal of the read data bit selector 405 to make the read data bit selector 405 in the non-selected state.

[0158] The test signal is obtained from the tracking bit line signal.

[0159] The bit line connected to each of the memory cells includes a non-inverted bit line and an inverted bit line.

[0160] The bit line signal terminal includes a non-inverted bit line signal terminal and an inverted bit line signal terminal.

[0161] The tracking bit line includes a non-inverted tracking bit line and an inverted tracking bit line, and the tracking bit line signal includes a non-inverted tracking bit line signal and an inverted tracking bit line signal.

[0162] The signal generation circuit 507 adopts the tracking circuit 413, and the test signal is obtained from the inverted tracking bit line signal in the tracking bit line signal.

[0163] The signal of the selection terminal of the read data bit selector 405 is obtained by the second logic circuit 411 logically combining the read address signal YR0 and the DFT signal.

[0164] The inverted tracking bit line signal is input to the input terminal of the third logic circuit 412, and the output terminal of the third logic circuit 412 outputs the test signal under the control of the control signal. By Figure 6B As shown, there is a delay circuit between the inverted tracking bit line signal provided to the first logic circuit 411 and the inverted tracking bit line signal provided to the third logic circuit 412, and the delay circuit is Figure 6B delay in the middle.

[0165] The detection mode of the read path circuit is based on the read mode, making the memory cell in the non-selected state and inputting the DFT signal and the control signal of the third logic circuit 412.

[0166] In the read mode, the DFT signal and the control signal of the third logic circuit 412 are not added, the second logic circuit 411 makes the signal of the selection end of the read data bit selector 405 be the read address signal YR0, and the third logic circuit 412 makes the test signal not output to the bit line signal end; in the read path circuit detection mode, the DFT signal and the control signal of the third logic circuit 412 are added, the second logic circuit 411 makes the signal of the selection end of the read data bit selector 405 be the DFT signal, and the third logic circuit 412 makes the test signal output to the bit line signal end.

[0167] The read data bit selector 405 is in the selection state when the signal of the selection end of the read data bit selector 405 is low, and the read data bit selector 405 is in the non-selection state when the signal of the selection end of the read data bit selector 405 is high.

[0168] The second logic circuit 411 is a first NOR gate.

[0169] The third logic circuit 412 comprises a first transmission gate 412a and a second transmission gate 412b.

[0170] The input end of the first transmission gate 412a is connected to the inverted tracking bit line signal, and the output end of the first transmission gate 412a is connected to the non-inverted bit line signal end.

[0171] The input end of the second transmission gate 412b is connected to the inverted tracking bit line signal, and the output end of the second transmission gate 412b is connected to the inverted bit line signal end.

[0172] The control signal of the third logic circuit 412 comprises a first selection signal SEL0 and a second selection signal SEL0_n which are mutually inverted.

[0173] The non-inverted control end of the first transmission gate 412a and the inverted control end of the second transmission gate 412b are connected to the first selection signal SEL0.

[0174] The inverted control end of the first transmission gate 412a and the non-inverted control end of the second transmission gate 412b are connected to the second selection signal SEL0_n.

[0175] The fault diagnosis logic control module of the testability design circuit of the SRAM embodiment can set a control fault diagnosis mode in a fault diagnosis process, wherein the write path circuit detection mode can turn on the read path circuit under the condition of writing the storage unit through the write path circuit, so that the detection of the write path circuit can be realized through the reading of the read path circuit; and the read path circuit detection mode can turn off the reading of the storage unit under the condition of turning on the read path circuit and change to read the set test signal, so that the detection of the read path circuit can be realized, and the judgment ability and efficiency of the functional failure fault occurring in the write path circuit and the read path circuit can be improved in the fault diagnosis process.

[0176] As Figure 7B shown, it is a circuit diagram of a 1R1W 8T storage unit of the existing SRAM; wherein 1R represents one read port, 1W represents one write port, and 8T represents eight transistors. The eight transistors are a first selection transistor 601, a second selection transistor 602, a first pull-up transistor 603, a second pull-up transistor 604, a first pull-down transistor 605, a second pull-down transistor 606, a read selection transistor 607, and a read pull-down transistor 608. The gate of the first selection transistor 601 and the gate of the second selection transistor 602 are connected to a write word line WWL, the drain of the first selection transistor 601 is connected to a bit line / BL, and the drain of the second selection transistor 602 is connected to a bit line BL. Figure 7B In the figure, the first selection transistor 601 is also represented by PG1, the second selection transistor 602 is also represented by PG2, the first pull-up transistor 603 is also represented by PU1, the second pull-up transistor 604 is also represented by PU2, the first pull-down transistor 605 is also represented by PD1, and the second pull-down transistor 606 is also represented by PD2. The read selection transistor 607 is also represented by RPG, and the read pull-down transistor 608 is also represented by RPD. Figure 7A As Figure 7B shown, the read selection transistor 607 and the read pull-down transistor 608 in the dashed box 609 are added. The bit line of the read selection transistor 607 is connected to a read bit line RBL, and the gate of the read selection transistor 607 is connected to a read word line RWL. The gate of the read pull-down transistor 608 is connected to a storage node Q.

[0177] The signals of the write word line WWL and the bit line / BL and BL can be added from the write port alone, the signals of the read word line RWL and the read bit line RBL can be added from the read port alone, so that the functions of reading and writing can be realized at the same time in the same read-write cycle. As Figure 7C shown, it is a circuit diagram of a 1R1W 8T storage unit of the existing SRAM; wherein 1R represents one read port, 1W represents one write port, and 8T represents eight transistors. The eight transistors are a first selection transistor 601, a second selection transistor 602, a first pull-up transistor 603, a second pull-up transistor 604, a first pull-down transistor 605, a second pull-down transistor 606, a read selection transistor 607, and a read pull-down transistor 608. The gate of the first selection transistor 601 and the gate of the second selection transistor 602 are connected to a write word line WWL, the drain of the first selection transistor 601 is connected to a bit line / BL, and the drain of the second selection transistor 602 is connected to a bit line BL. Figure 7BThe circuit diagram of the write path and the read path of the 1R1W 8T memory cell of the existing SRAM shown; the write path of data 1 is shown as the arrowed dashed line 610, the write path of data 0 is shown as the arrowed dashed line 611, and the read path is shown as the arrowed dashed line 612.

[0178] As shown in Figure 7D As shown in Figure 7B The signal-time diagrams of the 1R1W 8T memory cell of the existing SRAM in three read-write cycles are shown in Figure 7D The three read-write cycles are respectively denoted by the marks 701, 702 and 703, and the cycle sizes are the same and all use Same Cycle to denote.

[0179] Figure 7D The WWL signal in the above represents the signal of the write word line WWL, the RWL signal represents the signal of the read word line WWL, the RBL signal represents the signal of the read bit line RBL, and the SAE signal represents the enable signal of the sense amplifier.

[0180] In the read-write cycle 701, the WWL signal is earlier than the RWL signal, which is write first and then read; in the read-write cycle 702, the WWL signal is synchronous with the RWL signal, which will read and write at the same time; in the read-write cycle 703, the WWL signal is later than the RWL signal, which is read first and then write.

[0181] From the change of the RWL signal, it can be seen that in the read-write cycle 701, the high level of the RWL signal will decrease at the falling edge of the WWL signal, so it has Figure 7D a negative skew as shown in the above, which makes the actual falling line of the RWL signal be the solid line 706, which is greater than the value of the dashed line 705, and the difference between the solid line 706 and the reference line 704 is ΔRBL1.

[0182] In the read-write cycle 702, the high level of the RWL signal will not change, that is, it has Figure 7D a zero skew as shown in the above, which makes the actual falling line of the RWL signal be the line 705, and the difference between the line 705 and the reference line 704 is ΔRBL.

[0183] In the read-write cycle 703, the high level of the RWL signal will increase at the rising edge of the WWL signal, so it has Figure 7D a positive skew as shown in the above, which makes the actual falling line of the RWL signal be the solid line 707, which is less than the value of the dashed line 705, and the difference between the solid line 707 and the reference line 704 is ΔRBL2.

[0184] It can be seen that ΔRBL1 is less than ΔRBL, and ΔRBL2 is greater than ΔRBL. Therefore, the read window of ΔRBL2 is larger.

[0185] and Figure 7A compared with the 1RW 6T memory cell shown in Figure 7B The 1R1W 8T memory cell shown in

[0186] As Figure 8 shown in the circuit diagram of the read-write path decoupling circuit of the SRAM embodiment of the present application. In the read-write path decoupling circuit of the SRAM embodiment of the present application, the SRAM includes a memory cell area and an external control circuit area.

[0187] The memory cell area is formed with a memory cell array arranged by a plurality of memory cells 801, and the memory cells 801 in the same column are connected to the same bit line. Figure 8 A selected memory cell 801 is shown in Figure 8 The word line of the memory cell 801 shown in is WL0, and the bit line is BL0 and / BL0. Generally, WL0 indicates that the memory cell 801 is located in the first row, and BL0 and / BL0 indicate that the memory cell 801 is located in the first column. Figure 8 The memory cell 801 shown in Figure 7A uses the 1RW 6T memory cell shown in

[0188] A pre-charge circuit 809 connected to the bit line and used for pre-charging the bit line is provided, and the control end of the pre-charge circuit 809 is controlled by a PRE signal, which is used for charging the bit line before reading and writing.

[0189] The external control circuit area includes a write path circuit and a read path circuit.

[0190] The output end of the write path circuit and the input end of the read path circuit are both connected to a bit line signal end, and the bit line signal end is connected to the corresponding bit line through a write data bit selector 802; the bit line signal end is connected to the corresponding bit line through a read data bit selector 805.

[0191] The read-write path decoupling circuit is used for realizing a read-write mode in the working process of the SRAM, in which the write path circuit is in a conducting state, the write data bit selector 802 is in a selected state, the read data bit selector 805 is in a non-selected state, the read path circuit is in a conducting state, and the memory cell 801 is in a selected state. Figure 8As shown in the figure, the arrowed dashed line 901 represents the conducting path of writing data DATA and / DATA into the memory cell 801 through the write path circuit; the arrowed dashed line 902 represents the conducting path of reading data through the read path circuit. The write path circuit realizes the writing of the memory cell 801 and makes the input end of the write path circuit as the write port 815; the read path circuit realizes the reading of the bit line signal end and makes the output end of the read path circuit as the read port 814, which makes the 1RW single-port structure of the memory cell 801 realize the function of the dual-port, thereby improving the storage density. Figure 8 In some embodiments, the write port 815 is also denoted as Write Port, and the read port 814 is also denoted as Read Port.

[0192] The read path circuit comprises a sense amplifier 806, a read buffer 807 and a read latch 808.

[0193] The input end of the sense amplifier 806 is connected to the bit line signal end, the output end of the sense amplifier 806 is connected to the input end of the read buffer 807, the output end of the read buffer 807 is connected to the input end of the read latch 808, and the output end of the read latch 808 outputs a read signal.

[0194] The enable signal connected to the enable end of the sense amplifier 806 is the SAE signal or the SAEN signal; the SAEN signal is the inverse signal of the SAE signal. Figure 8 In some embodiments, the SAEN signal is denoted as / SAE, and the SAE signal is directly denoted as SAE. In some embodiments, the enable signal connected to the enable end of the sense amplifier 806 is the SAE signal.

[0195] The enable signal connected to the enable end of the read buffer 807 is the SAE signal or the SAEN signal. Figure 8 As shown in the figure, the read buffer 807 is composed of an inverter with an enable end. In some embodiments, the enable signal connected to the enable end of the read buffer 807 is the SAE signal and the SAEN signal.

[0196] The enable signal connected to the enable end of the read latch 808 is the SAE signal or the SAEN signal. Figure 8 As shown in the figure, the read latch 808 is formed by interlocking an inverter with an enable end and an inverter without an enable end. In some embodiments, the enable signal connected to the enable end of the read latch 808 is the SAE signal or the SAEN signal.

[0197] The write path circuit includes a write selector 803, a write driver circuit 804, and a write latch (not shown).

[0198] An output of the write driver circuit 804 is connected to an input of the write selector 803, an output of the write selector 803 is an output of the write path circuit, an input of the write driver circuit 804 is connected to an output of the write latch, and an input of the write latch is connected to a write signal.

[0199] An enable signal connected to an enable terminal of the write selector 803 is a WE signal or a WEN signal, and the WEN signal is an inverse signal of the WE signal. In some embodiments, the enable signal connected to the enable terminal of the write selector 803 is the WE signal, and the enable signal connected to the enable terminal of the write driver circuit 804 is the WEN signal. Figure 8 As shown, the write selector 803 is composed of a pair of NMOS. Figure 8 In some embodiments, the WEN signal is represented as / WE. The WE signal is obtained by inverting the WEN signal through an inverter (not shown).

[0200] An enable signal connected to an enable terminal of the write driver circuit 804 is a WE signal or a WEN signal, and the WEN signal is an inverse signal of the WE signal. In some embodiments, the enable signal connected to the enable terminal of the write selector 803 is the WE signal, and the enable signal connected to the enable terminal of the write driver circuit 804 is the WEN signal.

[0201] Data input to an input of the write driver circuit 804 is a pair of inverse data DATA and / DATA.

[0202] The read-write path decoupling circuit includes a fourth logic circuit 810, and in the read-write mode, the fourth logic circuit 810 provides a read-write control signal to the SAE signal.

[0203] In some embodiments, the fourth logic circuit 810 includes a first OR gate 811, a D flip-flop 812, and a second OR gate 813.

[0204] A first input of the second OR gate 813 is connected to a write clock signal WCLK, and a second input of the second OR gate 813 is connected to a read clock signal RCLK. An output of the second OR gate 813 is connected to a reset terminal of the D flip-flop 812.

[0205] A clock terminal of the D flip-flop 812 is connected to an address transition detection signal ATD_ADDR, and a D terminal of the D flip-flop 812 is connected to a working voltage VDD. ATD represents Address Transition Detection.

[0206] The first input end of the first OR gate 811 is connected with the Q end of the D flip-flop 812, the second input end of the first OR gate 811 is connected with a track bit line signal, and the output end of the first OR gate 811 outputs the SAE signal.

[0207] The read-write path decoupling circuit of the SRAM of the embodiment of the present application can realize the read-write mode by changing the write path circuit detection mode of the testability design circuit, can realize the write operation and the read operation of the storage unit 801 with the 1RW single-port structure in the same read-write cycle, makes the storage unit 801 with the 1RW single-port structure realize the function of the double-port, and thus can improve the storage density of the SRAM with the double-port function. Figure 8 As shown in the figure, the storage unit 801 in the read-write path decoupling circuit of the SRAM of the embodiment of the present application still adopts the 1RW 6T storage unit as shown in the figure, but the SRAM of the embodiment of the present application can also realize the read operation and the write operation at the same time, which is equivalent to realizing the function of the double-port. Figure 7A As shown in the figure, the storage unit 801 in the read-write path decoupling circuit of the SRAM of the embodiment of the present application still adopts the 1RW 6T storage unit as shown in the figure, but the SRAM of the embodiment of the present application can also realize the read operation and the write operation at the same time, which is equivalent to realizing the function of the double-port. Figure 7B As shown in the figure, the storage unit 801 in the read-write path decoupling circuit of the SRAM of the embodiment of the present application still adopts the 1RW 6T storage unit as shown in the figure, but the SRAM of the embodiment of the present application can also realize the read operation and the write operation at the same time, which is equivalent to realizing the function of the double-port.

[0208] The above has carried on the detailed explanation to the present application through the specific embodiment, but these do not constitute the limitation to the present application. In the case of not departing from the principle of the present application, the person skilled in the art can also make many variations and improvements, and these also should be regarded as the protection scope of the present application.

Claims

1. A testability design circuit of SRAM, characterized in that: the SRAM comprises a memory cell region and an external control circuit region; the memory cell region is formed with a memory cell array arranged by a plurality of memory cells, and the memory cells in the same column are connected to the same bit line; the external control circuit region comprises a write path circuit and a read path circuit; the output end of the write path circuit and the input end of the read path circuit are both connected to a bit line signal end, the bit line signal end is connected to the corresponding bit line through a write data bit selector, and the bit line signal end is connected to the corresponding bit line through a read data bit selector; the testability design circuit comprises a fault diagnosis logic control module; the fault diagnosis logic control module is used to control a fault diagnosis mode in a fault diagnosis process, the fault diagnosis mode comprises a write path circuit detection mode, in the write path circuit detection mode, the write path circuit is in an on state, the write data bit selector is in a selection state, the read data bit selector is in a non-selection state, the read path circuit is in an on state, and the memory cell is in a selection state; the write path circuit realizes writing to the memory cell, and the read path circuit realizes reading of the bit line signal end and thereby realizes detection of the write path circuit; the fault diagnosis mode further comprises a read path circuit detection mode; in the read path circuit detection mode, the write path circuit is in a non-on state, the write data bit selector is in a selection state, the read data bit selector is in a non-selection state, the read path circuit is in an on state, and the memory cell is in a non-selection state, the bit line signal end is connected to a test signal output by a signal generation circuit, and the read path circuit realizes reading of the test signal and thereby realizes detection of the read path circuit; the read path circuit comprises a sense amplifier, a read buffer, and a read latch; the input end of the sense amplifier is connected to the bit line signal end, the output end of the sense amplifier is connected to the input end of the read buffer, the output end of the read buffer is connected to the input end of the read latch, and the output end of the read latch outputs a read signal; the enable signal connected to the enable end of the sense amplifier is an SAE signal or an SAEN signal; the SAEN signal is an inverse signal of the SAE signal; the enable signal connected to the enable end of the read buffer is an SAE signal or an SAEN signal; the enable signal connected to the enable end of the read latch is an SAE signal or an SAEN signal; the fault diagnosis logic control module comprises a DFT signal generation module, and the DFT signal generation module is used to form a DFT signal; in the fault diagnosis detection, the DFT signal is provided to the SAE signal; the write path circuit comprises a write selector, a write drive circuit, and a write latch. ​ ​ ​ ​ ​ ​ ​ ​ 2. The SRAM design-for-test circuit of claim 1, wherein, ​ ​ ​ ​ ​ ​ ​ ​ An output terminal of the write drive circuit is connected to an input terminal of the write selector, an output terminal of the write selector is an output terminal of the write path circuit, an input terminal of the write drive circuit is connected to an output terminal of the write latch, and an input terminal of the write latch is connected to a write signal; An enable signal connected to an enable terminal of the write selector is a WE signal or a WEN signal, and the WEN signal is an inverse signal of the WE signal; An enable signal connected to an enable terminal of the write drive circuit is a WE signal or a WEN signal, and the WEN signal is an inverse signal of the WE signal.

3. The SRAM design-for-test circuit of claim 2, wherein: In the write path circuit detection mode, the DFT signal enables the sense amplifier, the read buffer and the read latch. The WE signal or the WEN signal enables the write selector, the write drive circuit and the write latch.

4. The SRAM design-for-test circuit of claim 3, wherein: The working mode of the SRAM includes a write mode and a read mode; In the write mode, the write path circuit is in a conductive state, the write data bit selector is in a selected state, the read data bit selector is in a non-selected state, the read path circuit is in a non-conductive state, and the storage unit is in a selected state; In the read mode, the write path circuit is in a non-conductive state, the write data bit selector is in a non-selected state, the read data bit selector is in a selected state, the read path circuit is in a conductive state, and the storage unit is in a selected state; The external control circuit area further includes a tracking circuit, the tracking circuit includes a tracking unit, the tracking unit has the same structure as the storage unit, the tracking unit is connected to a tracking bit line, and the tracking bit line provides a tracking bit line signal; In the write mode, the SAE signal is provided by the tracking bit line signal and enables the sense amplifier, the read buffer and the read latch.

5. The SRAM design-for-test circuit of claim 4, wherein: The SAE signal is obtained by logically combining the tracking bit line signal and the DFT signal through a first logic circuit; The write path circuit detection mode is obtained by adding the DFT signal to the write mode; in the write mode, the DFT signal is not added, the first logic circuit takes the SAE signal as the tracking bit line signal; in the write path circuit detection mode, the DFT signal is added, the first logic circuit takes the SAE signal as the DFT signal, and the DFT signal changes the write mode to the write path circuit detection mode.

6. The SRAM design-for-test circuit of claim 5, wherein: The SAE signal enables the sense amplifier, the read buffer and the read latch when the SAE signal is at a high level; The first logic circuit is a first OR gate.

7. The SRAM design-for-test circuit of claim 4, wherein: In the write mode, a write address signal is added to the selection terminal of the write data bit selector to make the write data bit selector in a selected state; In the read mode, a read address signal is added to the selection terminal of the read data bit selector to make the read data bit selector in a selected state.

8. The SRAM design-for-test circuit of claim 7, wherein: In the read path circuit detection mode, the DFT signal is added to the selection terminal of the read data bit selector to make the read data bit selector in a non-selected state; The test signal is obtained from the tracking bit line signal.

9. The SRAM design-for-test circuit of claim 8, wherein: The bit lines connected to each of the memory cells include a non-inverted bit line and an inverted bit line; The bit line signal end includes a non-inverted bit line signal end and an inverted bit line signal end; The tracking bit line includes a non-inverted tracking bit line and an inverted tracking bit line, and the tracking bit line signal includes a non-inverted tracking bit line signal and an inverted tracking bit line signal; The signal generation circuit uses the tracking circuit, and the test signal is obtained from the inverted tracking bit line signal.

10. The SRAM design-for-test circuit of claim 9, wherein: The signal of the selection end of the read data bit selector is obtained by logical combination of the read address signal and the DFT signal by the second logic circuit; The inverted tracking bit line signal is input to the input end of the third logic circuit, and the output end of the third logic circuit outputs the test signal under the control of the control signal; The read path circuit detection mode is based on the read mode, and the memory cells are in a non-selected state and the DFT signal and the control signal of the third logic circuit are added; In the read mode, the DFT signal and the control signal of the third logic circuit are not added, the second logic circuit makes the signal of the selection end of the read data bit selector be the read address signal, and the third logic circuit makes the test signal not output to the bit line signal end; in the read path circuit detection mode, the DFT signal and the control signal of the third logic circuit are added, and the second logic circuit makes the signal of the selection end of the read data bit selector be the DFT signal, and the third logic circuit makes the test signal output to the bit line signal end.

11. The SRAM design-for-test circuit of claim 10, wherein: The read data bit selector is in a selected state when the signal of the selection end of the read data bit selector is low, and the read data bit selector is in a non-selected state when the signal of the selection end of the read data bit selector is high; The second logic circuit is a first NOR gate.

12. The SRAM DFT circuit of claim 10, wherein: The third logic circuit includes a first transmission gate and a second transmission gate; The input end of the first transmission gate is connected to the inverted tracking bit line signal, and the output end of the first transmission gate is connected to the non-inverted bit line signal end; The input end of the second transmission gate is connected to the inverted tracking bit line signal, and the output end of the second transmission gate is connected to the inverted bit line signal end; The control signal of the third logic circuit includes a first selection signal and a second selection signal which are mutually inverted; The non-inverted control end of the first transmission gate and the inverted control end of the second transmission gate are connected to the first selection signal; The inverted control end of the first transmission gate and the non-inverted control end of the second transmission gate are connected to the second selection signal.

13. An SRAM read-write path decoupling circuit, comprising: The SRAM includes a memory cell region and an external control circuit region; The memory cell region is formed with a memory cell array formed by a plurality of memory cells arranged in the same column, and the memory cells in the same column are connected to the same bit line; The external control circuit region includes a write path circuit and a read path circuit; The read path circuit detection mode is based on the read mode, and the memory cells are in a non-selected state and the DFT signal and the control signal of the third logic circuit are added; The output end of the write path circuit and the input end of the read path circuit are connected to a bit line signal end, which is connected to the corresponding bit line through a write data bit selector and connected to the corresponding bit line through a read data bit selector; Each of the storage units adopts a 1RW single-port structure; The read-write path decoupling circuit is used to realize a read-write mode in the operation of the SRAM, in which the write path circuit is in a conducting state, the write data bit selector is in a selection state, the read data bit selector is in a non-selection state, the read path circuit is in a conducting state, and the storage unit is in a selection state; the write path circuit realizes writing to the storage unit and makes the input end of the write path circuit as a write port, the read path circuit realizes reading of the bit line signal end and makes the output end of the read path circuit as a read port, so that the storage unit of the 1RW single-port structure realizes the function of a dual-port, thereby improving the storage density.

14. The read-write path decoupling circuit for an SRAM of claim 13, wherein, The read path circuit comprises a sense amplifier, a read buffer and a read latch; The input end of the sense amplifier is connected to the bit line signal end, the output end of the sense amplifier is connected to the input end of the read buffer, the output end of the read buffer is connected to the input end of the read latch, and the output end of the read latch outputs a read signal; The enable signal connected to the enable end of the sense amplifier is an SAE signal or an SAEN signal; the SAEN signal is an inverse signal of the SAE signal; The enable signal connected to the enable end of the read buffer is an SAE signal or an SAEN signal; The enable signal connected to the enable end of the read latch is an SAE signal or an SAEN signal; The write path circuit comprises a write selector, a write drive circuit and a write latch; The output end of the write drive circuit is connected to the input end of the write selector, the output end of the write selector is the output end of the write path circuit, the input end of the write drive circuit is connected to the output end of the write latch, and the input end of the write latch is connected to a write signal; The enable signal connected to the enable end of the write selector is a WE signal or a WEN signal, and the WEN signal is an inverse signal of the WE signal; The enable signal connected to the enable end of the write drive circuit is a WE signal or a WEN signal, and the WEN signal is an inverse signal of the WE signal; The read-write path decoupling circuit comprises a fourth logic circuit, which provides a read-write control signal to the SAE signal in the read-write mode.

15. The read-write path decoupling circuit for an SRAM of claim 14, wherein: The fourth logic circuit comprises a first OR gate, a D flip-flop and a second OR gate; The first input end of the second OR gate is connected to a write clock signal, the second input end is connected to a read clock signal, and the output end of the second OR gate is connected to the reset end of the D flip-flop; The clock end of the D flip-flop is connected to an address change detection signal, and the D end is connected to an operating voltage; A first input terminal of the first OR gate is connected to a Q terminal of the D flip-flop, a second input terminal of the first OR gate is connected to a track bit line signal, and an output terminal of the first OR gate outputs the SAE signal.

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