Semiconductor laser chip and method of manufacturing

Abstract

The application provides a semiconductor laser chip and a preparation method. The semiconductor laser chip is characterized in that a composite film near a cavity surface is reserved as a protective film, so that the gold layer does not directly pull the InP material during cleavage, and the problem that the gold layer pulls the debris to be adsorbed on the cavity surface is avoided. In the process of manufacturing the P-face electrode gold layer, the electrode manufacturing is divided into two times. The first layer of the gold layer electrode is dense and thin, and only a small amount of the gold layer electrode is reserved near the two end portions of the ridge table, so that the gold layer electrode does not cause pulling during the basic cleavage. The second layer of the gold layer electrode is thick and does not cover the two end portions of the ridge table, so that the chip heat dissipation is guaranteed. Meanwhile, the double-groove area is planarized by BCB, so that the cleavage lines are avoided during the cleavage. The cavity surface is plated with an aluminum nitride passivation layer by using an ion-assisted plating film technology, so that the water vapor is prevented from slowly penetrating into the active layer from the optical film, and the reliability of the laser is effectively improved.

Description

[Technical Field]

[0001] This invention relates to the field of laser technology, and in particular to a semiconductor laser chip and its fabrication method. [Background Technology]

[0002] Semiconductor lasers possess advantages such as small size, light weight, low cost, and ease of mass production, and have broad development prospects in fields such as optical storage, optical communication, and national defense. However, as the applications of semiconductor laser devices become more widespread, the requirements for their output power, lifespan, and output stability are becoming increasingly stringent, and these have become significant factors limiting their application.

[0003] In semiconductor lasers, the resonant cavity is a crucial component, formed by natural cleavage planes. Typical cleavage processes involve splitting the ends of the bar strips with a cleaver, while the middle bars are naturally cleaved along the crystal phase. However, as semiconductor lasers continue to shrink in size, the width of the chip ridges is typically between 1-2 μm. At such a small size, the bar strip cavity surfaces are prone to misalignment during natural cleavage, leading to ripples on the chip cavity surface and causing chip failure. Furthermore, since the chip ridges are made of directly vapor-deposited gold, and gold is not crystalline but has a certain degree of ductility, the gold layer is stretched near the cleavage cavity surface during chip cleavage, causing damage and breakage of the InP material. InP debris adheres to the cavity surface, causing contamination. Moreover, the gold layer cross-section and the InP material cross-section are not on the same plane, resulting in excess gold layer adhering to the cavity surface. After coating, this metal is trapped between the optical film and the material, leading to gaps. The reason for the gaps in the different films is that different materials have different stress and coefficients of thermal expansion. During the light emission process, the chip temperature rises due to heat, and the different coefficients of thermal expansion between different materials create gaps between different film layers. Furthermore, the chip's cleavage surface is a non-polar surface, and the disruption of the material's crystal periodicity creates dangling bonds, resulting in many intrinsic defects, i.e., surface states, on the surface. When water vapor enters the active layer, it reacts with oxygen, causing the formation of nonradiative recombination centers at the cavity surface of the semiconductor laser. These accumulated charge carriers absorb photon energy during the optical gain process, generating electron-hole pairs, which induces nonradiative recombination, causing the cavity surface temperature to rise. This not only reduces the laser's output efficiency but also allows cavity surface defects to diffuse into the laser, accelerating laser aging, exacerbating the temperature rise, and ultimately leading to laser chip failure.

[0004] Currently, the solution to this problem is to use a passive waveguide mating process. Because there is no active layer near the cavity surface, oxidation contamination of the active layer at the cavity surface is avoided. Furthermore, no gold electrode layer needs to be fabricated near the cavity surface, avoiding the pulling of epitaxial material by the gold layer. However, the passive waveguide mating process is complex and expensive. Some manufacturers have adopted a method of not plating a gold layer near the cavity surface, but this method is more demanding on chip storage conditions and is not suitable for large-scale, low-cost production.

[0005] Therefore, overcoming the shortcomings of the existing technology is an urgent problem to be solved in this technical field. [Summary of the Invention]

[0006] The technical problem that this invention aims to solve is that small-sized ridges are prone to cleavage patterns during the natural cleavage process; since the gold layer is not a crystal, the electrode gold layer is stretched during the cleavage process, resulting in material debris and cavity surface particle contamination, which leads to oxidation failure of the optical dielectric film and laser cavity surface during use.

[0007] The present invention achieves the above objectives through the following technical solutions:

[0008] In a first aspect, a method for fabricating a semiconductor laser chip includes:

[0009] An epitaxial wafer 1 with a ridge waveguide structure is fabricated. The double groove portion of the ridge waveguide structure is filled to flatten the upper surface of the epitaxial wafer 1. A composite film 2 is grown on the upper surface of the flattened epitaxial wafer 1. The rectangular portion in the middle of the ridge waveguide structure is called the ridge 11.

[0010] Conductive regions 111 are photolithographically formed on the ridge 11. The conductive regions 111 are located at the middle position in the extension direction of the ridge 11. Composite films 2 of a first preset length are reserved on the upper surface of the ridge 11 near both ends.

[0011] Based on the length of the conductive area 111 of the ridge 11, the coverage length of the first gold layer 3 of the P-side electrode on the ridge 11 is determined, and the first gold layer 3 of the P-side electrode is formed on the conductive area 111 of the ridge 11 and the composite film 2. At the same time, the first gold layer 3 of the P-side electrode covers part of the composite film 2 near the upper surface of both ends of the ridge 11 and extends to both ends of the ridge 11.

[0012] A second gold layer 4 of P-side electrode is fabricated on the first gold layer 3 of P-side electrode on the ridge 11. The second gold layer 4 of P-side electrode covers the middle part of the first gold layer 3 of P-side electrode. A second preset length of the first gold layer 3 of P-side electrode is reserved on the upper surface of the ridge 11 near both ends and is not covered.

[0013] Preferably, the fabrication of the epitaxial wafer 1 with the ridge waveguide structure specifically includes:

[0014] After the epitaxial wafer 1 is fabricated, SiN is grown on the surface of the epitaxial wafer 1. x The mask layer is used to leave a double-groove pattern of the ridge waveguide structure by photolithography and etching. The InGaAs blocking layer on the surface of the double groove is removed, and then the ridge 11 of the ridge waveguide is obtained by solution etching.

[0015] Preferably, the process of filling the double-groove portion of the ridge waveguide structure to flatten the upper surface of the epitaxial wafer 1 specifically includes:

[0016] A silicon dioxide layer 5 is grown on the upper surface of the epitaxial wafer 1 using plasma chemical vapor deposition technology. A layer of BCB adhesive 6 is uniformly applied to the silicon dioxide layer 5. The BCB adhesive 6 in the double groove portion is left by photolithography and passivated. The BCB adhesive 6 fills the double groove portion, making the upper surface of the epitaxial wafer 1 planarized, and the remaining silicon dioxide layer 5 is removed.

[0017] Preferably, the growth of the composite film 2 on the surface of the planarized epitaxial wafer 1 specifically includes:

[0018] A silicon nitride thin film is grown on an epitaxial wafer 1 using plasma chemical vapor deposition technology, followed by the growth of a silicon oxide thin film to form a composite film 2.

[0019] Preferably, the fabrication of the first gold layer 3 of the P-side electrode on the conductive region 111 of the ridge 11 and the composite film 2 specifically includes:

[0020] A first electrode pattern is formed on the upper surface of the composite film 2 by photolithography. Based on the first electrode pattern, titanium, platinum and gold are sputtered sequentially by metal sputtering process to form the first gold layer 3 of the P-side electrode. The length of the first gold layer 3 of the P-side electrode is slightly larger than the length of the conductive area 111 in the middle part of the ridge 11, completely covering the conductive area 111 in the middle part of the ridge 11, and covering the part of the composite film 2 near the upper surface of the two ends of the ridge 11, extending to the two end faces of the ridge 11.

[0021] Preferably, the fabrication of the second gold layer 4 of the P-side electrode on the first gold layer 3 of the P-side electrode on the ridge 11 specifically includes:

[0022] The second electrode pattern is formed by photolithography on the upper surface of the first gold layer 3 of the P-side electrode, and the second gold layer 4 of the P-side electrode is fabricated by electroplating gold according to the second electrode pattern; wherein, the coverage area of ​​the second gold layer 4 of the P-side electrode is such that, except for the P-side electrode first gold layer 3 near the two ends of the ridge 11, all other P-side electrode first gold layers 3 are covered.

[0023] Preferably, after fabricating the second gold layer 4 of the P-side electrode, the method further includes:

[0024] The epitaxial wafer 1, excluding the area covered by the second gold layer 4 of the P-side electrode, is covered with a metal thermally conductive layer 7.

[0025] Preferably, after the N-face electrode fabrication and bar cleavage are completed, an aluminum nitride thin film is deposited on both end faces of the epitaxial wafer 1 as a passivation film 8.

[0026] Preferably, after depositing an aluminum nitride thin film on the cavity surfaces at both ends of the epitaxial wafer 1, the method further includes:

[0027] A high-reflectivity film 9 is deposited on the front cavity surface of the epitaxial wafer 1, and an antireflection film 10 is deposited on the rear cavity surface of the epitaxial wafer 1.

[0028] In a second aspect, a semiconductor laser chip, using a method for fabricating the semiconductor laser chip, includes:

[0029] The epitaxial wafer 1 is provided with a ridge waveguide structure, wherein the ridge waveguide structure is filled to make the epitaxial wafer 1 planarized, and the upper surface of the planarized epitaxial wafer 1 is covered with a composite film 2. The rectangular part in the middle of the ridge waveguide structure is called the ridge 11. The composite film 2 at the middle position in the extension direction of the ridge 11 is photolithographically etched into a conductive region 111. The upper surface of the ridge 11 near both ends is reserved with a first preset length of composite film 2.

[0030] A P-side electrode first gold layer 3 is provided on the conductive area 111 of the ridge 11 and the composite film 2. The P-side electrode first gold layer 3 completely covers the conductive area 111 in the middle part of the ridge 11, and at the same time covers part of the composite film 2 at both ends of the surface of the ridge 11, and extends to both ends of the ridge 11.

[0031] The first gold layer 3 of the P-side electrode is covered by a second gold layer 4 of the P-side electrode, which covers the middle part of the first gold layer 3 of the P-side electrode, while the first gold layer 3 of the P-side electrode near the upper surface of the ridge 11 at both ends is not covered.

[0032] The epitaxial wafer 1, except for the area covered by the second gold layer 4 of the P-side electrode, is covered with a metal thermally conductive layer 7.

[0033] An aluminum nitride thin film is deposited on both ends of the epitaxial wafer 1 as a passivation film 8.

[0034] The front cavity surface of the epitaxial wafer 1 is provided with a high-reflectivity film 9, and the rear cavity surface of the epitaxial wafer 1 is provided with an anti-reflection film 10.

[0035] Compared with the prior art, the beneficial effects of the present invention are:

[0036] This invention provides a semiconductor laser chip and its fabrication method. By retaining a composite film near the cavity surface, the gold layer is prevented from directly pulling the InP material during cleavage, thus avoiding the problem of gold layer debris adsorbing onto the cavity surface. During the fabrication of the P-side electrode gold layer, the electrode is fabricated in two stages. The first gold layer is dense and thin, with only a small amount retained near the ends of the ridges, ensuring no pulling occurs during basic cleavage. The second gold layer is thicker and does not cover the ends of the ridges, ensuring chip heat dissipation. Simultaneously, BCB planarization is performed on the double-groove region to prevent cleavage lines from appearing during the cleavage process.

[0037] Furthermore, in a preferred embodiment of the present invention, an aluminum nitride passivation layer is deposited on the cavity surface using ion-assisted coating technology, which prevents water vapor from slowly penetrating from the optical film into the active layer, effectively improving the reliability of the laser. [Attached Image Description]

[0038] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments of the present invention will be briefly described below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0039] Figure 1 A flowchart illustrating a method for fabricating a semiconductor laser chip according to an embodiment of the present invention;

[0040] Figure 2 This is a schematic diagram of the structure of an epitaxial wafer provided in an embodiment of the present invention;

[0041] Figure 3 A front view of the epitaxial wafer covered with a silicon dioxide layer in a method for fabricating a semiconductor laser chip according to an embodiment of the present invention;

[0042] Figure 4 A front view of the planarized epitaxial wafer in a method for fabricating a semiconductor laser chip according to an embodiment of the present invention;

[0043] Figure 5 A front view of a planarized epitaxial wafer covered with a composite film, provided in an embodiment of the present invention, for a method of fabricating a semiconductor laser chip;

[0044] Figure 6 A top view of a planarized epitaxial wafer covered with a composite film in a method for fabricating a semiconductor laser chip according to an embodiment of the present invention;

[0045] Figure 7A front view of the first gold layer covering the P-side electrode, provided in an embodiment of the present invention, for a method of fabricating a semiconductor laser chip;

[0046] Figure 8 This is a top view of the first gold layer covering the P-side electrode, which is a method for fabricating a semiconductor laser chip according to an embodiment of the present invention.

[0047] Figure 9 The method for fabricating a semiconductor laser chip according to an embodiment of the present invention includes a first gold layer covering the P-side electrode. Figure 8 A sectional view;

[0048] Figure 10 A front view of the second gold layer covering the P-side electrode in a method for fabricating a semiconductor laser chip according to an embodiment of the present invention;

[0049] Figure 11 This is a top view of the second gold layer covering the P-side electrode, which is provided in an embodiment of the present invention for a method of fabricating a semiconductor laser chip.

[0050] Figure 12 The second gold layer covering the P-side electrode is provided in the fabrication method of a semiconductor laser chip according to an embodiment of the present invention. Figure 11 A sectional view;

[0051] Figure 13 A front view of a method for fabricating a semiconductor laser chip according to an embodiment of the present invention, showing a covered metal thermally conductive layer.

[0052] Figure 14 A top view of a method for fabricating a semiconductor laser chip according to an embodiment of the present invention, showing a covered metal thermally conductive layer;

[0053] Figure 15 A method for fabricating a semiconductor laser chip according to an embodiment of the present invention includes a covered metal thermally conductive layer. Figure 14 A sectional view;

[0054] Figure 16 A top view of the passivation film covering a method for fabricating a semiconductor laser chip according to an embodiment of the present invention;

[0055] Figure 17 This is a top view of a method for fabricating a semiconductor laser chip according to an embodiment of the present invention, showing a coating of a high-reflectivity film and an anti-reflection film.

Detailed Implementation Methods

[0056] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0057] In the description of this invention, the terms "inner", "outer", "longitudinal", "lateral", "upper", "lower", "top", "bottom", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and do not require that this invention must be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0058] Furthermore, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0059] Example 1:

[0060] This invention provides a method for fabricating a semiconductor laser chip, such as... Figure 1 As shown, it includes the following steps:

[0061] In step 101, an epitaxial wafer 1 with a ridge waveguide structure is fabricated, wherein the rectangular portion in the middle of the ridge waveguide structure is called the ridge 11.

[0062] like Figure 2 As shown, in a typical example, the epitaxial wafer 1 is fabricated by the following method: using metal-organic chemical vapor deposition (MOCVD) technology, an n-InP buffer layer 12, an n-InAlAs layer 13, a multi-quantum-well active layer 14, a p-Inp layer 15, an InGaAsP etching barrier layer 16, and an InGaAs barrier layer 17 are sequentially grown on an InP substrate 18 to form the epitaxial wafer 1.

[0063] In this embodiment of the invention, a set of parameters is provided for the thickness of each layer, for reference in the related technical content of the invention. The reference thickness of the n-InP buffer layer 12 is approximately 0.13 μm; the reference thickness of the n-InAlAs layer 13 is approximately 0.05 μm; the multi-quantum-well layer 14 has 9 pairs of quantum wells, with a well reference width of approximately 5.5 nm and a compressive strain of 1.3%, a barrier reference width of approximately 8.5 nm and a tensile strain of 0.58%, and a quantum well PL reference wavelength of approximately 1273 nm; the reference thickness of the p-Inp layer 15 is approximately 0.06 μm; the reference thickness of the InGaAsP corrosion barrier layer 16 is approximately 1.45 μm; and the reference thickness of the InGaAs barrier layer 17 is approximately 0.2 μm. It should be noted that the corresponding material layers and their thicknesses are not the focus of this invention; they are merely presented as examples for relevance description in relation to other related features of the invention.

[0064] In step 102, filling the double-groove portion of the ridge waveguide structure to planarize the upper surface of the epitaxial wafer 1 includes:

[0065] like Figure 3 and Figure 4 As shown, the remaining SiNx mask layer on the surface of the epitaxial wafer 1 is first etched away using a buffered oxidized acid solution (BOE). Then, a silicon dioxide layer 5 with a reference thickness of 300 nm is grown on the surface of the epitaxial wafer 1 using plasma chemical vapor deposition. Photosensitive benzoyl cyclobutene resin (BCB) is used for spin coating, and BCB adhesive 6 is left in the double grooves by photolithography. Passivation treatment is then performed to obtain a planarized BCB adhesive 6 in the double grooves, thereby planarizing the upper surface of the epitaxial wafer 1. The reference spin speed for BCB spin coating is 3000 rad / s, and the reference temperature rise condition for passivation is 5℃ / 5min, held at a reference temperature of 250℃ for 3 hours. The BCB adhesive 6 fills the double groove portion, ensuring that the ridges 11 can be buffered under natural cleavage stress, greatly reducing the probability of cleavage lines appearing.

[0066] In step 103, a composite film 2 is grown on the surface of the epitaxial wafer 1. Since the epitaxial wafer 1 needs to be in contact with the P-side electrode to fulfill the conductivity requirements of the laser chip, a portion of the composite film 2 needs to be photolithographically etched to expose the epitaxial wafer 1 in contact with the P-side electrode. Therefore, this invention also relates to the following design:

[0067] like Figure 6 As shown, a conductive region 111 is photolithographically etched on the ridge 11. The conductive region 111 is located at the middle position in the extension direction of the ridge 11. A composite film 2 of a first preset length is reserved on the upper surface of the ridge 11 near both ends.

[0068] The first preset length is determined based on the length of the ridge 11 on the epitaxial wafer 1 and the conductivity requirements of the laser chip. The first preset length is 5-10 μm. The conductive region 111 is located in the middle of the extension direction of the ridge 11. Therefore, composite films 2 of the same length are reserved at both ends of the ridge 11.

[0069] The process of photolithographically etching the conductive region 111 on the ridge 11 includes: leaving a conductive region 111 pattern in the middle of the ridge 11 by photolithography according to a first preset length as required, and removing the composite film 2 in the middle part of the ridge 11 by reactive ion etching of the conductive region 111 pattern.

[0070] Step 104: Referencing the length of the conductive area 111 of the ridge 11, determine the coverage length of the first gold layer 3 of the P-side electrode on the ridge 11, and fabricate the first gold layer 3 of the P-side electrode on the conductive area 111 of the ridge 11 and the composite film 2. At the same time, the first gold layer 3 of the P-side electrode covers the portion of the composite film 2 near the upper surfaces of both ends of the ridge 11 and extends to both ends of the ridge 11.

[0071] like Figure 7-9 As shown, the conductive region 111 in the middle part of the ridge 11 is completely covered by the first gold layer 3 of the P-side electrode. The composite film 2 near both ends of the ridge 11 is covered by the first gold layer 3 of the P-side electrode from the middle region with a narrower width and extends to both ends of the ridge 11. The reference width of the first gold layer 3 of the P-side electrode covering the composite film 2 at both ends of the surface of the ridge 11 is 2-5 μm.

[0072] The first gold layer 3 of the P-side electrode completely covers the conductive region 111, ensuring the power supply between the epitaxial wafer 1 and the P-side electrode.

[0073] For conventional ridge waveguide structure chips, the P-side electrodes are fabricated using traditional evaporation electrode technology. The gold layer needs to take heat dissipation into account, and the gold layer thickness is generally more than 1 μm. When cleaving the end faces, it causes a large pulling effect on the ridge 11, resulting in damage to the ridge 11. Debris is adsorbed on the cavity surface, causing chip failure. In addition, metal falls off the cavity surface. Due to the large expansion coefficient of metal, gaps are easily formed between the optical film and the cavity surface.

[0074] Therefore, in this embodiment, the first gold layer 3 of the P-side electrode will not completely cover the composite film 2 on the ridge 11. Instead, while completely covering the conductive area 111, it will cover a portion of the composite film 2 at both ends of the ridge 11 and extend to the end faces of both ends of the ridge 11. Since the gold layer of the first gold layer 3 of the P-side electrode is relatively thin, it will not cause any pulling effect. Therefore, by retaining the composite film 2 near the upper surfaces of both ends of the ridge 11, the gold layer is prevented from being directly pulled to the InP material.

[0075] The first gold layer 3 of the P-side electrode laterally covers the composite film 2 above the ridge 11 and the double groove portion.

[0076] The fabrication of the first gold layer 3 of the P-side electrode on the conductive region 111 of the ridge 11 and the composite film 2 includes:

[0077] A first electrode pattern is formed on the upper surface of the composite film 2 by photolithography, and titanium, platinum and gold are sputtered sequentially according to the first electrode pattern to form the first gold layer 3 of the P-side electrode.

[0078] For conventional ridge waveguide structures, when using traditional evaporation electrode technology to fabricate P-side electrodes, the gold layer is not dense enough, and moisture can easily penetrate from the gold layer to corrode the active layer. However, using a metal layer fabricated by metal sputtering as an electrode can prevent moisture from penetrating from the front gold layer into the chip interior. Since there is no gold layer on the chip cleaving cavity surface, there is no metal at the interface when cleaving the chip bars. Therefore, direct contact between the optical film and the metal is prevented during coating, avoiding the increase in the metal's coefficient of thermal expansion when the chip emits light and heats up, which could lead to gaps between the optical film and the cavity surface.

[0079] The P-side electrode is fabricated by sequentially sputtering titanium, platinum, and gold using a metal sputtering process because titanium, as a metal, has excellent adhesion to silicon dioxide, while platinum and gold provide good ohmic contact. The reference thicknesses for sputtering titanium, platinum, and gold are 80 nm for titanium, 90 nm for platinum, and 300 nm for gold, with a reference sputtering power of 250 W. After 2 minutes at 410°C, the resistance of the alloy decreases significantly.

[0080] Then, the second gold layer 4 of the P-side electrode is electroplated on the first gold layer 3 of the P-side electrode to further enhance the heat dissipation effect.

[0081] In step 105, a second gold layer 4 of the P-side electrode is fabricated on the first gold layer 3 of the P-side electrode on the ridge 11, including:

[0082] like Figure 10-12As shown, a second electrode pattern is formed on the upper surface of the first gold layer 3 of the P-side electrode by photolithography, and the second gold layer 4 of the P-side electrode is fabricated by electroplating gold according to the second electrode pattern; wherein, the coverage area of ​​the second gold layer 4 of the P-side electrode is such that, except for the second preset length of the first gold layer 3 of the P-side electrode near the upper surfaces of both ends of the ridge 11, all other parts of the first gold layer 3 of the P-side electrode are covered; wherein the second preset length is slightly smaller than the first preset length, and the reference second preset length is 2.5-5um.

[0083] The second gold layer 4 of the P-side electrode has a reference thickness of 1 μm. The second electrode pattern is different from the first electrode pattern except for the portion of the ridge 11 near both ends. The other parts are the same as the first electrode pattern. After the second gold layer 4 of the P-side electrode is electroplated, it can further achieve a good heat dissipation effect.

[0084] To further enhance thermal conductivity, the present invention also relates to the following preferred designs:

[0085] In step 106, after the second gold layer 4 of the P-side electrode is electroplated, a metal thermally conductive layer 7 is applied to the other areas of the epitaxial wafer 1, excluding the portion covered by the second gold layer 4 of the P-side electrode.

[0086] like Figure 13-15 As shown, since the metal thermal conductive layer 7 cannot cover the second gold layer 4 of the P-side electrode, the metal thermal conductive layer 7 only covers the area excluding the part of the second gold layer 4 of the P-side electrode and fills the upper surface of the epitaxial wafer 1.

[0087] In step 107, after completing the fabrication of the N-face electrode and bar cleavage, an aluminum nitride thin film is deposited on both end faces of the epitaxial wafer 1 as a passivation film 8.

[0088] like Figure 16-17 As shown, the InP substrate thickness of the epitaxial wafer 1 is reduced to 90-100 μm, and then an N-side electrode is fabricated using metal sputtering technology. Titanium, platinum, and gold are sputtered sequentially as N-side electrodes, with reference sputtering thicknesses of 80 nm for titanium, 90 nm for platinum, and 300 nm for gold. The working principle is the same as that of the P-side electrode. After the N-side electrode is completed, the bar strips of the epitaxial wafer 1 are cleaved, and then an aluminum nitride thin film is deposited on the front and back cavity surfaces of the chip as a passivation film 8 using ECR ion-assisted deposition technology. The reference thickness of the passivation layer is 20-30 nm, with a reference RF power of 250 W and a reference microwave power of 300 W. The dense characteristics of the passivation film 8 grown using ECR ion-assisted deposition technology prevent moisture from penetrating into the active layer of the chip from the end face.

[0089] Using electron beam evaporation, an antireflective coating 10 is deposited on the front light-emitting surface of the bar, and a high-reflective coating 9 is deposited on the back light-emitting surface of the bar to complete the chip fabrication process.

[0090] The reference data provided in this embodiment represents only one possible solution under a specific scenario and is not limited to the above reference data. Those skilled in the art can design and adjust the data according to the actual situation. All related changes brought about by the data should be within the protection scope of this invention.

[0091] In conjunction with the embodiments of the present invention, a more detailed process for growing the composite film 2 in step 103 is also provided. In the following description, the key layer structure of the epitaxial wafer 1 exemplified in step 101 will be used for further explanation.

[0092] After the epitaxial wafer 1 is fabricated, a SiNx mask layer is grown on the surface of the epitaxial wafer 1, a double-groove pattern is left by photolithography etching, the InGaAs blocking layer on the surface of the double groove is removed, and then the ridge of the ridge waveguide 11 is obtained by solution etching.

[0093] The SiNx mask layer has a reference thickness of 120nm. Through the photolithography technique, a double-groove pattern is left on the SiNx mask layer. The rectangular part in the middle of the double-groove pattern is called the ridge 11.

[0094] Based on the already etched double-channel pattern of the ridge waveguide structure, the InGaAs barrier layer 17 on the surface of the double channel is first etched using reactive ion etching (RIE) technology. In this embodiment, the etching reference depth is approximately 450 nm. Then, after chemical etching, the ridge 11 of the ridge waveguide structure is obtained. The etching solution is a mixture of 36% HCl and H3PO4 in a volume ratio of 1:3, or other etching solutions that can achieve the same etching effect, all of which should be included within the scope of protection of this invention. The upper ridge reference width of the ridge 11 obtained after chemical etching is 1.8-2.0 μm, the lower ridge reference width is 1.6-1.8 μm, the reference depth of the double channel is 1.7-1.9 μm, and the reference width of the channel is 14-15 μm.

[0095] like Figure 5 As shown, a composite film 2 is grown on the surface of the planarized epitaxial wafer 1, comprising:

[0096] The remaining uncovered silicon dioxide layer 5 on the upper surface of the epitaxial wafer 1 is etched away using a buffered oxygen ether (BOE) solution. Then, a silicon nitride thin film with a reference thickness of 100 nm is grown on the surface of the epitaxial wafer 1 using plasma chemical vapor deposition. Next, a silicon dioxide thin film with a reference thickness of 300 nm is grown to form a composite film 2. The lengths of the silicon nitride thin film and the silicon dioxide thin film are designed by those skilled in the art according to the actual situation. Any composite film 2 design that can meet the functional application in this scenario should be within the protection scope of this invention.

[0097] The PEVCD reference RF power for growing the composite membrane 2 is 150W, and the reference temperature inside the chamber is 270-300℃.

[0098] The reason for using silicon nitride and silicon dioxide thin films as composite film 2 is that pure silicon nitride thin films exhibit compressive stress, while pure silicon dioxide thin films exhibit tensile stress. The silicon nitride and silicon dioxide composite film 2 can offset some of the stress, thus avoiding changes in the characteristics of the laser chip due to film stress.

[0099] Example 2:

[0100] This invention provides a semiconductor laser chip, which, based on the semiconductor laser chip fabrication method of Embodiment 1, demonstrates the structure of a fabricated semiconductor laser chip in a more specific scenario.

[0101] The epitaxial wafer 1 is provided with a ridge waveguide structure, wherein the ridge waveguide structure is filled to make the epitaxial wafer 1 planarized, and the upper surface of the planarized epitaxial wafer 1 is covered with a composite film 2. The rectangular part in the middle of the ridge waveguide structure is called the ridge 11. The composite film 2 at the middle position in the extension direction of the ridge 11 is photolithographically etched into a conductive region 111. The upper surface of the ridge 11 near both ends is reserved with a first preset length of composite film 2.

[0102] The ridge 11 has a length of 200 μm, the conductive region 111 at the middle position of the ridge 11 in the extension direction has a length of 180 μm, the first preset length is 10 μm, and a composite film 2 with a length of 10 μm is reserved on the upper surface of the ridge 11 near both ends.

[0103] A P-side electrode first gold layer 3 is disposed on the conductive area 111 of the ridge 11 and the composite film 2. The coverage length of the P-side electrode first gold layer 3 on the epitaxial wafer 1 other than the ridge 11 is 190 μm, and the coverage length of the P-side electrode first gold layer 3 on the ridge 11 is 200 μm. The conductive area 111 in the middle part of the ridge 11 is completely covered by the P-side electrode first gold layer 3. The composite film 2 near both ends of the ridge 11 is covered by the P-side electrode first gold layer 3 from the middle part and extends to both ends of the ridge 11. The width of the P-side electrode first gold layer 3 covering the composite film 2 at both ends of the surface of the ridge 11 is 2 μm.

[0104] The first gold layer 3 of the P-side electrode is constructed by sequentially sputtering titanium with a thickness of 80 nm, platinum with a thickness of 90 nm, and gold with a thickness of 300 nm using a metal sputtering process.

[0105] The first gold layer 3 of the P-side electrode is covered by a second gold layer 4 of the P-side electrode, which covers the middle part of the first gold layer 3 of the P-side electrode and has a coverage length of 190um.

[0106] The epitaxial wafer 1, excluding the portion covered by the second gold layer 4 of the P-side electrode, is covered with a metal thermally conductive layer 7, the metal thermally conductive layer 7 having a coverage length of 200 μm.

[0107] An aluminum nitride thin film is deposited on both ends of the epitaxial wafer 1 as a passivation film 8, and the thickness of the aluminum nitride thin film is 25 nm.

[0108] The front cavity surface of the epitaxial wafer 1 is provided with a high-reflectivity film 9, and the rear cavity surface of the epitaxial wafer 1 is provided with an anti-reflection film 10.

[0109] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for fabricating a semiconductor laser chip, characterized in that, include: An epitaxial wafer (1) with a ridge waveguide structure is fabricated. The double groove portion of the ridge waveguide structure is filled to flatten the upper surface of the epitaxial wafer (1). A composite film (2) is grown on the upper surface of the flattened epitaxial wafer (1). The rectangular portion in the middle of the ridge waveguide structure is called the ridge (11). Conductive regions (111) are photolithographically formed on the ridge (11). The conductive regions (111) are located in the middle position in the extension direction of the ridge (11). A composite film (2) of a first preset length is reserved on the upper surface of the ridge (11) near both ends. Based on the length of the conductive area (111) of the ridge (11), the coverage length of the first gold layer (3) of the P-side electrode on the ridge (11) is determined, and the first gold layer (3) of the P-side electrode is formed on the conductive area (111) of the ridge (11) and the composite film (2). At the same time, the first gold layer (3) of the P-side electrode covers part of the composite film (2) near the upper surface of both ends of the ridge and extends to both ends of the ridge (11). A second gold layer (4) of P-side electrode is fabricated on the first gold layer (3) of P-side electrode on the ridge. The second gold layer (4) of P-side electrode covers the middle part of the first gold layer (3) of P-side electrode. The upper surface of the ridge (11) near both ends is reserved with a second preset length of the first gold layer (3) of P-side electrode that is not covered. A first electrode pattern is formed by photolithography on the upper surface of the composite film (2). Based on the first electrode pattern, titanium, platinum and gold are sputtered sequentially by metal sputtering process to form the first gold layer (3) of the P-side electrode. The length of the first gold layer (3) of the P-side electrode is slightly greater than the length of the conductive area (111) in the middle part of the ridge (11), completely covering the conductive area (111) in the middle part of the ridge (11), while covering part of the composite film (2) near the upper surface of the two ends of the ridge (11), and extending to the two end faces of the ridge (11). The first gold layer (3) of the P-side electrode does not completely cover the composite film (2) on the ridge (11). Instead, while completely covering the conductive area (111), it covers part of the composite film (2) at both ends of the ridge (11) and extends to the end faces of both ends of the ridge (11). This does not cause a pulling effect. Therefore, by retaining the composite film (2) near the upper surface of both ends of the ridge (11), the gold layer is prevented from being directly pulled to the InP material.

2. The method for fabricating a semiconductor laser chip according to claim 1, characterized in that, The fabrication of the epitaxial wafer (1) with the ridge waveguide structure specifically includes: After the epitaxial wafer (1) is fabricated, SiN is grown on the surface of the epitaxial wafer (1). x The mask layer is used to leave a double-groove pattern of the ridge waveguide structure by photolithography and etching. The InGaAs blocking layer on the surface of the double groove is removed, and then the ridge of the ridge waveguide is obtained by solution etching (11).

3. The method for fabricating a semiconductor laser chip according to claim 1, characterized in that, The double-groove portion of the ridge waveguide structure is filled to flatten the upper surface of the epitaxial wafer (1), specifically including: A silicon dioxide layer (5) is grown on the upper surface of the epitaxial wafer (1) using plasma chemical vapor deposition technology. A layer of BCB adhesive (6) is uniformly applied to the silicon dioxide layer (5). The BCB adhesive (6) in the double groove portion is left by photolithography and passivated. The BCB adhesive (6) fills the double groove portion, making the upper surface of the epitaxial wafer (1) planarized, and the remaining silicon dioxide layer (5) is removed.

4. The method for fabricating a semiconductor laser chip according to claim 1, characterized in that, A composite film (2) is grown on the surface of the planarized epitaxial wafer (1), specifically including: A silicon nitride thin film was grown on an epitaxial wafer (1) using plasma chemical vapor deposition technology, followed by the growth of a silicon oxide thin film to form a composite film (2).

5. The method for fabricating a semiconductor laser chip according to claim 4, characterized in that, The fabrication of a second gold layer (4) on the first gold layer (3) of the P-side electrode on the ridge (11) specifically includes: A second electrode pattern is formed by photolithography on the upper surface of the first gold layer (3) of the P-side electrode, and the second gold layer (4) of the P-side electrode is fabricated by electroplating gold according to the second electrode pattern; wherein, the coverage area of ​​the second gold layer (4) of the P-side electrode is such that, except for the second preset length of the first gold layer (3) of the P-side electrode near the upper surfaces of both ends of the ridge (11) which is not covered, all the other first gold layers (3) of the P-side electrode are covered.

6. The method for fabricating a semiconductor laser chip according to claim 5, characterized in that, After fabricating the second gold layer (4) of the P-side electrode, the process further includes: A metal thermally conductive layer (7) is covered on the epitaxial wafer (1) except for the area covered by the second gold layer (4) of the P-side electrode.

7. The method for fabricating a semiconductor laser chip according to any one of claims 1-6, characterized in that, After completing the fabrication of the N-face electrode and bar cleavage, an aluminum nitride thin film is deposited on both ends of the epitaxial wafer (1) as a passivation film (8).

8. The method for fabricating a semiconductor laser chip according to claim 7, characterized in that, After depositing an aluminum nitride thin film on the cavity surfaces at both ends of the epitaxial wafer (1), the following is also included: A high-reflectivity film (9) is deposited on the front cavity surface of the epitaxial wafer (1), and an anti-reflection film (10) is deposited on the rear cavity surface of the epitaxial wafer (1).

9. A semiconductor laser chip, characterized in that, The semiconductor laser chip fabrication method according to any one of claims 1-8 comprises the following structure: The epitaxial wafer (1) is provided with a ridge waveguide structure, wherein the ridge waveguide structure is filled to make the epitaxial wafer (1) planarized, and the upper surface of the planarized epitaxial wafer (1) is covered with a composite film (2). The rectangular part in the middle of the ridge waveguide structure is called the ridge (11). The composite film (2) at the middle position of the ridge (11) in the extension direction is photolithographically etched into a conductive region (111). The upper surface of the ridge (11) near both ends is reserved with a first preset length of composite film (2). The conductive area (111) of the ridge (11) and the composite film (2) are provided with a P-side electrode first gold layer (3). The P-side electrode first gold layer (3) completely covers the conductive area (111) in the middle part of the ridge (11), and at the same time covers part of the composite film (2) at both ends of the surface of the ridge (11), and extends to both ends of the ridge (11). The first gold layer (3) of the P-side electrode is covered by a second gold layer (4) of the P-side electrode, which covers the middle part of the first gold layer (3) of the P-side electrode, and the first gold layer (3) of the P-side electrode near the upper surface of the ridge (11) at both ends is not covered. The epitaxial wafer (1) is covered with a metal thermally conductive layer in the area other than the portion covered by the second gold layer (4) of the P-side electrode; An aluminum nitride thin film is deposited on both ends of the epitaxial wafer (1) as a passivation film (8). The front cavity surface of the epitaxial wafer (1) is provided with a high reflectivity film (9), and the rear cavity surface of the epitaxial wafer (1) is provided with an antireflection film (10).

Images