Inp-based semiconductor laser chip and preparation method thereof

Abstract

The application provides an InP-based semiconductor laser chip and a preparation method. In the process of manufacturing a P surface electrode, a very dense gold layer is used as the electrode, thereby avoiding the problem that the gold layer is not easy to cleave due to connection in the traditional laser cleaving process, and preventing water vapor from corroding the active layer from the front surface of the chip. By retreating a part of the P surface electrode near the two ends of the ridge platform and then covering the retreated part with a dense protective layer, the active layer of the chip is double-protected in cooperation with the composite film under the P surface electrode, so that the water vapor cannot enter the active layer of the chip. The cavity surface is plated with an aluminum oxide passivation layer by using an ECR ion assisted film plating technology. The expansion coefficient of the aluminum oxide is similar to that of the InP material, and the film quality of the aluminum oxide is more dense. Therefore, the cavity surface will not cause a gap between different layers of materials due to heating of the chip, and the water vapor is also prevented from slowly penetrating into the active layer from the optical film.

Description

[Technical Field]

[0001] This invention relates to the field of laser technology, and provides an InP-based semiconductor laser chip and its fabrication method. [Background Technology]

[0002] With the development of high-speed optical communication systems, low loss, large capacity, and long distance have become the development direction of optical fiber transmission systems, and high-speed semiconductor laser chips are the core of the system. As semiconductor laser technology becomes more mature and its scale increases, it becomes more and more sensitive to the price of chips.

[0003] Generally, for a semiconductor laser to be used in a communication module, it first needs to be packaged. The semiconductor laser is packaged into a TO (Transfer Object), then the TO is packaged into a device, and finally into a module. The main components of a TO package include: a TO base, a TO cap, a lens, the laser chip, and a detector chip. During the packaging process, a protective gas is also filled to create a hermetically sealed space with only the protective gas atmosphere. The cost of hermetically sealed packaging accounts for approximately 30%. Why is it necessary to hermetically seal the laser? Mainly because after being packaged into a module, the laser is primarily used in outdoor base stations. Base stations are typically located outdoors. If the semiconductor laser chip is not hermetically sealed, it will be directly exposed to the air, where oxygen and moisture will cause corrosion and oxidation, leading to laser chip failure.

[0004] Research indicates that water vapor causes semiconductor laser chip failure primarily through two pathways: first, water vapor penetrates from the cavity surface optical film and contacts the active layer of the chip; second, water vapor enters through gaps created between different thin film layers and contacts the active layer. The gaps between different films arise because different materials have different stress and expansion coefficients. During light emission, heat causes the chip temperature to rise, and the difference in expansion coefficients between different materials creates gaps between the different film layers. Furthermore, the chip's cleavage surface is nonpolar, and the disruption of the material's crystal periodicity creates dangling bonds, resulting in numerous intrinsic defects, i.e., surface states, on the surface. When water vapor enters the active layer, it reacts with oxygen, causing the formation of nonradiative recombination centers on the cavity surface of the semiconductor laser. These accumulated charge carriers absorb photon energy during the optical gain process, generating electron-hole pairs, which induces nonradiative recombination, causing the cavity surface temperature to rise. This not only reduces the laser's output efficiency but also allows cavity surface defects to diffuse into the laser, accelerating laser aging, exacerbating the temperature rise, and ultimately leading to laser chip failure. Therefore, in order to prevent laser chips from failing due to moisture, the traditional method is to hermetically seal the laser chips to isolate them from the external environment. However, this packaging method results in high packaging costs for semiconductor laser chips.

[0005] If the process can prevent moisture from contacting the active layer of the laser chip, then hermetic packaging is unnecessary, saving significant costs. Therefore, overcoming the shortcomings of the existing technology is a pressing issue in this field. [Summary of the Invention]

[0006] The technical problem that this invention needs to solve is:

[0007] The problems with using laser chips in non-hermetic packaging are twofold: first, moisture can penetrate through the optical film and corrode the active layer on the cavity surface; second, moisture can enter the chip through the gaps between different film systems and corrode the active layer.

[0008] The present invention achieves the above objectives through the following technical solutions:

[0009] In a first aspect, a method for fabricating an InP-based semiconductor laser chip includes:

[0010] An epitaxial wafer 1 with a ridge waveguide structure is fabricated, and a composite film 2 is grown on the surface of the epitaxial wafer 1, wherein the rectangular portion in the middle of the ridge waveguide structure is called the ridge 11.

[0011] Conductive regions 111 are photolithographically formed on the ridge 11. The conductive regions 111 are located at the middle position in the extension direction of the ridge 11. Composite films 2 of a predetermined length are reserved on the upper surface of the ridge 11 near both ends.

[0012] Based on the length of the conductive region 111 of the ridge 11, the coverage length of the P-side electrode 3 on the ridge 11 is determined, and the P-side electrode 3 is fabricated on the conductive region 111 of the ridge 11 and the composite film 2.

[0013] A protective layer 4 is applied to the P-side electrode 3 and the composite film 2 on the ridge 11, covering the P-side electrode 3 on the ridge 11 and the composite film 2 reserved at both ends of the ridge 11.

[0014] Preferably, the fabrication of the epitaxial wafer 1 with the ridge waveguide structure specifically includes:

[0015] After the epitaxial wafer 1 is fabricated, SiN is grown on the surface of the epitaxial wafer 1. x The mask layer is used to leave a double-groove pattern of the ridge waveguide structure by photolithography and etching. The InGaAs blocking layer on the surface of the double groove is removed, and then the ridge 11 of the ridge waveguide is obtained by solution etching.

[0016] Preferably, the fabrication of the P-side electrode 3 on the composite film 2 specifically includes:

[0017] Electrode patterns are formed on the surface of the composite film 2 by photolithography. Based on the electrode patterns, titanium, platinum and gold are sputtered sequentially by metal sputtering process to fabricate the P-side electrode 3. The length of the P-side electrode 3 is slightly greater than the length of the reserved surface in the middle part of the ridge 11, completely covering the conductive area 111 in the middle part of the ridge 11, and covering the composite film 2 at both ends of the surface of the ridge 11.

[0018] Preferably, covering the ridge 11 with a protective layer 4 specifically includes:

[0019] A protective layer 4 pattern is formed by photolithography on the P-side electrode 3 on the ridge 11 and the upper surface of the composite film 2.

[0020] A silicon nitride thin film and a silicon dioxide thin film are grown sequentially using plasma chemical vapor deposition technology to form a protective layer 4; wherein, the protective layer 4 covers the P-side electrode 3 on the ridge 11 and the composite film 2 on the ridge 11.

[0021] Preferably, after forming the protective layer 4, the method further includes:

[0022] A metal thermally conductive layer 5 is applied to the area of ​​the epitaxial wafer 1, excluding the portion covered by the protective layer 4.

[0023] Preferably, covering the ridge 11 with a protective layer 4 specifically includes:

[0024] Photoresist 9 is filled on the ridge waveguide structure, and a protective layer 4 growth area is formed on the upper surface of the corresponding ridge 11 and the two sides of the ridge 11 at a predetermined height by photolithography; wherein, the upper surface of the ridge 11 is specifically manifested as an area covered with P-side electrode 3 and an area with composite film 2 reserved at both ends; the two sides of the ridge 11 are specifically manifested as an area covered with P-side electrode 3 and an area with composite film 2 reserved at both ends.

[0025] A silicon nitride thin film and a silicon dioxide thin film are grown sequentially using plasma chemical vapor deposition technology to form a protective layer 4. The protective layer 4 covers the upper surface and adjacent side surfaces of the P-side electrode 3 on the ridge 11 and the composite film 2 on the ridge 11.

[0026] Preferably, after forming the protective layer 4, the method further includes:

[0027] A metal thermally conductive layer 5 is applied to the area of ​​the epitaxial wafer 1, excluding the portion covered by the protective layer 4.

[0028] Preferably, after the N-face electrode fabrication and bar cleavage are completed, an aluminum oxide thin film is deposited on both end faces of the epitaxial wafer 1 as a passivation film 6.

[0029] Preferably, after depositing an aluminum oxide thin film on the cavity surfaces at both ends of the epitaxial wafer 1, the method further includes:

[0030] A high-reflectivity film 7 is deposited on the front cavity surface of the epitaxial wafer 1, and an antireflection film 8 is deposited on the rear cavity surface of the epitaxial wafer 1.

[0031] In a second aspect, an InP-based semiconductor laser chip, fabricated using the InP-based semiconductor laser chip fabrication method described in the first aspect, comprises the following structure:

[0032] A composite film 2 is coated on the upper surface of the epitaxial wafer 1 with a ridge waveguide structure. A conductive region 111 is photolithographically formed on the ridge 11. The conductive region 111 is located at the middle position in the extension direction of the ridge 11. A composite film 2 of a predetermined length is reserved on the upper surface of the ridge 11 near both ends.

[0033] P-surface electrodes 3 are provided on the conductive area 111 of the ridge 11 and the composite film 2. The length of the P-surface electrodes 3 is slightly greater than the length of the reserved surface in the middle part of the ridge 11, completely covering the conductive area 111 in the middle part of the ridge 11, and covering part of the composite film 2 at both ends of the surface of the ridge 11.

[0034] The ridge platform 11 is covered with a protective layer 4, which covers the P-side electrode 3 on the ridge platform 11 and the composite film 2 on the ridge platform 11.

[0035] The epitaxial wafer 1, excluding the area covered by the protective layer 4, is covered with a metal thermally conductive layer 5;

[0036] An aluminum oxide film is deposited on both ends of the epitaxial wafer 1 as a passivation film 6.

[0037] The front cavity surface of the epitaxial wafer 1 is provided with a high reflectivity film 7, and the rear cavity surface of the epitaxial wafer 1 is provided with an antireflection film 8.

[0038] Compared with the prior art, the beneficial effects of the present invention are:

[0039] The present invention provides an InP-based semiconductor laser chip and its fabrication method. In the process of fabricating the P-side electrode 3, the P-side electrode 3 near both ends of the ridge 11 is moved back by a certain area, and a dense protective layer 4 is used to correspond with the composite film 2 under the P-side electrode 3, thus providing double protection for the front side of the chip and preventing moisture from penetrating the active layer of the chip.

[0040] Furthermore, in a preferred embodiment of the present invention, the cavity surface is coated with an aluminum oxide passivation layer using ECR ion-assisted plating technology. Aluminum oxide not only has a similar coefficient of thermal expansion to InP material, but also has a denser film quality. Therefore, the cavity surface will not have gaps between different layers due to chip heating, and it also prevents moisture from slowly penetrating from the optical film into the active layer. [Attached Image Description]

[0041] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments of the present invention will be briefly described below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0042] Figure 1 A flowchart illustrating a method for fabricating an InP-based semiconductor laser chip according to an embodiment of the present invention;

[0043] Figure 2 This is a schematic diagram of the structure of an epitaxial wafer provided in an embodiment of the present invention;

[0044] Figure 3 A front view of the epitaxial wafer covering composite film in a method for fabricating an InP-based semiconductor laser chip according to an embodiment of the present invention;

[0045] Figure 4 A top view of an epitaxial wafer covering a composite film in a method for fabricating an InP-based semiconductor laser chip according to an embodiment of the present invention;

[0046] Figure 5 The epitaxial wafer covering composite film is provided in the fabrication method of an InP-based semiconductor laser chip according to an embodiment of the present invention. Figure 4 A sectional view;

[0047] Figure 6 A front view of the epitaxial wafer covering composite film in a method for fabricating an InP-based semiconductor laser chip according to an embodiment of the present invention;

[0048] Figure 7 A top view of the P-side electrode covering a method for fabricating an InP-based semiconductor laser chip according to an embodiment of the present invention.

[0049] Figure 8 The method for fabricating an InP-based semiconductor laser chip according to an embodiment of the present invention includes a P-side electrode. Figure 7 A sectional view;

[0050] Figure 9A front view of the protective layer covering a method for fabricating an InP-based semiconductor laser chip according to an embodiment of the present invention;

[0051] Figure 10 This is a top view of the protective layer covering a method for fabricating an InP-based semiconductor laser chip according to an embodiment of the present invention.

[0052] Figure 11 A protective coating for a method of fabricating an InP-based semiconductor laser chip provided in this embodiment of the invention. Figure 10 A sectional view;

[0053] Figure 12 A front view of the metal thermally conductive layer covering a method for fabricating an InP-based semiconductor laser chip according to an embodiment of the present invention;

[0054] Figure 13 A top view of the metal thermally conductive layer covering a method for fabricating an InP-based semiconductor laser chip according to an embodiment of the present invention;

[0055] Figure 14 A method for fabricating an InP-based semiconductor laser chip according to an embodiment of the present invention includes a covered metal thermally conductive layer. Figure 13 A sectional view;

[0056] Figure 15 A front view schematic diagram of the photolithography etching protective layer region in a method for fabricating an InP-based semiconductor laser chip according to an embodiment of the present invention;

[0057] Figure 16 A front view of photolithography etching and protective layer covering a method for fabricating an InP-based semiconductor laser chip according to an embodiment of the present invention;

[0058] Figure 17 A front view of the protective layer covering a method for fabricating an InP-based semiconductor laser chip according to an embodiment of the present invention;

[0059] Figure 18 This is a top view of the protective layer covering a method for fabricating an InP-based semiconductor laser chip according to an embodiment of the present invention.

[0060] Figure 19 A protective coating for a method of fabricating an InP-based semiconductor laser chip provided in this embodiment of the invention. Figure 18 A sectional view;

[0061] Figure 20 A front view of the metal thermally conductive layer covering a method for fabricating an InP-based semiconductor laser chip according to an embodiment of the present invention;

[0062] Figure 21 A top view of the metal thermally conductive layer covering a method for fabricating an InP-based semiconductor laser chip according to an embodiment of the present invention;

[0063] Figure 22 A method for fabricating an InP-based semiconductor laser chip according to an embodiment of the present invention includes a covered metal thermally conductive layer. Figure 21 A sectional view;

[0064] Figure 23 A top view of the passivation film covering a method for fabricating an InP-based semiconductor laser chip according to an embodiment of the present invention;

[0065] Figure 24 A top view of a method for fabricating an InP-based semiconductor laser chip according to an embodiment of the present invention, showing a coating of a high-reflectivity film and an anti-reflection film.

[0066] Figure 25 A top view of an InP-based semiconductor laser chip provided in an embodiment of the present invention;

[0067] Figure 26 An InP-based semiconductor laser chip provided as an embodiment of the present invention Figure 25 A sectional view;

[0068] Figure 27 A top view of an InP-based semiconductor laser chip provided in an embodiment of the present invention;

[0069] Figure 28 An InP-based semiconductor laser chip provided as an embodiment of the present invention Figure 27 A sectional view.

Detailed Implementation Methods

[0070] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0071] In the description of this invention, the terms "inner", "outer", "longitudinal", "lateral", "upper", "lower", "top", "bottom", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and do not require that this invention must be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0072] Furthermore, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0073] Example 1:

[0074] This invention provides a method for fabricating an InP-based semiconductor laser chip, such as... Figure 1 As shown, it includes the following steps:

[0075] In step 101, an epitaxial wafer 1 with a ridge waveguide structure is fabricated, and a composite film 2 is grown on the surface of the epitaxial wafer 1, wherein the rectangular portion in the middle of the ridge waveguide structure is called the ridge 11.

[0076] like Figure 2 As shown, in a typical example, the epitaxial wafer 1 is fabricated by the following method: using metal-organic chemical vapor deposition (MOCVD) technology, an n-InP buffer layer 12, an n-InAlAs layer 13, a multi-quantum-well active layer 14, a p-Inp layer 15, an InGaAsP etching barrier layer 16, and an InGaAs barrier layer 17 are sequentially grown on an InP substrate 11 to form the epitaxial wafer 1.

[0077] The thickness of each layer is provided in this embodiment for reference in related technical content. The thickness of the n-InP buffer layer 12 is approximately 0.13 μm, the thickness of the n-InAlAs layer 13 is approximately 0.05 μm, the multi-quantum-well layer 14 has 9 pairs of quantum wells with a well width of approximately 5.5 nm, a compressive strain of 1.3%, a barrier width of approximately 8.5 nm, a tensile strain of 0.58%, and a quantum well PL wavelength of approximately 1273 nm; the thickness of the p-Inp layer 15 is approximately 0.06 μm; the thickness of the InGaAsP corrosion barrier layer 16 is approximately 1.45 μm, and the thickness of the InGaAs barrier layer 17 is approximately 0.2 μm. It should be noted that the corresponding material layers and their thicknesses are not the focus of this invention; they are presented here merely as examples for relevance description to other related features of this invention.

[0078] In step 102, a conductive region 111 is photolithographically formed on the ridge 11. The conductive region 111 is located at the middle position in the extension direction of the ridge 11. A composite film 2 of a preset length is reserved on the upper surface of the ridge 11 near both ends.

[0079] Since the epitaxial wafer 1 needs to contact the P-side electrode 3 to fulfill the conductivity requirement of the laser chip, a portion of the composite film 2 needs to be photolithographically etched to expose the epitaxial wafer 1 below in contact with the P-side electrode 3, i.e., the conductive region 111 in step 102 above.

[0080] The preset length is determined based on the length of the ridge 11 on the epitaxial wafer 1 and the conductivity requirements of the laser chip. The conductive region 111 is located at the middle position of the ridge 11 extension direction, so there are composite films 2 with the same length at both ends of the ridge 11.

[0081] like Figure 4 and Figure 5 As shown, the process of photolithographically etching the conductive region 111 on the ridge 11 specifically includes: using a composite film 2 of a predetermined length as required, photolithographically leaving a conductive region 111 pattern in the middle of the ridge 11, and removing the composite film 2 in the middle of the ridge 11 using reactive ion etching.

[0082] In step 103, the coverage length of the P-side electrode 3 on the ridge 11 is determined by referring to the length of the conductive region 111 of the ridge 11, and the P-side electrode 3 is fabricated on the conductive region 111 of the ridge 11 and the composite film 2.

[0083] like Figures 6-8 As shown, a protective layer 4 is covered on the ridge 11 to cover the P-side electrode 3 on the ridge 11 and the composite film 2 reserved at both ends of the ridge 11.

[0084] The P-side electrode 3 completely covers the conductive region 111, ensuring the power supply between the epitaxial wafer 1 and the P-side electrode 3.

[0085] If the P-side electrode 3 also covers the composite film 2 at both ends of the ridge 11, the subsequent protective layer 4 cannot cover the P-side electrode 3 at both ends of the ridge 11. If the P-side electrode 3 deforms due to environmental factors, the P-side electrode 3 at the end of the ridge 11 may separate from the composite film 2 and generate cracks. Moisture enters from the cracks at the end of the end and slowly penetrates into the active layer of the conductive region 111.

[0086] Therefore, in this embodiment, the P-side electrode 3 does not completely cover the composite film 2 on the ridge 11. Instead, it completely covers the conductive area 111 while partially covering the composite film 2 at the upper and lower ends of the ridge 11. Since the covered portion of the composite film 2 at the upper and lower ends of the ridge 11 is limited, when the P-side electrode 3 deforms, moisture can easily enter the conductive area 111 through the cracks caused by the deformation. Therefore, the protective layer 4 is used to completely cover the P-side electrode 3 near the conductive area 111 at the ridge 11. This ensures that even if the P-side electrode 3 deforms due to environmental factors, it will be suppressed by the protective layer 4, preventing the P-side electrode 3 from separating from the composite film 2 and causing cracks. At the same time, it prevents moisture from slowly penetrating from the optical film into the active layer.

[0087] The P-side electrode 3, while retaining the composite film 2 at both the upper and lower ends, laterally covers the composite film 2 of the ridge 11 and the double groove portion.

[0088] In step 104, a protective layer 4 is applied to the P-side electrode 3 on the ridge 11 and the composite film 2 using a composite film 2 peeling process.

[0089] This is because the P-side electrode 3 may deform due to environmental factors, which could lead to cracks between the P-side electrode 3 and the composite film 2. Therefore, it is necessary to further protect the P-side electrode 3 and the composite film 2, hence the aforementioned protective layer 4.

[0090] like Figures 9-11 As shown, a protective layer 4 pattern is formed by photolithography on the P-side electrode 3 and the upper surface of the composite film 2 on the ridge 11. The protective layer 4 pattern covers the entire P-side electrode 3 and composite film 2 on the ridge 11. A composite film 2 peel-off process is used because peeling off the second composite film 2 will not damage the first protective layer 4. Specifically, the first layer of LOR adhesive is applied at a reference rotation speed of 3000 rad / s, baked at a reference temperature of 160°C for a reference duration of 3 minutes; then, the second layer of 512 adhesive is applied at a reference rotation speed of 3000 rad / s, baked at a reference temperature of 90°C, and exposed and developed to leave the protective layer 4 pattern. A silicon nitride thin film and a silicon dioxide thin film are sequentially grown using plasma chemical vapor deposition to form the protective layer 4.

[0091] The reference thickness of the silicon nitride film is 100 nm, the reference thickness of the silicon dioxide film is 100 nm, the reference RF power of the PEVCD for growing the protective layer 4 is 250 W, and the reference temperature inside the chamber is 50 °C. The protective layer 4 grown under the reference conditions is very dense, which further ensures that water vapor will not penetrate from the two end faces of the laser chip. However, the protective layer 4 has very high stress. Therefore, in the previous step of fabricating the P-side electrode 3, a chemical gold plating process is used to plate a gold layer. Since the chemically plated gold layer has a certain degree of flexibility, it can completely absorb the stress brought by the protective layer 4.

[0092] The protective layer 4 covers the P-side electrode 3 on the ridge 11 and the composite film 2 on the ridge 11.

[0093] The coverage area of ​​the protective layer 4 depends on the coverage area of ​​the P-side electrode 3. It covers all exposed P-side electrodes 3 and simultaneously covers the composite film 2 at the top and bottom ends that are not covered by P-side electrodes 3. This ensures that the exposed P-side electrodes 3 and composite film 2 on the upper and side surfaces of the ridge 11 are all covered by the protective layer 4. At the same time, the edge of the P-side electrode 3 that contacts the conductive area 111 on the epitaxial wafer 1 will not be exposed. This prevents moisture from entering through the crack when the P-side electrode 3 deforms and cracks appear on the upper surface of the epitaxial wafer 1 due to environmental factors. However, since a metal thermal conductive layer 5 needs to be added later, the metal thermal conductive layer 5 cannot cover the protective layer 4. Therefore, the area that the metal thermal conductive layer 5 can cover is relatively small.

[0094] In step 105, after the protective layer 4 is formed, a metal thermally conductive layer 5 is applied to the area of ​​the epitaxial wafer 1 other than the area covered by the protective layer 4.

[0095] like Figures 12-14 As shown, since the metal thermal conductive layer 5 cannot cover the protective layer 4, the metal thermal conductive layer 5 only covers the area excluding the part of the protective layer 4 and fills the upper surface of the epitaxial wafer 1. Therefore, when the protective layer 4 completely covers all P-side electrodes 3, the area that the metal thermal conductive layer 5 can cover is relatively small.

[0096] Considering that the protective layer 4 mainly protects the contact portion between the P-side electrode 3 and the conductive region 111 of the epitaxial wafer 1, preventing deformation of the P-side electrode 3 due to environmental factors, which could cause moisture to enter the conductive region 111 through cracks created by deformation, the protective layer 4 can only cover the P-side electrode 3 of the ridge 11 portion. The other portions, being too far from the conductive region 111, can be left without the protective layer 4. Instead, the protective layer 4 can be replaced with a metal thermally conductive layer 5 to further improve thermal conductivity. Therefore, another preferred solution is:

[0097] like Figures 15-19 As shown, covering the ridge 11 with a protective layer 4 includes:

[0098] Photoresist 9 is filled on the ridge waveguide structure, and a protective layer 4 growth area is formed on the upper surface of the corresponding ridge 11 and the two sides of the ridge 11 at a predetermined height by photolithography; wherein, the upper surface of the ridge 11 is specifically manifested as the area covered by the P-side electrode 3 and the area at both ends covered by the composite film 2; the two sides of the ridge 11 are specifically manifested as the area covered by the P-side electrode 3 and the area at both ends covered by the composite film 2.

[0099] The photoresist 9 covers the P-side electrode and composite film on the epitaxial wafer, and illuminates the upper surface of the ridge 11 and the two sides of the ridge 11 at a predetermined height. The photoresist 9 then etches the area and covers the photolithographically etched area with a protective layer 4.

[0100] Silicon nitride and silicon dioxide films are grown sequentially using plasma chemical vapor deposition to form a protective layer 4. The protective layer 4 covers the upper surface and adjacent side surfaces of the P-side electrode 3 on the ridge 11 and the composite film 2 on the ridge 11. After the protective layer 4 is completed, the remaining photoresist 9 is removed.

[0101] The preset height of the two sides is less than the height of the ridge 11 and much greater than the thickness of the P-side electrode 3; the protective layer 4 only covers the upper surface of the ridge 11 and the preset height area of ​​the two sides, ensuring that the front and rear ends and the left and right sides of the conductive area 111 that are in contact with the P-side electrode 3 are all covered by the protective layer 4, directly preventing the P-side electrode 3 near the conductive area 111 from deforming and causing water vapor to enter, while leaving the other positions except for the protective layer 4 to the metal heat-conducting layer 5.

[0102] like Figures 20-22 As shown, after the protective layer 4 is formed, a metal thermally conductive layer 5 is applied to the other areas of the epitaxial wafer 1, excluding the area covered by the protective layer 4.

[0103] Since the metal thermally conductive layer 5 cannot overlap with the protective layer 4, the metal thermally conductive layer 5 only covers the area excluding the part of the protective layer 4 and fills the upper surface of the epitaxial sheet 1. Compared with the previous solution, since the area covered by the protective layer 4 in this solution is only the upper surface and two sides of the ridge 11, the area occupied by the protective layer 4 is smaller. Therefore, the coverage area of ​​the metal thermally conductive layer 5 is larger, which further improves the thermal conductivity.

[0104] In step 106, after completing the fabrication of the N-face electrode and bar cleavage, an aluminum oxide thin film is deposited on both end faces of the epitaxial wafer 1 as a passivation film 6.

[0105] like Figure 23As shown, the InP substrate 11 of the epitaxial wafer 1 is thinned to 90-100 μm, and then an N-side electrode is fabricated using metal sputtering technology. Titanium, platinum, and gold are sputtered sequentially as N-side electrodes, with reference sputtering thicknesses of 80 nm for titanium, 90 nm for platinum, and 300 nm for gold. The working principle is the same as that of the P-side electrode 3. After the N-side electrode is completed, the bar strips of the epitaxial wafer 1 are cleaved, and then an aluminum oxide thin film is deposited on the front and back cavity surfaces of the chip as a passivation film 6 using ECR ion-assisted deposition technology. The reference thickness of the passivation layer is 20-30 nm, with a reference RF power of 250 W and a reference microwave power of 300 W. The dense characteristics of the passivation film 6 grown using ECR ion-assisted deposition technology prevent moisture from penetrating into the active layer of the chip from the end face.

[0106] like Figure 24 As shown, an antireflective film 8 is deposited on the front light-emitting surface of the bar strip using electron beam evaporation, and a high-reflective film 7 is deposited on the back light-emitting surface of the bar strip to complete the chip fabrication process.

[0107] The reference data provided in this embodiment represents only one possible solution under a specific scenario and is not limited to the above reference data. Those skilled in the art can design and adjust the data according to the actual situation. All related changes brought about by the data should be within the protection scope of this invention.

[0108] In conjunction with the embodiments of the present invention, a more detailed process for growing the composite film 2 in step 101 is also provided. In the following description, the key layer structure contained in the epitaxial wafer 1 exemplified in step 101 will be used for further explanation.

[0109] After the epitaxial wafer 1 is fabricated, a SiNx mask layer is grown on the surface of the epitaxial wafer 1, a double-groove pattern is left by photolithography etching, the InGaAs blocking layer on the surface of the double groove is removed, and then the ridge of the ridge waveguide 11 is obtained by solution etching.

[0110] The SiNx mask layer has a reference thickness of 120 nm, and its thickness is described with reference to the thickness of each layer in the epitaxial wafer in Example 1 above. Through the photolithography, a double-groove pattern is left on the SiNx mask layer, wherein the rectangular part in the middle of the double-groove pattern is called the ridge 11.

[0111] Based on the double-groove pattern of the ridge waveguide structure that has already been etched, the InGaAs barrier layer 17 on the surface of the double groove is first etched using reaction ion etching (RIE) technology. In this embodiment, the etching reference depth is approximately 450 nm. Then, the ridge 11 of the ridge waveguide structure is obtained after chemical etching. The etching solution is a mixture of 36% HCl and H3PO4 in a volume ratio of 1:3, or other etching solutions that can achieve the same etching effect should be included within the scope of protection of this invention.

[0112] like Figure 3 As shown, the growth of the composite film 2 on the surface of the epitaxial wafer 1 includes:

[0113] First, the remaining SiNx mask layer on the surface of the epitaxial wafer 1 is etched away using a buffered oxidized acid solution (BOE) to obtain a ridge waveguide structure. Then, a silicon nitride thin film is grown on the surface of the epitaxial wafer 1 using plasma chemical vapor deposition, followed by the growth of a silicon dioxide thin film, thereby forming a composite film 2. The lengths of the silicon nitride thin film and the silicon dioxide thin film are designed by those skilled in the art according to the actual situation. Any composite film 2 design that can meet the functional application in this scenario should be within the protection scope of this invention.

[0114] The silicon nitride-silicon dioxide composite film 2 is used because pure silicon nitride films exhibit compressive stress, while pure silicon dioxide films exhibit tensile stress. The silicon nitride-silicon dioxide composite film 2 can offset some of the stress, reducing the changes in laser chip characteristics caused by film stress.

[0115] In conjunction with the embodiments of the present invention, the fabrication of the P-side electrode 3 on the composite film 2 in step 103 is further provided in a more detailed manner, including:

[0116] Electrode patterns are formed on the surface of composite film 2 by photolithography. Based on these patterns, titanium, platinum, and gold are sequentially sputtered using a metal sputtering process to fabricate the P-side electrode 3. For conventional ridge waveguide structures, using traditional evaporation electrode technology to fabricate the P-side electrode 3 results in insufficient gold layer density, allowing moisture to easily penetrate and corrode the active layer. However, using a metal sputtering process to create a metal layer as an electrode prevents moisture from penetrating the front gold layer into the chip. Since there is no gold layer on the chip's cleaved cavity surface, there is no metal at the interface during chip cleaving bars. This prevents direct contact between the optical film and the metal during coating, avoiding the increase in the metal's coefficient of thermal expansion when the chip emits light and heats up, which could lead to gaps between the optical film and the cavity surface.

[0117] The P-side electrode 3 is fabricated by sequentially sputtering titanium, platinum, and gold using a metal sputtering process because titanium, as a metal, has excellent adhesion to silicon dioxide, while platinum and gold provide good ohmic contact. The reference thicknesses for sputtering titanium, platinum, and gold are 80 nm for titanium, 90 nm for platinum, and 300 nm for gold, respectively, with a reference sputtering power of 250 W. After the alloy is heated to 410°C for 2 minutes, the resistance decreases significantly. Then, a chemical gold plating process is used to deposit a gold layer, which further enhances the heat dissipation effect. The reference thickness of the chemical gold plating layer is 1 μm.

[0118] Example 2:

[0119] This invention provides an InP-based semiconductor laser chip, which, based on the fabrication method of the InP-based semiconductor laser chip in Example 1, presents a structure of the fabricated InP-based semiconductor laser chip in a more specific scenario.

[0120] like Figure 25 and Figure 26 As shown, in this embodiment, the protective layer 4 completely covers the P-side electrode 3, providing relatively more robust protection, but the coverage area of ​​the metal thermal conductive layer 5 is relatively small.

[0121] The upper surface of the epitaxial wafer 1 with the ridge waveguide structure is covered with a composite film 2. The rectangular part in the middle of the ridge waveguide structure is called the ridge 11. The composite film 2 at the middle position in the extension direction of the ridge 11 is photolithographically etched into a conductive region 111. A composite film 2 of a preset length is reserved on the upper surface of the ridge 11 near both ends.

[0122] The ridge 11 has a length of 200 μm, the conductive region 111 at the middle position of the ridge 11 in the extension direction has a length of 180 μm, and a composite film 2 with a length of 10 μm is reserved on the upper surface of the ridge 11 near both ends.

[0123] P-surface electrodes 3 are provided on the conductive area 111 of the ridge 11 and the composite film 2. The P-surface electrodes 3 have a coverage length of 190 μm on the ridge 11 and the double groove region, completely covering the conductive area 111 in the middle part of the ridge 11, and covering the composite film 2 on the upper surface of the ridge 11 and the double groove region near both ends by 5 μm each.

[0124] The P-side electrode 3 is specifically constructed by sequentially sputtering titanium with a thickness of 80 nm, platinum with a thickness of 90 nm and gold with a thickness of 300 nm using a metal sputtering process, and then electroplating a 1 μm thick gold layer using a chemical gold plating process.

[0125] A protective layer 4 covers the composite film 2 and the P-side electrode 3. The protective layer 4 has a coverage length of 200 μm, specifically consisting of a 100 nm silicon nitride and a 100 nm silicon dioxide thin film. The protective layer 4 completely covers the P-side electrode 3 on the epitaxial wafer 1, and also covers the composite film 2 at both ends that are not covered by the P-side electrode 3.

[0126] The epitaxial wafer 1, excluding the area covered by the protective layer 4, is covered with a metal thermally conductive layer 5, the metal thermally conductive layer 5 having a coverage length of 200um.

[0127] An aluminum oxide thin film is deposited on both ends of the epitaxial wafer 1 as a passivation film 6, and the thickness of the aluminum oxide thin film is 25 nm.

[0128] The front cavity surface of the epitaxial wafer 1 is provided with a high reflectivity film 7, and the rear cavity surface of the epitaxial wafer 1 is provided with an antireflection film 8.

[0129] Example 3:

[0130] This invention provides an InP-based semiconductor laser chip, which, based on the fabrication method of the InP-based semiconductor laser chip in Example 1, presents a structure of the fabricated InP-based semiconductor laser chip in a more specific scenario.

[0131] like Figure 27 and Figure 28 As shown, in this embodiment, the protective layer 4 only covers the P-side electrode 3 of the ridge 11 portion, providing targeted protection for the conductive area 111, thereby providing a larger coverage area for the metal thermal conductive layer 5 and further improving the thermal conductivity.

[0132] The upper surface of the epitaxial wafer 1 with the ridge waveguide structure is covered with a composite film 2. The rectangular part in the middle of the ridge waveguide structure is called the ridge 11. The composite film 2 at the middle position in the extension direction of the ridge 11 is photolithographically etched into a conductive region 111. A composite film 2 of a preset length is reserved on the upper surface of the ridge 11 near both ends.

[0133] The ridge 11 has a length of 200 μm, the conductive region 111 at the middle position of the ridge 11 in the extension direction has a length of 160 μm, and a composite film 2 with a length of 20 μm is reserved on the upper surface of the ridge 11 near both ends.

[0134] P-surface electrodes 3 are provided on the conductive area 111 of the ridge 11 and the composite film 2. The P-surface electrodes 3 have a coverage length of 180 μm on the ridge 11 and the double groove region, completely covering the conductive area 111 in the middle part of the ridge 11, and covering the composite film 2 on the upper surface of the ridge 11 and the double groove region near both ends by 10 μm each.

[0135] The P-side electrode 3 is made by sequentially sputtering titanium with a thickness of 80 nm, platinum with a thickness of 90 nm and gold with a thickness of 300 nm using a metal sputtering process, and then electroplating a 1 μm thick gold layer using a chemical gold plating process.

[0136] A protective layer 4 covers the composite film 2 and the P-side electrode 3. The protective layer 4 has a coverage length of 200 μm and is specifically a silicon nitride film with a thickness of 100 nm and a silicon dioxide film with a thickness of 100 nm. The protective layer 4 completely covers the P-side electrode 3 on the epitaxial wafer 1, and also covers the composite film 2 at both ends that are not covered by the P-side electrode 3.

[0137] The epitaxial wafer 1, excluding the area covered by the protective layer 4, is covered with a metal thermally conductive layer 5, the metal thermally conductive layer 5 having a coverage length of 200um.

[0138] An aluminum oxide thin film is deposited on both ends of the epitaxial wafer 1 as a passivation film 6, and the thickness of the aluminum oxide thin film is 30 nm.

[0139] The front cavity surface of the epitaxial wafer 1 is provided with a high reflectivity film 7, and the rear cavity surface of the epitaxial wafer 1 is provided with an antireflection film 8.

[0140] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for fabricating an InP-based semiconductor laser chip, characterized in that, include: An epitaxial wafer (1) with a ridge waveguide structure is fabricated, and a composite film (2) is grown on the surface of the epitaxial wafer (1), wherein the rectangular part in the middle of the ridge waveguide structure is called the ridge (11). Conductive regions (111) are photolithographically etched on the ridge (11). The conductive regions (111) are located in the middle position in the extension direction of the ridge (11). Composite films (2) of a preset length are reserved on the upper surface of the ridge (11) near both ends. Based on the length of the conductive area (111) of the ridge (11), the coverage length of the P-side electrode (3) on the ridge (11) is determined, and the P-side electrode (3) is fabricated on the conductive area (111) of the ridge (11) and the composite film (2). A protective layer (4) is placed on the P-side electrode (3) and the composite film (2) of the ridge (11) to cover the P-side electrode (3) on the ridge (11) and the composite film (2) reserved at both ends of the ridge (11); The P-side electrode (3) is recessed at both ends in the extension direction of the ridge (11) so that the protective layer (4) covers the end faces of both ends of the P-side electrode (3). Photoresist (9) is filled on the ridge waveguide structure, and a protective layer (4) growth area is formed on the upper surface of the corresponding ridge (11) and the two sides of the ridge (11) at a predetermined height by photolithography; wherein, the upper surface of the ridge (11) is specifically manifested as the area covered by the P-side electrode (3) and the area at both ends covered by the composite film (2); the two sides of the ridge (11) are specifically manifested as the area covered by the P-side electrode (3) and the area at both ends covered by the composite film (2); A protective layer (4) is formed by sequentially growing a silicon nitride thin film and a silicon dioxide thin film using plasma chemical vapor deposition technology. The protective layer (4) covers the upper surface and adjacent side surfaces of the P-side electrode (3) on the ridge (11) and the composite film (2) on the ridge (11).

2. The method for fabricating an InP-based semiconductor laser chip according to claim 1, characterized in that, The epitaxial wafer (1) with the ridge waveguide structure specifically includes: After the epitaxial wafer (1) is fabricated, SiN is grown on the surface of the epitaxial wafer (1). x The mask layer is used to leave a double-groove pattern of the ridge waveguide structure by photolithography and etching. The InGaAs blocking layer on the surface of the double groove is removed, and then the ridge of the ridge waveguide is obtained by solution etching (11).

3. The method for fabricating an InP-based semiconductor laser chip according to claim 1, characterized in that, The fabrication of a P-surface electrode (3) on the conductive region (111) of the ridge (11) and the composite film (2) specifically includes: Electrode patterns are formed by photolithography on the upper surface of the composite film (2), and titanium, platinum and gold are sputtered sequentially according to the electrode patterns to fabricate the P-side electrode (3); wherein the length of the P-side electrode (3) is slightly greater than the length of the reserved surface in the middle part of the ridge (11), completely covering the conductive area (111) in the middle part of the ridge (11), and covering part of the composite film (2) at both ends of the surface of the ridge (11).

4. The method for fabricating an InP-based semiconductor laser chip according to claim 1, characterized in that, The provision of a protective layer (4) covering the ridge (11) specifically includes: A protective layer (4) pattern is formed by photolithography on the P-side electrode (3) on the ridge (11) and the upper surface of the composite film (2); A protective layer (4) is formed by sequentially growing a silicon nitride thin film and a silicon dioxide thin film using plasma chemical vapor deposition technology; wherein the protective layer (4) covers the P-side electrode (3) on the ridge (11) and the composite film (2) on the ridge (11).

5. The method for fabricating an InP-based semiconductor laser chip according to claim 4, characterized in that, After forming the protective layer (4), the method further includes: A metal thermally conductive layer (5) is applied to the area of ​​the epitaxial wafer (1) excluding the portion covered by the protective layer (4).

6. The method for fabricating an InP-based semiconductor laser chip according to claim 1, characterized in that, After forming the protective layer (4), the method further includes: A metal thermally conductive layer (5) is applied to the area of ​​the epitaxial wafer (1) excluding the portion covered by the protective layer (4).

7. The method for fabricating an InP-based semiconductor laser chip according to any one of claims 1-6, characterized in that, After completing the fabrication of the N-face electrode and bar cleavage, an aluminum oxide thin film is deposited on both ends of the epitaxial wafer (1) as a passivation film (6).

8. The method for fabricating an InP-based semiconductor laser chip according to claim 7, characterized in that, After depositing an aluminum oxide thin film on the cavity surfaces at both ends of the epitaxial wafer (1), the method further includes: A high-reflectivity film (7) is deposited on the front cavity surface of the epitaxial wafer (1), and an anti-reflection film (8) is deposited on the rear cavity surface of the epitaxial wafer (1).

9. An InP-based semiconductor laser chip, characterized in that, The fabrication method of the InP-based semiconductor laser chip according to any one of claims 1-8 comprises the following structure: The epitaxial wafer (1) with a ridge waveguide structure is covered with a composite film (2) on its upper surface. The rectangular part in the middle of the ridge waveguide structure is called the ridge (11). The composite film (2) at the middle position of the ridge (11) in the extension direction is photolithographically etched into a conductive region (111). A composite film (2) of a preset length is reserved on the upper surface of the ridge (11) near both ends. P-face electrodes (3) are provided on the conductive area (111) of the ridge (11) and the composite film (2). The length of the P-face electrodes (3) is slightly greater than the length of the reserved surface in the middle part of the ridge (11), completely covering the conductive area (111) in the middle part of the ridge (11), and covering part of the composite film (2) at both ends of the surface of the ridge (11). A protective layer (4) is covered on the ridge (11), and the protective layer (4) covers the P-side electrode (3) on the ridge (11) and the composite film (2) on the ridge (11); the two ends of the P-side electrode (3) are recessed in the extension direction of the ridge (11) so that the protective layer (4) covers the two end faces of the P-side electrode (3). The epitaxial wafer (1) is covered with a metal thermally conductive layer (5) in the area other than the part covered by the protective layer (4). An aluminum oxide film is deposited on both ends of the epitaxial wafer (1) as a passivation film (6). The front end cavity surface of the epitaxial wafer (1) is provided with a high reflectivity film (7), and the rear end cavity surface of the epitaxial wafer (1) is provided with an antireflection film (8).

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