Decoder architecture for three-dimensional memory devices

Abstract

This application relates to decoder architectures for three-dimensional memory devices. In some cases, a decoder for a memory device can include two parts. A first part of the decoder can be fabricated on top of the memory array and can include a column decode portion that selectively biases an array of first decoding elements coupled with conductive pillars of the memory array and a word line decode portion that selectively biases an array of second decoding elements coupled with word lines of the memory array. A second part of the decoder can be implemented in a separate semiconductor device that can include a set of logic circuits configured to drive signals to a set of contacts that are joined to contacts of the first part to drive digit lines, voltage sources, and gate lines.

Description

[0001] Cross-referencing

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 830,042, filed June 1, 2022, entitled “DECODER ARCHITECTURES FOR THREE-DIMENSIONAL MEMORYDEVICES”, which is assigned to its assignee and is expressly incorporated herein by reference. Technical Field

[0003] The technical field relates to decoder architectures for three-dimensional memory devices. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to support one of two states, often represented by logic 1 or logic 0. In some instances, a single memory cell can support more than two states, any of which can be stored. To access the stored information, components can read (e.g., sense, detect, retrieve, identify, determine, evaluate) the stored states in the memory device. To store information, components can write (e.g., program, set, specify) states into the memory device.

[0005] Various types of memory devices and memory cells exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), auto-select memory, chalcogenide memory technology, etc. Memory cells can be described in terms of volatile or non-volatile configurations. Memory cells configured in a non-volatile configuration can maintain their stored logic state for a long period of time, even without an external power supply. Memory cells configured in a volatile configuration may lose their stored state when disconnected from an external power supply. Summary of the Invention

[0006] Describe an apparatus. The apparatus may include: a first semiconductor device including a plurality of word lines disposed in a hierarchy and a plurality of conductive pillars extending through the plurality of word lines, the first semiconductor device including: a first plurality of vertical transistors, each of the first plurality of vertical transistors selectively coupling a corresponding conductive pillar to a corresponding digital line of a plurality of digital lines; a second plurality of vertical transistors, each of the second plurality of vertical transistors selectively coupling a corresponding word line to a corresponding voltage source of a plurality of voltage sources; and a plurality of first contacts, a first subset of the plurality of first contacts coupled to the first plurality of vertical transistors, and a second subset of the plurality of first contacts coupled to the second plurality of vertical transistors; and a second semiconductor device including one or more logic circuits formed in a semiconductor substrate of the second semiconductor device, the second semiconductor device including: a plurality of second contacts; and a third plurality of transistors, at least a subset of the third plurality of transistors having terminals coupled to the plurality of second contacts, the plurality of first contacts of the first semiconductor device being engaged with the plurality of second contacts of the second semiconductor device.

[0007] Describe an apparatus. The apparatus may include: a plurality of word line boards of a memory array arranged in a plurality of layers, each word line board including one or more word line components extending in a first horizontal direction; a plurality of conductive pillars extending through the plurality of word line boards, wherein, at each word line board in the plurality of layers, one or more memory cells of the memory array are coupled to a corresponding conductive pillar and a corresponding component of the word line board; a plurality of digital lines extending in a second horizontal direction orthogonal to the first horizontal direction; and a decoder offset along a vertical direction from the plurality of layers and configured to bias the plurality of conductive pillars and the plurality of word line boards, the decoder including: a first portion including one or more logic circuits at least partially formed within a semiconductor substrate and associated with operating the memory array; and a second portion positioned along a vertical direction between the first portion of the decoder and the memory array, the second portion of the decoder including a first plurality of decoding elements configured to couple a corresponding conductive pillar to a corresponding digital line and a second plurality of decoding elements configured to couple a word line board to a corresponding voltage source among a plurality of voltage sources.

[0008] A method is described. The method may include: forming a layered assembly comprising a plurality of word lines arranged in a plurality of layers of a memory array, each word line including one or more word line components extending in a first horizontal direction, a plurality of conductive pillars extending through the plurality of word lines, and a plurality of digital lines coupled to the plurality of word lines and extending in a second horizontal direction orthogonal to the first horizontal direction; forming a first portion of a decoder in a first substrate above the layered assembly, the first portion of the decoder including a first plurality of decoding elements configured to couple corresponding conductive pillars to corresponding digital lines, and a second plurality of decoding elements configured to couple corresponding word lines to corresponding voltage sources of a plurality of voltage sources and a plurality of first contacts, each first contact being coupled to a corresponding subset of the first plurality of decoding elements or to a corresponding subset of the second plurality of decoding elements; forming a second portion of the decoder in a second substrate, the second portion of the decoder including a plurality of second contacts and a plurality of transistors, at least a subset of the plurality of transistors having terminals coupled to the plurality of second contacts; and engaging each of the plurality of first contacts to a corresponding second contact of the plurality of second contacts, wherein the engagement positions the first portion of the decoder between the layered assembly and the second portion of the decoder. Attached Figure Description

[0009] Figure 1 This describes an example of a memory array that supports a decoder architecture for a three-dimensional memory device, based on examples disclosed herein.

[0010] Figure 2 This is a top view illustrating an example of a memory array that supports a decoder architecture for a three-dimensional memory device, as illustrated in the examples disclosed herein.

[0011] Figure 3A and 3B This illustrates a side view of an example of a memory array that supports a decoder architecture for a three-dimensional memory device, as illustrated in the examples disclosed herein.

[0012] Figure 4 This describes an example of a system that supports a decoder architecture for a three-dimensional memory device, based on examples disclosed herein.

[0013] Figure 5 This describes an example of a system that supports a decoder architecture for a three-dimensional memory device, based on examples disclosed herein.

[0014] Figure 6 This describes an example of a system that supports a decoder architecture for a three-dimensional memory device, based on examples disclosed herein.

[0015] Figure 7 The flowchart illustrates one or more methods for supporting decoder architectures for three-dimensional memory devices, based on examples disclosed herein. Detailed Implementation

[0016] Some memory devices may include a decoder coupled to a memory array. In some cases, the decoder is operable to bias access lines of the memory array as part of accessing memory cells of the memory array. For example, the memory array may be an example of a three-dimensional memory array having a vertical stack of word line boards and a set of digital lines coupled to conductive pillars extending vertically through the stack of word line boards, wherein memory cells are located at the intersection of the conductive pillars and the word line boards. To access memory cells, the memory device may include a decoder operable to drive signals to selected word line boards and selected conductive pillars using a set of transistors. The selected word line boards may be selectively coupled to a voltage source operable to provide signals via the decoder. Similarly, selected conductive pillars may be selectively coupled to digital lines that can be used to transmit signals to and from sensing circuitry (e.g., a sense amplifier). In some cases, each word line board may contain a number of isolation segments that can be independently addressed by the decoder using dedicated transistors for each segment. This reduces unwanted capacitances (e.g., parasitic capacitances) generated by the word line board. However, using dedicated transistors for each segment of the word line board can result in a large number of transistors, which may increase the complexity of decoding word lines and conductive posts. Therefore, techniques for efficiently decoding word lines and conductive posts are needed.

[0017] As described herein, a decoder for a memory device may comprise two parts. A first part of the decoder may be fabricated on the same substrate as the memory array (e.g., below or on top of the memory array) and may include a pillar decoding section and a word line decoding section. The pillar decoding section may include a first array of decoding elements (e.g., transistors, such as vertical transistors or thin-film transistors (TFTs)) coupled to corresponding conductive pillars and digital lines extending in a first horizontal direction, while the word line decoding section may include a second array of decoding elements coupled to corresponding word line sections and voltage sources extending in the first horizontal direction. The pillar decoding section and the word line decoding section may further include a set of gate lines extending in a second horizontal direction and configured to activate a column of decoding elements. The second part of the decoder may be implemented in a separate semiconductor device (e.g., a separate substrate) that may include a set of logic circuitry, such as complementary metal-oxide-semiconductor (CMOS) circuitry, configured to drive signals to a set of contacts. In some cases, the contacts of the second part may be coupled to the contacts of the first part to drive the digital lines, voltage sources, and gate lines (e.g., using hybrid bonding). Due to the array structure of the first section, a single decoding element of the array can be selected and driven by driving a first signal via a first contact to activate a column of decoding elements containing the selected decoding element and by driving a second signal via a second contact to bias a voltage source or digital line coupled to the selected decoding element. Therefore, a smaller number of contacts relative to the number of decoding elements can be used to decode word line portions and conductive posts.

[0018] Firstly, in reference Figure 1 , 2 Features of this disclosure are described in the context of memory devices and arrays of types 3A and 3B. (See references...) Figures 4 to 6 The features of this disclosure are described in the context of the system. (Refer to device diagrams and references as shown in the references.) Figure 7 The flowcharts describing the decoder architecture involving a three-dimensional memory device are provided to further illustrate and describe these and other features of this disclosure.

[0019] Figure 1 This describes an example of a memory device 100 that supports a decoder architecture for a three-dimensional memory device, as disclosed herein. In some instances, the memory device 100 may be referred to as or comprise a memory die, a memory chip, or an electronic memory device. The memory device 100 may be operable to provide a location for storing information (e.g., a physical memory address) that is available for use by a system (e.g., for a host device coupled to the memory device 100 to write or read information).

[0020] Memory device 100 may include one or more memory cells 105, each programmable to store different logic states (e.g., programmed states from a set of two or more possible states). For example, memory cell 105 may be operable to store one bit of information at a time (e.g., logic 0 or logic 1). In some instances, memory cell 105 (e.g., multi-level memory cell 105) may be operable to store more than one bit of information at a time (e.g., logic 00, logic 01, logic 10, logic 11). In some instances, memory cells 105 may be arranged in an array.

[0021] Memory cell 105 may use configurable materials to store logical states. These configurable materials may be referred to as memory elements, storage elements, memory storage elements, material elements, material memory elements, material portions, or material portions with write polarity, etc. The configurable material of memory cell 105 may refer to chalcogenide-based storage components. For example, chalcogenide storage elements may be used in phase-change memory cells, threshold processing memory cells, or auto-select memory cells, as well as other architectures.

[0022] In some instances, the material of memory cell 105 may comprise chalcogenide materials or other alloys, including selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), silicon (Si), or indium (In), or various combinations thereof. In some instances, chalcogenide materials primarily comprising selenium (Se), arsenic (As), and germanium (Ge) may be referred to as SAG alloys. In some instances, SAG alloys may also comprise silicon (Si), and such chalcogenide materials may be referred to as SiSAG alloys. In some instances, SAG alloys may comprise silicon (Si) or indium (In), or combinations thereof, and such chalcogenide materials may be referred to as SiSAG alloys or InSAG alloys, or combinations thereof. In some instances, chalcogenide materials may comprise additional elements, such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F), each in atomic or molecular form.

[0023] In some instances, memory cell 105 may be an example of a phase-change memory cell. In such instances, the material used in memory cell 105 may be based on an alloy (e.g., the alloys listed above) and operable to change to a different physical state (e.g., undergo a phase transition) during normal operation of memory cell 105. For example, phase-change memory cell 105 may be associated with a relatively disordered atomic configuration (e.g., a relatively amorphous state) and a relatively ordered atomic configuration (e.g., a relatively crystalline state). The relatively disordered atomic configuration may correspond to a first logic state (e.g., a reset state, logic 0), and the relatively ordered atomic configuration may correspond to a second logic state (e.g., a logic state different from the first logic state, a set state, logic 1).

[0024] In some instances (e.g., for threshold processing memory cell 105, for auto-select memory cell 105), some or all of the set of logic states supported by memory cell 105 may be associated with a relatively disordered atomic configuration of a chalcogenide material (e.g., amorphous materials are operable to store different logic states). In some instances, the storage elements of memory cell 105 may be instances of auto-select memory elements. In such instances, the material used in memory cell 105 may be based on an alloy (e.g., alloys listed above) and operable to undergo changes in different physical states during normal operation of memory cell 105. For example, auto-select or threshold processing memory cell 105 may have a high threshold voltage state and a low threshold voltage state. The high threshold voltage state may correspond to a first logic state (e.g., a reset state, logic 0), and the low threshold voltage state may correspond to a second logic state (e.g., a logic state different from the first logic state, a set state, logic 1).

[0025] During a write operation (e.g., a programming operation) of the self-selected or threshold-processed memory cell 105, the polarity of the write operation can affect (e.g., determine, set, program) the behavior or characteristics of the material of the memory cell 105, such as the threshold processing characteristics of the material (e.g., threshold voltage). For different logic states stored by the material of the memory cell 105, the difference between the threshold processing characteristics of the material of the memory cell 105 (e.g., the difference between the threshold voltage when the material is storing logic state '0' versus when the material is storing logic state '1') can correspond to the read window of the memory cell 105.

[0026] Memory device 100 may include access lines arranged in a pattern (e.g., a grid pattern), such as row lines 115 extending along an illustrative x-direction and column lines 125 extending along an illustrative y-direction. The access lines may be formed of one or more conductive materials. In some instances, row line 115 or a portion thereof may be referred to as a word line. In some instances, column line 125 or a portion thereof may be referred to as a number line or bit line. References to access lines or the like are interchangeable without affecting understanding. Memory cells 105 may be located at the intersection of access lines (e.g., row lines 115 and column lines 125). In some instances, memory cells 105 may also be arranged (e.g., addressed) along an illustrative z-direction, for example in an embodiment where a group of memory cells 105 are located at different levels (e.g., layers, stacks, planes, hierarchies) along the illustrative z-direction. In some instances, the memory device 100, which includes memory cells 105 at different levels, may be supported by access lines, decoders, and other supporting circuitry systems with different configurations than those shown.

[0027] Operations such as read and write operations can be performed on memory cell 105 by activating access lines (e.g., one or more of row lines 115 or column lines 125) and other access lines associated with alternative configurations. For example, memory cell 105 can be accessed based on its intersection by activating row lines 115 and column lines 125 (e.g., applying voltage to row lines 115 or column lines 125). The intersection of row lines 115 and column lines 125 and other access lines in various two-dimensional or three-dimensional configurations may be referred to as the address of memory cell 105. In some instances, access lines may be conductive lines coupled to memory cell 105 and can be used to perform access operations on memory cell 105. In some instances, memory device 100 may perform operations in response to commands, which may be issued by a host device coupled to memory device 100 or generated by memory device 100 (e.g., by local memory controller 150).

[0028] The access memory unit 105 can be controlled by one or more decoders, such as row decoder 110 or column decoder 120, and other examples. For instance, row decoder 110 can receive row addresses from local memory controller 150 and activate row line 115 based on the received row addresses. Column decoder 120 can receive column addresses from local memory controller 150 and activate column line 125 based on the received column addresses.

[0029] Sensing component 130 may be operable to detect the state of memory cell 105 (e.g., material state, resistance state, threshold state) and determine the logic state of memory cell 105 based on the detected state. Sensing component 130 may include one or more sensing amplifiers that convert (e.g., amplify) signals generated by accessing memory cell 105 (e.g., signals from column line 125 or other access lines). Sensing component 130 may compare the signal detected from memory cell 105 with a reference 135 (e.g., reference voltage, reference charge, reference current). The detected logic state of memory cell 105 may be provided as an output of sensing component 130 (e.g., provided to input / output component 140) and may be indicated to another component of memory device 100 or to a host device coupled to memory device 100.

[0030] The local memory controller 150 can control access to memory cells 105 through various components (e.g., row decoder 110, column decoder 120, sensing component 130, and other components). In some instances, one or more of the row decoder 110, column decoder 120, and sensing component 130 may co-address with the local memory controller 150. The local memory controller 150 may be operable to receive information (e.g., commands, data) from one or more different controllers (e.g., an external memory controller associated with a host device, another controller associated with memory device 100), translate the information into signaling usable by memory device 100, perform one or more operations on memory cells 105, and transmit data from memory device 100 to a host device based on the performance of one or more operations. The local memory controller 150 may generate row address signals and column address signals to activate access lines, such as target row line 115 and target column line 125. The local memory controller 150 may also generate and control various signals (e.g., voltage, current) used during operation of memory device 100. Generally, the amplitude, shape, or duration of the applied signal discussed herein may vary, and the various operations discussed for operating memory device 100 may differ.

[0031] The local memory controller 150 may be operable to perform one or more access operations on one or more memory cells 105 of the memory device 100. Examples of access operations may include write operations, read operations, refresh operations, precharge operations, or activation operations, etc. In some instances, access operations may be performed by the local memory controller 150 in response to an access command (e.g., from a host device) or otherwise coordinated. The local memory controller 150 may be operable to perform other access operations not listed herein or other operations related to the operation of the memory device 100 that are not directly related to accessing the memory cells 105.

[0032] In some cases, the decoder of memory device 100 may comprise two parts. A first part of the decoder may be fabricated on top of the memory array and may include a pillar decoding section (e.g., column decoder 120) and a word line decoding section (e.g., row decoder 110). The pillar decoding section may include a first array of decoding elements (e.g., transistors, such as vertical transistors or thin-film transistors (TFTs)) coupled to corresponding conductive pillars and digital lines (e.g., column lines 125) extending in a first horizontal direction, while the word line decoding section may include a second array of decoding elements coupled to corresponding word line sections (e.g., row lines 115) and voltage sources extending in the first horizontal direction. The pillar decoding section and the word line decoding section may further include a set of gate lines extending in a second horizontal direction and configured to activate a column of decoding elements. The second part of the decoder may be implemented in a separate semiconductor device, which may include a set of logic circuitry, such as complementary metal-oxide-semiconductor (CMOS), configured to drive signals to a set of contacts. In some cases, the contacts of the second part may be coupled to the contacts of the first part to drive the digital lines, voltage sources, and gate lines (e.g., using hybrid bonding). Due to the array structure of the first section, a single decoding element of the array can be selected and driven by driving a first signal via a first contact to activate a column of decoding elements containing the selected decoding element and by driving a second signal via a second contact to bias a voltage source or digital line coupled to the selected decoding element. Therefore, a smaller number of contacts relative to the number of decoding elements can be used to decode word line portions and conductive posts.

[0033] Memory device 100 may include any number of non-transitory computer-readable media supporting a decoder architecture for a three-dimensional memory device. For example, local memory controller 150, row decoder 110, column decoder 120, sensing component 130, or input / output component 140, or any combination thereof, may include or access one or more non-transitory computer-readable media containing storage instructions (e.g., firmware) for performing the functions attributed to memory device 100 herein. For example, if executed by memory device 100, such instructions may cause memory device 100 to perform one or more associated functions as described herein.

[0034] Figure 2 , 3A Section 3B illustrates an example of a memory array 200 supporting a decoder architecture for a three-dimensional memory device, as disclosed herein. The memory array 200 may be included in the memory device 100, and an example of a three-dimensional arrangement of memory cells 105 accessible by various conductive structures (e.g., access lines) is illustrated. Figure 2 Explain the relationship between memory array 200 and, for example: Figure 3A and 3BThe top cross-sectional view of the cutting plane AA shown in the figure (e.g., section AA). Figure 3A Explain the relationship between memory array 200 and, for example: Figure 2 The side section view of the cutting plane BB shown in the figure (e.g., section BB). Figure 3B Explain the relationship between memory array 200 and, for example: Figure 2 The diagram shows a side cross-sectional view of the cutting plane CC (e.g., section CC). The cross-sectional view may be an example of a cross-sectional view of the memory array 200, where some aspects (e.g., dielectric structures) are omitted for clarity. The elements of the memory array 200 may be described relative to the x, y, and z directions, as shown... Figure 2 , 3A As explained in each of 3B. Although Figure 2 , 3A Some elements included in 3B are labeled with numerical indicators, but other corresponding elements are not labeled, though they are the same or will be understood to be similar, in order to increase the visibility and clarity of the depicted features. Furthermore, although a number of repeating elements are shown in the illustrative example of memory array 200, the techniques described herein are applicable to any number of such elements, or the ratio of one repeating element to another.

[0035] In an example of memory array 200, memory cells 105 and word lines 205 can be configured according to hierarchy 230 (e.g., such as...). Figure 3A and 3B The stacks, layers, planes, and hierarchies described herein are distributed along the z-direction. In some instances, the z-direction may be orthogonal to the substrate (not shown) of the memory array 200, which may lie below the illustrated structure along the z-direction. Although the illustrative example of the memory array 200 includes four layers 230, the memory array 200 according to the examples disclosed herein may include any number of one or more layers 230 along the z-direction (e.g., 64 layers, 128 layers).

[0036] Each word line 205 may be an example of a portion of an access line formed of one or more conductive materials (e.g., one or more metal portions, one or more metal alloy portions). As illustrated, the word line 205 may be formed in a comb-like structure, including portions (e.g., protrusions, teeth) extending along the y-direction through gaps (e.g., alternating gaps) between the pillars 220. For example, as illustrated, the memory array 200 may include two word lines 205 per level 230 (e.g., odd-number line 205-a-n1 and even-number line 205-a-n2 according to a given level n), wherein such word lines 205 of the same level 230 may be described as interleaved (e.g., wherein portions of the odd-number line 205-a-n1 protrude along the y-direction between portions of the even-number line 205-a-n2, and vice versa). In some instances, (e.g., level 230) odd-number lines 205 may be associated with a first memory cell 105 on a first side of a given pillar 220 (e.g., along the x-direction), and (e.g., level 230) even-number lines may be associated with a second memory cell 105 on a second side of a given pillar 220 (e.g., along the x-direction, opposite the first memory cell 105). Therefore, in some instances, a memory cell 105 of a given level 230 may be addressed (e.g., selected, activated) based on either even-number lines 205 or odd-number lines 205.

[0037] Each pillar 220 may be an example of a portion (e.g., a conductive pillar portion) of an access line formed from one or more conductive materials (e.g., one or more metal portions, one or more metal alloy portions). As illustrated, the pillars 220 may be arranged in a two-dimensional array (e.g., in the xy plane) having a first number of pillars 220 along a first direction (e.g., eight pillars along the x-direction, i.e., eight rows of pillars) and a second number of pillars 220 along a second direction (e.g., five pillars along the y-direction, i.e., five columns of pillars). Although the illustrative example of memory array 200 includes a two-dimensional arrangement of eight pillars 220 along the x-direction and five pillars 220 along the y-direction, memory array 200 according to the examples disclosed herein may include any number of pillars 220 along the x-direction and any number of pillars 220 along the y-direction. Furthermore, as illustrated, each pillar 220 may be coupled to a corresponding set of memory cells 105 (e.g., one or more memory cells 105 of each level 230 along the z-direction). The column 220 may have a cross-sectional area in the xy plane extending along the z-direction. Although illustrated by a circular cross-sectional area in the xy plane, the column 220 may be formed in different shapes, such as having an elliptical, square, rectangular, polygonal, or other cross-sectional area in the xy plane.

[0038] Each memory cell 105 may contain a chalcogenide material. In some instances, memory cells 105 may be instances of threshold-processing memory cells. Each memory cell 105 may be accessed (e.g., addressed, selected) based on the intersection between word line 205 (e.g., a hierarchy selection, which may include even or odd selections within hierarchy 230) and cylinder 220. For example, as illustrated, the selected memory cell 105-a of hierarchy 230-a-3 may be accessed based on the intersection between cylinder 220-a-43 and word line 205-a-32.

[0039] An access bias (e.g., access voltage V) can be applied across memory cell 105. 存取 The memory cell 105 can be accessed (e.g., written to or read from the memory cell) using a first voltage (which can be positive or negative). In some instances, this can be achieved by using a first voltage (e.g., V). 存取 / 2) Bias the selected word line 205 and pass it through a second voltage (e.g., -V). 存取 / 2) A bias voltage is applied to the selected column 220 to provide an access bias, the second voltage having the opposite sign to the first voltage. For the selected memory cell 105-a, a corresponding access bias voltage (e.g., the first voltage) may be applied to word line 205-a-32, while other unselected word lines 205 may be grounded (e.g., biased to 0V). In some instances, the word line bias may be provided by word line drivers (not shown) coupled to one or more of the word lines 205.

[0040] To apply a corresponding access bias (e.g., a second voltage) to post 220, post 220 may be configured to be selectively coupled to sensing line 215 (e.g., a digital line, column line, or access line extending along the y-direction) via a corresponding transistor 225 coupled between post 220 and sensing line 215 (e.g., physically or electrically). In some instances, transistor 225 may be a vertical transistor (e.g., a transistor with a channel along the z-direction, a transistor with a semiconductor junction along the z-direction), which may be formed over the substrate of memory array 200 using various techniques (e.g., thin-film technology). In some instances, the selected post 220, the selected sensing line 215, or a combination thereof may be a reference. Figure 1 The described instance of the selected column line 125 (e.g., a bit line).

[0041] Transistor 225 (e.g., the channel portion of transistor 225) may be activated by gate line 210 (e.g., an activation line, select line, row line, or access line extending along the x-direction), said gate line being coupled to the gate of a corresponding group of transistors 225 (e.g., a group along the x-direction). In other words, each of the pillars 220 may have a first end (e.g., a bottom end facing the negative z-direction) configured for coupling with an access line (e.g., a sensing line 215). In some instances, gate line 210, transistor 225, or both may be considered components of row decoder 110 (e.g., as pillar decoder components). In some instances, the selection (e.g., bias) of pillar 220 or sensing line 215, or various combinations thereof, may be supported by column decoder 120 or sensing component 130, or both.

[0042] To adjust the corresponding access bias (e.g., -V) 存取 / 2) Applied to post 220-a-43, sense line 215-a-4 can be biased with an access bias voltage, and gate line 210-a-3 can be grounded (e.g., biased to 0V) or additionally biased with an activation voltage. In an example where transistor 225 is an n-type transistor, gate line 210-a-3 is biased with a voltage relatively higher than the voltage at which sense line 215-a-4 can activate transistor 225-a (e.g., to operate transistor 225-a in a conductive state), thereby coupling post 220-a-43 to sense line 215-a-4 and biasing post 220-a-43 with an associated access bias voltage. However, transistor 225 may contain different channel types or may operate according to different bias schemes to support various access operations.

[0043] In some instances, unselected pillars 220 in memory array 200 may be electrically floated when transistor 225-a is activated, or may be coupled to another voltage source (e.g., ground, via a high-resistance path, via a leakage path) to prevent voltage drift of pillar 220. For example, a ground voltage applied to gate line 210-a-3 may not activate other transistors coupled to gate line 210-a-3 because the ground voltage of gate line 210-a-3 may not be greater than the voltage of other sensing lines 215 (e.g., which may be biased with ground voltage or float). Furthermore, including... Figure 3A Other unselected gate lines 210 shown in the diagram 210-a-5 can be equal to or similar to an access bias (e.g., -V). 存取 The voltage is biased by a voltage (or some other negative bias or a bias voltage relatively close to the access bias voltage) such that transistor 225 along the unselected gate line 210 is not activated. Therefore, transistor 225-b coupled to gate line 210-a-5 can be deactivated (e.g., operated in a non-conductive state), thereby isolating the voltage of sensing line 215-a-4 from pillar 220-a-45 and the other pillars 220.

[0044] During a write operation, a write bias can be applied across memory cell 105 (e.g., where V0 = V0). 存取 =V 写入 A write bias (which can be a positive or negative voltage) is applied to the memory cell 105. In some instances, the polarity of the write bias can affect (e.g., determine, set, program) the behavior or characteristics of the material of the memory cell 105, such as the threshold voltage of the material. For example, applying a write bias with a first polarity can set the material of the memory cell 105 to have a first threshold voltage that can be associated with storing logic 0. Furthermore, applying a write bias with a second polarity (e.g., opposite to the first polarity) can set the material of the memory cell to have a second threshold voltage that can be associated with storing logic 1. For different logic states stored by the material of the memory cell 105, the difference between the threshold voltages of the material of the memory cell 105 (e.g., the difference between the threshold voltages when the material is storing logic state '0' versus when the material is storing logic state '1') can correspond to the read window of the memory cell 105.

[0045] During a read operation, a read bias can be applied across memory cell 105 (e.g., where V0 = V0). 存取 =V 读取 The memory cell 105 is read using a voltage (which can be positive or negative). In some instances, the logic state of the memory cell 105 can be evaluated based on whether the memory cell 105 is thresholded in the presence of an applied read bias. For example, this read bias may cause the memory cell 105 storing a first logic state (e.g., logic 0) to undergo thresholding (e.g., allowing current flow, allowing current above a threshold current), and may not cause the memory cell 105 storing a second logic state (e.g., logic 1) to undergo thresholding (e.g., disallowing current flow, allowing current below a threshold current).

[0046] In some cases, the decoder of the memory device including the memory array 200 may comprise two parts. The first part of the decoder may be fabricated as a portion of the same substrate as the memory array 200 (e.g., below or above the memory array) and may include a pillar decoding portion selectively biasing conductive pillars 220 and a word line decoding portion selectively biasing word lines 205. The pillar decoding portion may include a first array of decoding elements (e.g., transistors, such as vertical transistors or TFTs) coupling the respective conductive pillars 220 to digital lines (e.g., sensing lines 215) extending in a first horizontal direction, while the word line decoding portion may include a second array of decoding elements coupling the respective word lines 205 to a voltage source extending in the first horizontal direction. The pillar decoding portion and the word line decoding portion may further include a set of gate lines 210 extending in a second horizontal direction and configured to activate a column of decoding elements. The second part of the decoder may be implemented in a separate semiconductor device (e.g., a separate substrate) that may include a set of logic circuitry, such as CMOS circuitry, configured to drive signals to a set of contacts. In some cases, the contacts of the second portion can be coupled to the contacts of the first portion to drive digital lines, voltage sources, and gate lines 210 (e.g., using hybrid coupling). Due to the array structure of the first portion, a single decoding element of the array can be activated by driving a first signal via the first contact. The decoding element can bias selected word line portions or digital lines via a voltage source or other driver coupled to the decoding element via the second contact. Therefore, a smaller number of contacts relative to the number of decoding elements can be used to decode word line portions and conductive posts.

[0047] Figure 4 This describes an example of a system 400 that supports a decoder architecture for a three-dimensional memory device, as disclosed herein. System 400 may include a memory array 410 and a decoder 415 configured to bias the memory array 410 as part of an access operation to memory cells 405. In some cases, the memory array 410 and decoder 415 may be as described in the references... Figures 1 to 3B An example of the corresponding device described.

[0048] For example, decoder 415 may include a row decoder (e.g., row decoder 110) configured to decode word line board 475 and a column decoder (e.g., column decoder 120) configured to bias conductive posts 420 (e.g., conductive posts 220). Conductive posts 420 may extend vertically (e.g., in the z-direction) through memory array 410 and may be coupled to one or more digital lines 440 using transistors 445. Word line board 475 may be as referenced... Figures 2 to 3BThe described word line 205 is an example and can be arranged in multiple vertically extending layers (e.g., multiple vertically stacked layers or tiers), each layer containing a pair of interlaced comb structures. Each comb structure may contain a corresponding set of word line components extending horizontally (e.g., in the y-direction) through the memory array 410 and can be configured to apply voltage to the memory cell 405. For example, the decoder 415 may include one or more conductive lines 450 selectively coupled to the word line board 475 using one or more transistors 445.

[0049] Decoder 415 may be implemented in two parts. For example, decoder 415 may include a first part 425 and a second part 430. The first part 425 may include a set of digital lines 440 extending horizontally in the x-direction (e.g., generally orthogonal to the word line component) and a set of conductive lines 450 extending horizontally in the x-direction.

[0050] The first portion 425 may include a first set of decoding elements 423, each decoding element 477 in the first set coupled to a corresponding conductive post 420 and a digital line 440. The first portion 425 may also include a second set of decoding elements 427, each decoding element 477 in the second set coupled to a corresponding word line board 475 (e.g., a word line comb structure) and a conductive line 450. The first set of decoding elements 423 and the second set of decoding elements 427 may be arranged in a grid pattern, comprising one or more rows of decoding elements 477 extending in the x-direction (e.g., along the word line component direction) and one or more columns of decoding elements 477 extending in the y-direction (e.g., along the digital line direction). Additionally, the first portion 425 may include one or more gate lines 455 extending in the y-direction and each configured to activate a row of decoding elements 477.

[0051] In some cases, the decoding element 477 may be an example of a TFT and may be configured as a vertical transistor (e.g., it may have a vertical channel orientation). For example, the decoding element 477 may include a transistor 445 having a first terminal 460-a (e.g., a source terminal) and a second terminal 460-b (e.g., a drain terminal), and a channel region 463. Additionally, a gate line 455 may be arranged adjacent to the channel region of the transistor 445 and may be configured to activate or deactivate the transistor 445 using a voltage applied to the gate line 455. Thus, the first portion 425 may be fabricated as a portion of the memory array 410. That is, the memory array 410 and the first portion 425 may be included in the same first semiconductor device 435. For example, the first portion 425 may be formed over the memory array 410 by depositing one or more layers of material and patterning the first set of transistors 445 and the second set of transistors 445 to couple with the conductive pillars 420 and the word line board 475, respectively.

[0052] In some cases, the digital line 440 and the conductive line 450 may be patterned over a first group of transistors 445 and a second group of transistors 445, respectively. For example, the digital line 440 may extend over a column of transistors 445 in the first group and may be selectively coupled to a corresponding column of conductive posts 420 using the column of transistors 445. Additionally, a single conductive line 450 may extend over a column of transistors 445 in the second group and may be selectively coupled to a group of word lines 475 using the column of transistors 445. In some cases, the conductive line 450 may be selectively coupled to multiple levels of word lines 475 (e.g., a first transistor 445 may couple a first word line 475 of a first level to the conductive line 450, and a second transistor 445 may couple a second word line 475 of a second level to the conductive line 450).

[0053] In some instances, a set of digital lines 440, a set of conductive lines 450, and a set of gate lines 455 may each be coupled to a corresponding contact in a first set of contacts exposed on the surface of the first semiconductor device, each contact being configured to drive the corresponding digital line 440, conductive line 450, or gate line 455 using circuitry included in a second portion 430 of the decoder 415. For example, the first set of contacts may engage or couple to a second set of contacts 465 of the second portion 430, which may include circuitry configured to bias the second set of contacts 465.

[0054] In some cases, the second portion 430 may be an example of a second semiconductor device, which includes one or more logic circuits, such as CMOS circuits, formed within a semiconductor substrate 470. The semiconductor substrate may further include a set of transistors having terminals coupled to a second set of contacts.

[0055] In some cases, the second semiconductor device may be manufactured separately from the first semiconductor device 435. Therefore, the manufacturing system 400 may include bonding or coupling the first semiconductor device 435 and the second semiconductor device (e.g., the second portion 430 of the decoder 415). For example, each contact 465 in one set of contacts may be bonded to a corresponding contact in the first set of contacts. That is, each contact 465 of the second portion 430 may be coupled to a digital line 440, a conductive line 450, or a gate line 455 via a corresponding contact in the first set of contacts. In some cases, this technique of bonding the first semiconductor device 435 and the second semiconductor device may be referred to as hybrid bonding.

[0056] Figure 5This describes an example of a memory system 500 that supports a decoder architecture for a three-dimensional memory device, as disclosed herein. The memory system 500 may include a first semiconductor device 535 and a second semiconductor device 530. Semiconductor devices 530 and 535 may each be configured to operate according to instructions from a memory controller 550, which may be as described in reference... Figure 1 An example of the described local memory controller 150. Alternatively, the memory controller 550 may be located on the second semiconductor device 530.

[0057] The second semiconductor device 530 may be a decoder (e.g., as referenced) that includes a semiconductor substrate (e.g., a CMOS substrate). Figure 4 An example of a portion of the described decoder 415 is described, the decoder having one or more logic circuits configured to independently drive signals to a set of contacts. The decoder may include a word line decoder biasing word lines of memory array 505 and a pillar decoder biasing conductive pillars of memory array 505. Furthermore, the word line decoder and the pillar decoder may each include a first portion and a second portion respectively located in a second semiconductor device 530 and a first semiconductor device 535. In some cases, the first set of contacts of the second semiconductor device 530 may correspond to the output of the first portion of the word line decoder 520, and the second set of contacts of the second semiconductor device 530 may correspond to the output of the first portion of the pillar decoder 510. The first portion of the word line decoder 520 and the first portion of the pillar decoder 510 may respectively drive signals to the second portion of the word line decoder 525 and the second portion of the pillar decoder 510 located in the first semiconductor device 535.

[0058] The first semiconductor device 535 may include a memory array 505, which may be as described in reference. Figure 2 An example of the described three-dimensional memory array 200. That is, the memory array 505 may comprise a vertical stack of word line boards having word line components extending into the memory regions of the memory array 505 (e.g., as referenced). Figure 3A and 3B The described character line 205, as referenced Figure 4 The letterplate 475 and letterplate components are described. The stacked hierarchical letterplates may contain multiple interlaced comb-like structures (e.g., such as...). Figure 2 (as depicted in the text), which may correspond to the even and odd number lines of the said level. In some cases, a comb structure in a set of interleaved comb structures may include one or more isolation portions that can reduce the capacitance between a portion of the comb structure and other components of the memory array 505 (e.g., parasitic capacitance between even and odd number lines between individual word line levels, and other instances).

[0059] Additionally, the first semiconductor device 535 may include a set of conductive pillars extending vertically through the word line board stack and into the memory region (e.g., as referenced). Figures 2 to 4 The conductive pillars 220 and 420 are described. Each memory cell of the memory array 505 can be associated with a unique combination of word line portion and conductive pillar. Therefore, in order to access the memory cell of the memory array 505, the memory controller can be configured to independently bias the word line portion and conductive pillar corresponding to the memory cell.

[0060] For example, to bias a conductive pillar, the memory controller 550 can transmit instructions to a first portion of the pillar decoder 510 to drive a first signal and a second signal to a first contact coupled to a gate line and a second contact coupled to a digital line in a second portion of the pillar decoder 515, respectively. Thus, the gate line can activate decoding elements, such as vertical transistors or TFTs, arranged in the second portion of the pillar decoder 515 to couple the conductive pillar to the digital line, thereby biasing the conductive pillar using the second signal.

[0061] Additionally, to bias the word line portion, the memory controller 550 can transmit instructions to a first portion of the word line decoder 520 to drive a first signal and a second signal to a first contact coupled to a gate line and a second contact coupled to a conductive line of a second portion of the word line decoder 525, respectively. Thus, the gate line can activate decoding elements, such as vertical transistors or TFTs, arranged in the second portion of the word line decoder 525 to couple the word line portion to a voltage source, thereby biasing the word line portion using the second signal. In some cases, the instructions transmitted to the first portion of the word line decoder 520 may include an indication of the level of the word line portion and an indication of the word line portion itself. That is, to address the word line portion, the memory controller 550 may include an address of the level of the word line portion and an address of the word line portion within that level.

[0062] In some cases, each decoding element of the second portion of word line decoder 525 may include a second vertical transistor selectively coupled to a second voltage source (e.g., a ground voltage source). In some cases, the first portion of word line decoder 520 may include an additional set of contacts coupled to a counterpart in the second voltage source to drive a signal to the second voltage source. Thus, the first transistor of the decoding element may bias the word line portion to a voltage of the voltage source (e.g., a power supply voltage), and the second transistor of the decoding element may bias the word line portion to a voltage of the second voltage source (e.g., ground). In some cases, the first portion of word line decoder 520 and the second portion of word line decoder 525 may be configured as a complete decoder for a word line board (e.g., a given word line board may be activated based on a word line board index).

[0063] Figure 6This describes an example of a system 600 that supports a decoder architecture for a three-dimensional memory device, as disclosed herein. System 600 may include a top cross-sectional view of a first semiconductor device 635 and a second semiconductor device 630. The first semiconductor device 635 may include, as referenced... Figure 4 and 5 The first semiconductor device 435 or the first semiconductor device 535 described herein, or examples thereof. The second semiconductor device 630 may include, as referenced Figure 4 and 5 The second part 430 or the second semiconductor device 530 described herein, or an example thereof.

[0064] For example, the first semiconductor device 635 may include a second portion of a decoder configured to access memory cells of a memory array of the first semiconductor device 635. In some cases, the second portion of the decoder may include a second pillar decoder portion 615 (e.g., as referenced). Figure 5 The second portion of the described pillar decoder 515 may include a set of digital lines 640 extending in the x-direction and a first set of transistors 645 arranged in one or more rows extending in the x-direction and one or more columns extending in the y-direction, the first set of transistors 645 being configured to selectively couple corresponding conductive pillars of the memory array to the digital lines 640 in the set of digital lines 640. Additionally, the second pillar decoder portion 615 may include a set of gate lines 655 extending in the y-direction and configured to activate a column of transistors 645.

[0065] The first semiconductor device 635 may also include a second word line decoder section 625-a (e.g., as referenced). Figure 5 The second word line decoder portion 625-a, as described in the second part of the word line decoder 525, may include a set of conductive lines 650 extending in the x-direction and coupled to a voltage source, and a second set of transistors 645 arranged in one or more rows extending in the x-direction and one or more columns extending in the y-direction. The second set of transistors 645 is configured to selectively couple corresponding portions of the word line board of the memory array to the conductive lines 650 in the set of conductive lines 650. Additionally, the second word line decoder portion 625-a may include a set of gate lines 655 extending in the y-direction and configured to activate a column of transistors 645. In some cases, the first semiconductor device 635 may include an additional word line decoder portion 625-b. In such cases, the word line decoder portion 625-a may correspond to a first word line board portion (e.g., even-number lines) at each level of the memory array, while the additional word line decoder portion 625-b may correspond to a second word line board portion (e.g., odd-number lines) at each level of the memory array.

[0066] To drive signals to the word line board portion and conductive posts, the first semiconductor device may include a first set of contacts 670, each contact being connected to a second set of contacts 665 of the second semiconductor device 630 (e.g., as referenced). Figure 4 The corresponding contact in the described contact 465) is coupled. The second semiconductor device 630 may include a first portion of a decoder configured to access memory cells of the memory array of the first semiconductor device 635. For example, the second semiconductor device 630 may include a first pillar decoder portion 610 (e.g., as referenced). Figure 5 The first part of the described column decoder 510 and the first word line decoder part 620-a (e.g., as referenced) Figure 5 The first part of the described word line decoder 520. In some cases, the second semiconductor device 630 may include an additional word line decoder part 620-b. Thus, the first word line decoder part 620-a may correspond to a first word line board portion (e.g., even number lines) at each level of the memory array, while the additional word line decoder part 620-b may correspond to a second word line board portion (e.g., odd number lines) at each level of the memory array.

[0067] In some cases, the first set of contacts 670 may be coupled to the second set of contacts 665. That is, each contact 670 in the first set of contacts may be coupled to a corresponding contact in the second set of contacts 665. For example, each contact 665 of the pillar decoder section 610 may be coupled to the digital line 640 or the gate line 655 through the corresponding contact 670 of the second pillar decoder section 615, while each contact 665 of the word line decoder section 620-a may be coupled to the conductive line 650 or the gate line 655 through the corresponding contact 670 of the word line decoder section 625-a. In some cases, this technique for coupling the first semiconductor device 435 and the second semiconductor device may be referred to as hybrid coupling.

[0068] In some cases, the second set of contacts 665 may be arranged in one or more rows or columns. For example, the column decoder section 610 may include a row of contacts 665 that engage with a corresponding row of contacts 670 of the second column decoder section 615. Therefore, the row of contacts 665 may be configured to drive the gate line 655 of the second column decoder section 615. Similarly, the column decoder section 610 may include a column of contacts 665 that engage with a corresponding column of contacts 670 of the second column decoder section 615. Therefore, the column of contacts 665 may be configured to drive the digital line 640 of the second column decoder section 615. However, those skilled in the art will understand that other configurations of the second set of contacts 665 are possible.

[0069] Due to the array structure of transistors 645, in order to bias a conductive pillar or word line portion, a first signal can be driven to a gate line coupled to a transistor 645 associated with the same conductive pillar or word line portion, and a second signal can be driven to a digital line 640 or a voltage source coupled to transistors 645. Therefore, the gate line can activate transistors to couple conductive pillars to digital lines or word line portions to voltage sources, and thus drive the second signal to the conductive pillars or word line portions. Therefore, the number of contacts for each semiconductor can be less than the number of transistors 645. For example, if the second pillar decoding portion 615 contains 16 transistors 645, such as... Figure 6 As described, the first column decoder section 615 may contain eight contacts 670 (e.g., four contacts 670 drive each row and four contacts drive each column). More generally, if the second column decoder section 615 or the second word line decoder section 625a contains N rows of transistors 645 and M columns of transistors 645 (e.g., a total of N*M transistors 645), then the first column decoder section 615 or the first word line decoder section 625a may contain N+M contacts 670.

[0070] Figure 7 The flowchart illustrates a method 700 supporting a decoder architecture for a three-dimensional memory device according to an example disclosed herein. Operation of method 700 may be implemented by a process flow manager or its components as described herein. For example, operation of method 700 may be implemented by, as referenced... Figures 1 to 6 The described process flow manager executes the function. In some instances, the process flow manager can execute a set of instructions to control the functional elements of the device to perform the described function. Alternatively, the process flow manager may use dedicated hardware to perform aspects of the described function.

[0071] At 705, the method may include forming a layered assembly comprising a plurality of word line boards arranged in multiple layers of a memory array, each word line board including one or more word line components extending in a first horizontal direction, a plurality of conductive posts extending through the plurality of word line boards, and a plurality of digital lines coupled to the plurality of word line boards and extending in a second horizontal direction orthogonal to the first horizontal direction. Operation of 705 may be performed according to examples disclosed herein. In some examples, aspects of operation of 705 may be performed by an array forming component.

[0072] At 710, the method may include forming a first portion of a decoder in a first substrate above a layered assembly. The first portion of the decoder includes a first plurality of decoding elements configured to couple corresponding conductive pillars to corresponding digital lines, and a second plurality of decoding elements configured to couple corresponding word line boards to corresponding voltage sources among a plurality of voltage sources and a plurality of first contacts, each first contact being coupled to a corresponding subset of the first plurality of decoding elements or to a corresponding subset of the second plurality of decoding elements. Operation of 710 may be performed according to examples disclosed herein. In some examples, aspects of operation of 710 may be performed by the first decoder forming assembly.

[0073] At 715, the method may include forming a second portion of a decoder in a second substrate, the second portion of the decoder including a plurality of second contacts and a plurality of transistors, at least a subset of the plurality of transistors having terminals coupled to the plurality of second contacts. Operation of 715 may be performed according to examples disclosed herein. In some examples, aspects of operation of 715 may be performed by a second decoder forming component.

[0074] At 720, the method may include engaging each of a plurality of first contacts with a corresponding second contact of a plurality of second contacts, wherein said engagement positions a first portion of the decoder between a layered assembly and a second portion of the decoder. Operation of 720 may be performed according to examples disclosed herein. In some instances, aspects of operation of 720 may be performed by a decoder engagement assembly.

[0075] In some instances, the device as described herein may perform one or more methods, such as method 700. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) or any combination thereof for performing aspects of this disclosure:

[0076] Aspect 1: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for performing the following: forming a hierarchical assembly comprising a plurality of word line boards arranged in multiple levels of a memory array, each word line board comprising one or more word line components extending in a first horizontal direction, a plurality of conductive posts extending through the plurality of word line boards, and a plurality of digital lines coupled to the plurality of word line boards and extending in a second horizontal direction orthogonal to the first horizontal direction; forming a first portion of a decoder in a first substrate above the hierarchical assembly, the first portion of the decoder comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for performing the following: forming a hierarchical assembly comprising a plurality of word line components arranged in a first horizontal direction, each word line board comprising one or more word line components extending in a first horizontal direction, a plurality of conductive posts extending through the plurality of word line boards, and a plurality of digital lines coupled to the plurality of word line boards and extending in a second horizontal direction orthogonal to the first horizontal direction; forming a first portion of a decoder in a first substrate above the hierarchical assembly, the first portion of the decoder comprising a plurality of digital lines configured to couple corresponding conductive posts to phase... A first plurality of decoding elements for a digital line, and a second plurality of decoding elements configured to couple a corresponding word line board to a corresponding voltage source of a plurality of voltage sources and a plurality of first contacts, each first contact being coupled to a corresponding subset of the first plurality of decoding elements or to a corresponding subset of the second plurality of decoding elements; a second portion of a decoder is formed in a second substrate, the second portion of the decoder including a plurality of second contacts and a plurality of transistors, at least a subset of the plurality of transistors having terminals coupled to the plurality of second contacts; and each of the plurality of first contacts is joined to a corresponding second contact of the plurality of second contacts, wherein the joining positions the first portion of the decoder between the layered assembly and the second portion of the decoder.

[0077] Aspect 2: The method, apparatus, or non-transitory computer-readable medium according to Aspect 1, wherein the first portion forming the decoder includes operations, features, circuitry, logic, components, or instructions, or any combination thereof, for performing the following operations: forming a corresponding first vertical transistor in each of a first plurality of decoding elements, the corresponding first vertical transistor including a first terminal coupled to a corresponding conductive post and a second terminal coupled to a corresponding digital line; and forming a corresponding second vertical transistor in each of a second plurality of decoding elements, the corresponding second vertical transistor including a first terminal coupled to a corresponding word line portion and a second terminal coupled to a corresponding voltage source among a plurality of voltage sources.

[0078] Aspect 3: The method, apparatus, or non-transitory computer-readable medium according to aspect 2, wherein the first portion forming the decoder further includes operations, features, circuitry, logic, components, or instructions, or any combination thereof, for performing: forming a first plurality of gate lines, each of the first plurality of gate lines being coupled to a corresponding subset of a first vertical transistor and to a corresponding first contact of a plurality of first contacts; and forming a second plurality of gate lines, each of the second plurality of gate lines being coupled to a corresponding subset of a second vertical transistor and to a corresponding first contact of a plurality of first contacts.

[0079] Aspect 4: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 3, wherein a first plurality of decoding elements are arranged in a first grid structure, the first grid structure comprising one or more rows extending in a first horizontal direction and one or more columns extending in a second horizontal direction orthogonal to the first horizontal direction; and a second plurality of decoding elements are arranged in a second grid structure, the second grid structure comprising one or more rows extending in the first horizontal direction and one or more columns extending in the second horizontal direction.

[0080] It should be noted that the methods described herein describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods may be combined.

[0081] Describe a device. An overview of aspects of the device as described herein is provided below:

[0082] Aspect 5: An apparatus comprising: a first semiconductor device including a plurality of word lines disposed in a hierarchy and a plurality of conductive pillars extending through the plurality of word lines, the first semiconductor device including: a first plurality of vertical transistors, each of the first plurality of vertical transistors selectively coupling a corresponding conductive pillar to a corresponding digital line of a plurality of digital lines; a second plurality of vertical transistors, each of the second plurality of vertical transistors selectively coupling a corresponding word line to a corresponding voltage source of a plurality of voltage sources; and a plurality of first contacts, a first subset of the plurality of first contacts coupled to the first plurality of vertical transistors, and a second subset of the plurality of first contacts coupled to the second plurality of vertical transistors; a second semiconductor device including one or more logic circuits formed in a semiconductor substrate of the second semiconductor device, the second semiconductor device including: a plurality of second contacts; and a third plurality of transistors, at least a subset of the third plurality of transistors having terminals coupled to the plurality of second contacts, the plurality of first contacts of the first semiconductor device being engaged with the plurality of second contacts of the second semiconductor device.

[0083] Aspect 6: The apparatus according to aspect 5, wherein the first semiconductor device further comprises: a first plurality of gate lines, each of the first plurality of gate lines being coupled to a corresponding subset of a first plurality of vertical transistors and to a corresponding contact of a plurality of first contacts; and a second plurality of gate lines, each of the second plurality of gate lines being coupled to a corresponding subset of a second plurality of vertical transistors and to a corresponding contact of a plurality of first contacts.

[0084] Aspect 7: The device according to aspect 6, wherein each of the first plurality of vertical transistors includes a first terminal coupled to a corresponding conductive pillar of the plurality of conductive pillars, a second terminal coupled to a corresponding digital line of the plurality of digital lines, and a gate coupled to a corresponding gate line of the first plurality of gate lines.

[0085] Aspect 8: The apparatus according to any one of aspects 6 to 7, wherein each of the second plurality of vertical transistors includes a first terminal coupled to a corresponding portion of a word line board in the plurality of word line boards, a second terminal coupled to a corresponding voltage source in the plurality of voltage sources, and a gate coupled to a corresponding gate line in the second plurality of gate lines.

[0086] Aspect 9: The device according to any one of aspects 6 to 8, wherein the first semiconductor device further includes a third plurality of vertical transistors, each of the third plurality of vertical transistors selectively coupling a corresponding portion of a word line board to a corresponding ground source.

[0087] Aspect 10: The device according to any one of aspects 6 to 9, wherein each of the plurality of digital lines is coupled to a corresponding contact of the plurality of first contacts, and each of the plurality of voltage sources is coupled to a corresponding contact of the plurality of first contacts.

[0088] Aspect 11: The device according to any one of aspects 6 to 10, wherein a first plurality of vertical transistors are arranged in a first grid structure, the first grid structure comprising one or more rows extending in a first horizontal direction and one or more columns extending in a second horizontal direction orthogonal to the first horizontal direction; and a second plurality of vertical transistors are arranged in a second grid structure, the second grid structure comprising one or more rows extending in the first horizontal direction and one or more columns extending in the second horizontal direction.

[0089] Aspect 12: The device according to aspect 11, wherein a plurality of first contacts include a first row of contacts extending in a first horizontal direction, each of the first row of contacts being coupled to a corresponding gate line of a plurality of first gate lines and a corresponding second contact of a plurality of second contacts, the plurality of first contacts further including a first column of contacts extending in a second horizontal direction, each of the first column of contacts being coupled to a corresponding digital line of a plurality of digital lines and a corresponding second contact of a plurality of second contacts.

[0090] Aspect 13: The device according to aspect 12, wherein the plurality of first contacts further includes a second row of contacts extending in a first horizontal direction, each of the second row of first contacts being coupled to a corresponding gate line of a second plurality of gate lines and a corresponding second contact of a plurality of second contacts, the plurality of first contacts further including a second column of contacts extending in a second horizontal direction, each of the second column of first contacts being coupled to a corresponding voltage source of a plurality of voltage sources and a corresponding second contact of a plurality of second contacts.

[0091] Aspect 14: The device according to any one of aspects 5 to 13, wherein the number of the plurality of first contacts is less than the sum of the number of the first plurality of vertical transistors and the number of the second plurality of vertical transistors.

[0092] Aspect 15: The apparatus according to any one of aspects 5 to 14, wherein each of the first plurality of vertical transistors and each of the second plurality of vertical transistors comprises a corresponding thin-film transistor (TFT).

[0093] Describe a device. An overview of aspects of the device as described herein is provided below:

[0094] Aspect 16: An apparatus comprising: a plurality of word lines of a memory array arranged in a plurality of layers, each word line including one or more word line components extending in a first horizontal direction; a plurality of conductive pillars extending through the plurality of word lines, wherein at each word line of the plurality of layers, one or more memory cells of the memory array are coupled to a corresponding conductive pillar and a corresponding component of the word line; a plurality of digital lines extending in a second horizontal direction orthogonal to the first horizontal direction; and a decoder offset along a vertical direction from the plurality of layers and configured to bias the plurality of conductive pillars and the plurality of word lines, the decoder comprising: a first portion including one or more logic circuits at least partially formed within a semiconductor substrate and associated with operating the memory array; and a second portion positioned along a vertical direction between the first portion of the decoder and the memory array, the second portion of the decoder including a first plurality of decoding elements configured to couple a corresponding conductive pillar to a corresponding digital line and a second plurality of decoding elements configured to couple a word line to a corresponding voltage source among a plurality of voltage sources.

[0095] Aspect 17: The apparatus according to aspect 16, wherein the decoder further comprises: a first plurality of gate lines, each of the first plurality of gate lines being coupled to a corresponding subset of a first plurality of contacts of a first portion of the decoder and a second portion of the decoder, and coupled to one or more logic circuits; and a second plurality of gate lines, each of the second plurality of gate lines being coupled to a corresponding subset of a second plurality of contacts of a second portion of the decoder and a second portion of the decoder, and coupled to one or more logic circuits.

[0096] Aspect 18: The device according to aspect 17, wherein each of the first plurality of decoding elements includes a corresponding vertical transistor having a first terminal coupled to a corresponding conductive post of a plurality of conductive posts, a second terminal coupled to a corresponding digital line of a plurality of digital lines, and a gate coupled to a corresponding gate line of a first plurality of gate lines.

[0097] Aspect 19: The apparatus according to any one of aspects 17 to 18, wherein each of the second plurality of decoding elements includes a corresponding vertical transistor having a first terminal coupled to a corresponding portion of a word line board in the plurality of word line boards, a second terminal coupled to a corresponding voltage source in the plurality of voltage sources, and a gate coupled to a corresponding gate line in the second plurality of gate lines.

[0098] Aspect 20: The apparatus according to any one of aspects 17 to 19, wherein each of the second plurality of decoding elements comprises a corresponding first vertical transistor and a corresponding second vertical transistor, the corresponding first vertical transistor having a first terminal coupled to a corresponding portion of a word line board in the plurality of word line boards, a second terminal coupled to a corresponding voltage source in the plurality of voltage sources, and a gate coupled to a corresponding gate line in the second plurality of gate lines, and the corresponding second vertical transistor having a first terminal coupled to a corresponding portion of a word line board in the plurality of word line boards, a second terminal coupled to a corresponding ground source, and a gate coupled to a corresponding gate line in the second plurality of gate lines.

[0099] Aspect 21: The device according to any one of aspects 17 to 20, wherein each of the plurality of digital lines is coupled to a corresponding contact of a first plurality of contacts, and each of the plurality of voltage sources is coupled to a corresponding contact of a second plurality of contacts.

[0100] Aspect 22: The apparatus according to any one of aspects 17 to 21, wherein: a first plurality of decoding elements are arranged in a first grid structure, the first grid structure comprising one or more rows extending in a first horizontal direction and one or more columns extending in a second horizontal direction; and a second plurality of decoding elements are arranged in a second grid structure, the second grid structure comprising one or more rows extending in the first horizontal direction and one or more columns extending in the second horizontal direction.

[0101] Aspect 23: The device according to aspect 22, wherein: a first plurality of contacts comprises a row of contacts extending in a first horizontal direction, each of the row of contacts being coupled to a corresponding gate line of a first plurality of gate lines and one or more logic circuits; the first plurality of contacts further comprises a column of contacts extending in a second horizontal direction, each of the column of contacts being coupled to a corresponding digital line of a plurality of digital lines and one or more logic circuits; and a second plurality of contacts comprises a row of contacts extending in the first horizontal direction, each of the row of contacts being coupled to a corresponding gate line of a second plurality of gate lines and one or more logic circuits; the second plurality of contacts further comprises a column of contacts extending in the second horizontal direction, each of the column of contacts being coupled to a corresponding voltage source of a plurality of voltage sources and one or more logic circuits.

[0102] Aspect 24: The device according to any one of aspects 17 to 23, wherein the number of the first plurality of contacts is less than the number of the first plurality of decoding elements.

[0103] Aspect 25: The device according to any one of aspects 17 to 24, wherein the number of the second plurality of contacts is less than the number of the second plurality of decoding elements.

[0104] The information and signals described herein can be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, the signal may represent a bus of signals, which may have various bit widths.

[0105] The terms “electronic connectivity,” “conductive contact,” “connection,” and “coupling” refer to the relationship between components that enables the flow of signals between them. Components are considered electronically connected (or electrically contacting, connected, or coupled) to each other if any conductive path exists between them that enables the flow of signals between them at any given time. At any given time, the conductive path between components that are electronically connected (or electrically contacting, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or an indirect conductive path between connected components that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, can be used to interrupt the signal flow between connected components for a period of time.

[0106] The term "coupling" refers to the condition that shifts from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via a conductive path, while in a closed-circuit relationship, signals can travel between components via a conductive path. When a component, such as a controller, couples other components together, the component initially allows a change in the flow of signals between the other components via conductive paths that were previously not permitted.

[0107] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. When a controller isolates two components, it prevents changes in the conductive path used to allow signals to flow between the components.

[0108] As used herein, the term "layer" or "level" refers to a layer or sheet of geometry (e.g., relative to a substrate). Each layer or level may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer or level may be a three-dimensional structure in which two dimensions are greater than the third dimension, such as a thin film. A layer or level may contain different elements, components, and / or materials. In some instances, a layer or level may consist of two or more sublayers or sublevels.

[0109] As used herein, the term "electrode" can refer to an electrical conductor and, in some instances, can serve as an electrical contact to a memory cell or other component of a memory array. An electrode may comprise traces, wires, conductive lines, conductive layers, etc., that provide a conductive path between elements or components of the memory array.

[0110] The devices containing memory arrays discussed herein can be formed on semiconductor substrates, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0111] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, a drain, and a gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped, for example, degenerate, semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or a channel. If the channel is n-type (i.e., the majority of charge carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority of charge carriers are holes), then the FET may be called a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor can be "turned on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor can be "turned off" or "deactivated."

[0112] The exemplary configurations described herein, in conjunction with the accompanying drawings, are intended to represent all implementable or claim-scoped instances. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior to" other instances. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without such specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0113] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a dash following the reference numeral and a second numeral used to differentiate them among similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0114] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or codes on or transmitted over a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located in various locations, including distributed configurations such that portions of the functions are implemented in different physical locations.

[0115] For example, the various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed with the following components designed to perform the functions described herein: a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0116] As used herein, the word "or" in a list of items included in the claims (e.g., a list of items beginning with phrases such as "at least one of..." or "one or more of...") indicates a comprehensive list, such that a list of at least one of, for example, A, B, or C means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on conditions A and B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0117] Computer-readable media includes non-transitory computer storage media and communication media, with communication media including any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then such coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these are also included within the scope of computer-readable media.

[0118] The description herein is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: A first semiconductor device includes a plurality of word lines arranged in a hierarchy, a plurality of conductive posts extending through the plurality of word lines, and a first portion of a decoder, the first portion of the decoder including: A plurality of vertical transistors, each of the plurality of vertical transistors selectively coupling a corresponding conductive post to a corresponding digital line of a plurality of digital lines; A second plurality of vertical transistors, each of the second plurality of vertical transistors selectively coupling a corresponding word line to a corresponding voltage source among a plurality of voltage sources; and A plurality of first contacts, a first subset of the plurality of first contacts being coupled to a plurality of first vertical transistors, and a second subset of the plurality of first contacts being coupled to a plurality of second vertical transistors; and A second semiconductor device includes a second portion of the decoder, the second portion of the decoder including one or more logic circuits formed within a semiconductor substrate of the second semiconductor device, the second portion of the decoder including: Multiple second contacts; and A third plurality of transistors, at least a subset of which have terminals coupled to the plurality of second contacts, wherein the plurality of first contacts of the first portion of the decoder engage with the plurality of second contacts of the second portion of the decoder.

2. The device of claim 1, wherein the first portion of the decoder further comprises: A plurality of gate lines, each of the plurality of gate lines being coupled to a corresponding subset of the plurality of vertical transistors and to a corresponding contact of the plurality of first contacts; and The second plurality of gate lines, each of the second plurality of gate lines being coupled to a corresponding subset of the second plurality of vertical transistors and to a corresponding contact of the plurality of first contacts.

3. The device of claim 2, wherein each of the first plurality of vertical transistors includes a first terminal coupled to a corresponding conductive post of the plurality of conductive posts, a second terminal coupled to a corresponding digital line of the plurality of digital lines, and a gate coupled to a corresponding gate line of the first plurality of gate lines.

4. The device of claim 2, wherein each of the second plurality of vertical transistors includes a first terminal coupled to a corresponding portion of a word line board in the plurality of word line boards, a second terminal coupled to a corresponding voltage source in the plurality of voltage sources, and a gate coupled to a corresponding gate line in the second plurality of gate lines.

5. The device of claim 2, wherein the first portion of the decoder further comprises a third plurality of vertical transistors, each of the third plurality of vertical transistors selectively coupling a corresponding portion of the word line board to a corresponding ground source.

6. The device according to claim 2, wherein: Each of the plurality of digital lines is coupled to a corresponding contact among the plurality of first contacts; and Each of the plurality of voltage sources is coupled to a corresponding contact among the plurality of first contacts.

7. The device according to claim 2, wherein: The first plurality of vertical transistors are arranged in a first grid structure, the first grid structure including one or more rows extending in a first horizontal direction and one or more columns extending in a second horizontal direction orthogonal to the first horizontal direction; and The second plurality of vertical transistors are arranged in a second grid structure, the second grid structure including one or more rows extending in the first horizontal direction and one or more columns extending in the second horizontal direction.

8. The device of claim 7, wherein the plurality of first contacts includes a first row of contacts extending in the first horizontal direction, each first contact in the first row of contacts being coupled to a corresponding gate line of the plurality of gate lines and a corresponding second contact of the plurality of second contacts, the plurality of first contacts further including a first column of contacts extending in the second horizontal direction, each first contact in the first column of contacts being coupled to a corresponding digital line of the plurality of digital lines and a corresponding second contact of the plurality of second contacts.

9. The device of claim 8, wherein the plurality of first contacts further includes a second row of contacts extending in the first horizontal direction, each first contact in the second row of contacts coupling a corresponding gate line of the plurality of gate lines to a corresponding second contact of the plurality of second contacts, the plurality of first contacts further including a second column of contacts extending in the second horizontal direction, each first contact in the second column of contacts coupling a corresponding voltage source of the plurality of voltage sources to a corresponding second contact of the plurality of second contacts.

10. The device of claim 1, wherein the number of the plurality of first contacts is less than the sum of the number of the first plurality of vertical transistors and the number of the second plurality of vertical transistors.

11. The device of claim 1, wherein each of the first plurality of vertical transistors and each of the second plurality of vertical transistors comprises a corresponding thin-film transistor (TFT).

12. An apparatus comprising: The memory array has multiple word line boards arranged in multiple layers, each word line board including one or more word line components extending in a first horizontal direction; Multiple conductive pillars extend through the multiple word line boards, wherein at each word line board of the multiple levels, one or more memory cells of the memory array are coupled to the corresponding conductive pillar and a corresponding component of the word line board; Multiple digital lines extending in a second horizontal direction orthogonal to the first horizontal direction; and A decoder, offset vertically from the plurality of layers and configured to bias the plurality of conductive pillars and the plurality of word lines, the decoder including a first portion associated with a first semiconductor device and a second portion associated with a second semiconductor device, wherein the first portion includes a first plurality of contacts coupled to a second plurality of contacts of the second portion, the decoder including: The first portion includes one or more logic circuits at least partially formed within a semiconductor substrate and associated with operating the memory array; and The second portion, positioned along the vertical direction between the first portion of the decoder and the memory array, includes a first plurality of decoding elements configured to couple corresponding conductive pillars to corresponding digital lines and a second plurality of decoding elements configured to couple word line boards to corresponding voltage sources among a plurality of voltage sources.

13. The device of claim 12, wherein the decoder further comprises: The first plurality of gate lines, each of the first plurality of gate lines being coupled to a corresponding subset of the first plurality of contacts that couple the first portion of the decoder to the second portion of the decoder and to the one or more logic circuits. and The second plurality of gate lines, each of the second plurality of gate lines, is coupled to a corresponding subset of the second plurality of gates using a corresponding gate in the second plurality of gates that couple the first portion of the decoder to the second portion of the decoder, and is coupled to the one or more logic circuits.

14. The device of claim 13, wherein each of the first plurality of decoding elements comprises a corresponding vertical transistor having a first terminal coupled to a corresponding conductive post of the plurality of conductive posts, a second terminal coupled to a corresponding digital line of the plurality of digital lines, and a gate coupled to a corresponding gate line of the first plurality of gate lines.

15. The device of claim 13, wherein each of the second plurality of decoding elements comprises a corresponding vertical transistor having a first terminal coupled to a corresponding portion of a word line board in the plurality of word line boards, a second terminal coupled to a corresponding voltage source in the plurality of voltage sources, and a gate coupled to a corresponding gate line in the second plurality of gate lines.

16. The device of claim 13, wherein each of the second plurality of decoding elements comprises a corresponding first vertical transistor and a corresponding second vertical transistor, the corresponding first vertical transistor having a first terminal coupled to a corresponding portion of the word line board of the plurality of word line boards, a second terminal coupled to a corresponding voltage source of the plurality of voltage sources, and a gate coupled to a corresponding gate line of the second plurality of gate lines, and the corresponding second vertical transistor having a first terminal coupled to a corresponding portion of the word line board of the plurality of word line boards, a second terminal coupled to a corresponding ground source, and a gate coupled to a corresponding gate line of the second plurality of gate lines.

17. The device according to claim 13, wherein: Each of the plurality of digital lines is coupled to a corresponding contact in the plurality of contacts; and Each of the plurality of voltage sources is coupled to a corresponding contact in the second plurality of contacts.

18. The device according to claim 13, wherein: The first plurality of decoding elements are arranged in a first grid structure, the first grid structure including one or more rows extending in the first horizontal direction and one or more columns extending in the second horizontal direction; and The second plurality of decoding elements are arranged in a second grid structure, the second grid structure including one or more rows extending in the first horizontal direction and one or more columns extending in the second horizontal direction.

19. The apparatus according to claim 18, wherein: The first plurality of contacts include a row of contacts extending in the first horizontal direction, each contact in the row coupling a corresponding gate line of the first plurality of gate lines to the one or more logic circuits; the first plurality of contacts further include a column of contacts extending in the second horizontal direction, each contact in the column coupling a corresponding digital line of the plurality of digital lines to the one or more logic circuits; and The second plurality of contacts include a row of contacts extending in the first horizontal direction, each of the row of contacts being coupled to a corresponding gate line of the second plurality of gate lines and the one or more logic circuits; the second plurality of contacts further include a column of contacts extending in the second horizontal direction, each of the column of contacts being coupled to a corresponding voltage source of the plurality of voltage sources and the one or more logic circuits.

20. The device of claim 13, wherein the number of the first plurality of contacts is less than the number of the first plurality of decoding elements.

21. The device of claim 13, wherein the number of the second plurality of contacts is less than the number of the second plurality of decoding elements.

22. A method comprising: A layered assembly is formed, the layered assembly including multiple word line boards of a memory array arranged in multiple layers, each word line board including one or more word line components extending in a first horizontal direction, multiple conductive pillars extending through the multiple word line boards, and multiple digital lines coupled to the multiple word line boards and extending in a second horizontal direction orthogonal to the first horizontal direction. A first portion of a decoder is formed in a first substrate above the layered assembly. The first portion of the decoder includes a first plurality of decoding elements configured to couple corresponding conductive pillars to corresponding digital lines, and a second plurality of decoding elements configured to couple corresponding word line boards to corresponding voltage sources among a plurality of voltage sources and a plurality of first contacts. Each first contact is coupled to a corresponding subset of the first plurality of decoding elements or to a corresponding subset of the second plurality of decoding elements. A second portion of the decoder is formed in a second substrate, the second portion of the decoder including a plurality of second contacts and a plurality of transistors, at least a subset of the plurality of transistors having terminals coupled to the plurality of second contacts; and Each of the plurality of first contacts is engaged with a corresponding second contact of the plurality of second contacts, wherein the engagement positions the first portion of the decoder between the layered assembly and the second portion of the decoder.

23. The method of claim 22, wherein the first portion forming the decoder comprises: In each of the plurality of decoding elements, a corresponding first vertical transistor is formed, the corresponding first vertical transistor including a first terminal coupled to a corresponding conductive post and a second terminal coupled to a corresponding digital line; and In each of the second plurality of decoding elements, a corresponding second vertical transistor is formed, the corresponding second vertical transistor including a first terminal coupled to a corresponding word line portion and a second terminal coupled to a corresponding voltage source among the plurality of voltage sources.

24. The method of claim 23, wherein the first portion forming the decoder further comprises: A first plurality of gate lines are formed, each of the first plurality of gate lines being coupled to a corresponding subset of the first vertical transistor and to a corresponding first contact of the plurality of first contacts; and A second plurality of gate lines are formed, each of the second plurality of gate lines being coupled to a corresponding subset of the second vertical transistor and to a corresponding first contact of the plurality of first contacts.

25. The method of claim 22, wherein the first plurality of decoding elements are arranged in a first grid structure, the first grid structure including one or more rows extending in the first horizontal direction and one or more columns extending in a second horizontal direction orthogonal to the first horizontal direction; and the second plurality of decoding elements are arranged in a second grid structure, the second grid structure including one or more rows extending in the first horizontal direction and one or more columns extending in the second horizontal direction.

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