Post-encapsulation repair management

Abstract

The present disclosure relates to post package repair management. A soft post package repair (sPPR) request is detected. Data stored in a target row of a memory array associated with the sPPR request is written to a buffer. Non-maintenance requests executing on the target row are suspended. In response to suspending non-maintenance requests executing on the target row, the sPPR request is executed on the target row. After completing the sPPR request, non-maintenance requests executing on the target row are resumed and the data stored in the buffer is written to the repaired target row.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor memories and methods, and more specifically to apparatus, systems and methods for post-package repair (PPR) management. Background Technology

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic systems. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory may require power to maintain its data (e.g., host data, error data, etc.) and includes random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), and thyristor random access memory (TRAM), etc. Non-volatile memory provides persistent data by retaining the stored data when not powered and includes NAND flash memory, NOR flash memory, ferroelectric random access memory (FeRAM), and resistive variable memory, such as phase-change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), such as spin torque transfer random access memory (STT RAM), etc.

[0003] A memory device may be coupled to a host computer (e.g., a host computing device) to store data, commands, and / or instructions for use by the host computer or electronic system during operation. For example, data, commands, and / or instructions may be transferred between the host computer and the memory device during operation of a computing or other electronic system. A controller may be used to manage the transfer of data, commands, and / or instructions between the host computer and the memory device. Summary of the Invention

[0004] This disclosure relates to a method for post-package repair management, comprising: detecting a soft post-package repair (sPPR) request; writing data stored in a memory array in a target row associated with the sPPR request to a buffer; pausing non-maintenance requests on the target row; in response to pausing non-maintenance requests on the target row, performing the sPPR request on the target row; and after completing the sPPR request: resuming non-maintenance requests on the target row; and writing the data stored in the buffer to the repaired target row.

[0005] Another aspect of this disclosure relates to a method for post-packaging repair management, comprising: detecting a hard post-packaging repair (hPPR) request, wherein the hPPR request is associated with a target row of a memory array; setting PPR parameters of a local controller of the memory array, wherein the PPR parameters indicate the target row; and executing the hPPR request on the target row to remap an address corresponding to the target row to a different row of the memory array.

[0006] Another aspect of this disclosure relates to an apparatus for post-packaging repair management, comprising: a control circuitry system including a buffer, wherein the control circuitry system is configured to: suspend execution of a request associated with a target address and a memory device and a post-packaging repair (PPR) request; write data at the target address to the buffer; and execute the PPR request on a line of the memory device corresponding to the target address.

[0007] Another aspect of this disclosure relates to an apparatus for post-packaging repair management, comprising: a memory device; and a local controller residing on the memory device, wherein the local controller is configured to: execute a post-packaging repair (PPR) request on a first line of the memory device corresponding to a target address associated with the memory device; as part of executing the PPR request, remap the target address to a second line of the memory device; and reset a refresh counter of the local controller after the PPR request is completed.

[0008] Another aspect of this disclosure relates to a non-transitory medium that stores instructions associated with post-packaging repair management, the instructions being executable by a processing device to: detect a post-packaging repair (PPR) request associated with a target row address associated with a memory device; execute the PPR request on the row of the memory device corresponding to the target row address; and, after the PPR request is completed, resume execution of the request associated with the target row address. Attached Figure Description

[0009] Figure 1 This illustration presents a functional block diagram of a computing system comprising post-package repair (PPR) management, according to several embodiments of the present disclosure.

[0010] Figure 2 This is a diagram representing PPR management according to several embodiments of the present disclosure.

[0011] Figure 3 This is a flowchart corresponding to a method for sPPR according to some embodiments of the present disclosure.

[0012] Figure 4This is a flowchart corresponding to a method for hPPR according to some embodiments of this disclosure.

[0013] Figure 5 This is a block diagram of a computer system implementing PPR management according to several embodiments of the present disclosure. Detailed Implementation

[0014] This describes systems, apparatus, and methods related to post-packaging repair (PPR) management. Memory devices may incorporate PPR capabilities to address transient and non-transient memory faults. For example, the memory device controller may detect permanent and / or transient errors based on error correction codes (ECC). PPR enables the controller to remap faulty rows of the memory device to another row. For example, PPR may be performed as soft PPR (sPPR) and / or hard PPR (hPPR).

[0015] hPPR may include permanently remapping access from the erroneous row to another row. sPPR may include temporarily remapping access from the erroneous row to another row. While remapping of a row as part of sPPR can withstand a "hot" reset, it may not withstand a restart, depending on the implementation. On the other hand, remapping of a row as part of hPPR can withstand any type of reset, including a restart, due to the non-volatile programming performed as part of hPPR.

[0016] The memory device can notify the host that maintenance is required. For example, a compute fast link (CXL) memory device can notify the host via a CXL event report. Although some embodiments described herein include CXL memory devices, embodiments of this disclosure are not limited thereto.

[0017] CXL is a high-speed CPU-to-device and CPU-to-memory interconnect designed to accelerate the performance of next-generation data centers. CXL technology maintains memory coherence between the CPU memory space and the memory on the attached device, which allows for higher-performance resource sharing, reduced software stack complexity, and lower overall system cost.

[0018] CXL is designed as an industry-open standard interface for high-speed communications, as accelerators are increasingly used to supplement CPUs to support emerging applications such as artificial intelligence and machine learning. CXL technology is built on the Peripheral Component Interconnect Rapid (PCIe) infrastructure, thereby leveraging the PCIe physical and electrical interfaces to provide high-level protocols in the domain, such as I / O protocols, memory protocols (e.g., initially allowing hosts and accelerators to share memory), and coherence interfaces. Aspects of this disclosure provide a unified interface for managing maintenance commands, particularly PPR requests. For example, mailbox commands can be added to the command set of the CXL memory device to initiate maintenance operations such as PPR.

[0019] As used herein, the singular forms “a / an” and “the” include both singular and plural references, unless the context clearly indicates otherwise. Furthermore, the word “may” is used throughout this application in an permissive sense (i.e., possible, able) rather than a mandatory sense (i.e., required). The term “comprising” and its derivatives mean “including (but not limited to)”. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediary component), whether wired or wireless, including connections such as electrical, optical, magnetic, and the like. The terms “data” and “data value” are used interchangeably herein and may have the same meaning, depending on the context.

[0020] The diagrams in this document follow a numbering convention, where the first one or a few digits correspond to the diagram number, and the remaining digits identify the elements or components within the diagram. Similar elements or components between different diagrams can be identified by using similar numbers. For example, element 122 could represent... Figure 1 Component 22 in, and similar components in Figure 2 The symbol 222 may be used. Similar elements within the figures may be designated using hyphens and additional numbers or letters. It should be understood that elements shown in the various embodiments herein may be added, interchanged, and / or eliminated to provide several additional embodiments of this disclosure. Furthermore, it should be understood that the scale and relative dimensions of the elements provided in the figures are intended to illustrate certain embodiments of this disclosure and should not be construed as limiting.

[0021] Figure 1 This illustration shows a functional block diagram of a computing system 101 comprising PPR management, according to several embodiments of the present disclosure. The computing system 101 includes a memory module 111. The memory module 111 may include a memory controller 100 and one or more memory and / or memory devices coupled thereto.

[0022] The memory controller 100 may include a front-end section 104, a central controller section 110, and a back-end section 115. The computing system 101 may further include a host 103, memory devices 122-1, ..., 122-N (collectively referred to as memory devices 122), and memory 127. Memory 127 may be a flash memory accessible via a Serial Peripheral Interface (SPI). Memory 127 may include other circuitry, firmware, software, or the like, either individually or in combination. In some embodiments, non-volatile memory may be used to store persistent code images, data, configuration parameters, and / or logs.

[0023] Front-end portion 104 includes interfaces for coupling memory controller 100 to host 103 via input / output (I / O) paths 102-1, 102-2, ..., 102-M (e.g., collectively referred to as I / O paths 102). The front-end portion includes interface management circuitry for managing the I / O paths 102. The front-end portion may include any number of I / O paths 102 (e.g., eight, sixteen I / O paths 102). In some embodiments, I / O paths 102 may be configured as a single port. In some embodiments, the interface between memory controller 100 and host 103 may be a PCIe physical and electrical interface operating according to the CXL protocol. In some embodiments, computing system 101 may be a CXL-compliant memory system (e.g., the memory system may include a PCIe / CXL interface).

[0024] Central controller section 110 includes cache memory 112 (or a cache). However, embodiments of this disclosure are not limited to central controller section 110 including cache memory. For example, if a buffer (e.g., a dedicated buffer) is allocated for temporarily storing data of rows being repaired, then cache memory may not be necessary.

[0025] In some embodiments, in response to receiving a read request for data stored in cache memory 112, the data can be provided to host 103 according to the request without further access to memory device 122. In some embodiments, in response to receiving a write request, the data can be stored in cache memory 112 before being written to memory device 122.

[0026] In some embodiments, the central controller section 110 may receive a PPR request from the memory device 122 and, in response to the PPR request, perform PPR on the rows of the memory device 122 associated with the PPR request. In some embodiments, the central controller section 110 may autonomously analyze the row reliability of the memory device 122 and perform PPR on the rows of the memory device 122 based on the analysis. In some embodiments, the central controller section 110 may receive a PPR request from the host 103 and, in response to the PPR request, perform PPR on the rows of the memory device 122 associated with the PPR request. Whether the central controller section 110 performs PPR in response to a PPR request or autonomously may be based on, and depend on, the internal policy of the central controller section 110.

[0027] Non-limiting examples of memory operations include memory operations that read data from cache memory 112 and / or memory device 122 and operations that write data to cache memory 112 and / or memory device 122. In some embodiments, the central controller portion 110 may control the writing of multiple pages of data substantially simultaneously.

[0028] As used herein, the term "substantially" implies that the characteristics are not absolute but close enough to achieve the advantages of the characteristics. For example, "substantially simultaneous" is not limited to operations that are performed absolutely simultaneously and may include timing that is intended to be simultaneous but may not be precisely simultaneous due to manufacturing limitations. For example, media controllers utilized "substantially simultaneous" may not start or end at exactly the same time due to read / write latency that may be exhibited by various interfaces. For example, multiple memory controllers may be used such that they simultaneously write data to the memory device, regardless of whether one of the media controllers starts or terminates before another.

[0029] Back-end portion 115 may include a media control circuitry and a physical (PHY) layer coupling memory controller 100 to memory device 122. As used herein, the term "PHY layer" generally refers to the physical layer in the Open Systems Interconnection (OSI) model of a computing system. The PHY layer may be the first (e.g., lowest) layer of the OSI model and is used to transmit data over a physical data transmission medium. In some embodiments, the physical data transmission medium may include channels 125-1, ..., 125-N (collectively referred to as channel 125). Among other possible buses, channel 125 may include, for example, a 16-pin data bus and a 2-pin data mask inversion (DMI) bus. In some embodiments, back-end portion 115 may communicate (e.g., transmit and / or receive) data to and / or receive data from memory device 122 via the data bus. In some embodiments, error detection information and / or error correction information may be communicated to and / or from memory device 122 via the DMI bus. However, embodiments of this disclosure are not limited thereto. For example, back-end portion 115 may transmit data and / or error detection information and / or error correction information to and / or from memory device 122 via the DMI bus. Error detection information and / or error correction information may be transmitted simultaneously with data exchange. In some embodiments, data and ECC information may be mapped separately on the data and DMI buses in different ways to improve (potentially maximize) the performance of computing system 101.

[0030] An example of memory device 122 is dynamic random access memory (DRAM). DRAM may operate according to, for example, a Low Power Double Data Rate (LPDDRx) protocol (e.g., LPDDRx DRAM device, LPDDRx memory, etc.). The "x" in LPDDRx refers to any generation of the protocol (e.g., LPDDR5). In some embodiments, at least one of memory devices 122 is operated as an LPDDRx DRAM device with enabled low power features, and at least one of memory devices 122 is operated as an LPDDRx DRAM device with at least one disabled low power feature.

[0031] In some embodiments, the memory controller 100 may include a management unit 105 for initializing, configuring, and / or monitoring the characteristics of the memory controller 100. The management unit 105 may include an I / O bus for managing out-of-band data and / or commands, a management unit controller for executing instructions associated with initializing, configuring, and / or monitoring the characteristics of the memory controller, and a management unit memory for storing data associated with initializing, configuring, and / or monitoring the characteristics of the memory controller 100. As used herein, the term "out-of-band data and / or commands" generally refers to data and / or commands transmitted via a transmission medium different from the primary transmission medium of the network. For example, out-of-band data and / or commands may be data and / or commands transmitted to the network using a transmission medium different from that used for transmitting data within the network.

[0032] In some embodiments, according to this disclosure, management unit 105 may be configured to provide PPR management. However, embodiments of this disclosure are not limited thereto. For example, according to this disclosure, other parts, components, and / or circuitry of memory controller 100 may be configured to provide PPR management individually or in combination.

[0033] In some embodiments, memory controller 100 may include a buffer, such as cache 112. In some embodiments, memory controller 100 may be configured to provide a PPR. For example, memory controller 100 may be configured to (or configured to cause) write data at a target address associated with a memory device (e.g., memory device 122-1) and a PPR request to the buffer. The target address may be a row address associated with the memory device. Memory controller 100 may be configured to (or configured to cause) execute the PPR request on the row of the memory device corresponding to the target address, and suspend the execution of the request associated with the target address in response to the execution of the PPR request. As used herein, “concurrency” means performing an action at least partially concurrent with the execution of another action. The phrase “parallel” may be used herein as a synonym for concurrency. Memory controller 100 may be configured to (or configured to cause) write data stored in the buffer to the memory device at the target address. The memory controller 100 may be configured to (or configured to cause) resume the execution of the request associated with the target address in response to the completion of the PPR request.

[0034] The memory controller 100 may be a system controller coupled to the memory device. Although in Figure 1Unless otherwise stated herein, components and / or functionality of the memory controller 100 may reside on the memory device (e.g., a local controller). The memory controller 100 may be configured to receive PPR requests from a host device (e.g., host 103) and / or the memory device. As described herein, in some embodiments, the memory controller 100 may autonomously monitor the reliability of rows on the memory device and perform PPRs determined by the memory controller 100.

[0035] Despite Figure 1 Unless otherwise stated, components and / or functionality of the memory controller 100 may reside on the memory device (e.g., a local controller). In some embodiments, the memory controller 100 may be configured to provide hPPR. For example, the memory controller 100 may be configured to (or configured to cause) execute a PPR request at a target address associated with the memory device. The memory controller 100 may be configured to (or configured to cause) concurrently suspend the execution of the request associated with the target address with the execution of the PPR request. The memory controller 100 may be configured to (or configured to cause) reset its refresh counter in response to completion of the PPR request. Refreshing the refresh counter of the memory controller 100 may enable multiple memory controllers (e.g., local controllers) to synchronize, allowing concurrent operation of the memory controllers.

[0036] Figure 2 Figure 230 represents PPR management according to several embodiments of this disclosure. (Associated with...) Figure 2 Any steps and operations described can be associated with Figure 1 The memory controller 100 described herein shall execute this. The host 203 and memory module 211 may be similarly associated with... Figure 1 The host 103 and one or more memory modules 111 are described.

[0037] Memory module 211 (e.g., control circuitry residing on and / or coupled to memory module 211) can determine that memory module 211 needs to perform internal maintenance operations, such as performing PPR on one or more rows of memory module 211. As illustrated by FIG230, memory module 211 can provide log information (e.g., one or more event records) to host 203. The log information can be a data structure indicating the conditions of memory module 211. The log information can contain flags (e.g., maintenance flags) associated with the corresponding addresses (e.g., device logical address (DLA), device physical address (DPA), host physical address (HPA)) of rows corresponding to memory device 222, which, when set, indicate that memory module 211 has determined that maintenance operations need to be performed on the corresponding rows. The log information can contain the target address to which maintenance operations are to be performed (e.g., the address of the affected or erroneous row). The log information can contain the type of maintenance operation (e.g., PPR) to be performed on the row of memory module 211 corresponding to the target address. Maintenance flags indicating lines requiring repair can be sent via log information. However, if resources for performing a PPR are exhausted, the host may receive a signal indicating resource exhaustion when attempting to perform the PPR. Resources are spare lines in the memory device; the lines to be repaired are temporarily remapped to the spare lines for sPPR or permanently remapped to the spare lines for hPPR.

[0038] If the row cannot be repaired via sPPR (i.e., there are insufficient resources available to perform sPPR), then hPPR can be performed to permanently remap the target address to a different row of memory module 211. If the row can be repaired via sPPR (i.e., there are sufficient resources available to perform sPPR), then either sPPR or hPPR can be performed to temporarily or permanently remap the target address to a different row of the memory device, respectively. A non-limiting example of a standard for performing sPPR instead of hPPR is execution time. The execution time of hPPR can be longer than the execution time of sPPR.

[0039] like Figure 2 As indicated by 232, host 203 may request event logs from memory module 211. As indicated by 234, memory module 211 may transmit event logs to host 203. As indicated by 236, host 203 may transmit commands to memory module 211 to initiate maintenance operations performed by memory module 211. The type of maintenance operation to be performed may be based on event logs from memory module 211.

[0040] As indicated in 238, commands provided by host 203 may include a payload indicating the type of maintenance operation to be performed (e.g., PPR), the method for performing said type of maintenance operation (e.g., sPPR), and / or input payloads for operation-specific parameters. Non-limiting examples of operation-specific parameters include querying resource flags and target addresses. As indicated in 240, commands from host 203 may include a return code identifying exhausted resources used for repair.

[0041] although Figure 2 The present disclosure describes how host 203 initiates maintenance operations by transmitting commands, but the embodiments are not limited thereto. For example, in some embodiments, memory module 211 may initiate maintenance operations without commands from an external source (e.g., host 203). However, in some embodiments, memory module 211 may require activation by host 203 to initiate maintenance operations.

[0042] Figure 3 This is a flowchart corresponding to a method 350 for sPPR according to some embodiments of the present disclosure. Method 350 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 350 is associated with... Figure 1 The described memory controller 100 performs the actions. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0043] In 352, method 350 may include detecting sPPR requests, for example, associated with... Figure 2 The described maintenance operation command. The sPPR request can be issued by the host and received by a memory device coupled thereto. In some embodiments, the sPPR request can be issued internally (e.g., associated with...). Figure 1 The memory module 111 described has a memory controller 100, and is received by a local controller of the memory device (e.g., the logic circuitry of the memory device 122). In sPPR, the data is preserved by copying the data stored in the target row from the target row to another row.

[0044] In method 350, at 353, the method may include writing data from a target row associated with an sPPR request, stored in a memory array (e.g., memory device 122), to a buffer (e.g., cache 112). Writing the data from the target row to the buffer may include setting a reservation flag (e.g., a reservation bit) associated with the target row. Setting the reservation flag ensures that the data from the target row is not overwritten and / or altered while stored in the buffer. This is important because once the target row is repaired as part of the sPPR, the data will be written back to the target row. Setting the reservation flag may include changing a bit to a specific state (e.g., 1). Writing the data from the target row to the buffer may include writing the data from the target row to the buffer in a piecemeal manner (e.g., byte-by-byte). The data from the target row may be written to the buffer via multiple write operations, each write operation writing a corresponding subset of the data from the target row. In some embodiments, a first write operation may be performed to write a first portion of the data from the target row to the buffer, and a second write operation may be performed to write a second portion of the data from the target row to the buffer. After the data is written to the buffer, a reservation flag is set to prevent data from being evicted from the buffer.

[0045] In 354, method 350 may include pausing the execution of a non-maintenance request on the target row. In 355, method 350 may include, in response to pausing the execution of the non-maintenance request on the target row, executing an sPPR request to repair the target row. The sPPR request may be executed by the local controller of the memory array. Although in Figure 3 While not explicitly stated, portions of method 350 described in association with 354 and 355 may occur in parallel. In some embodiments, the memory device may queue requests from the memory device controller in a queue of the memory device's local controller.

[0046] By transferring data stored in the target row to a buffer and remapping the target row to the buffer, requests associated with the target row can be served via the buffer and the data stored therein without affecting functionality. This mitigates the potential danger of data loss and / or data unavailability during PPR. For example, in some embodiments, non-maintenance requests can be performed on the buffer concurrently with the execution of sPPR requests. Memory controller 100 can serve non-maintenance requests while repairing the target row by executing non-maintenance requests associated with the target row from a host (e.g., host 103) on the buffer. Memory controller 100 can execute non-maintenance requests on the buffer and sPPR requests on the target row in parallel.

[0047] In step 356, method 350 may include resuming non-maintenance requests on the target row after the sPPR request is completed, and writing data stored in the buffer to the repaired target row. Requests queued while execution of requests associated with the target row is suspended may be executed. Writing data may include unsetting a reservation flag. Unsetting the reservation flag allows data stored in the buffer to be overwritten and / or modified. Unsetting the reservation flag may include changing a bit to a specific state (e.g., 0) opposite to the state corresponding to when the reservation flag was set. In some embodiments, method 350 may include resetting a refresh counter of the controller coupled to the memory array after the sPPR request is completed.

[0048] Figure 4 This is a flowchart corresponding to method 470 for hPPR according to some embodiments of this disclosure. Method 470 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 470 is performed by a process logic associated with... Figure 1 The described memory controller 100 performs the actions. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0049] At 472, method 470 may include detecting an hPPR request. The hPPR request is associated with a target row of the memory array (e.g., memory device 122). The hPPR request may be issued by a host and received by a memory module coupled thereto (e.g., memory module 111). In some embodiments, the hPPR request may be issued internally (e.g., by memory controller 100, memory device controller) and received by a local controller of the memory array. At 473, method 470 may include setting PPR parameters of the local controller of the memory array. The PPR parameters may indicate the target row.

[0050] In 474, method 470 may include performing an hPPR request on the target row to remap the address corresponding to the target row to a different row of the memory array. Although Figure 4Not explicitly stated, but method 470 may include having the local controller execute the request on a different row. Because hPPR remaps the address from the row corresponding to the target row to the row corresponding to the different row, the request associated with the address can be executed once the hPPR request is complete. In some embodiments, method 470 may include resetting the local controller's refresh counter after the hPPR request is completed.

[0051] Figure 5 This is a block diagram of a computer system 586 implementing PPR management according to several embodiments of the present disclosure. The computer system 586 may be a machine within which a set of instructions can be executed, causing the machine to perform any or more of the methodologies discussed herein. In some embodiments, the computer system 586 may correspond to a host system (e.g., associated with...). Figure 1 The described host (103) includes, is coupled to, or utilizes one or more memory modules (e.g., memory module 111), or can be used to perform operations of a controller (e.g., memory controller 100) to execute an operating system to perform operations associated with PPR management. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a local access network (LAN), intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer-to-peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0052] The machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by said machine. Furthermore, while a single machine is described, the term "machine" should also be considered to include any collection of machines that individually or collectively execute a set (or more) of instructions to perform any or more of the methods discussed herein.

[0053] The computer system 586 includes a processing device 587, a main memory 590 (e.g., ROM, flash memory, DRAM, such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), a static memory 589 (e.g., flash memory, static random access memory (SRAM)), and a data storage device 593, which communicate with each other via a bus 588.

[0054] Processing device 587 represents one or more general-purpose processing devices, such as a microprocessor, central processing unit, or the like. More specifically, processing device 587 may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or multiple processors implementing combinations of instruction sets. Processing device 587 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 587 is configured to execute instructions 591 for performing the operations and steps discussed herein. Computer system 587 may further include a network interface device 595 for communication via a network 596.

[0055] Data storage system 593 may include machine-readable storage medium 594 (also referred to as computer-readable medium) thereon storing one or more sets of instructions 591 or software embodying any or more of the methodologies or functions described herein. Instructions 591 may also reside wholly or at least partially in main memory 590 and / or processing device 587 during execution by computer system 586, which also constitute machine-readable storage medium. In some embodiments, machine-readable storage medium 594, data storage system 593, and / or main memory 590 may correspond to memory module 111 and / or memory device 122.

[0056] In some embodiments, instruction 591 may include instructions for implementing PPR management (in... Figure 5 (Indicated at 592) Functional instructions. For example, instruction 591 may include instructions for detecting a PPR request associated with a target row address associated with a memory device and executing the PPR request. Instruction 591 may include instructions for concurrently suspending the execution of the request associated with the target row address with the execution of the PPR request. Instruction 591 may include instructions for resuming the execution of the request associated with the target row address after the PPR request has been completed.

[0057] Instruction 591 may include instructions for writing data at a target row address to a buffer in response to a PPR request being an sPPR request, executing the sPPR request at the target row address, and writing data stored in the buffer to a memory device at the target row address in response to the completion of the sPPR request. Instruction 591 may include instructions for concurrently setting a reserved flag associated with the target row address in conjunction with the execution of the sPPR request. Instruction 591 may include instructions for canceling the setting of the reserved flag in response to the completion of the sPPR request.

[0058] Instruction 591 may include instructions for executing an hPPR request at a target row address in response to the PPR request being an hPPR request. Instruction 591 may also include instructions for resetting a refresh counter associated with the memory device in response to completion of the hPPR request.

[0059] Although machine-readable storage medium 594 is shown as a single medium in the exemplary embodiments, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include (but is not limited to) solid-state memory, optical media, and magnetic media.

[0060] Although specific embodiments have been illustrated and described herein, those skilled in the art will understand that arrangements calculated to achieve the same results may replace the specific embodiments shown. This disclosure is intended to cover adaptations or variations of one or more embodiments of this disclosure. It should be understood that the foregoing description has been done in an illustrative rather than restrictive manner. Those skilled in the art will understand, upon reviewing the foregoing description, combinations of the foregoing embodiments and other embodiments not explicitly described herein. The scope of one or more embodiments of this disclosure includes other applications in which the foregoing structures and processes are used. Therefore, the scope of one or more embodiments of this disclosure should be determined with reference to the appended claims and the full scope of the equivalents entitled to by such claims.

[0061] In the foregoing detailed embodiments, for the purpose of simplifying this disclosure, some features are grouped together in a single embodiment. This approach of the disclosure should not be construed as reflecting an intention that the disclosed embodiments must use more features than expressly recited in each claim. Rather, as reflected in the appended claims, the subject matter of the invention exists in fewer than all the features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed embodiments, wherein each claim is an independent, separate embodiment.

Claims

1. A method for post-package repair (PPR) management, comprising: detecting a soft post-package repair (sPPR) request; writing data stored in a target row of a memory array associated with the sPPR request to a buffer; suspending execution of non-maintenance requests on the target row; in response to suspending execution of non-maintenance requests on the target row, executing the sPPR request on the target row; and after completing the sPPR request: resuming execution of non-maintenance requests on the target row; and writing the data stored in the buffer to the target row.

2. The method of claim 1, wherein writing the data of the target row to the buffer comprises setting a reserved flag associated with the target row.

3. The method of claim 2, wherein writing repaired data comprises unsetting the reserved flag.

4. The method of claim 1, wherein writing the data of the target row to the buffer comprises: performing a first write operation to write a first portion of the data of the target row to the buffer; and performing a second write operation to write a second portion of the data of the target row to the buffer.

5. The method of claim 1, wherein suspending execution of requests associated with the target row comprises queuing requests associated with the target row while repairing the target row.

6. The method of claim 1, further comprising executing non-maintenance requests on data stored in the buffer concurrently with executing the sPPR request on the target row.

7. The method of claim 1, wherein suspending execution of non-maintenance requests on the target row occurs concurrently with executing the sPPR request on the target row.

8. The method of claim 1, further comprising resetting a refresh counter of a controller coupled to the memory array after completing the sPPR request.

9. A method for post-package repair (PPR) management, comprising: detecting a hard post-package repair (hPPR) request, wherein the hPPR request is associated with a target row of a memory array; setting a PPR parameter of a local controller of the memory array, wherein the PPR parameter indicates the target row; executing the hPPR request on the target row to remap an address corresponding to the target row to a different row of the memory array; and resetting a refresh counter of the local controller after completing the hPPR request.

10. The method of claim 9, further comprising executing requests associated with the target row by the local controller after completing the hPPR request.

11. An apparatus for post-package repair (PPR) management, comprising: control circuitry comprising a buffer, wherein the control circuitry is configured to: suspend execution of requests associated with a target address associated with a memory device and a post-package repair (PPR) request; write data at the target address to the buffer; and and performing the PPR request on a row of the memory device corresponding to the target address.

12. The apparatus of claim 11, wherein the control circuitry is further configured to write the data stored by the buffer at the target address to the memory device.

13. The apparatus of claim 11, wherein the control circuit is further configured to resume execution of requests associated with the target address after completion of the PPR request.

14. The apparatus of claim 11, further comprising the memory device, wherein the control circuitry comprises a memory controller of a memory module that includes the memory device.

15. The apparatus of claim 11, further comprising the memory device, wherein the control circuitry comprises a local controller that resides on the memory device.

16. The apparatus of claim 11, wherein the control circuit is further configured to receive the PPR request from a host.

17. The apparatus of claim 11, wherein the control circuit is further configured to receive the PPR request from the memory device.

18. An apparatus for post-package repair (PPR) management, comprising: a memory device; and a local controller that resides on the memory device, wherein the local controller is configured to: execute a post-package repair (PPR) request on a first row of the memory device corresponding to a target address associated with the memory device; as part of executing the PPR request, remap the target address to a second row of the memory device; and reset a refresh counter of the local controller after completion of the PPR request.

19. A non-transitory medium storing instructions executable by a processing device to: detect a post-package repair (PPR) request associated with a target row address associated with a memory device; execute the PPR request on a row of the memory device corresponding to the target row address; in response to the PPR request being a soft PPR (sPPR) request: write data at the target row address to a buffer; execute the sPPR request at the target row address; and in response to completion of the sPPR request, write the data stored in the buffer at the target row address to the memory device; in response to the PPR request being a hard PPR (hPPR) request: execute the hPPR request at the target row address; and in response to completion of the hPPR request, reset a refresh counter associated with the memory device; and resume execution of requests associated with the target row address after completion of the PPR request.

20. The medium of claim 19, further storing instructions executable to: set a reservation flag associated with the target row address concurrently with execution of the sPPR request; and in response to completion of the sPPR request, unset the reservation flag. ​

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