Semiconductor memory device and method of operating the same

Abstract

The present disclosure relates to a semiconductor memory device and an operating method thereof. A semiconductor memory device includes a memory cell array including memory cells, a peripheral circuit performing a read / verify operation of a selected memory cell, and a control logic circuit controlling a read / verify operation of the peripheral circuit. The control logic circuit controls the peripheral circuit to apply a first voltage to a selected word line connected with the selected memory cell, to float an unselected word line among unselected word lines which is adjacent to the selected word line, to apply a first underdrive voltage lower than the first voltage to the selected word line during at least a part of a period when the unselected word line adjacent to the selected word line is floated, and to apply a second voltage higher than the first underdrive voltage and lower than the first voltage to the selected word line.

Description

Technical Field

[0001] This disclosure relates to semiconductor memory devices, and more specifically, to semiconductor memory devices with improved read speeds and methods of operating the same. Background Technology

[0002] Semiconductor memory devices can be formed as a two-dimensional structure arranged horizontally on a semiconductor substrate, or as a three-dimensional structure stacked vertically on a semiconductor substrate. Three-dimensional memory devices are designed to overcome the integration limitations of two-dimensional memory devices and can include multiple memory cells stacked vertically on a semiconductor substrate. Summary of the Invention

[0003] The embodiments disclosed herein relate to semiconductor memory devices with improved read speeds and methods of operating thereof.

[0004] According to embodiments of this disclosure, a semiconductor memory device includes a memory cell array, peripheral circuitry, and control logic circuitry. The memory cell array includes a plurality of memory cells. The peripheral circuitry is configured to perform a read operation and / or a verification operation on a selected memory cell among the plurality of memory cells. The control logic circuitry is configured to control the read operation and / or the verification operation of the peripheral circuitry. The control logic circuitry is configured to control the peripheral circuitry to apply a first voltage to a selected word line connected to the selected memory cell, causing an unselected word line adjacent to the selected word line (excluding the selected word line) to float, applying a first underdrive voltage lower than the first voltage to the selected word line during at least a portion of the time the unselected word line adjacent to the selected word line is floated, and applying a second voltage higher than the first underdrive voltage and lower than the first voltage to the selected word line.

[0005] According to another embodiment of this disclosure, a method of operating a semiconductor memory device is used to perform read operations and / or verification operations on a plurality of memory cells. The method of operating the semiconductor memory device includes the steps of: applying a first voltage to a selected word line connected to the selected memory cell, and applying a read pass voltage to unselected word lines other than the selected word line; floating an unselected word line adjacent to the selected word line; and applying a first underdrive voltage lower than the first voltage to the selected word line during at least a portion of the time the unselected word line adjacent to the selected word line is floating.

[0006] According to another embodiment of this disclosure, a method of operating a semiconductor memory device is used to perform read operations and / or verification operations on a plurality of memory cells. The method of operating the semiconductor memory device includes the following steps: applying a first voltage to a selected word line; applying a first read pass voltage to an unselected word line not adjacent to the selected word line; applying a second read pass voltage greater than the first read pass voltage to the unselected word line adjacent to the selected word line; floating the unselected word line adjacent to the selected word line; and applying a first underdrive voltage lower than the first voltage to the selected word line during at least a portion of the time the unselected word line adjacent to the selected word line is floating.

[0007] This technology can provide semiconductor memory devices with improved read speeds and methods of operation thereof. Attached Figure Description

[0008] Figure 1 This is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0009] Figure 2 It is shown Figure 1 Isometric diagrams of implementations of memory cell arrays.

[0010] Figure 3 It is shown Figure 2 The circuit diagram of any one of the memory blocks BLKa from BLK1 to BLKz.

[0011] Figure 4 It is shown that it includes Figure 1 A circuit diagram illustrating an implementation of any one of the storage blocks BLKb among the multiple storage blocks BLK1 to BLKz in the memory cell array 110.

[0012] Figure 5 It is a graph showing the threshold voltage distribution of a multi-level unit.

[0013] Figure 6 This is a timing diagram illustrating a method of operating a semiconductor memory device according to an embodiment of the present disclosure.

[0014] Figure 7 This is a timing diagram illustrating a method of operating a semiconductor memory device according to another embodiment of the present disclosure.

[0015] Figure 8 This is a timing diagram illustrating a method of operating a semiconductor memory device according to yet another embodiment of the present disclosure.

[0016] Figure 9 This is a flowchart illustrating a method of operating a semiconductor memory device according to yet another embodiment of the present disclosure.

[0017] Figure 10 This is a flowchart illustrating a method of operating a semiconductor memory device according to yet another embodiment of the present disclosure.

[0018] Figure 11 This is a timing diagram illustrating a method of operating a semiconductor memory device according to yet another embodiment of the present disclosure.

[0019] Figure 12 This is a flowchart illustrating a method of operating a semiconductor memory device according to yet another embodiment of the present disclosure.

[0020] Figure 13 This is a timing diagram illustrating a method of operating a semiconductor memory device according to yet another embodiment of the present disclosure.

[0021] Figure 14 This is a flowchart illustrating a method of operating a semiconductor memory device according to yet another embodiment of the present disclosure.

[0022] Figure 15 This is a block diagram illustrating an application example 2000 of a storage device including a semiconductor memory device according to an embodiment of the present disclosure.

[0023] Figure 16 It shows that it includes references Figure 15 A block diagram of a computing system describing a storage device. Detailed Implementation

[0024] The specific structural or functional descriptions illustrating embodiments of the concepts disclosed in this specification or application are for the purpose of describing embodiments of the concepts disclosed herein, and embodiments of the concepts disclosed herein may be implemented in various forms and should not be construed as limited to the embodiments described in this specification or application.

[0025] Figure 1 This is a block diagram illustrating a semiconductor memory device 100 according to an embodiment of the present disclosure.

[0026] Reference Figure 1 The semiconductor memory device 100 includes a memory cell array 110, an address decoder 120, a read / write circuit 130, a control logic circuit 140, and a voltage generator 150.

[0027] The memory cell array 110 includes multiple memory blocks BLK1 to BLKz. The multiple memory blocks BLK1 to BLKz are connected to the address decoder 120 via word lines. The multiple memory blocks BLK1 to BLKz are connected to the read / write circuitry 130 via bit lines BL1 to BLm. Each of the multiple memory blocks BLK1 to BLKz includes multiple memory cells. In one embodiment, the multiple memory cells are non-volatile memory cells and can be configured as non-volatile memory cells with a vertical channel structure. The memory cell array 110 can be configured as a two-dimensional memory cell array. According to one embodiment, the memory cell array 110 can be configured as a three-dimensional memory cell array.

[0028] Each memory cell in the plurality of memory cells included in the memory cell array 110 may store at least one bit of data. In one embodiment, each memory cell in the plurality of memory cells included in the memory cell array 110 may be a single-level cell (SLC) storing one bit of data. In another embodiment, each memory cell in the plurality of memory cells included in the memory cell array 110 may be a multi-level cell (MLC) storing two bits of data. In yet another embodiment, the plurality of memory cells included in the memory cell array 110 may include a plurality of memory cells each storing three or more data bits.

[0029] Address decoder 120, read / write circuitry 130, and voltage generator 150 operate as peripheral circuitry 105 driving memory cell array 110. Address decoder 120 is connected to memory cell array 110 via word line WL. Address decoder 120 is configured to operate in response to control logic circuitry 140. Address decoder 120 receives address ADDR. Address ADDR may include block address, column address, row address, etc.

[0030] Address decoder 120 is configured to decode block addresses from received addresses. Address decoder 120 selects at least one memory block based on the decoded block address. Additionally, during a read operation, address decoder 120 applies a read voltage Vread generated by voltage generator 150 to the selected word line of the selected memory block and applies a voltage Vpass to the remaining unselected word lines. Furthermore, during a program verification operation, address decoder 120 applies a verification voltage generated by voltage generator 150 to the selected word line of the selected memory block and applies a voltage Vpass to the remaining unselected word lines.

[0031] Address decoder 120 is configured to decode the column address of the received address. Address decoder 120 sends the decoded column address to read / write circuit 130.

[0032] Read and programming operations on the semiconductor memory device 100 are performed on a page-by-page basis. The addresses received when requesting read and programming operations include block address, row address, and column address. Address decoder 120 selects a memory block and a word line based on the block address and row address. The column address is decoded by address decoder 120 and provided to read / write circuitry 130.

[0033] Address decoder 120 may include block decoder, row decoder, column decoder, address buffer, etc.

[0034] The read / write circuit 130 includes multiple page buffers PB1 to PBm. The read / write circuit 130 can operate as a "read circuit" during read operations of the memory cell array 110 and as a "write circuit" during write operations of the memory cell array 110. The multiple page buffers PB1 to PBm are connected to the memory cell array 110 via bit lines BL1 to BLm. During read and program verification operations, in order to sense the threshold voltage of the memory cell, the multiple page buffers PB1 to PBm continuously supply sensing current to the bit lines connected to the memory cell while sensing changes in the amount of current flowing through the sensing node according to the programming state of the corresponding memory cell, and latch the sensed changes as sensed data. The read / write circuit 130 operates in response to a page buffer control signal output from the control logic circuit 140.

[0035] During a read operation, the read / write circuit 130 senses the data in the memory cell, temporarily stores the read data, and outputs the data DATA to the input / output buffer (not shown) of the semiconductor memory device 100. In one embodiment, in addition to a page buffer (or page register), the read / write circuit 130 may also include a column select circuit, etc.

[0036] Control logic circuitry 140 is connected to address decoder 120, read / write circuitry 130, and voltage generator 150. Control logic circuitry 140 receives commands CMD and control signals CTRL via input / output buffers (not shown) of semiconductor memory device 100. Control logic circuitry 140 is configured to control the overall operation of semiconductor memory device 100 in response to control signal CTRL. Additionally, control logic circuitry 140 outputs control signals for adjusting the precharge potential levels of sensing nodes in multiple page buffers PB1 to PBm. Control logic circuitry 140 can control read / write circuitry 130 to perform read operations on memory cell array 110. Simultaneously, control logic circuitry 140 can determine the operating voltage of word line WL applied to memory cell array 110 during read and / or verification operations. In one embodiment, control logic circuitry 140 can control peripheral circuitry 105 to apply over-drive voltage or under-drive voltage to the selected word line during read operations. Overdrive voltage is a voltage higher than the read or verification voltage applied to the selected word line, and is used to quickly increase the voltage of the selected word line to the read or verification voltage. Underdrive voltage is a voltage lower than the read or verification voltage applied to the selected word line, and is used to quickly decrease the voltage of the selected word line to the read or verification voltage.

[0037] Furthermore, according to embodiments of this disclosure, when an underdrive voltage or an overdrive voltage is applied to the selected word line, the control logic circuit 140 can control the peripheral circuit 105 to float the unselected word lines located adjacent to the selected word line. By floating the unselected word lines located adjacent to the selected word line, the settling time required to increase or decrease the voltage of the selected word line can be reduced. As a result, the read speed or verification speed of the semiconductor memory device 100 is improved.

[0038] Figure 2 It is shown Figure 1 An isometric diagram of an embodiment of the memory cell array 110.

[0039] Reference Figure 2 The memory cell array 110 includes multiple memory blocks BLK1 to BLKz. Each memory block may have a three-dimensional structure. Each memory block includes multiple memory cells stacked on a substrate. The multiple memory cells are arranged along the +X, +Y, and +Z directions. (Refer to...) Figure 3 Describe the structure of each storage block in more detail.

[0040] Figure 3 It is shown Figure 2The circuit diagram of any one of the memory blocks BLKa from BLK1 to BLKz.

[0041] Reference Figure 3 The storage block BLKa comprises multiple cell strings CS11 to CS1m and CS21 to CS2m. Within the storage block BLKa, m cell strings can be arranged along the row direction (i.e., the +X direction). Figure 3 In this context, two unit strings can be arranged along the column direction (i.e., the +Y direction). However, this is for ease of description, and it can be understood that three or more unit strings can be arranged along the column direction.

[0042] Each of the multiple cell strings CS11 to CS1m and CS21 to CS2m may include at least one source selection transistor SST, a first memory cell MC1 to the nth memory cell MCn, and at least one drain selection transistor DST.

[0043] The selector transistors SST and DST, and each of the memory cells MC1 to MCn, can have similar structures. In one embodiment, each of the selector transistors SST and DST, and each of the memory cells MC1 to MCn, may include a channel layer, a tunneling insulating layer, a charge storage layer, and a barrier insulating layer. In one embodiment, pillars for providing the channel layer may be provided in each cell string. In one embodiment, pillars for providing at least one of the channel layer, tunneling insulating layer, charge storage layer, and barrier insulating layer may be provided in each cell string.

[0044] The source selection transistor SST of each cell string is connected between the common source line CSL and the memory cells MC1 to MCn.

[0045] In one implementation, source-select transistors in cell strings arranged in the same row are connected to source-select lines extending in the row direction, and source-select transistors in cell strings arranged in different rows are connected to different source-select lines. Figure 4 In the first row, the source selection transistors CS11 to CS1m are connected to the first source selection line SSL1. The source selection transistors CS21 to CS2m in the second row are connected to the second source selection line SSL2.

[0046] In another embodiment, the source selection transistors of cell strings CS11 to CS1m and CS21 to CS2m can be connected together to a single source selection line.

[0047] The first memory cell MC1 to the nth memory cell MCn of each cell string are connected between the source selection transistor SST and the drain selection transistor DST.

[0048] The gates of the first memory cell MC1 to the nth memory cell MCn in each cell string are respectively connected to the first word line WL1 to the nth word line WLn.

[0049] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and memory cells MC1 to MCn. The DST of cell strings arranged in the row direction is connected to drain select lines extending in the row direction. The drain select transistors of cell strings CS11 to CS1m in the first row are connected to the first drain select line DSL1. The drain select transistors of cell strings CS21 to CS2m in the second row are connected to the second drain select line DSL2.

[0050] A string of cells arranged in the column direction is connected to a bit line extending in the column direction. Figure 4 In the diagram, the cell strings CS11 and CS21 of the first column are connected to the first bit line BL1. The cell strings CS1m and CS2m of the m-th column are connected to the m-th bit line BLm.

[0051] In a row-oriented cell string, memory cells connected to the same word line constitute a page. For example, memory cells in cell strings CS11 to CS1m in the first row, connected to the first word line WL1, constitute one page. Memory cells in cell strings CS21 to CS2m in the second row, connected to the first word line WL1, constitute another page. A cell string arranged in a row direction can be selected by choosing either drain select lines DSL1 or DSL2. A page of the selected cell string can be selected by choosing any of the word lines WL1 to WLn.

[0052] In another embodiment, even-numbered bit lines and odd-numbered bit lines can be provided instead of the first bit line BL1 to the m-th bit line BLm. Additionally, respectively, even-numbered cell strings from the row-oriented cell strings CS11 to CS1m or CS21 to CS2m can be connected to the even-numbered bit lines, and odd-numbered cell strings from the row-oriented cell strings CS11 to CS1m or CS21 to CS2m can be connected to the odd-numbered bit lines.

[0053] In one implementation, at least one of the first memory cells MC1 to the nth memory cell MCn can be used as a dummy memory cell. For example, at least one or more dummy memory cells are provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCn. Alternatively, at least one or more dummy memory cells are provided to reduce the electric field between the drain selection transistor DST and the memory cells MC1 to MCn. With more dummy memory cells provided, the operational reliability of memory block BLK1 increases; however, the size (i.e., physical size) of memory block BLK1 increases. With fewer dummy memory cells provided, the size (i.e., physical size) of memory block BLK1 can be reduced; however, the operational reliability of memory block BLK1 may also decrease.

[0054] Reference Figure 3 Each of the multiple cell strings CS11 to CS1m and CS21 to C2M can be formed in an "I" shape between bit lines BL1 to BLm and the common source line CSL. However, this is just one example; another type of memory block is also possible. For example, each of the multiple cell strings included in the memory block can be formed in a "U" shape. In this case, each cell string can include a pipe transistor. Additionally, the first group of memory cells included in each cell string can be connected in series between the source select transistor and the pipe transistor. That is, the first group of memory cells and the second group of memory cells can be connected via the pipe transistor. Simultaneously, the second group of memory cells included in each cell string can be connected in series between the pipe transistor and the drain select transistor. The gate of the pipe transistor in each cell string can be connected to a pipe line.

[0055] Figure 4 It is shown that it includes Figure 1 A circuit diagram illustrating an implementation of any one of the storage blocks BLKb among the multiple storage blocks BLK1 to BLKz in the memory cell array 110.

[0056] Reference Figure 4 The memory block BLKb includes multiple cell strings CS1 to CSm. The multiple cell strings CS1 to CSm can be connected to multiple bit lines BL1 to BLm respectively. Each of the cell strings CS1 to CSm includes at least one source selection transistor SST, a first memory cell MC1 to an nth memory cell MCn, and at least one drain selection transistor DST.

[0057] The selector transistors SST and DST, and each of the memory cells MC1 to MCn, can have similar structures. In one embodiment, each of the selector transistors SST and DST, and each of the memory cells MC1 to MCn, may include a channel layer, a tunneling insulating layer, a charge storage layer, and a barrier insulating layer. In one embodiment, pillars for providing the channel layer may be provided in each cell string. In one embodiment, pillars for providing at least one of the channel layer, tunneling insulating layer, charge storage layer, and barrier insulating layer may be provided in each cell string.

[0058] The source selection transistor SST of each cell string is connected between the common source line CSL and the memory cells MC1 to MCn.

[0059] The first memory cell MC1 to the nth memory cell MCn of each cell string are connected between the source selection transistor SST and the drain selection transistor DST.

[0060] The drain selection transistor (DST) of each cell string is connected between the corresponding bit line and memory cells MC1 to MCn.

[0061] Memory cells connected to the same word line constitute a page. Cell strings CS1 to CSm can be selected by choosing the drain select line DSL. A page within the selected cell string can be selected by choosing any of the word lines WL1 to WLn.

[0062] In another embodiment, even-numbered bit lines and odd-numbered bit lines can be used instead of the first bit line BL1 to the m-th bit line BLm. The even-numbered cell strings CS1 to CSm can be connected to the even-numbered bit lines, and the odd-numbered cell strings can be connected to the odd-numbered bit lines, respectively.

[0063] Figure 5 It is a graph showing the threshold voltage distribution of a multi-level unit.

[0064] Reference Figure 5 The threshold voltage of a multilevel cell (MLC) can be included in any of the erase state E, the first programming state PV1, the second programming state PV2, and the third programming state PV3. The semiconductor memory device and its operation method according to this disclosure can be applied not only to MLCs, but also to three-level cell (TLC), four-level cell (QLC), or memory cells storing five or more bits of data. However, for ease of discussion, the following description is based on MLCs.

[0065] During a read operation, a first read voltage R1 can be applied to the selected word line to distinguish between erase state E and first programming state PV1. Additionally, a second read voltage R2 can be applied to the selected word line to distinguish between first programming state PV1 and second programming state PV2. Simultaneously, a third read voltage R3 can be applied to the selected word line to distinguish between second programming state PV2 and third programming state PV3. During a read operation, a read pass voltage Vpass can be applied to the unselected word line.

[0066] Simultaneously, during the verification operation performed during the programming operation, the first verification voltage Vvr1 can be used for the verification operation of the first programming state PV1. Additionally, the second verification voltage Vvr2 can be used for the verification operation of the second programming state PV2. Simultaneously, the third verification voltage Vvr3 can be used for the verification operation of the third programming state PV3. The verification operation of the selected memory cell included in the semiconductor memory device can be performed in a manner similar to that used for reading the selected memory cell. The semiconductor memory device and its operation method according to embodiments of this disclosure can be used for both reading and verification operations of the selected memory cell. However, for ease of discussion, this disclosure is described below based on the reading operation of the selected memory cell. However, this disclosure is not limited thereto and can also be applied to the verification operation of the selected memory cell.

[0067] Figure 6 This is a timing diagram illustrating a method of operating a semiconductor memory device according to an embodiment of the present disclosure.

[0068] Reference Figure 6 A read operation on a selected memory cell can be performed using a method of operating a semiconductor memory device according to embodiments of the present disclosure. The read operation on the selected memory cell may include a channel initialization step, a threshold voltage sensing step for the selected memory cell, and a word line equalization step. Figure 6 In the process, a channel initialization step is performed during time period t1 to t2, a threshold voltage sensing step is performed during time period t2 to t8, and a word line equalization step is performed during time period t8 to t9.

[0069] At time t1, the on-state voltage Von is applied to the selected drain select line and the source select line, and also to the unselected drain select line and the source select line. Simultaneously, the read pass voltage Vpass is applied to the selected word line connected to the memory cell to be read, and also to the unselected word line. With the on-state voltage Von applied to the drain select line and the source select line, the read pass voltage Vpass is applied to all word lines, thus enabling channel initialization.

[0070] At time t2, a cutoff voltage Voff is applied to the unselected drain-select and source-select lines. The cutoff voltage Voff can be a voltage capable of turning off the drain-select and source-select transistors, and in one embodiment, the cutoff voltage Voff can be ground. Figure 3 As shown, when two cell strings are arranged in the column direction (i.e., the +Y direction), the drain select line and source select line connected to the cell string that includes the memory cell to be read become the selected drain select line and source select line, respectively. Simultaneously, the drain select line and source select line connected to the cell string that does not include the memory cell to be read become the unselected drain select line and source select line, respectively. At the same time, the on-state voltage Von continues to be applied to the selected drain select line and source select line.

[0071] At time t2, an underdrive voltage Vun can be applied to the selected word line. The underdrive voltage Vun can be used to rapidly reduce the voltage of the selected word line from the read pass voltage Vpass. Therefore, the underdrive voltage Vun is determined to be lower than the subsequently applied first read voltage R1. Meanwhile, the read pass voltage Vpass continues to be applied to the unselected word line.

[0072] At time t3, a first read voltage R1 is applied to the selected word line. Prior to this, because an underdrive voltage Vun was applied to the selected word line during periods t2 to t3, the voltage of the selected word line can rapidly decrease from the read pass voltage Vpass to the first read voltage R1. During periods t3 to t4, it is determined whether the threshold voltage of the selected memory cell is greater than the first read voltage.

[0073] At time t4, a first overdrive voltage Vov1 is applied to the selected word line. The first overdrive voltage Vov1 can be used to rapidly increase the voltage of the selected word line from the first read voltage R1. Therefore, the first overdrive voltage Vov1 is determined to be higher than the second read voltage R2 subsequently applied.

[0074] At time t5, the second read voltage R2 is applied to the selected word line. Prior to this, because the first overdrive voltage Vov1 was applied to the selected word line during time periods t4 to t5, the voltage of the selected word line can rapidly increase from the first read voltage R1 to the second read voltage R2. During time periods t5 to t6, it is determined whether the threshold voltage of the selected memory cell is greater than the second read voltage.

[0075] At time t6, a second overdrive voltage Vov2 is applied to the selected word line. The second overdrive voltage Vov2 can be used to rapidly increase the voltage of the selected word line from the second read voltage R2. Therefore, the second overdrive voltage Vov2 is determined to be higher than the subsequently applied third read voltage R3.

[0076] At time t7, the third read voltage R3 is applied to the selected word line. Prior to this, because the second overdrive voltage Vov2 was applied to the selected word line during periods t6 to t7, the voltage of the selected word line can rapidly increase from the second read voltage R2 to the third read voltage R3. During periods t7 to t8, it is determined whether the threshold voltage of the selected memory cell is greater than the third read voltage.

[0077] At time t8, a cutoff voltage Voff can be applied to the selected drain select line DSL and the source select line SSL. Simultaneously, at time t8, an equalization voltage Veq is applied to the selected word line and the unselected word line. This performs an equalization operation on the word lines.

[0078] At time t9, the cutoff voltage Voff is applied to the word line. Read operations can end after time t9.

[0079] Reference Figure 6 A first read voltage R1 is applied to the selected word line during periods t3 to t4, a second read voltage R2 is applied during periods t5 to t6, and a third read voltage R3 is applied during periods t7 to t8. That is, the read voltages are applied sequentially from the lowest read voltage R1 to the highest read voltage R3, according to their magnitude. In this case, the difference between the read pass voltage Vpass applied to the selected word line during periods t1 to t2 and the first read voltage R1 applied during periods t3 to t4 is relatively large. Therefore, despite the use of an underdrive voltage Vun, the time for the voltage of the selected word line to stabilize from the read pass voltage Vpass to the first read voltage R1 is still relatively long. This results in a decrease in the read speed of the selected memory cell.

[0080] Figure 7 This is a timing diagram illustrating a method of operating a semiconductor memory device according to another embodiment of the present disclosure. (See also...) Figure 7 , in order to Figure 6 The operation shown is similar to the method used to perform the read operation, except that the read voltage is applied to the selected word line from the highest read voltage R3 to the lowest read voltage R1. Therefore, overlapping descriptions are omitted.

[0081] exist Figure 7 In the process, a channel initialization step is performed during time period t11 to t12, a threshold voltage sensing step is performed during time period t12 to t18, and a word line equalization step is performed during time period t18 to t19.

[0082] At time t11, the on-state voltage Von is applied to the selected drain select line and the source select line, and the on-state voltage Von is also applied to the unselected drain select line and the unselected source select line. Simultaneously, the read pass voltage Vpass is applied to the selected word line connected to the memory cell to be read, and the read pass voltage is also applied to the unselected word line.

[0083] At time t12, a cutoff voltage Voff is applied to the unselected drain select line and the source select line. Additionally, at time t12, a first underdrive voltage Vun1 can be applied to the selected word line. The first underdrive voltage Vun1 can be used to rapidly reduce the voltage of the selected word line from the read pass voltage Vpass. Therefore, the first underdrive voltage Vun1 is determined to be lower than the subsequently applied third read voltage R3.

[0084] At time t13, a third read voltage R3 is applied to the selected word line. Prior to this, because a first underdrive voltage Vun1 was applied to the selected word line during periods t12 to t13, the voltage of the selected word line can rapidly decrease from the read pass voltage Vpass to the third read voltage R3. During periods t13 to t14, it is determined whether the threshold voltage of the selected memory cell is greater than the third read voltage.

[0085] At time t14, a second underdrive voltage Vun2 is applied to the selected word line. The second underdrive voltage Vun2 can be used to rapidly reduce the voltage of the selected word line from the third read voltage R3. Therefore, the second underdrive voltage Vun2 is determined to be lower than the subsequently applied second read voltage R2.

[0086] At time t15, the second read voltage R2 is applied to the selected word line. Prior to this, because the second underdrive voltage Vun2 was applied to the selected word line during periods t14 to t15, the voltage of the selected word line can rapidly decrease from the third read voltage R3 to the second read voltage R2. During periods t15 to t16, it is determined whether the threshold voltage of the selected memory cell is greater than the second read voltage.

[0087] At time t16, a third underdrive voltage Vun3 is applied to the selected word line. The third underdrive voltage Vun3 can be used to rapidly reduce the voltage of the selected word line from the second read voltage R2. Therefore, the third underdrive voltage Vun3 is determined to be lower than the subsequently applied first read voltage R1.

[0088] At time t17, a first read voltage R1 is applied to the selected word line. Prior to this, because a third underdrive voltage Vun3 was applied to the selected word line during periods t16 to t17, the voltage of the selected word line can rapidly decrease from the second read voltage R2 to the first read voltage R1. During periods t17 to t18, it is determined whether the threshold voltage of the selected memory cell is greater than the first read voltage.

[0089] At time t18, a cutoff voltage Voff can be applied to the selected drain select line DSL and the source select line SSL. Simultaneously, at time t18, an equalization voltage Veq is applied to the selected word line and the unselected word line. This performs an equalization operation on the word lines.

[0090] At time t19, the cutoff voltage Voff is applied to the word line. Read operations can end after time t19.

[0091] Reference Figure 7 A third read voltage R3 is applied to the selected word line during periods t13 to t14, a second read voltage R2 is applied to the selected word line during periods t15 to t16, and a first read voltage R1 is applied to the selected word line during periods t17 to t18. That is, the read voltages are applied sequentially from the highest read voltage R3 to the lowest read voltage R1 according to their magnitude. In this case, the difference between the read pass voltage Vpass applied to the selected word line during periods t11 to t12 and the third read voltage R3 applied to the selected word line during periods t13 to t14 is relatively small. Therefore, the voltage of the selected word line stabilizes from the read pass voltage Vpass to the third read voltage R3 in a relatively short time. As a result, the read speed of the selected memory cell is improved.

[0092] Reference Figure 7 During the period t12 to t13 when the first underdrive voltage Vun1 is applied to the selected word line, the read pass voltage Vpass is applied to the unselected word line. In this case, the voltage drop rate of the selected word line is reduced by the capacitance between the selected word line and the adjacent word line. This results in a decrease in the read speed of the semiconductor memory device.

[0093] According to the semiconductor memory device and its operating method according to embodiments of the present disclosure, when an underdrive voltage is applied to the selected word line, the unselected word line adjacent to the selected word line is floated. This increases the voltage drop rate of the selected word line, and consequently, also increases the read speed of the semiconductor memory device.

[0094] Figure 8 This is a timing diagram illustrating a method of operating a semiconductor memory device according to another embodiment of the present disclosure. (See also...) Figure 8Except that when underdrive voltages Vun1, Vun2, and Vun3 are applied to the selected word line, the unselected word line located adjacent to the selected word line is floated, in a manner similar to Figure 7 The method shown is used to execute the operation. Figure 8 The operating method is shown. Therefore, overlapping descriptions have been omitted. Figure 8 In this context, the selected word line is denoted as the i-th word line WLi. The i-th word line WLi is one of the word lines from the first word line WL1 to the nth word line WLn, which is connected to the selected memory cell.

[0095] exist Figure 8 In the process, a channel initialization step is performed during time period t21 to t22, a threshold voltage sensing step is performed during time period t22 to t28, and a word line equalization step is performed during time period t28 to t29.

[0096] At time t21, the on-state voltage Von is applied to the selected drain select line and the source select line, and the on-state voltage Von is also applied to the unselected drain select line and the source select line. Simultaneously, the read pass voltage Vpass is applied to the selected word line connected to the memory cell to be read, and the read pass voltage is also applied to the unselected word line.

[0097] At time t22, a cutoff voltage Voff is applied to the unselected drain select line and source select line. Additionally, at time t22, a first underdrive voltage Vun1 can be applied to the selected word line WLi. At time t22, the unselected word lines WLi-1 and WLi+1, located adjacent to the selected word line WLi, are floated. Simultaneously, at time t22, the read pass voltage Vpass can continue to be applied to the unselected word lines WL1 to WLi-2 and WLi+2 to WLn, which are not adjacent to the selected word line WLi. During the period t22 to t23, because the unselected word lines WLi-1 and WLi+1, located adjacent to the selected word line WLi, are floated, the voltage of the selected word line WLi can decrease more rapidly.

[0098] At time t23, a third read voltage R3 is applied to the selected word line WLi, and a read pass voltage Vpass is applied to the unselected word lines WLi-1 and WLi+1, which are located adjacent to the selected word line. During the period t23 to t24, it is determined whether the threshold voltage of the selected memory cell is greater than the third read voltage.

[0099] In this method, during time periods t24 to t25, the unselected word lines WLi-1 and WLi+1, located adjacent to the selected word line WLi, can be floated. This allows the voltage of the selected word line WLi to rapidly decrease from the third read voltage R3 to the second read voltage R2. Furthermore, during time periods t26 to t27, the unselected word lines WLi-1 and WLi+1, located adjacent to the selected word line WLi, can also be floated. This allows the voltage of the selected word line WLi to rapidly decrease from the second read voltage R2 to the first read voltage R1.

[0100] like Figure 8 As shown, in the semiconductor memory device and its operation method according to an embodiment of the present disclosure, during the periods t22 to t23, t24 to t25, and t26 to t27 when underdrive voltages Vun1, Vun2, and Vun3 are applied to the selected word line WLi, the unselected word lines WLi-1 and WLi+1 adjacent to the selected word line are floated. This increases the voltage drop rate of the selected word line, and consequently, also increases the read speed of the semiconductor memory device.

[0101] at the same time, Figure 8 An embodiment is shown in which only the unselected word lines WLi-1 and WLi+1, located immediately adjacent to the selected word line WLi, are floated; however, this disclosure is not limited thereto. According to one embodiment, p word lines WLi-1 to WLi-p, continuously arranged from the selected word line WLi to the source select line SSL, and q word lines WLi+1 to WLi+q, continuously arranged from the selected word line WLi in the direction of the drain select line DSL, can be floated. Here, p and q can be integers greater than 1.

[0102] Reference Figure 8 The periods t22 to t23 during which the unselected word lines WLi-1 and WLi+1, located adjacent to the selected word line, remain floating, and the periods t22 to t23 during which an underdrive voltage is applied to the selected word line WLi, are shown as the same. However, this is an example, and this disclosure is not limited thereto.

[0103] In one embodiment, the period during which adjacent unselected word lines WLi-1 and WLi+1 remain in a floating state can be longer than the period during which an underdrive voltage is applied to the selected word line WLi. In another embodiment, the period during which an underdrive voltage is applied to the selected word line WLi can be included within the period during which adjacent unselected word lines WLi-1 and WLi+1 remain in a floating state.

[0104] In another embodiment, the period during which adjacent unselected word lines WLi-1 and WLi+1 remain in a floating state can be shorter than the period during which an underdrive voltage is applied to the selected word line WLi. In one embodiment, the period during which adjacent unselected word lines WLi-1 and WLi+1 remain in a floating state can be included within the period during which an underdrive voltage is applied to the selected word line WLi.

[0105] In another embodiment, the period during which adjacent unselected word lines WLi-1 and WLi+1 remain floating may overlap at least partially with the period during which an underdrive voltage is applied to the selected word line WLi. In this case, the underdrive voltage may be applied to the selected word line WLi after the adjacent unselected word lines WLi-1 and WLi+1 have been floating, or the adjacent unselected word lines WLi-1 and WLi+1 may be floating after the underdrive voltage has been applied to the selected word line WLi.

[0106] Figure 9 This is a flowchart illustrating a method of operating a semiconductor memory device according to yet another embodiment of the present disclosure. Referring hereafter... Figure 8 and Figure 9 To describe this disclosure.

[0107] Reference Figure 9 A method for operating a semiconductor memory device according to another embodiment of the present disclosure includes the following steps: applying a read pass voltage to a selected word line and an unselected word line (S110); floating the unselected word line adjacent to the selected word line (S120); applying an underdrive voltage corresponding to a higher read voltage to the selected word line (S130); applying a read pass voltage to the unselected word line adjacent to the selected word line and applying a higher read voltage to the selected word line (S140); floating the unselected word line adjacent to the selected word line (S150); applying an underdrive voltage corresponding to a lower read voltage lower than the higher read voltage to the selected word line (S160); and applying a lower read voltage to the selected word line (S170).

[0108] In step S110, the read pass voltage Vpass can be applied to the selected word lines WLi and the unselected word lines WL1 to WLi-1 and WLi+1 to WLn for channel initialization. That is, step S110 can correspond to... Figure 8 The operations during the period from t21 to t22.

[0109] Subsequently, in step S120, the unselected word lines WLi-1 and WLi+1 adjacent to the selected word line WLi are floated. Additionally, in step S130, an underdrive voltage corresponding to the higher read voltage is applied to the selected word line.

[0110] A higher read voltage can refer to a read voltage that is relatively higher than a lower read voltage. Figure 8 This disclosure is described based on a first read voltage R1 to a third read voltage R3 for read operations on an MLC, but the disclosure is not limited thereto. That is, according to this disclosure, a read voltage can be applied to the selected word line to perform a channel initialization operation, a relatively higher higher read voltage can be applied to the selected word line, and then a relatively lower lower read voltage can be applied to the selected word line.

[0111] Reference Figure 8 For example, in one implementation, the higher read voltage can be a third read voltage R3. In this case, the underdrive voltage corresponding to the higher read voltage can be a first underdrive voltage Vun1. Alternatively, the lower read voltage can be a second read voltage R2 or a first read voltage R1. When the lower read voltage is the second read voltage R2, the underdrive voltage corresponding to the lower read voltage can be a second underdrive voltage Vun2. Meanwhile, when the lower read voltage is the first read voltage R1, the underdrive voltage corresponding to the lower read voltage can be a third underdrive voltage Vun3.

[0112] In another embodiment, the higher read voltage can be a second read voltage R2. In this case, the underdrive voltage corresponding to the higher read voltage can be a second underdrive voltage Vun2. Alternatively, the lower read voltage can be a first read voltage R1, and the underdrive voltage corresponding to the lower read voltage can be a third underdrive voltage Vun3.

[0113] In the following description, the case where the higher read voltage is the third read voltage R3 and the lower read voltage is the second read voltage R2 is used as an example to illustrate this disclosure. In step S130, a first underdrive voltage Vun1 corresponding to the higher read voltage (i.e., the third read voltage R3) is applied to the selected word line WLi. That is, steps S120 and S130 can be performed during time period t22 to t23. Figure 9 In this case, step S120 is executed after step S130, but this disclosure is not limited thereto. That is, step S120 can be executed after step S130, or steps S120 and S130 can be executed simultaneously.

[0114] Subsequently, in step S140, a read voltage Vpass is applied to the unselected word lines WLi-1 and WLi+1 adjacent to the selected word line WLi, and a higher read voltage (i.e., the third read voltage R3) is applied to the selected word line WLi. Step S140 corresponds to... Figure 8 The operations performed during the period from t23 to t24.

[0115] Subsequently, in step S150, the unselected word lines WLi-1 and WLi+1 adjacent to the selected word line WLi are floated. Additionally, in step S160, a second underdrive voltage Vun2 corresponding to the lower read voltage (i.e., the second read voltage R2) is applied to the selected word line. That is, steps S150 and S160 can be performed during time period t24 to t25.

[0116] Subsequently, in step S170, a read voltage Vpass is applied to the unselected word lines WLi-1 and WLi+1 adjacent to the selected word line WLi, and a lower read voltage (i.e., the second read voltage R2) is applied to the selected word line WLi. Step S170 corresponds to... Figure 8 The operations performed during the period from t25 to t26.

[0117] Figure 10 This is a flowchart illustrating a method of operating a semiconductor memory device according to yet another embodiment of the present disclosure. Figure 10 In the context of Figure 9 A flowchart of a method for operating a semiconductor memory device according to yet another embodiment of the present disclosure is shown in different aspects of the method.

[0118] Reference Figure 10 A method for operating a semiconductor memory device according to another embodiment of the present disclosure includes the following steps: applying a read pass voltage to a selected word line and an unselected word line (S200); floating the unselected word line adjacent to the selected word line (S210); applying an underdrive voltage corresponding to a third read voltage from a first read voltage to a third read voltage to the selected word line (S220); applying a read pass voltage to the unselected word line adjacent to the selected word line, and applying the third read voltage to the selected word line (S230); floating the unselected word line adjacent to the selected word line... The line is floated (S240); an underdrive voltage corresponding to the second read voltage is applied to the selected word line (S250); a read pass voltage is applied to the unselected word line adjacent to the selected word line, and the second read voltage is applied to the selected word line (S260); the unselected word line adjacent to the selected word line is floated (S270); an underdrive voltage corresponding to the first read voltage is applied to the selected word line (S280); and a read pass voltage is applied to the unselected word line adjacent to the selected word line, and the first read voltage is applied to the selected word line (S290).

[0119] In step S200, a read voltage Vpass can be applied to the selected word lines WLi and the unselected word lines WL1 to WLi-1 and WLi+1 to WLn for channel initialization. That is, step S200 can correspond to... Figure 8 The operations during the period from t21 to t22.

[0120] Subsequently, in step S210, the unselected word lines WLi-1 and WLi+1 adjacent to the selected word line WLi are floated. Additionally, in step S220, an underdrive voltage Vun1 corresponding to the third read voltage R3 is applied to the selected word line WLi. That is, steps S210 and S220 can be performed during time periods t22 to t23. Figure 10 In this case, step S220 is executed after step S210, but this disclosure is not limited thereto. That is, step S210 can be executed after step S220, or steps S210 and S220 can be executed simultaneously.

[0121] Subsequently, in step S230, a read voltage Vpass is applied to the unselected word lines WLi-1 and WLi+1 adjacent to the selected word line WLi, and a third read voltage R3 is applied. Step S230 corresponds to... Figure 8 The operations performed during the period from t23 to t24.

[0122] Subsequently, in step S240, the unselected word lines WLi-1 and WLi+1 adjacent to the selected word line WLi are floated. Additionally, in step S250, a second underdrive voltage Vun2 corresponding to the second read voltage R2 is applied to the selected word line. That is, steps S240 and S250 can be performed during time periods t24 to t25.

[0123] Subsequently, in step S260, a read voltage Vpass is applied to the unselected word lines WLi-1 and WLi+1 adjacent to the selected word line WLi, and a second read voltage R2 is applied to the selected word line WLi. Step S260 corresponds to... Figure 8 The operations performed during the period from t25 to t26.

[0124] Subsequently, in step S270, the unselected word lines WLi-1 and WLi+1 adjacent to the selected word line WLi are floated. Additionally, in step S280, a third underdrive voltage Vun3 corresponding to the first read voltage R1 is applied to the selected word line. That is, steps S270 and S280 can be performed during time period t26 to t27.

[0125] Subsequently, in step S290, a read voltage Vpass is applied to the unselected word lines WLi-1 and WLi+1 adjacent to the selected word line WLi, and a first read voltage R1 is applied to the selected word line WLi. Step S290 corresponds to... Figure 8 The operations performed during the period from t27 to t28.

[0126] According to reference Figures 8 to 10In the embodiments of this disclosure described, during the periods t22 to t23, t24 to t25, and t26 to t27 when underdrive voltages Vun1, Vun2, and Vun3 are applied to the selected word line WLi, the unselected word lines WLi-1 and WLi+1 adjacent to the selected word line are floated. This increases the voltage drop rate of the selected word line, and consequently, also increases the read speed of the semiconductor memory device.

[0127] However, when the unselected word lines WLi-1 and WLi+1 adjacent to the selected word line are floated and underdrive voltages Vun1, Vun2, and Vun3 are applied to the selected word line WLi, the voltages of the unselected word lines WLi-1 and WLi+1 become lower than the read pass voltage Vpass during periods t22 to t23, t24 to t25, and t26 to t27. This can affect the cell current when sensing the threshold voltage of the memory cell during subsequent periods t23 to t24, t25 to t26, and t27 to t28, and become a factor that reduces read accuracy.

[0128] According to another embodiment of this disclosure, a higher read pass voltage than that applied to other unselected word lines is applied to the unselected word lines WLi-1 and WLi+1 adjacent to the selected word line. Therefore, even when underdrive voltages Vun1, Vun2, and Vun3 are applied to the selected word line WLi, the unselected word lines WLi-1 and WLi+1 adjacent to the selected word line are floated, and the voltages of the unselected word lines WLi-1 and WLi+1 adjacent to the selected word line are reduced, which can reduce or minimize the impact on the cell current when sensing the threshold voltage of the memory cell. As a result, read accuracy can be improved. In the following, reference is made to... Figure 11 and Figure 12 To describe this disclosure.

[0129] Figure 11 This is a timing diagram illustrating a method of operating a semiconductor memory device according to yet another embodiment of the present disclosure. (Refer to...) Figure 11 Except that the first read pass voltage Vpass1 is applied to the unselected word lines WL1 to WLi-2 and WLi+2 to WLn that are not adjacent to the selected word line WLi, and the second read pass voltage Vpass2 is applied to the unselected word lines WLi-1 and WLi+1 that are adjacent to the selected word line WLi, in a manner similar to Figure 8 The method shown is used to execute the operation. Figure 11 The operating method is shown. Therefore, overlapping descriptions have been omitted.

[0130] At time t31, a first read pass voltage Vpass1 is applied to the unselected word lines WL1 to WLi-2 and WLi+2 to WLn, which are not adjacent to the selected word line WLi, and a second read pass voltage Vpass2 is applied to the unselected word lines WLi-1 and WLi+1, which are adjacent to the selected word line WLi. The first read pass voltage Vpass1 can be... Figure 5 The read pass voltage Vpass shown is essentially the same. The second read pass voltage Vpass2 can be higher than the first read pass voltage Vpass1. Subsequently, during time period t32 to t33, when the unselected word lines WLi-1 and WLi+1 adjacent to the selected word line WLi are floated and the first underdrive voltage Vun1 is applied to the selected word line WLi, the voltages of the unselected word lines WLi-1 and WLi+1 adjacent to the selected word line WLi can be reduced from the second read pass voltage Vpass2. However, because the second read pass voltage Vpass2 is higher than the first read pass voltage Vpass1, even if the voltages of the unselected word lines WLi-1 and WLi+1 adjacent to the selected word line WLi are reduced, the impact on the cell current when sensing the threshold voltage of the memory cell can be reduced or minimized. As a result, read accuracy can be improved.

[0131] Subsequently, during time periods t33 to t34, t35 to t36, and t37 to t38, the second read pass voltage Vpass2 can be applied to the unselected word lines WLi-1 and WLi+1 adjacent to the selected word line WLi.

[0132] Figure 12 This is a flowchart illustrating a method of operating a semiconductor memory device according to yet another embodiment of the present disclosure.

[0133] Reference Figure 12 A method for operating a semiconductor memory device according to another embodiment of the present disclosure includes the following steps: applying a first read pass voltage to a selected word line and an unselected word line not adjacent to the selected word line, and applying a second read pass voltage greater than the first read pass voltage to the unselected word line adjacent to the selected word line (S310); floating the unselected word line adjacent to the selected word line (S320); applying an underdrive voltage corresponding to a higher read voltage to the selected word line (S330); applying a second read pass voltage to the unselected word line adjacent to the selected word line, and applying a higher read voltage to the selected word line (S340); floating the unselected word line adjacent to the selected word line (S350); applying an underdrive voltage corresponding to a lower read voltage lower than the higher read voltage to the selected word line (S360); and applying a second read pass voltage to the unselected word line adjacent to the selected word line, and applying a lower read voltage to the selected word line (S370). Figure 12The method of operating the semiconductor memory device shown is similar to Figure 9 The method shown differs in that a first read pass voltage is applied to an unselected word line that is not adjacent to the selected word line, and a second read pass voltage greater than the first read pass voltage is applied to the unselected word line that is adjacent to the selected word line. Therefore, overlapping descriptions are omitted.

[0134] In step S310, a first read pass voltage Vpass1 can be applied to the selected word line WLi for channel initialization, and the first read pass voltage Vpass1 can also be applied to the unselected word lines WL1 to WLi-2 and WLi+2 to WLn that are not adjacent to the selected word line WLi. Additionally, in step S310, a second read pass voltage Vpass2 can be applied to the unselected word lines WLi-1 and WLi+1 that are adjacent to the selected word line WLi. That is, step S310 can correspond to... Figure 11 The operations during the period from t31 to t32.

[0135] Subsequently, in step S320, the unselected word lines WLi-1 and WLi+1 adjacent to the selected word line WLi are floated. Additionally, in step S330, an underdrive voltage corresponding to the higher read voltage is applied to the selected word line. (See reference...) Figure 9 The present disclosure is described using the case where the higher read voltage is the third read voltage R3 and the lower read voltage is the second read voltage R2 as an example. In step S330, a first underdrive voltage Vun1 corresponding to the higher read voltage (i.e., the third read voltage R3) is applied to the selected word line WLi. That is, steps S320 and S330 can be performed during time period t32 to t33.

[0136] Subsequently, in step S340, a second read pass voltage Vpass2 is applied to the unselected word lines WLi-1 and WLi+1 adjacent to the selected word line WLi, and a higher read voltage (i.e., a third read voltage R3) is applied to the selected word line WLi. Step S340 corresponds to... Figure 11 The operations performed during the period from t33 to t34.

[0137] Subsequently, in step S350, the unselected word lines WLi-1 and WLi+1 adjacent to the selected word line WLi are floated. Additionally, in step S360, a second underdrive voltage Vun2 corresponding to the lower read voltage (i.e., the second read voltage R2) is applied to the selected word line. That is, steps S350 and S360 can be performed during time period t34 to t35.

[0138] Subsequently, in step S370, a second read pass voltage Vpass2 is applied to the unselected word lines WLi-1 and WLi+1 adjacent to the selected word line WLi, and a lower read voltage (i.e., the second read voltage R2) is applied to the selected word line WLi. Step S370 corresponds to... Figure 11 The operations performed during the period from t35 to t36.

[0139] According to reference Figure 11 and Figure 12 In the described implementation, a first read pass voltage Vpass1 is applied to the unselected word lines WL1 to WLi-2 and WLi+2 to WLn, which are not adjacent to the selected word line WLi, and a second read pass voltage Vpass2, which is higher than the first read pass voltage, is applied to the unselected word lines WLi-1 and WLi+1, which are adjacent to the selected word line WLi. Therefore, even if the voltage of the unselected word lines WLi-1 and WLi+1 adjacent to the selected word line WLi is reduced because the unselected word lines WLi-1 and WLi+1 are floated and underdrive voltages Vun1, Vun2, and Vun3 are applied to the selected word line WLi, the impact on the cell current when sensing the threshold voltage of the memory cell can be reduced or minimized. As a result, read accuracy can be improved.

[0140] According to reference Figure 11 and Figure 12 In the described implementation, a fixed second read pass voltage Vpass2 is applied to the adjacent unselected word lines WLi-1 and WLi+1, regardless of the voltage drop width of the selected word line WLi. In this case, it is not easy to control the voltages of the adjacent unselected word lines WLi-1 and WLi+1 when sensing the threshold voltage of the selected memory cell.

[0141] According to another embodiment of this disclosure, the read pass voltage applied to adjacent unselected word lines WLi-1 and WLi+1 is determined based on the voltage drop width of the selected word line WLi. Therefore, the stability of the read operation is improved. Hereinafter, reference is made to... Figure 13 and Figure 14 To describe this disclosure.

[0142] Figure 13 This is a timing diagram illustrating a method of operating a semiconductor memory device according to yet another embodiment of the present disclosure.

[0143] Reference Figure 13 In addition to the second read pass voltage Vpass2, the third read pass voltage Vpass3, the fourth read pass voltage Vpass4, and the fifth read pass voltage Vpass5 being applied to the unselected word lines WLi-1 and WLi+1 adjacent to the selected word line WLi, Figure 11The operation method shown is to perform Figure 13 The operating method is shown. Therefore, overlapping descriptions have been omitted.

[0144] At time t41, a first read pass voltage Vpass1 is applied to the unselected word lines WL1 to WLi-2 and WLi+2 to WLn, which are not adjacent to the selected word line WLi, and a second read pass voltage Vpass2 is applied to the unselected word lines WLi-1 and WLi+1, which are adjacent to the selected word line WLi. The first read pass voltage Vpass1 can be... Figure 5 The read pass voltages Vpass shown are essentially the same. The second read pass voltage Vpass2 can be higher than the first read pass voltage Vpass1. Additionally, the second read pass voltage can be determined based on the voltage drop width of the selected word line WLi during time period t42 to t43.

[0145] Specifically, when the voltage drop width of the selected word line WLi is large during time period t42 to t43, the voltage drop width of the floating unselected word lines WLi-1 and WLi+1 may also be large. Therefore, in this case, a relatively higher voltage can be determined as the second read pass voltage Vpass2. Conversely, when the voltage drop width of the selected word line WLi is small during time period t42 to t43, the voltage drop width of the floating unselected word lines WLi-1 and WLi+1 may also be small. Therefore, in this case, a relatively lower voltage can be determined as the second read pass voltage Vpass2.

[0146] For example, the second read voltage can be determined based on Equation 1 below.

[0147] [Formula 1]

[0148] Vpass2=Vpass1+k1(Vpass1-Vun1)

[0149] In Equation 1 above, k1 is a positive number. Therefore, the second read pass voltage Vpass2 can be a voltage greater than the first read pass voltage Vpass1, and can be a voltage determined based on the difference between the first read pass voltage Vpass1 and the first underdrive voltage Vun1.

[0150] Simultaneously, at time t43, a third read pass voltage Vpass3 is applied to the unselected word lines WLi-1 and WLi+1 adjacent to the selected word line WLi. The third read pass voltage Vpass3 can be higher than the first read pass voltage Vpass1. Furthermore, the third read pass voltage can be determined based on the voltage drop width of the selected word line WLi during time periods t44 to t45. For example, the third read pass voltage can be determined based on Equation 2 below.

[0151] [Equation 2]

[0152] Vpass3 = Vpass1 + k2(R3 - Vun2)

[0153] In Equation 2 above, k2 is a positive number. Therefore, the third read pass voltage Vpass3 can be a voltage greater than the first read pass voltage Vpass1, and can be a voltage determined based on the difference between the third read voltage R3 and the second underdrive voltage Vun2.

[0154] Additionally, at time t45, a fourth read pass voltage Vpass4 is applied to the unselected word lines WLi-1 and WLi+1 adjacent to the selected word line WLi. The fourth read pass voltage Vpass4 can be higher than the first read pass voltage Vpass1. Furthermore, the fourth read pass voltage can be determined based on the voltage drop width of the selected word line WLi during time periods t46 to t47. For example, the fourth read pass voltage can be determined based on Equation 3 below.

[0155] [Formula 3]

[0156] Vpass4 = Vpass1 + k3(R2 - Vun3)

[0157] In Equation 3 above, k3 is a positive number. Therefore, the fourth read pass voltage Vpass4 can be a voltage greater than the first read pass voltage Vpass1, and can be a voltage determined based on the difference between the second read voltage R2 and the third underdrive voltage Vun3.

[0158] Figure 14 This is a flowchart illustrating a method of operating a semiconductor memory device according to yet another embodiment of the present disclosure.

[0159] Reference Figure 14 A method for operating a semiconductor memory device according to another embodiment of the present disclosure includes the following steps: applying a first read pass voltage to a selected word line and an unselected word line not adjacent to the selected word line, and applying a second read pass voltage greater than the first read pass voltage to the unselected word line adjacent to the selected word line (S410); floating the unselected word line adjacent to the selected word line (S420); applying an underdrive voltage corresponding to a higher read voltage to the selected word line (S430); applying a third read pass voltage to the unselected word line adjacent to the selected word line, and applying a higher read voltage to the selected word line (S440); floating the unselected word line adjacent to the selected word line (S450); applying an underdrive voltage corresponding to a lower read voltage lower than the higher read voltage to the selected word line (S460); and applying a fourth read pass voltage to the unselected word line adjacent to the selected word line, and applying a lower read voltage to the selected word line (S470). Figure 14The method of operating the semiconductor memory device shown is similar to Figure 12 The method shown differs in that a second, third, or fourth read pass voltage is applied to an unselected word line adjacent to the selected word line. Therefore, overlapping descriptions are omitted. See also... Figure 9 and Figure 12 The present disclosure is described using the case in which the higher read voltage is the third read voltage R3 and the lower read voltage is the second read voltage R2 as an example.

[0160] In step S410, a first read pass voltage Vpass1 can be applied to the selected word line WLi for channel initialization, and the first read pass voltage Vpass1 can also be applied to the unselected word lines WL1 to WLi-2 and WLi+2 to WLn that are not adjacent to the selected word line WLi. Additionally, in step S410, a second read pass voltage Vpass2 can be applied to the unselected word lines WLi-1 and WLi+1 that are adjacent to the selected word line WLi.

[0161] As described above, the second read-through voltage can be determined based on the difference between the first read-through voltage and the underdrive voltage corresponding to the higher read voltage. Specifically, the second read-through voltage can be determined based on the difference between the first read-through voltage and the first underdrive voltage. That is, the second read-through voltage can be determined based on Equation 1 above.

[0162] Subsequently, in step S420, the unselected word lines WLi-1 and WLi+1 adjacent to the selected word line WLi are floated. Additionally, in step S430, an underdrive voltage corresponding to the higher read voltage is applied to the selected word line. In step S430, a first underdrive voltage Vun1 corresponding to the higher read voltage (i.e., the third read voltage R3) is applied to the selected word line WLi.

[0163] Subsequently, in step S440, a third read pass voltage Vpass3 is applied to the unselected word lines WLi-1 and WLi+1 adjacent to the selected word line WLi, and a higher read voltage (i.e., the third read voltage R3) is applied to the selected word line WLi. The third read pass voltage can be determined based on the difference between the higher read voltage and the underdrive voltage corresponding to the lower read voltage. More specifically, the third read pass voltage Vpass3 can be determined based on the difference between the third read voltage R3 and the second underdrive voltage Vun2. That is, the third read pass voltage can be determined based on Equation 2 above.

[0164] Subsequently, in step S450, the unselected word lines WLi-1 and WLi+1 adjacent to the selected word line WLi are floated. Additionally, in step S460, a second underdrive voltage Vun2 corresponding to the lower read voltage (i.e., the second read voltage R2) is applied to the selected word line.

[0165] Subsequently, in step S470, a fourth read pass voltage Vpass2 is applied to the unselected word lines WLi-1 and WLi+1 adjacent to the selected word line WLi, and a lower read voltage (i.e., the second read voltage R2) is applied to the selected word line WLi.

[0166] According to reference Figure 13 and Figure 14 The described implementation determines the read pass voltage applied to the adjacent unselected word lines WLi-1 and WLi+1 based on the voltage drop width of the selected word line WLi. This improves the stability of the read operation.

[0167] Reference Figures 6 to 14 This disclosure describes embodiments of a read operation applied to a selected memory cell. However, this disclosure is not limited thereto and can also be applied to a verification operation of the selected memory cell.

[0168] Figure 15 This is a block diagram illustrating an application example of a storage device 2000 including a semiconductor memory device according to an embodiment of the present disclosure.

[0169] Reference Figure 15 The storage device 2000 includes a semiconductor memory device 2100 and a controller 2200. The semiconductor memory device 2100 includes a plurality of semiconductor memory chips. The plurality of semiconductor memory chips are divided into a plurality of groups.

[0170] exist Figure 15 In this process, multiple groups communicate with the controller 2200 via channels CH1 to CHk, respectively. Each semiconductor memory chip communicates with a reference... Figure 1 One of the described semiconductor memory devices 100 is similarly configured and operated.

[0171] Each group is configured to communicate with controller 2200 via a common channel. Controller 2200 is configured to control multiple memory chips of semiconductor memory device 2100 via multiple channels CH1 to CHk.

[0172] exist Figure 15 In this configuration, multiple semiconductor memory chips are connected to a single channel. However, it should be understood that the memory device 2000 can be modified so that only one semiconductor memory chip is connected to a single channel.

[0173] Figure 16 It shows that it includes references Figure 15 Block diagram of a computing system 3000 with a described storage device.

[0174] Reference Figure 16 The computing system 3000 includes a central processing unit 3100, random access memory (RAM) 3200, user interface 3300, power supply 3400, system bus 3500 and storage device 2000.

[0175] Storage device 2000 is electrically connected to central processing unit 3100, RAM 3200, user interface 3300 and power supply 3400 via system bus 3500. Data provided through user interface 3300 or processed by central processing unit 3100 is stored in storage device 2000.

[0176] exist Figure 16 In this configuration, the semiconductor memory device 2100 is connected to the system bus 3500 via the controller 2200. However, the semiconductor memory device 2100 can also be configured to be directly connected to the system bus 3500. In this case, the functions of the controller 2200 are performed by the central processing unit 3100 and the RAM 3200.

[0177] Cross-references to related applications

[0178] This application claims priority to Korean Patent Application No. 10-2022-0068155, filed with the Korean Intellectual Property Office on June 3, 2022, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: A memory cell array, wherein the memory cell array comprises a plurality of memory cells; Peripheral circuitry, wherein the peripheral circuitry performs at least one of a read operation and a verification operation on a selected memory cell among the plurality of memory cells; as well as A control logic circuit that controls at least one of the read operation and the verification operation of the peripheral circuit. The control logic circuit controls the peripheral circuit to apply a first voltage to the selected word line connected to the selected memory cell, causing the unselected word lines adjacent to the selected word line to float. During at least a portion of the time that the unselected word lines adjacent to the selected word line are floated, a first underdrive voltage lower than the first voltage is applied to the selected word line, and a second voltage higher than the first underdrive voltage but lower than the first voltage is applied to the selected word line.

2. The semiconductor memory device according to claim 1, wherein, The first voltage is the voltage that is read through, and The second voltage is the first read voltage used for the read operation.

3. The semiconductor memory device according to claim 2, wherein, The control logic circuit controls the peripheral circuit to apply the read pass voltage to the unselected word line when the first voltage is applied to the selected word line.

4. The semiconductor memory device according to claim 2, wherein, The control logic circuit controls the peripheral circuit to apply the read pass voltage to the unselected word line that is not adjacent to the selected word line when the unselected word line adjacent to the selected word line is floated.

5. The semiconductor memory device according to claim 2, wherein, The control logic circuit controls the peripheral circuit to apply the read pass voltage to the unselected word line when a second voltage, which is higher than the first underdrive voltage and lower than the first voltage, is applied to the selected word line.

6. The semiconductor memory device according to claim 2, wherein, After the first read voltage is applied to the selected word line, the control logic circuit controls the peripheral circuit to float the unselected word line adjacent to the selected word line. When the unselected word line adjacent to the selected word line is floated, a second underdrive voltage lower than the first read voltage is applied to the selected word line, and a second read voltage higher than the second underdrive voltage and lower than the first read voltage is applied to the selected word line.

7. A method of operating a semiconductor memory device, the method being used to perform at least one of a read operation and a verification operation on a plurality of memory cells, the method comprising the following steps: A first voltage is applied to the selected word line connected to the selected memory cell among the plurality of memory cells, and a read pass voltage is applied to the unselected word lines other than the selected word lines; Make the unselected character lines that are adjacent to the selected character lines float. as well as During at least a portion of the time period during which the unselected word line adjacent to the selected word line is floated, a first underdrive voltage lower than the first voltage is applied to the selected word line.

8. The method according to claim 7, wherein, The first voltage is the read-through voltage.

9. The method of claim 8, further comprising the step of applying the first underdrive voltage to the selected word line after applying the first underdrive voltage to the selected word line: The read is performed by applying a voltage to the unselected word line adjacent to the selected word line; as well as A first read voltage, higher than the first underdrive voltage and lower than the read pass voltage, is applied to the selected word line.

10. The method of claim 9, further comprising the step of, after applying the read voltage to the unselected word line adjacent to the selected word line and applying the first read voltage to the selected word line: Make the unselected character line adjacent to the selected character line float; as well as A second underdrive voltage lower than the first read voltage is applied to the selected word line.

11. The method according to claim 7, wherein, The first voltage is the first read voltage used for the read operation.

12. The method of claim 11, further comprising the step of applying the first underdrive voltage to the selected word line after applying the first underdrive voltage to the selected word line: The read is performed by applying a voltage to the unselected word line adjacent to the selected word line; as well as A second read voltage, higher than the first underdrive voltage and lower than the first read voltage, is applied to the selected word line.

13. A method of operating a semiconductor memory device, the method comprising performing at least one of a read operation and a verification operation on a plurality of memory cells, the method comprising the steps of: A first voltage is applied to the selected word line, a first read pass voltage is applied to the unselected word line that is not adjacent to the selected word line, and a second read pass voltage greater than the first read pass voltage is applied to the unselected word line that is adjacent to the selected word line. Make the unselected character lines adjacent to the selected character lines float; as well as During at least a portion of the time period during which the unselected word line adjacent to the selected word line is floated, a first underdrive voltage lower than the first voltage is applied to the selected word line.

14. The method according to claim 13, wherein, The first voltage is the first read-through voltage.

15. The method of claim 14, further comprising the step of applying the first underdrive voltage to the selected word line after applying the first underdrive voltage to the selected word line: The third read is applied by voltage to the unselected word line adjacent to the selected word line; as well as A first read voltage, higher than the first underdrive voltage and lower than the first read pass voltage, is applied to the selected word line.

16. The method according to claim 15, wherein, The second read pass voltage is determined based on the difference between the first read pass voltage and the first underdrive voltage.

17. The method according to claim 16, wherein, The second reading is determined by the voltage as follows: Vpass2=Vpass1+k1(Vpass1-Vun1), Wherein, Vpass1 is the first read pass voltage, Vpass2 is the second read pass voltage, Vun1 is the first underdrive voltage, and k1 is a positive number.

18. The method of claim 15, further comprising the step of, after applying the third read voltage to the unselected word line adjacent to the selected word line and applying the first read voltage to the selected word line: Make the unselected character line adjacent to the selected character line float; as well as A second underdrive voltage lower than the first read voltage is applied to the selected word line.

19. The method according to claim 18, wherein, The third read pass voltage is determined based on the difference between the first read voltage and the second underdrive voltage.

20. The method according to claim 19, wherein, The third reading is determined by the voltage using the following formula: Vpass3=Vpass1+k2(R3-Vun2), Wherein, Vpass1 is the first read pass voltage, Vpass3 is the third read pass voltage, R3 is the first read voltage, Vun2 is the second underdrive voltage, and k2 is a positive number.

21. The method of claim 18, further comprising the step of applying the second underdrive voltage to the selected word line after applying the second underdrive voltage to the selected word line: The fourth read voltage is applied to the unselected word line adjacent to the selected word line; as well as A second read voltage lower than the first read voltage is applied to the selected word line.

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