Sigma-delta modulator circuit

Abstract

Embodiments of the present disclosure provide a Sigma-delta modulator circuit. The modulator circuit comprises an integration module, an adder module, a comparator, a feedback digital-to-analog conversion module; the integration module integrates the difference between an input signal and the output of the feedback digital-to-analog conversion module to obtain an integrator output result, the adder module performs summation operation on the input signal and the integration output result, the output of the adder module is connected to the comparator, the output of the comparator is fed back to the integration module through the feedback digital-to-analog conversion module, and the output of the comparator is an output signal; the modulator circuit is controlled by three clock signals, i.e. a first clock signal, a second clock signal and a third clock signal, the first clock signal and the second clock signal are two-phase non-overlapping clock signals, and the third clock signal arrives earlier than the second clock signal; under the control of the three clock signals, the Sigma-delta modulator circuit with high common-mode input capability and low input offset voltage is realized.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of integrated circuit technology, and more specifically, to Sigma-delta modulator circuits. Background Technology

[0002] Currently, conventional Sigma-delta modulators operate under low supply voltage conditions (typically less than 5.5V). However, in some practical applications, the input common-mode voltage can be very high, reaching tens of V. Directly using a conventional low-voltage Sigma-delta modulator for analog-to-digital conversion would damage the modulator. For applications with high input common-mode voltage, a common approach is to insert a buffer between the input signal and the modulator. This buffer withstands very high common-mode input voltages, and its output is a low voltage, which is then sent to the ADC for conversion. The drawback of this structure is the need for a dedicated buffer to handle high common-mode input voltages, increasing power consumption and circuit complexity. Summary of the Invention

[0003] The embodiments described herein provide a Sigma-delta modulator circuit.

[0004] According to a first aspect of this disclosure, a Sigma-delta modulator circuit is provided, the modulator circuit comprising: an integrator module, an adder module, a comparator, and a feedback digital-to-analog converter module; wherein, the integrator module integrates the difference between the input signal and the output of the feedback digital-to-analog converter module to obtain an integrator output result; the adder module sums the input signal with the integrated output result; the output of the adder module is connected to the comparator; the output of the comparator is fed back to the integrator module through the feedback digital-to-analog converter module; the output of the comparator is an output signal; the input signal is a high common-mode input signal; the sampling capacitor in the first-stage integrator unit of the integrator module is a high-voltage capacitor; the feedback capacitor in the feedback digital-to-analog converter module is a high-voltage capacitor; and the adder module is connected to the integrator module through the high-voltage capacitor. The input signal is received; the modulator circuit is controlled by three clock signals: a first clock signal, a second clock signal, and a third clock signal. The three clock signals have the same period. The first clock signal and the second clock signal are two non-overlapping clock signals. The third clock signal arrives before the second clock signal. When the first clock signal is high, the integrator module and the adder module sample the signal and store the offset voltage of the transconductance operational amplifier of the first-stage integrator unit. When the third clock signal is high, the adder module performs a summation operation, the comparator performs a comparison operation, and the result of the comparison operation is latched. When the second clock signal is high, the integrator module performs an integration operation to eliminate the offset voltage and feeds back the output of the comparator to the integrator module for subtraction.

[0005] In some embodiments of this disclosure, if the modulator circuit is a one-bit quantization, second-order full feedforward structure, the integration module includes a first-stage integration unit and a second-stage integration unit, the first-stage integration unit and the second-stage integration unit are connected in series, the first-stage integration unit performs an integration operation on the input signal, and the second-stage integration unit performs an integration operation on the output result of the first-stage integration unit.

[0006] In some embodiments of this disclosure, the input signal includes a first input signal and a second input signal. The first-stage integration unit includes four first switches, four second switches, two first sampling capacitors, a first transconductance operational amplifier, and two first integration capacitors. The two ends of the first first switch are respectively connected to the first input signal and one end of the first first sampling capacitor. The two ends of the second first switch are respectively connected to the second input signal and one end of the second first sampling capacitor. The third and fourth first switches are respectively connected in parallel across the first transconductance operational amplifier. The two ends of the first second switch are respectively connected to the second input signal and one end of the first first sampling capacitor. The two ends of the second second switch are respectively connected to the first input signal and one end of the second first sampling capacitor. The third second switch is connected in series with the first first integration capacitor and then in parallel with the first transconductance operational amplifier. The fourth second switch is connected in series with the second first integration capacitor and then in parallel with the first transconductance operational amplifier. The other ends of the two first sampling capacitors are respectively connected to the first transconductance operational amplifier. The control signal for the first switch is the first clock signal, and the control signal for the second switch is the second clock signal.

[0007] In some embodiments of this disclosure, the second-stage integration unit includes four first switches, four second switches, two second sampling capacitors, a second transconductance operational amplifier, and two second integration capacitors. One end of the first second switch is grounded, and the other end of the first second switch is connected to one end of the first first switch and one end of the first second sampling capacitor. One end of the second second switch is grounded, and the other end of the second second switch is connected to one end of the second first switch and one end of the second second sampling capacitor. The other end of the first first switch is connected to the output terminal of the first-stage integration unit. The other end of the second first switch is also connected to the output terminal of the first-stage integration unit. One end of the third first switch is grounded, and the other end of the third first switch is connected to the other end of the first second sampling capacitor and one end of the third second switch. One end of the fourth first switch is grounded, and the other end of the fourth first switch is connected to the other end of the second second sampling capacitor and one end of the fourth second switch. The other ends of the third and fourth second switches are connected to the second transconductance operational amplifier. The two second integration capacitors are connected in parallel across the second transconductance operational amplifier. The control signal for the first switch is the first clock signal, and the control signal for the second switch is the second clock signal.

[0008] In some embodiments of this disclosure, the adder module includes eight first switches, eight third switches, a third transconductance operational amplifier, two first feedforward capacitors, two second feedforward capacitors, two third feedforward capacitors, and two summing capacitors. The first first switch is connected to the first input signal and one end of the first first feedforward capacitor, respectively. The second first switch is connected to the first input signal and one end of the second first feedforward capacitor, respectively. The first third switch is connected to the second input signal and one end of the first first feedforward capacitor, respectively. The second third switch is connected to the second input signal and one end of the second first feedforward capacitor, respectively. One end of the third third switch is grounded, and the other end is connected to one end of the first second feedforward capacitor and one end of the first first switch in the second-stage integration unit, respectively. One end of the fourth third switch is grounded, and the other end is connected to one end of the second second feedforward capacitor and one end of the second first switch in the second-stage integration unit, respectively. One end of the fifth third switch is grounded, and the other end is connected to one end of the first third feedforward capacitor and one end of the third first switch, respectively. The sixth third switch... One end of the third switch is grounded. The other end of the sixth third switch is connected to one end of the second third feedforward capacitor and one end of the fourth first switch, respectively. The other end of the third first switch is connected to the output terminal of the second-stage integrator. The other end of the fourth first switch is connected to the output terminal of the second-stage integrator. One end of the fifth first switch is grounded. The other end of the fifth first switch is connected to the other end of the first first feedforward capacitor, the other end of the first second feedforward capacitor, the other end of the first third feedforward capacitor, and one end of the seventh third switch, respectively. One end of the sixth first switch is grounded. The other end of the sixth first switch is connected to the other end of the second first feedforward capacitor, the other end of the second second feedforward capacitor, the other end of the second third feedforward capacitor, and one end of the eighth third switch, respectively. The other ends of the seventh and eighth third switches are connected to the third transconductance operational amplifier, respectively. The seventh first switch is connected in parallel with the first summing capacitor and then in parallel across the third transconductance operational amplifier. The eighth first switch is connected in parallel with the second summing capacitor and then in parallel across the third transconductance operational amplifier. The control signal for the first switch is the first clock signal, and the control signal for the third switch is the third clock signal.

[0009] In some embodiments of this disclosure, the feedback digital-to-analog conversion module includes a digital-to-analog conversion unit, two first switches, two second switches, and two feedback capacitors. One end of each of the two second switches is connected to one end of the digital-to-analog conversion unit. One end of the first first switch is grounded, and the other end of the first first switch is connected to the other end of the first second switch and one end of the first feedback capacitor. One end of the second first switch is grounded, and the other end of the second first switch is connected to the other end of the second second switch and one end of the second feedback capacitor. The other end of the digital-to-analog conversion unit is connected to the comparator. The other end of the first feedback capacitor is connected to the first first sampling capacitor, and the other end of the second feedback capacitor is connected to the second first sampling capacitor.

[0010] In some embodiments of this disclosure, the comparator is a one-bit quantizer, the digital-to-analog converter is a one-bit digital-to-analog converter, and the control signal of the comparator is the third clock signal.

[0011] In some embodiments of this disclosure, if the modulator circuit is a multi-bit quantization, high-order full feedforward structure, the integration module is extended to a higher order by adding integration units, and the comparator is a multi-bit quantization comparator.

[0012] In some embodiments of this disclosure, the input signal is a sensor signal.

[0013] In some embodiments of this disclosure, the duration of the third clock signal in each cycle ranges from more than one-tenth of the cycle to less than or equal to one-fifth of the cycle.

[0014] The Sigma-Delta modulator circuit of this disclosure includes an integrator module, an adder module, a comparator, and a feedback digital-to-analog converter module. The integrator module integrates the difference between the input signal and the output of the feedback digital-to-analog converter module to obtain the integrator output. The adder module sums the input signal with the integrated output. The output of the adder module is connected to the comparator, and the output of the comparator is fed back to the integrator module through the feedback digital-to-analog converter module. The output of the comparator is the output signal. The modulator circuit is controlled by three clock signals: a first clock signal, a second clock signal, and a third clock signal. The first and second clock signals are non-overlapping two-phase clock signals, and the third clock signal arrives before the second clock signal. Under the control of these three clock signals, a Sigma-Delta modulator with high common-mode input capability and low input offset voltage is achieved. Compared to the conventional structure of adding a dedicated buffer to handle high common-mode input voltage in a Sigma-Delta modulator circuit, this design is simpler, reduces power consumption, and reduces input offset voltage while still handling high common-mode input voltage. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0016] Figure 1 This is a schematic block diagram of a Sigma-delta modulator circuit according to an embodiment of the present disclosure;

[0017] Figure 2 These are three clock signals according to embodiments of this disclosure;

[0018] Figure 3 This is an exemplary circuit diagram of a Sigma-delta modulator circuit according to an embodiment of the present disclosure.

[0019] The elements in the attached diagram are schematic and not drawn to scale. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0021] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0022] In all embodiments of this disclosure, additionally, terms such as “first” and “second” are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0023] First, it should be noted that the Sigma-delta modulator circuit in this embodiment is a Sigma-Delta modulator circuit with high common-mode input capability and low input offset voltage. Specifically, it utilizes capacitive coupling technology, allowing a high-voltage capacitor to withstand high common-mode input voltage, thereby realizing a Sigma-delta modulator circuit capable of withstanding high common-mode input voltage; simultaneously, it employs correlated double sampling technology to reduce input offset voltage. The specific circuit structure will be described in detail below.

[0024] Figure 1 An exemplary block diagram of a Sigma-delta modulator circuit 10 is shown. Figure 1 In the example, the modulator circuit 10 includes: an integrator module 11, an adder module 12, a comparator 13, and a feedback digital-to-analog converter module 14; wherein, the integrator module 11 integrates the difference between the input signal (Vip and Vin) and the output of the feedback digital-to-analog converter module 14 to obtain the integrator output result; the adder module 12 sums the input signal with the integrated output result; the output of the adder module 12 is connected to the comparator 13; and the output of the comparator 13 is fed back to the integrator module 14 through the feedback digital-to-analog converter module 14. Block 11, the output of the comparator 13 is the output signal (Doutn and Doutp); the input signal is a high common-mode input signal, the sampling capacitor in the first-stage integration unit 111 of the integration module 11 is a high-voltage capacitor, the feedback capacitor in the feedback digital-to-analog conversion module 14 is a high-voltage capacitor, and the adder module 12 receives the input signal through the high-voltage capacitor; it should be noted that the high-voltage capacitor involved in this embodiment can withstand a voltage of tens of volts, and the specific voltage value is related to the process used, and can be adaptively selected according to the actual process.

[0025] The modulator circuit in this embodiment of the disclosure uses a first clock signal Φ1, a second clock signal Φ2, and a third clock signal Φ3. 2a Three clock signals control, such as Figure 2 As shown, the three clock signals have the same period. The first clock signal Φ1 and the second clock signal Φ2 are two non-overlapping clock signals. The third clock signal Φ... 2a Before the second clock signal Φ2 arrives, when the first clock signal Φ1 is high, the integration module 11 and the adder module 12 sample, and the offset voltage of the transconductance operational amplifier of the first-stage integration unit 111 is sampled and stored, and the third clock signal Φ2 arrives first. 2aWhen the second clock signal Φ2 is high, the adder module 12 performs a summation operation, the comparator 13 performs a comparison operation, and the result of the comparison operation is latched. When the second clock signal Φ2 is high, the integrator module 11 performs an integration operation to eliminate the offset voltage, and the output of the comparator 13 is fed back to the integrator module 11 for subtraction. It should be noted that the third clock signal Φ 2a The duration is very short, just enough for adder module 12 to complete the addition operation and comparator 13 to complete the comparison operation. In practical applications, the third clock signal Φ 2a The duration within each cycle can range from more than one-tenth of the cycle to less than or equal to one-fifth of the cycle.

[0026] Under the control of three clock signals, a Sigma-Delta modulator circuit with high common-mode input capability and low input offset voltage was implemented. The following section combines... Figure 3 The circuit will be explained in more detail, such as... Figure 3 The diagram shows a Sigma-delta modulator circuit 10 with a one-bit quantization, second-order fully feedforward structure. The integration module 11 includes a first-stage integration unit 111 and a second-stage integration unit 112, connected in series. The first-stage integration unit 111 integrates the difference between the input signal and the output of the feedback digital-to-analog converter module 14, while the second-stage integration unit 112 integrates the output of the first-stage integration unit 111. The input signal includes a first input signal Vip and a second input signal Vin. The first-stage integration unit 111 includes four first switches S1, four second switches S2, and two first sampling capacitors C. S 1. First transconductance operational amplifier OTA1; two first integrating capacitors C int1In this configuration, the first switch 11101 is connected to the first input signal Vip and one end of the first sampling capacitor 11105, respectively; the second switch 11102 is connected to the second input signal Vin and one end of the second sampling capacitor 11106, respectively; the first switch 11103 is connected to the second input signal Vin and one end of the first sampling capacitor 11105, respectively; the second switch 11104 is connected to the first input signal Vip and one end of the second sampling capacitor 11106, respectively; the third switch 11107 is connected in series with the first integrating capacitor 11108 and then in parallel with the first transconductance operational amplifier OTA1; the fourth switch 11109 is connected in series with the second integrating capacitor 11110 and then in parallel with the first transconductance operational amplifier OTA1; the third switch 11111 and the fourth switch 11112 are connected in parallel across the first transconductance operational amplifier OTA1, respectively; and the two first sampling capacitors C... S The other ends of 1 (11105 and 11106) are respectively connected to the first transconductance operational amplifier OTA1. The control signal of the first switch S1 is the first clock signal Φ1, and the control signal of the second switch S2 is the second clock signal Φ2.

[0027] The second-stage integration unit 112 includes four first switches S1, four second switches S2, and two second sampling capacitors C. S 2. Second transconductance operational amplifier OTA2, two second integrating capacitors C int2In this configuration, one end of the first second switch 11203 is grounded, and the other end of the first second switch 11203 is connected to one end of the first first switch 11201 and one end of the first second sampling capacitor 11205. One end of the second second switch 11204 is grounded, and the other end of the second second switch 11204 is connected to one end of the second first switch 11202 and one end of the second second sampling capacitor 11206. The other end of the first first switch 11201 is connected to the output terminal of the first-stage integration unit 111. Specifically, the other end of the first first switch 11201 is connected to one end of the first first integrating capacitor 11105 and one end of the first transconductance operational amplifier OTA1 of the first-stage integration unit 111. The other end of the second first switch 11202 is connected to the output terminal of the first-stage integration unit 111. The output terminals of 11 are connected as follows: specifically, the other end of the second first switch 11202 is connected to one end of the second first integrating capacitor 11106 of the first stage integrating unit 111 and one end of the first transconductance operational amplifier OTA1, respectively; one end of the third first switch 11207 is grounded; the other end of the third first switch 11207 is connected to the other end of the first second sampling capacitor 11205 and one end of the third second switch 11209, respectively; one end of the fourth first switch 11208 is grounded; the other end of the fourth first switch 11208 is connected to the other end of the second second sampling capacitor 11206 and one end of the fourth second switch 11210, respectively; the other ends of the third second switch 11209 and the fourth second switch 11210 are connected to the second transconductance operational amplifier OTA2, respectively; and the two second integrating capacitors C... int2 (11211 and 11212) are connected in parallel across the second transconductance operational amplifier OTA2, the control signal of the first switch S1 is the first clock signal Φ1, and the control signal of the second switch S2 is the second clock signal Φ2.

[0028] Adder module 12 includes eight first switches S1, eight third switches S3, a third transconductance operational amplifier OTA3, and two first feedforward capacitors C. f1 Two second feedforward capacitors C f2 Two third feedforward capacitors C f3Two summing capacitors C0 are used. The first switch 1201 is connected to the first input signal Vip and one end of the first feedforward capacitor 1202, respectively. The second switch 1203 is connected to the first input signal Vip and one end of the second feedforward capacitor 1204, respectively. The first switch 1205 is connected to the second input signal Vin and one end of the first feedforward capacitor 1202, respectively. The second switch 1206 is connected to the second input signal Vin and one end of the second feedforward capacitor 1204, respectively. One end of the third switch 1207 is grounded, and the other end of the third switch 1207 is connected to the first feedforward capacitor 1204. One end of the feed capacitor 1208 is connected to one end of the first switch 11201 in the second-stage integration unit 112. One end of the fourth third switch 1209 is grounded, and the other end of the fourth third switch 1209 is connected to one end of the second second feed capacitor 1210 and one end of the second first switch 11202 in the second-stage integration unit 112. One end of the fifth third switch 1211 is grounded, and the other end of the fifth third switch 1211 is connected to one end of the first third feed capacitor 1212 and one end of the third first switch 1213. One end of the sixth third switch 1214 is grounded, and the other end of the sixth third switch 1214 is connected to the second third feed capacitor 1210. One end of switch 5 is connected to one end of the fourth first switch 1216. The other end of the third first switch 1213 is connected to the output of the second-stage integrator 112. Specifically, the other end of the third first switch 1213 is connected to one end of the first second integrating capacitor 11211 of the second-stage integrator 112 and one end of the second transconductance operational amplifier OTA2. The other end of the fourth first switch is connected to the output of the second-stage integrator 112. Specifically, the other end of the fourth first switch 1216 is connected to one end of the second second integrating capacitor 11212 of the second-stage integrator 112 and one end of the second transconductance operational amplifier OTA2. One end of the fifth first switch 1217 is connected to... The other end of the fifth first switch 1217 is connected to the other ends of the first first feedforward capacitor 1202, the first second feedforward capacitor 1208, the first third feedforward capacitor 1212, and the seventh third switch 1219. One end of the sixth first switch 1218 is grounded. The other end of the sixth first switch 1218 is connected to the other ends of the second first feedforward capacitor 1204, the second second feedforward capacitor 1210, the second third feedforward capacitor 1215, and the eighth third switch 1220. The other ends of the seventh third switch 1219 and the eighth third switch 1220 are respectively connected to the third transconductance operational amplifier OTA3.The seventh first switch 1221 is connected in parallel with the first summing capacitor 1222, and then in parallel across the third transconductance operational amplifier OTA3. The eighth first switch 1223 is connected in parallel with the second summing capacitor 1224, and then in parallel across the third transconductance operational amplifier OTA3. The control signal for the first switch S1 is the first clock signal Φ1, and the control signal for the third switch S3 is the third clock signal Φ. 2a .

[0029] The feedback analog-to-digital converter module 14 includes an analog-to-digital converter unit 1401, two first switches S1, two second switches S2, and two feedback capacitors C. fb In this configuration, one end of each of the two second switches S2 (1402 and 1403) is connected to one end of the digital-to-analog converter unit 1401. One end of the first switch 1404 is grounded, and the other end of the first switch 1404 is connected to the other end of the first second switch 1402 and one end of the first feedback capacitor 1406. One end of the second switch 1405 is grounded, and the other end of the second switch 1405 is connected to the other end of the second second switch 1403 and one end of the second feedback capacitor 1407. The other end of the digital-to-analog converter unit 1401 is connected to the comparator 13, that is, the other end of the digital-to-analog converter unit is connected to the output terminal of the comparator 13. The other end of the first feedback capacitor 1406 is connected to the first first sampling capacitor 11105, and the other end of the second feedback capacitor 1407 is connected to the second first sampling capacitor 11106.

[0030] Comparator 13 is a one-bit quantizer, the digital-to-analog converter unit 1401 is a one-bit digital-to-analog converter, and the control signal for comparator 13 is the third clock signal Φ. 2a .

[0031] Combination Figure 3 The circuit diagram shown Figure 2 The clock control signal shows that when Φ1 is high, it is the sampling phase; Cs1 samples the input signal, and Cs2 samples the output voltage of the first-stage integrator 111. The feedforward capacitor C... f1 C f2 C f3 The input signal Vip, the output voltage of the first-stage integrator 111, and the output voltage of the second-stage integrator 112 are sampled respectively. Simultaneously, phase Φ1 short-circuit the input and output of OTA1, allowing Cs1 to sample and store the offset voltage of OTA1. This is to eliminate the influence of the OTA1 offset voltage during Φ2, which is how the correlated double sampling technique achieves low input offset voltage. Simultaneously, phase Φ1 performs a clearing operation on OTA3, ensuring that the result of the previous summation is eliminated before each addition operation. Then Φ... 2aWhen the phase goes high, adder module 12 sums the input signal, the output voltage of the first-stage integrator 111, and the output voltage of the second-stage integrator 112. The result is sent to a one-bit quantizer (i.e., comparator 13) for comparison. The comparison result is latched by an internal latch and used to feed back the Φ2 phase to the first-stage integrator 111 for subtraction. Then, the Φ2 phase goes high, and the first-stage integrator 111 and the second-stage integrator 112 complete the integration operation. The first-stage integrator 111 simultaneously samples the input signal twice, thus canceling out the high common-mode voltage and giving the entire modulator a high common-mode input capability. It should be noted that the two first sampling capacitors C S 1. Two first feedforward capacitors C f1 Two feedback capacitors C fb These are high-voltage capacitors, capable of withstanding tens of volts. The specific voltage value depends on the manufacturing process and can be selected appropriately based on the actual application. Two first sampling capacitors C S 2 is a low-voltage capacitor.

[0032] Compared to conventional sigma delta modulators, the sigma delta modulator in this embodiment adopts a capacitively coupled structure at its input stage. Combined with dual sampling technology, at the end of phase Φ2, a charge of 2*Cs*VIN (VIN represents the useful signal riding on the common-mode voltage at one end) is transferred to the output of the first-stage integrator 111. Therefore, while keeping the gain of the integrator (first-stage integrator 111) constant, the value of the first-stage sampling capacitor Cs1 only needs to be half of the design value. This cancels out the high common-mode input voltage, performing only the integration operation on the useful signal. It can also be noted that the feedforward input signal passes through the high-voltage capacitor C... f1 This achieves high common-mode voltage cancellation and transmits the useful signal to adder module 12. Similarly, C f1 The value is also half of the theoretical value (the theoretical value is the value obtained from MATLAB modeling when designing the sigma delta modulator).

[0033] In this embodiment, the sigma delta modulator employs correlated double sampling technology at the input to eliminate the offset voltage of the first-stage operational transconductance amplifier (OTA1). This makes the sigma delta modulator more suitable for high-precision sensor detection, especially in applications with high common-mode input. Specifically, it can be applied in fields such as high-end current sensing, industrial and medical devices, automotive, and power audio.

[0034] Additionally, it should be noted that for Figure 3The high common-mode, low offset Sigma-delta modulator can be easily extended to higher-order, multi-bit structures. Specifically, the integration module 11 is extended to a higher order by adding an integration unit, and the comparator 13 is a multi-bit quantization comparator, thus obtaining a high common-mode, low offset Sigma-delta modulator with a multi-bit quantization, high-order, fully feedforward structure.

[0035] In summary, the Sigma-delta modulator circuit according to the embodiments of this disclosure has a simple structure, low power consumption, and is able to withstand high common-mode input voltage and reduce input offset voltage.

[0036] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatuses and methods according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0037] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0038] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0039] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A Sigma-delta modulator circuit, characterized in that, The modulator circuit includes: an integrator module, an adder module, a comparator, and a feedback digital-to-analog converter module; wherein, the integrator module integrates the difference between the input signal and the output of the feedback digital-to-analog converter module to obtain the integrator output result; the adder module sums the input signal with the integrated output result; the output of the adder module is connected to the comparator; the output of the comparator is fed back to the integrator module through the feedback digital-to-analog converter module; the output of the comparator is the output signal; the input signal is a high common-mode input signal; the sampling capacitor in the first-stage integrator unit of the integrator module is a high-voltage capacitor; the feedback capacitor in the feedback digital-to-analog converter module is a high-voltage capacitor; and the adder module receives the input signal through the high-voltage capacitor. The modulator circuit is controlled by three clock signals: a first clock signal, a second clock signal, and a third clock signal. The three clock signals have the same period. The first clock signal and the second clock signal are two non-overlapping clock signals. The third clock signal arrives before the second clock signal. When the first clock signal is high, the integrator module and the adder module sample the voltage and store the offset voltage of the transconductance operational amplifier of the first-stage integrator unit. When the third clock signal is high, the adder module performs a summation operation, the comparator performs a comparison operation, and the result of the comparison operation is latched. When the second clock signal is high, the integrator module performs an integration operation to eliminate the offset voltage and feeds back the output of the comparator to the integrator module for subtraction.

2. The Sigma-delta modulator circuit according to claim 1, characterized in that, If the modulator circuit is a one-bit quantization, second-order full feedforward structure, the integration module includes a first-stage integration unit and a second-stage integration unit. The first-stage integration unit and the second-stage integration unit are connected in series. The first-stage integration unit performs an integration operation on the difference between the input signal and the output of the feedback digital-to-analog converter module, and the second-stage integration unit performs an integration operation on the output result of the first-stage integration unit.

3. The Sigma-delta modulator circuit according to claim 2, wherein the input signal includes a first input signal and a second input signal, characterized in that, The first-stage integration unit includes four first switches, four second switches, two first sampling capacitors, a first transconductance operational amplifier, and two first integrating capacitors. The two ends of the first first switch are respectively connected to the first input signal and one end of the first first sampling capacitor. The two ends of the second first switch are respectively connected to the second input signal and one end of the second first sampling capacitor. The third and fourth first switches are respectively connected in parallel across the first transconductance operational amplifier. The two ends of the first second switch are respectively connected to the second input signal and one end of the first first sampling capacitor. The two ends of the second second switch are respectively connected to the first input signal and one end of the second first sampling capacitor. The third second switch is connected in series with the first first integrating capacitor and then in parallel with the first transconductance operational amplifier. The fourth second switch is connected in series with the second first integrating capacitor and then in parallel with the first transconductance operational amplifier. The other ends of the two first sampling capacitors are respectively connected to the first transconductance operational amplifier. The control signal for the first switches is the first clock signal, and the control signal for the second switches is the second clock signal.

4. The Sigma-delta modulator circuit according to claim 2, characterized in that, The second-stage integration unit includes four first switches, four second switches, two second sampling capacitors, a second transconductance operational amplifier, and two second integration capacitors. One end of the first second switch is grounded, and the other end is connected to one end of the first first switch and one end of the first second sampling capacitor. One end of the second second switch is grounded, and the other end is connected to one end of the second first switch and one end of the second second sampling capacitor. The other end of the first first switch is connected to the output terminal of the first-stage integration unit. The other end of the second first switch is also connected to the output terminal of the first-stage integration unit. One end of the third first switch is grounded, and the other end is connected to the other end of the first second sampling capacitor and one end of the third second switch. One end of the fourth first switch is grounded, and the other end is connected to the other end of the second second sampling capacitor and one end of the fourth second switch. The other ends of the third and fourth second switches are connected to the second transconductance operational amplifier. The two second integration capacitors are connected in parallel across the second transconductance operational amplifier. The control signal for the first switches is the first clock signal, and the control signal for the second switches is the second clock signal.

5. The Sigma-delta modulator circuit according to claim 4, characterized in that, The adder module includes eight first switches, eight third switches, a third transconductance operational amplifier, two first feedforward capacitors, two second feedforward capacitors, two third feedforward capacitors, and two summing capacitors. The first first switch is connected to the first input signal and one end of the first first feedforward capacitor, respectively. The second first switch is connected to the first input signal and one end of the second first feedforward capacitor, respectively. The first third switch is connected to the second input signal and one end of the first first feedforward capacitor, respectively. The second third switch is connected to the second input signal and one end of the second first feedforward capacitor, respectively. One end of the third third switch is grounded, and the other end is connected to one end of the first second feedforward capacitor and one end of the first first switch in the second-stage integration unit, respectively. One end of the fourth third switch is grounded, and the other end is connected to one end of the second second feedforward capacitor and one end of the second first switch in the second-stage integration unit, respectively. One end of the fifth third switch is grounded, and the other end is connected to one end of the first third feedforward capacitor and one end of the third first switch, respectively. One end of the sixth third switch is grounded. The other end of the sixth third switch is connected to one end of the second third feedforward capacitor and one end of the fourth first switch, respectively. The other end of the third first switch is connected to the output of the second-stage integrator. The other end of the fourth first switch is connected to the output of the second-stage integrator. One end of the fifth first switch is grounded. The other end of the fifth first switch is connected to the other end of the first first feedforward capacitor, the other end of the first second feedforward capacitor, the other end of the first third feedforward capacitor, and one end of the seventh third switch, respectively. One end of the sixth first switch is grounded. The other end of the sixth first switch is connected to the other end of the second first feedforward capacitor, the other end of the second second feedforward capacitor, the other end of the second third feedforward capacitor, and one end of the eighth third switch, respectively. The other ends of the seventh and eighth third switches are connected to the third transconductance operational amplifier, respectively. The seventh first switch is connected in parallel with the first summing capacitor and then in parallel across the third transconductance operational amplifier. The eighth first switch is connected in parallel with the second summing capacitor and then in parallel across the third transconductance operational amplifier. The control signal for the first switch is the first clock signal, and the control signal for the third switch is the third clock signal.

6. The Sigma-delta modulator circuit according to claim 3, characterized in that, The feedback analog-to-digital converter module includes an analog-to-digital converter unit, two first switches, two second switches, and two feedback capacitors. One end of each of the two second switches is connected to one end of the analog-to-digital converter unit. One end of the first first switch is grounded, and the other end of the first first switch is connected to the other end of the first second switch and one end of the first feedback capacitor. One end of the second first switch is grounded, and the other end of the second first switch is connected to the other end of the second second switch and one end of the second feedback capacitor. The other end of the analog-to-digital converter unit is connected to the comparator. The other end of the first feedback capacitor is connected to the first first sampling capacitor, and the other end of the second feedback capacitor is connected to the second first sampling capacitor.

7. The Sigma-delta modulator circuit according to claim 2, characterized in that, The comparator is a one-bit quantizer, the digital-to-analog converter is a one-bit digital-to-analog converter, and the control signal for the comparator is the third clock signal.

8. The Sigma-delta modulator circuit according to claim 2, characterized in that, If the modulator circuit is a multi-bit quantization, high-order full feedforward structure, the integration module is extended to a higher order by adding integration units, and the comparator is a multi-bit quantization comparator.

9. The Sigma-delta modulator circuit according to claim 1, characterized in that, The input signal is a sensor signal.

10. The Sigma-delta modulator circuit according to claim 1, characterized in that, The duration of the third clock signal in each cycle is greater than one-tenth of the cycle and less than or equal to one-fifth of the cycle.

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