A sensor analog front-end circuit with reduced power consumption and a method of operation thereof

Abstract

The application discloses a sensor analog front-end circuit with reduced power consumption and a working method thereof. The sensor analog front-end circuit comprises a sample-and-hold module and a sampling bias current / BJT core module, wherein the sampling bias current / BJT core module has a pre-charge mode and a conversion mode; in the pre-charge mode, a stable bias current is generated by using a triode, and a current source control signal is saved in the sample-and-hold module; in the conversion mode, a fixed-size bias current is obtained by receiving the current source control signal, and environmental temperature information is converted into a voltage signal output. The application adopts a dual-mode design, and compared with a conventional design, the circuit is reduced by half, the total bias current is reduced, the circuit power consumption is reduced, and the circuit area is effectively reduced. The application uses a capacitor to transfer a bias current signal, and can play a filtering role, so that the noise of the circuit is reduced.

Description

Technical Field

[0001] The present invention relates to the field of chips, and in particular to a sensor analog front-end circuit and a working method thereof that effectively reduces power consumption. Background Art

[0002] The development of temperature sensors has a long history. For example, the thermometer is a simple and primitive temperature sensor. With the advent of the electrical age, the demand for more accurate temperature data has increased, leading to the increasing use of temperature sensor chips implemented using integrated circuits. This has led to the development of integrated temperature sensors becoming a research focus in recent years. With the increasing use of information technology, research on CMOS intelligent temperature sensors has become a popular research area. Currently, CMOS temperature sensors are widely used in systems-on-chips (SoCs), high-performance microprocessors, radio frequency identification tags, the Internet of Things, and other fields.

[0003] CMOS temperature sensors use temperature-dependent CMOS elements as temperature sensors to measure temperature. Commonly used CMOS temperature sensors include parasitic BJTs, MOSFETs, and temperature-controlled resistors. Furthermore, research is actively exploring new temperature-sensing materials and devices. Currently, the development of CMOS temperature sensor chips focuses on low power consumption, small footprint, and high quality factor. A variety of new structures have also been developed to enable chips to operate at lower power supply voltages. CMOS temperature sensor chip design typically considers the specific application scenario, ensuring a balance between accuracy and price to achieve the best cost-effectiveness. Summary of the Invention

[0004] The purpose of the present invention is to provide a sensor analog front-end circuit and a working method thereof that effectively reduces power consumption. Compared with conventional analog front-end circuits, in this circuit, V BE and △V BE Instead of always using the input signal, the voltage is maintained by a sampling capacitor, thereby reducing the power consumption of the analog front end. This circuit combines the charge and discharge characteristics of the capacitor with the coordination of the analog front end, such as using a BJT combined with a switch capacitor to obtain ΔV using the charge and discharge time difference. BE With V BE The current source between the BJT and the power supply voltage is replaced with a switch, reducing voltage drop and lowering the power supply voltage requirement. Traditional BJT analog front ends require current bias circuits and BJT core circuits, which consume a lot of power. This circuit uses capacitor charging to store the bias voltage, then uses a switch to switch between the bias circuit and the core circuit, achieving circuit reuse and saving power.

[0005] To achieve the above objectives, the present invention provides a sensor analog front-end circuit that effectively reduces power consumption, including a sample-and-hold module and a sampling bias current / BJT core module, wherein:

[0006] The sampling bias current / BJT core module is a dual-mode circuit, which implements a pre-charge mode and a conversion mode by a single circuit module, and its mode is controlled by a mode control signal. When the mode control signal is high, the sampling bias current / BJT core module operates in the pre-charge mode, using a transistor to generate a stable bias current and storing the current source control signal in the sample-and-hold module. When the mode control signal is low, the sampling bias current / BJT core module operates in the conversion mode, receiving the current source control signal to obtain a fixed bias current and converting the ambient temperature information into a voltage signal for output.

[0007] The sampling and holding module is used to store the current source control information output by the sampling bias current / BJT core module in the pre-charge mode, and transmit it to the sampling bias current / BJT core module in the conversion mode.

[0008] According to a preferred solution of the present invention, the sampling and holding module at least includes a capacitor C S and a first switch module SW1; the sampling bias current / BJT core module includes a first MOS tube M A , the second MOS tube M B 、The first transistor Q B1 、The second transistor Q B2 , bias resistor R BIAS , a second switch module SW2, a third switch module SW3 and a fourth switch module SW4;

[0009] Among them, the capacitor C S One end of the power supply V DD The other end is connected to the first MOS tube M A The gate of the second MOS tube M B The gate of the first MOS tube M is connected to one end of the first switch module SW1. A And the second MOS tube M B The source and power supply V DD connected;

[0010] The first MOS tube M A The drain of the first switch module SW1 and the other end of the first output terminal V of the sensor analog front-end circuit are connected. BE1 , one end of the second switch module SW2, the first transistor Q B1 The collector of the second switch module SW2 is connected in common, and the other end of the second switch module SW2 is connected to the first transistor Q B1 The base of the first transistor Q is connected to one end of the third switch module SW3. B1 The emitter and bias resistor R BIASOne end of the fourth switch module SW4 is connected; the bias resistor R BIAS The other end of the fourth switch module SW4 is connected to the ground GND;

[0011] The second MOS tube M B The drain of the sensor is connected to the second output terminal V BE2 、The second transistor Q B2 The collectors of the second transistor Q B2 The collector of the second transistor Q is connected to the base. B2 The base of the second transistor Q is connected to the other end of the third switch module SW3. B2 The emitter connection is connected to ground GND.

[0012] According to a preferred embodiment of the present invention, the sensor analog front-end circuit for effectively reducing power consumption further includes a signal conversion circuit, which includes a first inverter, a delay device, and a second inverter connected in sequence; the input signal of the signal conversion circuit is the mode control signal Φ AFE , the output signal of the first inverter is Φ AFEB The output signal of the delay device is Φ AFEBD , the output signal of the second inverter is Φ AFED ;

[0013] The control signal of the first switch module SW1 is Φ AFE , the control signal of the second switch module SW2 is Φ AFEB , the control signal of the third switch module SW3 is Φ AFE , the control signal of the fourth switch module SW4 is Φ AFED The first switch module SW1, the second switch module SW2, the third switch module SW3 and the fourth switch module SW4 are turned on when the control signal is high and turned off when the control signal is low.

[0014] The present invention also provides a method for operating the sensor analog front-end circuit that effectively reduces power consumption:

[0015] When the mode control signal Φ AFE =1, when the circuit operates in the pre-charge mode, the sampling bias current / BJT core module is used as the sampling bias current module, and the first MOS tube M A , the second MOS tube M B Working as a mirror current source, when the circuit is stable, the capacitor C S Charging is completed, the gate voltage of the first MOS tube and the second MOS tube is V B Stable driving voltage required for current source;

[0016] When ΦAFE When =0, the circuit works in the conversion mode, at this time the circuit works as a BJT core module, through the capacitor C S control voltage, so that the first MOS M A , the second MOS M B The current remains unchanged, when the circuit is stable, the capacitor C S slowly discharges, V B remains essentially unchanged, the MOS base voltage is stable, so that its output current remains stable. At this time, the dependence between the transistor collector current and temperature is used to generate a negative temperature coefficient of V BE1 , V BE2 and positive temperature coefficient of ΔV BE , where ΔV BE is the difference between V BE1 , V BE2 , so as to realize the conversion of temperature information into corresponding voltage.

[0017] The present application has at least the following advantages:

[0018] 1. Save power consumption: the present application adopts dual-mode design, compared with the conventional design, reduces half of the circuit, thus reducing the total bias current, and reducing the circuit power consumption.

[0019] 2. Reduce noise: the present application uses capacitor to transfer bias current signal, which can play a filtering role, thereby reducing the noise of the circuit.

[0020] 3. Reduce circuit area: the present application adopts dual-mode design, uses the same circuit to realize two functions through mode control signal, effectively reduces the circuit area without affecting the circuit function. BRIEF DESCRIPTION OF DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of the provided drawings.

[0022] Figure 1 is a conventional analog front-end basic circuit diagram for comparison;

[0023] Figure 2 is a basic block diagram of the analog front-end in the embodiment of the present application;

[0024] Figure 3 is a dual-module conversion schematic diagram of the analog front-end in the embodiment of the present application;

[0025] Figure 4This is a schematic diagram of a specific analog front-end circuit in the embodiment;

[0026] Figure 5 Signal relationship diagram in the basic circuit of the analog front end. DETAILED DESCRIPTION

[0027] The present invention will be further described and illustrated below in conjunction with specific embodiments. The embodiments are merely illustrative of the present disclosure and do not limit its scope. The technical features of the various embodiments of the present invention may be combined accordingly, provided that there is no conflict between them.

[0028] like Figure 1 As shown in FIG, a conventional analog front-end circuit applied to a temperature sensor consists of two modules, including a bias current module on the left and a BJT core module on the right.

[0029] The bias current module uses transistors to provide a stable bias current. For transistors, according to their basic principles, their base-emitter voltage and collector current satisfy:

[0030]

[0031] As for I S The same two transistors, their V BE The difference satisfies:

[0032]

[0033] Therefore, in the bias current module, the bias current I BIAS The size meets:

[0034]

[0035] In the BJT core module, the principle of the transistor is the same as that in the bias current module, so the final measurement can be obtained:

[0036]

[0037] like Figure 2 and Figure 3 As shown, the present invention discloses a sensor analog front-end circuit that effectively reduces power consumption, including a sampling and holding module and a sampling bias current / BJT core module.

[0038] The sampling bias current / BJT core module is a dual-mode circuit, which implements a pre-charge mode and a conversion mode by a single circuit module, and its mode is controlled by a mode control signal. When the mode control signal is high, the sampling bias current / BJT core module operates in the pre-charge mode, using a transistor to generate a stable bias current and storing the current source control signal in the sample-and-hold module. When the mode control signal is low, the sampling bias current / BJT core module operates in the pre-charge mode, receiving the current source control signal to obtain a fixed bias current and converting the ambient temperature information into a voltage signal for output.

[0039] The sampling and holding module is used to store the current source control information output by the sampling bias current / BJT core module in the pre-charge mode, and transmit it to the sampling bias current / BJT core module in the conversion mode.

[0040] like Figure 3 As shown, the sampling and holding module of the present invention includes at least a capacitor C S and a first switch module SW1; the sampling bias current / BJT core module includes a first MOS tube M A , the second MOS tube M B 、The first transistor Q B1 、The second transistor Q B2 , bias resistor R BIAS , a second switch module SW2, a third switch module SW3 and a fourth switch module SW4;

[0041] Among them, the capacitor C S One end of the power supply V DD The other end is connected to the first MOS tube M A The gate of the second MOS tube M B The gate of the first MOS tube M is connected to one end of the first switch module SW1. A And the second MOS tube M B The source and power supply V DD connected;

[0042] The first MOS tube M A The drain of the first switch module SW1 and the other end of the first output terminal V of the sensor analog front-end circuit are connected. BE1 , one end of the second switch module SW2, the first transistor Q B1 The collector of the second switch module SW2 is connected in common, and the other end of the second switch module SW2 is connected to the first transistor Q B1 The base of the first transistor Q is connected to one end of the third switch module SW3. B1 The emitter and bias resistor R BIAS One end of the fourth switch module SW4 is connected; the bias resistor RBIAS The other end of the fourth switch module SW4 is connected to the ground GND;

[0043] The second MOS tube M B The drain of the sensor is connected to the second output terminal V BE2 、The second transistor Q B2 The collectors of the second transistor Q B2 The collector of the second transistor Q is connected to the base. B2 The base of the second transistor Q is connected to the other end of the third switch module SW3. B2 The emitter connection is connected to ground GND.

[0044] like Figure 5 As shown, the sensor analog front-end circuit for effectively reducing power consumption further includes a signal conversion circuit, which includes a first inverter, a delay device, and a second inverter connected in sequence; the input signal of the signal conversion circuit is the mode control signal Φ AFE , the output signal of the first inverter is Φ AFEB The output signal of the delay device is Φ AFEBD , the output signal of the second inverter is Φ AFED Φ AFE is the input pulse signal that changes with a fixed period, Φ AFEB For Φ AFE The opposite signal, Φ AFEBD is Φ AFEB The signal obtained after a certain delay, Φ AFED For Φ AFEBD The control signal of the first switch module SW1 is Φ AFE , the control signal of the second switch module SW2 is Φ AFEB , the control signal of the third switch module SW3 is Φ AFE , the control signal of the fourth switch module SW4 is Φ AFED The first switch module SW1, the second switch module SW2, the third switch module SW3 and the fourth switch module SW4 are turned on when the control signal is high and turned off when the control signal is low.

[0045] like Figure 4 The present invention is shown as Figure 3 The circuit block diagram shown in FIG. Figure 3 Based on the first MOS tube M A With the second MOS tube M BIt is realized by eight repeated units as shown in the dotted box. Each unit includes a current source PMOS tube and a dynamic matching unit. Each dynamic matching unit consists of two inverters and two PMOS tubes, which are controlled by the corresponding control signal SEL. When the corresponding control signal SEL is high, the output current of the current source PMOS tube flows through the second output terminal V BE2 At this time, the role of the PMOS tube is the same as Figure 3 M in B On the contrary, when the corresponding control signal SEL is at a low level, the output current of the current source PMOS tube flows through the first output terminal V BE1 At this time, the role of the PMOS tube is the same as Figure 3 M in A same.

[0046] exist Figure 3 Based on the above, the fourth switch SW4 is realized by a switch NMOS tube MN and a switch PMOS tube MP, both of which are affected by the output Φ of the signal conversion circuit delay device. AFEBD Control. Among them, when Φ AFEBD When the signal is high, the switch NMOS tube MN is turned on and the switch PMOS tube MP is turned off, so that the first transistor Q B1 The emitter is directly grounded, and its effect is the same as Figure 3 The fourth switch SW4 is closed; on the contrary, when Φ AFEBD When the signal is low, the switch PMOS tube MP is turned on and the switch NMOS tube MN is turned off, so that the first transistor Q B1 The emitter is biased through the resistor R BIAS Grounding has the same effect as Figure 3 The fourth switch SW4 is turned off.

[0047] like Figure 4 As shown, in this embodiment, the sampling and holding module includes a capacitor C S and the first switch module SW1; sampling bias current / BJT core module includes: eight identical current mirror PMOS tubes M S1 ~M S8 , dynamic element matching module, the first transistor Q B1 、The second transistor Q B2 , switch PMOS tube MP, switch NMOS tube MN, bias resistor R BIAS , a second switch module SW2, a third switch module SW3 and a signal conversion circuit.

[0048] Among them, the capacitor C S One end of the power supply V DD The other end is connected to one end of the first switch module SW1, eight current mirror PMOS tubes M S1~M S8 The other end of the first switch module SW1 is connected to the first output terminal V BE1 connected;

[0049] The dynamic element matching module includes eight identical and parallel dynamic element matching units; eight current mirror PMOS tubes M S1 ~M S8 The source and power supply V DD connected, and its drain is connected to the corresponding dynamic element matching unit; the dynamic element matching module is respectively connected to the first output terminal V BE1 and the second output terminal V BE2 The input signal of the dynamic element matching module is the eight-bit one-hot code signal SEL<7:0>, which is used as the input signal of the eight dynamic element matching units. S1 To M S8 As a unit current source, the deviation caused by current mismatch is reduced and the matching accuracy of the current mirror is improved.

[0050] The first output terminal V BE1 Also with the first transistor Q B1 The collector of the first transistor Q B1 The emitter of the second transistor Q is connected to the source of the switch PMOS tube MP and the drain of the switch NMOS tube MN. B2 The base of the second transistor Q B2 The collector and the second output terminal V BE2 Connected, the second transistor Q B2 The emitter of the first transistor Q is connected to the ground GND. B1 The collector and base of the first transistor Q are connected via the second switch module SW2. B1 The base of the second transistor Q B2 The bases are connected via a third switch module SW3.

[0051] The dynamic element matching module of this embodiment is controlled by the eight-bit selection signal SEL<7:0>, which is used to select M each time. S1 To M S8 One of the SEL<7:0> bits is used as a unit current source, and dynamic element matching technology is used to reduce the deviation caused by current mismatch and improve the matching accuracy of the current mirror. In each ΦAFE cycle, only one bit of SEL<7:0> is low, and the rest of the bits are high. A different signal is selected as the low level in each cycle. <0> to SEL <7> After one round of selection, it will be selected as low level again from SEL <0> Start selecting.

[0052] When the state control signal Φ AFEWhen it is high, the circuit is in pre-charge mode. At this time, switches SW1 and SW3 are turned on, and Q B1 The emitter current flows through the resistor R BIAS , due to the existence of the current mirror, the current flowing through Q B1 and Q B2 The collector current of the two transistors is proportional to the current of the collector. According to the above, the ΔV BE Is a temperature-dependent value. This voltage is equal to the resistance R BIAS The voltage across both ends can thus obtain a stable bias current I BIAS When the circuit is stable, the unit bias current remains stable and the capacitor C S Charging is completed, making the gate voltage of the MOS tube V B Keep stable. When the state control signal Φ AFE When it is low, the circuit is in conversion mode. At this time, switches SW2 and SW4 are turned on, and Q B1 The emitter current does not flow through the resistor R BIAS , due to the sampling capacitor C S The existence of , at this time the unit bias current source remains stable, ΔV BE It is a value related to temperature, so the temperature information can be transferred to the voltage ΔV through the circuit. BE The SEL signal controls the MOS tube M C11 and M C12 Choose M S1 Whether it is selected as a unit current source. At the same time, this structure also forms a cascode amplifier, amplifying the effect of voltage on current.

[0053] for Figure 1 For the conventional front-end circuit shown in FIG, the total power consumption is:

[0054] P 总 =I BIAS .(R IBIAS +R QB1 +R BIAS )+mI BIAS .(R IBIAS +R QB2 )+

[0055] I BIAS .(R IBIAS +R QB3 )+pI BIAS .(R IBIAS +R QB4 )

[0056] Assuming m = p, since the same current flows through, assuming R QB1 =R QB3 , R QB2 =RQB4 .

[0057] For a conventional front-end circuit, the total power consumption is:

[0058] P 总 =I BIAS .[(2+2m)R IBIAS +R BIAS +2R QB1 +2mR QB2 ]

[0059] For the analog front-end circuit disclosed in the present invention, assuming that its mode switching period is T, wherein the duty cycle of the pre-charge mode is D, its total power consumption is:

[0060] P 总 =[DT.[I BIAS .(R IBIAS +R QB1 +R BIAS )+mI BIAS .(R IBIAS +R QB2 )]+(1-D)T.[I BIAS .(R IBIAS +R QB1 )+mI BIAS .(R IBIAS +R QB2 )]] / T

[0061] =I BIAS .[(1+m)R IBIAS +DR BIAS +R QB1 +mR QB2 ]

[0062] Obviously, the power consumption of the circuit disclosed in the present invention is much less than that of the conventional front-end circuit, ignoring the bias resistor R BIAS , the power consumption of other parts is only half of that of the conventional circuit, and the power consumed in the bias resistor is also reduced to D times the original power (D < 1).

[0063] The above-described embodiments merely illustrate several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. Persons skilled in the art will readily appreciate that variations and modifications may be made without departing from the scope of the present invention, all of which fall within the scope of protection of the present invention.

Claims

1. A sensor analog front-end circuit with reduced power consumption, characterized in that: Includes sample and hold module, sampling bias current / BJT core module, including: The sampling bias current / BJT core module is a dual-mode circuit, which implements a pre-charge mode and a conversion mode by a single circuit module, and its mode is controlled by a mode control signal. When the mode control signal is high, the sampling bias current / BJT core module operates in the pre-charge mode, using a transistor to generate a stable bias current and storing the current source control signal in the sample-and-hold module. When the mode control signal is low, the sampling bias current / BJT core module operates in the conversion mode, receiving the current source control signal to obtain a fixed bias current and converting the ambient temperature information into a voltage signal for output. The sampling and holding module is used to store the current source control information output by the sampling bias current / BJT core module in the pre-charge mode, and transmit it to the sampling bias current / BJT core module in the conversion mode.

2. The sensor analog front-end circuit with reduced power consumption according to claim 1, characterized in that: The sampling and holding module at least includes a capacitor C S and a first switch module SW1; the sampling bias current / BJT core module includes a first MOS tube M A , the second MOS tube M B 、The first transistor Q B1 、The second transistor Q B2 , bias resistor R BIAS , a second switch module SW2, a third switch module SW3 and a fourth switch module SW4; Among them, the capacitor C S One end of the power supply V DD The other end is connected to the first MOS tube M A The gate of the second MOS tube M B The gate of the first MOS tube M is connected to one end of the first switch module SW1. A And the second MOS tube M B The source and power supply V DD connected; The first MOS tube M A The drain of the first switch module SW1 and the other end of the first output terminal V of the sensor analog front-end circuit are connected. BE1 , one end of the second switch module SW2, the first transistor Q B1 The collector of the second switch module SW2 is connected in common, and the other end of the second switch module SW2 is connected to the first transistor Q B1 The base of the first transistor Q is connected to one end of the third switch module SW3. B1 The emitter and bias resistor R BIAS One end of the fourth switch module SW4 is connected; the bias resistor R BIAS The other end of the fourth switch module SW4 is connected to the ground GND; The second MOS tube M B The drain of the sensor is connected to the second output terminal V BE2 、The second transistor Q B2 The collectors of the second transistor Q B2 The collector of the second transistor Q is connected to the base. B2 The base of the second transistor Q is connected to the other end of the third switch module SW3. B2 The emitter connection is connected to ground GND.

3. The sensor analog front-end circuit with reduced power consumption according to claim 2, characterized in that The device also includes a signal conversion circuit, which includes a first inverter, a delay device, and a second inverter connected in sequence; the input signal of the signal conversion circuit is the mode control signal Φ AFE , the output signal of the first inverter is Φ AFEB The output signal of the delay device is Φ AFEBD , the output signal of the second inverter is Φ AFED ; The control signal of the first switch module SW1 is Φ AFE , the control signal of the second switch module SW2 is Φ AFEB , the control signal of the third switch module SW3 is Φ AFE , the control signal of the fourth switch module SW4 is Φ AFED The first switch module SW1, the second switch module SW2, the third switch module SW3 and the fourth switch module SW4 are turned on when the control signal is high and turned off when the control signal is low.

4. A method for operating the sensor analog front-end circuit according to claim 3, characterized in that: When the mode control signal Φ AFE =1, when the circuit operates in the pre-charge mode, the sampling bias current / BJT core module is used as the sampling bias current module, and the first MOS tube M A , the second MOS tube M B Working as a mirror current source, when the circuit is stable, the capacitor C S Charging is completed, the gate voltage of the first MOS tube and the second MOS tube is V B Stable driving voltage required for current source; When Φ AFE = 0, the circuit works in the conversion mode, at this time the circuit is used as a BJT core module, through the capacitor C S Control voltage, so that the first MOS tube M A , the second MOS tube M B The current remains constant; when the circuit is stable, the capacitor C S Slowly discharge, maintain V B The potential remains basically unchanged, the base voltage of the MOS tube is stable, so that its output current remains stable; at this time, the dependence between the transistor collector current and temperature is used to generate a negative temperature coefficient V BE1 、V BE2 and the positive temperature coefficient ΔV BE , where ΔV BE V BE1 、V BE2 The difference between the two values ​​is used to convert the temperature information into the corresponding voltage.

5. The method according to claim 4, characterized in that The switching mode is as follows: the mode control signal Φ AFE Directly control the switches in the circuit, change the circuit structure through the switches, and thus realize the switching of the circuit working mode.

6. The method according to claim 4, characterized in that When the mode control signal Φ AFE =1, the first switch module SW1 is turned on, the second switch module SW2 is turned off, the third switch module SW3 is turned on, and the fourth switch module SW4 is turned off; when the mode control signal Φ AFE =0, the first switch module SW1 is turned off, the second switch module SW2 is turned on, the third switch module SW3 is turned off, and the fourth switch module SW4 is turned on.

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