Refresh address generation circuit and method, memory, electronic device

Abstract

The present disclosure relates to the technical field of semiconductor, and relates to a refresh address generation circuit and method, a memory, and an electronic device. The refresh address generation circuit comprises a refresh control circuit and an address generator. The refresh control circuit is configured to sequentially receive a plurality of first refresh instructions and perform first refresh operations respectively, output a first clock signal when the number of the first refresh operations is less than a preset number value, and output a second clock signal when the number of the first refresh operations is equal to the preset number value n, wherein n is a positive integer greater than or equal to 1. The address generator is coupled to the refresh control circuit, and prestores a first address and receives the first clock signal or the second clock signal. During each first refresh operation, the address generator outputs a first address to be refreshed in response to the first clock signal, and the first address to be refreshed comprises the first address. In response to the second clock signal, the address generator changes the first address. The refresh address generation circuit can provide refresh addresses for refreshing the same memory block.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a refresh address generation circuit and method, a memory, and an electronic device. Background Technology

[0002] With technological advancements, dynamic random access memory (DRAM) now features not only an all-bank refresh mode but also a same-bank refresh mode during refresh. In same-bank refresh mode, the same address needs to be refreshed across multiple memory blocks. This necessitates an address generation circuit capable of implementing same-bank refresh.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to provide a refresh address generation circuit and method, a memory, and an electronic device, which can provide refresh addresses in the same memory block refresh mode.

[0005] According to a first aspect of this disclosure, a refresh address generation circuit is provided, the refresh address generation circuit comprising:

[0006] A refresh control circuit is used to sequentially receive multiple first refresh instructions and perform first refresh operations respectively. When the number of first refresh operations is less than a preset number, a first clock signal is output. When the number of first refresh operations is equal to the preset number n, a second clock signal is output, where n is a positive integer greater than or equal to 1.

[0007] An address generator, coupled to the refresh control circuit, pre-stores a first address and receives either the first clock signal or the second clock signal. During each of the first refresh operations, the address generator outputs a first address to be refreshed in response to the first clock signal. The first address to be refreshed includes the first address. Additionally, the address generator changes the first address in response to the second clock signal.

[0008] According to one embodiment of this disclosure, the refresh control circuit includes:

[0009] A refresh window signal generation circuit receives the first refresh instruction and a refresh window reset signal, and is used to generate a refresh window signal according to the first refresh instruction and the refresh window reset signal. The pulse duration of the refresh window signal is the window time for the refresh control circuit to perform one refresh operation. The refresh window reset signal is used to reset the refresh window signal generation circuit after one refresh operation is completed.

[0010] A clock pulse generation circuit, coupled to the refresh window signal generation circuit, is used to generate the first clock signal before the number of the first refresh instructions received by the clock pulse generation circuit is less than or equal to n and the first refresh operation ends in the nth time, or to generate the second clock signal after the number of the first refresh instructions received by the clock pulse generation circuit is n and the refresh operation ends in the nth time.

[0011] According to one embodiment of this disclosure, the clock pulse generation circuit includes:

[0012] The counting circuit receives the first refresh instruction and the counting reset signal, and is used to count the first refresh instruction and output a counting signal. The counting circuit is reset according to the counting reset signal.

[0013] A count reset signal generation circuit, coupled to the counting circuit and the refresh window signal generation circuit, is used to generate the count reset signal when there are n first refresh instructions and after the nth first refresh operation is completed.

[0014] The first pulse generation sub-circuit, coupled to the counting reset signal generation circuit, is used to generate the first clock signal based on the counting signal when the first refresh instruction is less than n, or to generate the second clock signal based on the counting reset signal when the first refresh instruction is equal to n.

[0015] According to one embodiment of this disclosure, the refresh window signal generation circuit includes:

[0016] n refresh window sub-signal generation circuits, each of the refresh window sub-signal generation circuits receives a refresh window reset signal and sequentially receives a plurality of the first refresh instructions, and the refresh window sub-signal generation circuits sequentially output a plurality of refresh window sub-signals according to the first refresh instructions and the refresh window reset signal;

[0017] A refresh window sub-signal processing circuit, coupled to n refresh window sub-signal generation circuits, is used to sequentially receive multiple refresh window sub-signals and perform logical operations on the refresh window sub-signals to output the refresh window signal.

[0018] According to one embodiment of this disclosure, the refresh control circuit further receives a second refresh instruction to perform a second refresh operation;

[0019] The multiple refresh window sub-signal generation circuits simultaneously receive a second refresh instruction and a refresh window reset signal, and each refresh window sub-signal generation circuit is used to generate the same refresh window sub-signal according to the second refresh instruction and the second refresh window reset signal.

[0020] The refresh window sub-signal processing circuit receives multiple refresh window sub-signals, performs logical operations on the refresh window sub-signals, and outputs the refresh window signal.

[0021] According to one embodiment of this disclosure, the refresh control circuit further includes:

[0022] The second pulse generation sub-circuit is coupled to the refresh window signal generation circuit. It is used to receive the refresh window signal and the address command signal, generate the first pulse of the third clock signal when the first refresh operation or the second refresh operation begins, and output the second pulse of the third clock signal according to the first pulse of the address command signal, thereby outputting the third clock signal.

[0023] An internal refresh window signal generation circuit is used to generate the internal refresh window signal according to the third clock signal, wherein the first pulse of the internal refresh window signal is generated after the first pulse of the third clock signal and ends before the second pulse of the third clock signal is generated, and the second pulse of the internal refresh window signal is generated after the second pulse of the third clock signal and ends before the pulse of the refresh window signal ends.

[0024] The address command signal generation circuit is used to generate a first pulse and a second pulse of the address command signal based on the effective level of the precharge signal. The first pulse of the address command signal is used to generate the second pulse of the internal refresh signal and the second pulse of the third clock signal. The effective level of the precharge signal is the effective level generated in response to the falling edge of the internal refresh window signal.

[0025] A refresh window reset signal generation circuit receives the precharge signal and generates the pulse of the refresh window reset signal based on the falling edge of the second pulse of the precharge signal.

[0026] According to one embodiment of this disclosure, the refresh control circuit further includes:

[0027] A signal selection circuit, coupled to the counting circuit, the first pulse generation sub-circuit, and the second pulse generation sub-circuit, is used to output the first clock signal or the second clock signal when the refresh control circuit performs the first refresh operation, or to output the third clock signal according to the counting signal when the refresh control circuit performs the second refresh operation.

[0028] According to one embodiment of this disclosure, the refresh control circuit further includes:

[0029] The address flag signal generation circuit is used to generate a rising edge of the address flag signal based on the first rising edge of the address command signal, and to generate a falling edge of the address flag signal based on the falling edge of the refresh window signal.

[0030] The address generator includes:

[0031] An address counter, which pre-stores the first address and is coupled to the signal selection circuit, is used to change the first address to a third address according to the second clock signal, or to change the first address according to the third clock signal and output a fourth address and a fifth address in sequence, wherein the first address, the fourth address and the fifth address are three consecutive addresses.

[0032] The address processing circuit, connected to the address counter and the refresh window sub-signal generation circuit, is used to receive the address flag signal and obtain the first address when the refresh control circuit performs the first refresh operation, and output the first address before the rising edge of the address flag signal arrives, or output the second address after the rising edge of the address flag signal arrives.

[0033] The address processing circuit is further configured to, when the refresh control circuit performs the second refresh operation, sequentially acquire the fourth address and the fifth address, and sequentially output the fourth address and the fifth address according to the plurality of refresh window sub-signals.

[0034] According to one embodiment of this disclosure, the address processing circuit includes:

[0035] An address calculation circuit is coupled to the address counter, and the address calculation unit is used to perform addition or subtraction operations on the first address to obtain the second address;

[0036] The address selection circuit is coupled to the address counter, the address calculation circuit and the refresh window sub-signal generation circuit, respectively. It is used to output the first address when the first refresh instruction is received and the address flag signal is low, and to output the second address when the address flag signal is high, or to output the fourth address and the third address sequentially according to the multiple refresh window sub-signals when the second refresh instruction is received.

[0037] According to one embodiment of this disclosure, the counting circuit includes:

[0038] There are n first inverters, and each first inverter receives a first refresh instruction.

[0039] There are n first latches, each with its set terminal connected to a first inverter. The reset terminals of the n first latches are configured to receive a count reset signal, and the output terminals of the n first latches are configured to output the count signal. When the number of the first refresh operation is equal to a preset value, the count reset signal resets the n first latches.

[0040] According to one embodiment of this disclosure, the counting reset signal generation circuit includes:

[0041] A first AND gate, the input of which receives the counting signal;

[0042] The second inverter, whose input is connected to the refresh window signal generation circuit, inverts the refresh window signal.

[0043] The second AND gate has its input terminals connected to the output terminals of the first AND gate and the second inverter, respectively.

[0044] A first delay unit, the input of which is connected to the output of the second AND gate;

[0045] A third inverter, the input of which is connected to the output of the first delay unit;

[0046] The third AND gate, whose input is connected to the output of the second AND gate and the output of the third inverter, outputs the count reset signal.

[0047] According to one embodiment of the present disclosure, the first pulse generation circuit includes:

[0048] A second delay unit, the input of which is connected to the output of the third AND gate;

[0049] A third delay unit, the input of which is connected to the output of the second delay unit;

[0050] The first OR gate has its input terminals connected to the output terminals of the third AND gate and the third delay unit, respectively. When the number of the first refresh instructions is less than n, the output terminal of the first OR gate outputs the first clock signal according to the counting signal, or when the number of the first refresh instructions is equal to n, the output terminal of the first OR gate outputs the second clock signal according to the counting reset signal.

[0051] According to one embodiment of this disclosure, the second pulse generation circuit includes:

[0052] A seventh delay unit, the input of which is connected to the refresh window signal generation circuit to receive the refresh window signal;

[0053] The seventh inverter has its input terminal connected to the output terminal of the seventh delay unit;

[0054] The input terminals of the sixth AND gate are respectively connected to the refresh window signal generation circuit and the output terminal of the seventh inverter;

[0055] The eighth inverter, the input of which is connected to the address flag signal generation circuit;

[0056] The seventh AND gate, the input of which is connected to the output of the eighth inverter and the address command signal generation circuit respectively;

[0057] The input terminals of the second NOR gate are respectively connected to the output terminals of the sixth AND gate and the seventh AND gate;

[0058] The ninth inverter has its input terminal connected to the output terminal of the second NOR gate, and its output terminal connected to the signal selection circuit.

[0059] According to one embodiment of this disclosure, the internal refresh window signal generation circuit includes:

[0060] The fourth latch has its set terminal connected to the output terminal of the second NOR gate, and its reset terminal connected to the address command signal generation circuit. The internal refresh window signal is generated based on the third clock signal.

[0061] According to one embodiment of this disclosure, the address command signal generation circuit includes:

[0062] The fifth inverter receives a pre-charge signal at its input terminal;

[0063] The fourth delay unit, the input of which is connected to the output of the fifth inverter;

[0064] The fourth AND gate, whose input is connected to the output of the fifth inverter and the fourth delay, outputs an address command signal.

[0065] According to one embodiment of this disclosure, the address flag signal generation circuit includes:

[0066] The input of the sixth inverter is connected to the output of the fourth AND gate;

[0067] The second latch has its set terminal connected to the output terminal of the sixth inverter, and it outputs an address flag signal.

[0068] According to one embodiment of this disclosure, the refresh window reset signal generation circuit includes:

[0069] The fifth AND gate receives the signal output by the second latch and the precharge signal at its input terminals, respectively.

[0070] A sixth delay unit, the input of which is connected to the output of the fifth AND gate;

[0071] The tenth inverter is connected to the output of the sixth delay unit and outputs the refresh window reset signal.

[0072] According to one embodiment of this disclosure, the refresh window sub-signal generation circuit includes:

[0073] The first NOR gate receives the first refresh instruction and the second refresh instruction at its input terminals, respectively.

[0074] The third latch has its set terminal connected to the output terminal of the first NOR gate, its reset terminal connected to the output terminal of the tenth inverter, and its output terminal outputs a refresh window sub-signal.

[0075] According to one embodiment of this disclosure, the refresh window sub-signal processing circuit includes:

[0076] The third OR gate, whose input is connected to the output of a plurality of third latches, outputs the refresh window signal.

[0077] According to one embodiment of this disclosure, the address selection circuit includes:

[0078] A ninth AND gate, the input terminals of which are respectively connected to multiple refresh window sub-signal generation circuits;

[0079] The eleventh inverter, the input terminal of which is connected to the address identifier signal generation circuit, is used to receive the address identifier signal;

[0080] The fourth NOR gate, the input of which is connected to the output of the ninth AND gate and the output of the eleventh inverter respectively;

[0081] A multiplexer, connected to the address counter, the address arithmetic circuit, and the fourth NOR gate, is used to respond to the signal output by the fourth NOR gate when performing the first refresh operation with the first address or the second address; or when performing the second refresh operation with the fourth address or the third address.

[0082] According to one embodiment of this disclosure, the signal selection circuit includes:

[0083] The third NOR gate, the input of which receives the counting signal;

[0084] The second OR gate has its input terminals connected to the first pulse generation circuit and the second pulse generation circuit, respectively.

[0085] The eighth AND gate has its input terminals connected to the output terminals of the third NOR gate and the second OR gate, respectively, and its output terminal is connected to the address generator.

[0086] According to a second aspect of this disclosure, a refresh address generation method is provided for the circuit described above, the method being used in the same memory block refresh mode, the method comprising:

[0087] The number of times the first refresh operation is performed by the refresh control circuit upon receiving the first refresh command;

[0088] When the number of times the refresh control circuit performs the first refresh operation is less than a preset number, the control address generator maintains its output address.

[0089] When the number of times the refresh control circuit performs the first refresh operation equals a preset value, the control address generator changes the address it outputs.

[0090] According to one embodiment of this disclosure, the method further includes:

[0091] When the refresh control circuit receives the second refresh instruction, it controls the address generator to output the full memory block refresh address.

[0092] According to a third aspect of this disclosure, a memory is provided, the memory including the refresh address generation circuit described above.

[0093] According to a fourth aspect of this disclosure, an electronic device is provided, the electronic device including the memory described above.

[0094] The refresh address generation circuit provided in this embodiment includes a refresh control circuit and an address generator. The refresh control circuit is used to sequentially receive multiple first refresh instructions and perform first refresh operations respectively. When the number of first refresh operations is less than a preset number, it outputs a first clock signal. When the number of first refresh operations is equal to the preset number n, it outputs a second clock signal. The address generator is coupled to the refresh control circuit and pre-stores a first address and receives the first clock signal or the second clock signal. The address generator outputs a first address to be refreshed in response to the first clock signal. The first address to be refreshed includes the first address. After outputting the first address to be refreshed, the address generator changes the first address in response to the second clock signal, thereby realizing the provision of refresh addresses to the memory in the same memory block refresh mode.

[0095] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0096] The above and other features and advantages of this disclosure will become more apparent from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0097] Figure 1 A schematic diagram of a first refresh address generation circuit provided for an exemplary embodiment of this disclosure;

[0098] Figure 2 A schematic diagram of a second refresh address generation circuit provided for an exemplary embodiment of this disclosure;

[0099] Figure 3 A schematic diagram of a third refresh address generation circuit provided for an exemplary embodiment of this disclosure;

[0100] Figure 4 A schematic diagram of a first refresh window signal generation circuit provided for an exemplary embodiment of this disclosure;

[0101] Figure 5 A schematic diagram of an address generator provided for an exemplary embodiment of this disclosure;

[0102] Figure 6 A signal timing diagram of a refresh address generation circuit provided for an exemplary embodiment of this disclosure;

[0103] Figure 7 A flowchart illustrating a first refresh address generation method provided as an exemplary embodiment of this disclosure;

[0104] Figure 8A flowchart of a second refresh address generation method provided as an exemplary embodiment of this disclosure. Detailed Implementation

[0105] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0106] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced without one or more of the specific details described, or other methods, components, materials, apparatuses, steps, etc., can be employed. In other instances, well-known structures, methods, apparatuses, implementations, materials, or operations are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0107] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, or in one or more software-hardened modules, or in different network and / or processor devices and / or microcontroller devices.

[0108] In DDR5 (Double Data Rate SDRAM 5, fifth generation double data rate synchronous dynamic random access memory), it not only has the full memory block refresh mode inherited from DDR4, but also the same memory block refresh mode.

[0109] In full memory block refresh mode, all memory blocks are refreshed together; in other words, all memory blocks are refreshed at the same address at the same time. Related technologies utilize a counter's output as the refresh address generator. Each time a row is refreshed, the counter's output is incremented by 1, serving as the address for the next row. When all rows have been refreshed, the counter is reset and starts counting again for the next round of refresh.

[0110] In the same memory block refresh mode, the same memory blocks in different memory block groups are refreshed line by line simultaneously. That is, the same line of different memory blocks cannot be refreshed at the same time in this mode, and the refresh address generator in related technologies will encounter the problem of address generation and storage.

[0111] This exemplary embodiment first provides a refresh address generation circuit, such as Figure 1 As shown, the refresh address generation circuit includes a refresh control circuit 100 and an address generator 200. The refresh control circuit 100 is used to sequentially receive multiple first refresh instructions (Same Bank CMD) and perform first refresh operations respectively. When the number of first refresh operations is less than a preset value, it outputs a first clock signal; and when the number of first refresh operations is equal to the preset value n, it outputs a second clock signal, where n is a positive integer greater than or equal to 1. The address generator 200 is coupled to the refresh control circuit 100, and pre-stores a first address and receives the first clock signal or the second clock signal. During each first refresh operation, the address generator 200 outputs a first address to be refreshed in response to the first clock signal. The first address to be refreshed includes a first address. The address generator 200 changes the first address in response to the second clock signal.

[0112] The refresh address generation circuit provided in this embodiment includes a refresh control circuit 100 and an address generator 200. The refresh control circuit 100 is used to sequentially receive multiple first refresh instructions (Same Bank CMD) and perform first refresh operations respectively. When the number of first refresh operations is less than a preset value, it outputs a first clock signal. When the number of first refresh operations is equal to the preset value n, it outputs a second clock signal. The address generator 200 is coupled to the refresh control circuit 100, and pre-stores a first address and receives the first clock signal or the second clock signal. The address generator 200 outputs a first address to be refreshed in response to the first clock signal. The first address to be refreshed includes the first address. After outputting the first address to be refreshed, the address generator 200 changes the first address in response to the second clock signal, thereby realizing the provision of refresh addresses to the memory in the same memory block refresh mode.

[0113] It should be noted that, in the embodiments of this application, the coupling methods include: direct electrical connection, and electrical connection through other electrical components (such as resistors, timers, or inverters). The term "coupling" as used below will encompass these methods, and will not be elaborated upon further.

[0114] The refresh address generation circuit provided in the embodiments of this disclosure will now be described in detail:

[0115] The refresh control circuit 100 may include a refresh window signal generation circuit 120 and a clock pulse generation circuit 110. The refresh window signal generation circuit 120 receives a first refresh instruction (Same Bank CMD) and a refresh window reset signal (RefershWindow Reset), and generates a refresh window signal (Refersh Window) based on these instructions. The pulse duration of the refresh window signal (Refersh Window) is the window time for the refresh control circuit 100 to perform one refresh operation. The refresh window reset signal (RefershWindow Reset) is used to reset the refresh window signal generation circuit 120 after one refresh operation. The clock pulse generation circuit 110 is coupled to the refresh window signal generation circuit 120 and generates a first clock signal when the number of first refresh instructions (Same Bank CMD) received by the clock pulse generation circuit 110 is less than or equal to n and before the end of the nth first refresh operation, or when the number of first refresh instructions (Same Bank CMD) received by the clock pulse generation circuit 110 is n and after the end of the nth refresh operation.

[0116] The first refresh instruction, Same Bank CMD, can be a refresh instruction for the same memory block, and the number of Same Bank CMD instructions can be the same as the number of memory blocks. For example, if the memory block group in the memory has n (n is a positive integer greater than or equal to 2) memory blocks, then the number of Same Bank CMD instructions can be n. The n Same Bank CMD instructions can be sequentially input to the refresh window signal generation circuit 120 and the clock pulse generation circuit 110. Before the n Same Bank CMD instructions are sequentially input to the refresh window signal generation circuit 120 and the clock pulse generation circuit 110, the clock pulse generation circuit 110 maintains the output of a first clock signal. After the n Same Bank CMD instructions are sequentially input to the refresh window signal generation circuit 120 and the clock pulse generation circuit 110, the clock pulse generation circuit 110 responds to the n Same Bank CMD instructions by outputting a second clock signal. The Same Bank refresh clock signal, SameBank CBR CLK, includes both the first clock signal and the second clock signal; the second clock signal is a pulse signal, while the first clock signal remains low.

[0117] The clock pulse generation circuit 110 includes a counting circuit 111, a counting reset signal generation circuit 112, and a first pulse generation sub-circuit 113. The counting circuit 111 receives a first refresh instruction (Same Bank CMD) and a counting reset signal (Bank Counter Reset), and is used to count the first refresh instruction (Same Bank CMD) and output a counting signal (Bank Counter). The counting circuit 111 is reset according to the counting reset signal (Bank Counter Reset). The counting reset signal generation circuit 112 is coupled to the counting circuit 111 and the refresh window signal generation circuit 120, and is used to generate the counting reset signal (Bank Counter Reset) after the first refresh instruction (Same Bank CMD) is n and after the nth first refresh operation. The first pulse generation sub-circuit 113 is coupled to the counting reset signal generation circuit 112, and is used to generate a first clock signal according to the counting signal (Bank Counter) when the first refresh instruction (Same Bank CMD) is less than n, or to generate a second clock signal according to the counting reset signal (Bank Counter Reset) when the first refresh instruction (Same Bank CMD) is equal to n.

[0118] The refresh window signal generation circuit 120 includes n refresh window sub-signal generation circuits 121 and a refresh window sub-signal processing circuit 122. Each refresh window sub-signal generation circuit 121 receives a refresh window reset signal Refersh WindowReset and sequentially receives multiple first refresh instructions Same Bank CMD. The refresh window sub-signal generation circuit 121 outputs multiple refresh window sub-signals sequentially according to the first refresh instructions Same Bank CMD and the refresh window reset signal Refersh Window Reset. The refresh window sub-signal processing circuit 122 is coupled to the n refresh window sub-signal generation circuits 121 and is used to sequentially receive multiple refresh window sub-signals, perform logical operations on the refresh window sub-signals, and output the refresh window signal Refersh Window.

[0119] Since the memory has at least two refresh modes—same memory block refresh and full memory block refresh—the refresh address generation circuit provided in this embodiment is also used to output the full memory block refresh address. Based on this, the refresh control circuit 100 also receives a second refresh instruction All Bank CMD to perform a second refresh operation (full memory block refresh operation); wherein, multiple refresh window sub-signal generation circuits 121 simultaneously receive a second refresh instruction All Bank CMD and a refresh window reset signal Refersh Window Reset, and each refresh window sub-signal generation circuit 121 is used to generate the same refresh window sub-signal according to the second refresh instruction All Bank CMD and the second refresh window reset signal Refersh Window Reset. The refresh window sub-signal processing circuit 122 receives multiple refresh window sub-signals and performs logical operations on the refresh window sub-signals to output the refresh window signal Refersh Window.

[0120] Furthermore, the refresh control circuit 100 also includes: a second pulse generation sub-circuit 130, an internal refresh window signal generation circuit 140, a refresh window reset signal generation circuit 170, and an address command signal SB 2. nd ADDR CMD generation circuit 150, signal selection circuit 180, and address flag signal SB 2 nd ADDR flag generation circuit 160.

[0121] The second pulse generation sub-circuit 130 is coupled to the refresh window signal generation circuit 120 and is used to receive the refresh window signal Refresh Window and the address command signal SB2. nd ADDR CMD generates the first pulse of the third clock signal at the start of the first or second refresh operation, and according to the address command signal SB 2. nd The first pulse of ADDR CMD outputs the second pulse of the third clock signal, thereby outputting the third clock signal.

[0122] The internal refresh window signal generation circuit 140 is used to generate an internal refresh window signal Inner ACT Window based on a third clock signal, wherein the first pulse of the internal refresh window signal Inner ACT Window is generated after the first pulse of the third clock signal and ends before the second pulse of the third clock signal is generated, and the second pulse of the internal refresh window signal Inner ACT Window is generated after the second pulse of the third clock signal and ends before the pulse of the refresh window signal Refresh window ends.

[0123] Address command signal SB 2 ndThe ADDR CMD generation circuit 150 is coupled to the internal refresh window signal generation circuit 140, and the address command signal SB 2. nd The ADDR CMD generation circuit 150 is used to generate the address command signal SB 2 based on the valid level of the precharge signal Inner PRE CMD. nd The first and second pulses of ADDR CMD, address command signal SB 2 nd The first pulse of ADDR CMD is used to generate the second pulse of the internal refresh signal and the second pulse of the third clock signal. The effective level of the precharge signal Inner PRE CMD is the effective level generated in response to the falling edge of the internal refresh window signal Inner ACT Window.

[0124] The window refresh reset signal generation circuit 170 is coupled to the address flag signal SB 2. nd The ADDR flag generation circuit 160 and n refresh window sub-signal generation circuits 121, and the refresh window reset signal generation circuit 170 receive the precharge signal InnerPRE CMD and are used to generate the refresh window reset signal Refresh Window Reset pulse based on the falling edge of the second pulse of the precharge signal InnerPRE CMD.

[0125] The signal selection circuit 180 is coupled to the counting circuit 111, the first pulse generation sub-circuit 113, and the second pulse generation sub-circuit 130. It is used to output a first clock signal or a second clock signal from the counting signal Bank Couter when the refresh control circuit 100 performs a first refresh operation, or to output a third clock signal from the counting signal Bank Couter when the refresh control circuit 100 performs a second refresh operation. Address flag signal SB 2 nd The ADDR flag generation circuit 160 is coupled to the address command signal SB 2. nd ADDR CMD generation circuit 150, address flag signal SB 2 nd ADDR flag generation circuit 160 is used to generate the address command signal SB 2. nd The address flag signal SB2 is generated on the first rising edge of ADDR CMD. nd The rising edge of the ADDR flag generates the address flag signal SB2 based on the falling edge of the Refresh Window signal. nd The falling edge of the ADDR flag.

[0126] Address generator 200 includes an address counter 210 and an address processing circuit 220. Address counter 210 pre-stores a first address and is coupled to a signal selection circuit 180. It is used to change the first address to a third address according to a second clock signal, or to change the first address according to a third clock signal and sequentially output a fourth and fifth address, where the first, fourth, and fifth addresses are three consecutive addresses. Address processing circuit 220 is connected to address counter 210 and refresh window sub-signal generation circuit 121, and is used to receive address flag signal SB2 during the first refresh operation performed by refresh control circuit 100. nd ADDRflag is retrieved, and the first address is obtained, in the address flag signal SB2. nd The first address is output before the rising edge of the ADDR flag arrives, or, on the address flag signal SB2... nd The second address is output after the rising edge of the ADDR flag arrives. The address processing circuit 220 is also used to sequentially obtain the fourth address and the fifth address when the refresh control circuit 100 performs the second refresh operation, and to sequentially output the fourth address and the fifth address according to the multiple refresh window sub-signals.

[0127] The address processing circuit 220 includes an address arithmetic circuit 221 and an address selection circuit 222. The address arithmetic circuit 221 is coupled to an address counter 210, and the address arithmetic unit is used to perform addition or subtraction operations on a first address to obtain a second address. The address selection circuit 222 is coupled to the address counter 210, the address arithmetic circuit 221, and the refresh window sub-signal generation circuit 121, and is used to select the address when receiving the first refresh instruction Same Bank CMD and the address flag signal SB2. nd When the ADDR flag is low, the first address is output and the address flag signal SB2 is active. nd When the ADDR flag is high, the second address is output; or when the second refresh instruction All Bank CMD is received, the fourth and third addresses are output sequentially according to the multiple refresh window sub-signals.

[0128] The counting circuit 111 includes: n first inverters PI1 and n first latches RS1. Each first inverter PI1 receives a first refresh instruction Same Bank CMD. The set terminals of the n first latches RS1 are respectively connected to a first inverter PI1. The reset terminals of the n first latches RS1 are configured to receive a count reset signal Bank Count Reset. The output terminals of the n first latches RS1 are configured to output a count signal Bank Count. When the number of first refresh operations is equal to a preset value, the count reset signal Bank Count Reset resets the n first latches RS1.

[0129] In this circuit, the first latch RS1 can be an RS latch, and n first latches RS1 are connected in parallel. The first refresh instruction, Same Bank CMD, can be output through a refresh instruction output circuit, which can have n output terminals, each outputting one first refresh instruction, Same Bank CMD. The set terminal of each first latch RS1 is connected to the output terminal of a refresh instruction output circuit through a first inverter PI1. The output terminal of the first latch RS1 refers to the output terminal corresponding to the set terminal of the first latch RS1.

[0130] For example, the first refresh instruction Same Bank CMD can be a high-level pulse signal, which is converted to a low-level signal after passing through the first inverter PI1. This low-level signal is then transmitted to the corresponding first latch RS1.

[0131] For example, the refresh instruction output circuit outputs the first refresh instruction Same Bank CMD to the first first latch RS1 at time t1, and the same instruction to the second first latch RS1 at time t2, until the refresh instruction output circuit outputs the first refresh instruction Same Bank CMD to the nth first latch RS1 at time tN. Upon receiving the trigger edge of the first refresh instruction Same Bank CMD, the first latch RS1 outputs a counting signal Bank Counter. The n first latches RS1 sequentially receive the first refresh instruction Same Bank CMD and sequentially output the counting signal Bank Counter. For instance, after receiving the corresponding first refresh instruction Same Bank CMD, the first latch RS1 outputs a high-level signal.

[0132] The counting reset signal generation circuit 112 includes: a first AND gate AG1, a second inverter PI2, a second AND gate AG2, a first delay D1, a third inverter PI3, a third AND gate AG3, and a fourth inverter PI4. The input of the first AND gate AG1 receives the counting signal Bank Counter. The input of the second inverter PI2 is connected to the refresh window signal generation circuit 120 to invert the refresh window signal Refresh Window. The input of the second AND gate AG2 is connected to the output of the first AND gate AG1 and the output of the second inverter PI2. The input of the first delay D1 is connected to the output of the second AND gate AG2. The input of the third inverter PI3 is connected to the output of the first delay D1. The input of the third AND gate AG3 is connected to the output of the second AND gate AG2 and the output of the third inverter PI3. The outputs of the fourth inverter PI4 and the third AND gate AG3 are connected to output the counting reset signal Bank Counter Reset.

[0133] The first AND gate AG1 can have n inputs, and each input of the first AND gate AG1 is connected to a first latch RS1. The first AND gate AG1 performs an AND operation on the counting signals Bank Count output by the n first latches RS1. For example, when all n first latches RS1 output the counting signal Bank Count (high level signal), the first AND gate AG1 outputs a high level signal.

[0134] The input of the second inverter PI2 is connected to the output of the refresh window signal generation circuit 120. The refresh window signal generation circuit 120 outputs a refresh window signal, Refersh Window, and the second inverter PI2 is used to invert the refresh window signal Refersh Window. The second AND gate AG2 has two inputs, which are respectively connected to the output of the first AND gate AG1 and the output of the second inverter PI2.

[0135] The first delay unit D1 delays the signal output by the second AND gate AG2 by a first preset time. The third inverter PI3 inverts the signal output by the first delay unit D1. The third AND gate AG3 receives the signal output by the second AND gate AG2 and the signal output by the third inverter PI3, respectively, and performs an AND operation on the two signals to form a first pulse signal.

[0136] The input of the fourth inverter PI4 is connected to the third AND gate AG3, and the output of the fourth inverter PI4 outputs the count reset signal Bank Count Reset. That is, the first pulse signal is transmitted to the fourth inverter PI4, and the first pulse signal passes through the fourth inverter PI4 to obtain the count reset signal Bank Count Reset. The output of the fourth inverter PI4 is connected to the reset terminal of the first latch RS1. When the first latch RS1 receives the trigger edge of the count reset signal Bank Count Reset, the output of the first latch RS1 is reset.

[0137] For example, the Bank Counter Reset signal outputs a low-level signal at time t5. At this time, the reset terminal of the first latch RS1 receives a low-level signal, and the set terminal of the first latch RS1 receives a high-level signal. Therefore, after time t5, the output terminal of the first latch RS1 outputs a low-level signal, realizing the reset of the output terminal.

[0138] The first pulse generation sub-circuit 113 includes: a second delay D2, a third delay D3, and a first OR gate OG1. The input of the second delay D2 is connected to the output of the third AND gate AG3; the input of the third delay D3 is connected to the output of the second delay D2; the input of the first OR gate OG1 is connected to the output of the third AND gate AG3 and the output of the third delay D3, respectively. The output of the first OR gate OG1 outputs a first clock signal according to the counting signal BankCouter when the first refresh instruction Same Bank CMD is less than n, or outputs a second clock signal according to the counting reset signal BankCouter Reset when the first refresh instruction Same Bank CMD is equal to n.

[0139] In this circuit, the second delay unit D2 is connected to the output of the third AND gate AG3. After the first pulse signal passes through the second delay unit D2, it is delayed by a second preset time to obtain the second pulse signal. The second pulse signal is then transmitted to the third delay unit D3 and the first OR gate OG1. The second pulse signal passes through the third delay unit D3 to obtain the third pulse signal, which is then transmitted to the first OR gate OG1. The second pulse signal and the second pulse signal are then ORed to obtain the second clock signal.

[0140] Address command signal SB 2 ndThe ADDR CMD generation circuit 150 includes a fifth inverter PI5, a fourth delay circuit D4, and a fourth AND gate AG4. The input of the fifth inverter PI5 receives the pre-charge signal Inner PRE CMD; the input of the fourth delay circuit D4 is connected to the output of the fifth inverter PI5; the input of the fourth AND gate AG4 is connected to the outputs of both the fifth inverter PI5 and the fourth delay circuit D4, outputting the address command signal SB2. nd ADDR CMD.

[0141] The inner refresh window signal, Inner ACT Window, can be determined by the inner refresh window signal generation circuit 140. For example, the inner refresh window signal generation circuit 140 generates the inner refresh window signal Inner ACT Window, which is transmitted to the memory block control circuit 300. The memory block control circuit 300 responds to the inner refresh window signal Inner ACT Window by generating a precharge signal Inner PRE CMD, and refreshes the memory block according to the inner refresh window signal Inner ACT Window and the address to be refreshed. The inner refresh window signal Inner ACT Window has two pulses, and the precharge signal Inner PRE CMD is formed on the falling edge of the two pulses of the inner refresh window signal Inner ACT Window. The precharge signal Inner PRE CMD is inverted after passing through the fifth inverter PI5, and delayed for a fourth preset time after passing through the fourth delay timer D4. These two signals are then passed through the fourth AND gate AG4 to obtain the address command signal SB 2. nd The first and second pulses of ADDR CMD.

[0142] Address flag signal SB 2 nd The ADDR flag generation circuit 160 includes: a sixth inverter PI6 and a second latch RS2. The input of the sixth inverter PI6 is connected to the output of the fourth AND gate AG4; the set input of the second latch RS2 is connected to the output of the sixth inverter PI6, and the second latch RS2 outputs the address flag signal SB2. nd ADDR flag.

[0143] Among them, the sixth inverter PI6 receives the address command signal SB2. nd ADDR CMD, the sixth inverter PI6 corresponds to the address command signal SB 2. nd ADDR CMD is reversed, and the reversed address command signal SB 2 ndADDR CMD is transmitted to the set input of the second latch RS2. The reset input of the second latch RS2 receives the refresh window signal Refersh window, and the inverted address command signal SB 2 of the second latch RS2 is also received. nd Output address flag signal SB2 when the trigger edge of ADDR CMD arrives. nd The ADDR flag is reset when the Refresh Window signal (Refersh Window) is triggered.

[0144] The refresh window reset signal generation circuit 170 includes: a fifth AND gate AG5, a sixth delay circuit D6, and a tenth inverter PI10. The input of the fifth AND gate AG5 receives the signal output from the second latch RS2 and the precharge signal Inner PRECMD, respectively. An intermediate pulse signal is generated based on the falling edge of the second pulse of the precharge signal Inner PRECMD. The input of the sixth delay circuit D6 is connected to the output of the fifth AND gate AG5. The tenth inverter PI10 is connected to the output of the sixth delay circuit D6. The intermediate pulse signal is generated by the sixth delay circuit D6 and the tenth inverter PI10 to generate the pulse of the refresh window reset signal Refresh WindowReset.

[0145] A fifth delay circuit D5 can also be provided between the fifth AND gate AG5 and the second latch RS2. The fifth delay circuit D5 is used to adjust the address flag signal SB2. nd The ADDR flag is set to delay for the fifth preset time.

[0146] The refresh window sub-signal generation circuit 121 includes: a first NOR gate NOG1 and a third latch RS3. The input of the first NOR gate NOG1 receives the first refresh instruction Same Bank CMD and the second refresh instruction All Bank CMD, respectively. The set terminal of the third latch RS3 is connected to the output terminal of the first NOR gate NOG1, the reset terminal of the third latch RS3 is connected to the output terminal of the tenth inverter PI10, and the output terminal of the third latch RS3 outputs the refresh window sub-signal.

[0147] Specifically, when the first NOR gate NOG1 receives the first refresh instruction Same Bank CMD, the third latch RS3 outputs a refresh window sub-signal based on the signal output by the first NOR gate NOG1 in response to the first refresh instruction Same Bank CMD and the refresh window reset signal Refersh Window Reset.

[0148] The refresh window sub-signal processing circuit 122 includes a third OR gate OG3. The input of the third OR gate OG3 is connected to the output of multiple third latches RS3 to output the refresh window signal Refresh Window.

[0149] The third OR gate OG3 has n inputs, each connected to a third latch RS3. When a refresh window sub-signal is received at any input of the third OR gate OG3, the third OR gate OG3 outputs the effective level of the refresh window signal Refersh Window.

[0150] The second pulse generation sub-circuit 130 includes: a seventh delay circuit D7, a seventh inverter PI7, a sixth AND gate AG6, an eighth inverter PI8, a seventh AND gate AG7, a second NOR gate NOG2, and a ninth inverter PI9. The input of the seventh delay circuit D7 is connected to the refresh window signal generation circuit 120 to receive the refresh window signal "Refersh Window". The input of the seventh inverter PI7 is connected to the output of the seventh delay circuit D7. The input of the sixth AND gate AG6 is connected to both the refresh window signal generation circuit 120 and the output of the seventh inverter PI7. The input of the eighth inverter PI8 is connected to the address flag signal SB2. nd ADDRflag generation circuit 160; the input of the seventh AND gate AG7 is connected to the output of the eighth inverter PI8 and the address command signal SB2, respectively. nd ADDR CMD generation circuit 150; the input of the second NOR gate NOG2 is connected to the output of the sixth AND gate AG6 and the output of the seventh AND gate AG7 respectively; the input of the ninth inverter PI9 is ​​connected to the output of the second NOR gate NOG2, and the output of the ninth inverter PI9 is ​​connected to the signal selection circuit 180.

[0151] The refresh window signal, Refersh window, is transmitted to the seventh delay unit D7 and the sixth AND gate AG6. The seventh delay unit D7 delays the Refersh window signal for a seventh preset time, and the seventh inverter PI7 inverts the delayed Refersh window signal. The signal output from the seventh inverter PI7 and the Refersh window signal are then passed through the sixth AND gate AG6 to obtain the fifth pulse signal, Inner 1. st ACT CMD. The eighth inverter PI8 receives the signal output from the fifth delay D5 and inverts it. The seventh AND gate AG7 receives the address command signal SB2 output from the eighth inverter PI8 and the fourth AND gate AG4. nd ADDR CMD generates the sixth pulse signal. The fifth pulse signal is Inner1. st The ACT CMD and the sixth pulse signal are passed through the second NOR gate NOG2 to obtain the seventh pulse signal, and the seventh pulse signal is passed through the ninth inverter PI9 to form the third clock signal.

[0152] The internal refresh window signal generation circuit 140 includes a fourth latch RS4. The set terminal of the fourth latch RS4 is connected to the output terminal of the second NOR gate NOG2, and the reset terminal of the fourth latch RS4 is connected to the address command signal SB2. nd The ADDR CMD generation circuit 150 generates the inner refresh window signal Inner ACT Window based on the third clock signal.

[0153] The signal selection circuit 180 includes a third NOR gate NOG3, a second OR gate OG2, and an eighth AND gate AG8. The input of the third NOR gate NOG3 receives the counting signal Bank Counter. The input of the second OR gate OG2 is connected to the first pulse generation circuit and the second pulse generation circuit, respectively. The input of the eighth AND gate AG8 is connected to the output of the third NOR gate NOG3 and the output of the second OR gate OG2, respectively. The output of the eighth AND gate AG8 is connected to the address generator 200.

[0154] The input of the third NOR gate NOG3 is connected to the output of each of the n first latches RS1. NOG3 receives signals from the n first latches RS1. In the same memory block refresh mode, NOG3 responds to the counting signal Bank Couter and outputs a valid signal after the counting circuit 111 receives a preset number of first refresh instructions (Same Bank CMD). In the full memory block refresh mode, the n first latches output low-level signals, and NOG3 continuously outputs a valid signal. The input of the second OR gate OG2 is connected to the output of the first OR gate OG1 and the output of the ninth inverter PI9. The input of the eighth AND gate AG8 is connected to the output of the third NOR gate NOG3 and the output of the second OR gate OG2. In the same memory block refresh mode, AG8 shields the third clock signal, that is, in the same memory block refresh mode, AG8 shields the signal output by the second pulse generation sub-circuit 130 and outputs either the first clock signal or the second clock signal to the address generator 200 according to the counting signal Bank Couter.

[0155] Address counter 210 is connected to the eighth AND gate AG8. When the memory is operating in the same memory block refresh mode, address counter 210 maintains its output address (first address) in response to the first clock signal and changes its output address (third address) in response to the second clock signal. When the memory is operating in full memory block refresh mode, address counter 210 changes its output address (fourth address and fifth address) in response to the third clock signal.

[0156] The address selection circuit 222 includes: a ninth AND gate AG9, an eleventh inverter PI11, a fourth NOR gate NOG4, and a multiplexer 21. The input of the ninth AND gate AG9 is connected to multiple refresh window sub-signal generation circuits 121. The input of the eleventh inverter PI11 is connected to an address identifier signal generation circuit to receive the address identifier signal. The input of the fourth NOR gate NOG4 is connected to the output of the ninth AND gate AG9 and the output of the eleventh inverter PI11. The multiplexer 21 is connected to the address counter 210, the address arithmetic circuit 221, and the fourth NOR gate NOG4, and is used to respond to the signal output by the fourth NOR gate NOG4 during the first refresh operation by outputting either the first address or the second address (outputting the first address on the first rising edge of the address identifier signal and the second address on the second rising edge of the address identifier signal). Alternatively, during the second refresh operation, it outputs either the fourth address or the fifth address (outputting the fourth address and the fifth address sequentially once on the rising edge of each refresh window sub-signal).

[0157] Address calculation circuit 221 may include an adder connected to address counter 210 and address selection circuit 222. The adder performs an addition operation on the address n output by address counter 210 to obtain address n+1, and transmits the result to address selection circuit 222. Alternatively, address calculation circuit 221 may include a subtractor connected to address counter 210 and address selection circuit 222. The subtractor performs a subtraction operation on the address n output by address counter 210 to obtain address n-1, and transmits the result to address selection circuit 222.

[0158] In this embodiment, the first preset time of the first delay unit D1 can be 1 nanosecond, the second preset time of the second delay unit D2 can be 2 nanoseconds, the third preset time of the third delay unit D3 can be 5 nanoseconds, the fourth preset time of the fourth delay unit D4 can be 1 nanosecond, the fifth preset time of the fifth delay unit D5 can be 1 nanosecond, the sixth preset time of the sixth delay unit D6 can be 5 nanoseconds, and the seventh preset time of the seventh delay unit D7 can be 2 nanoseconds. Of course, in practical applications, the delay time of each delay unit can also be other times determined according to the timing of the refresh address generation circuit, and this embodiment is not limited to this.

[0159] The following is combined with Figure 6The timing diagram shown illustrates the refresh address generation circuit provided in this embodiment, with N=4. Except for the first refresh instruction Same Bank CMD, the counter signal Bank Counter, the counter reset signal BankCounter Reset, and the Same Bank refresh clock signal Same Bank CBR CLK, all signals are shown as waveforms over four cycles. If each cycle's waveform includes two valid pulses, the valid pulse occurring earlier in the timing sequence is the first pulse, and the valid pulse occurring later in the timing sequence is the second pulse. The signal waveforms in subsequent figures are also divided according to a similar rule, which will not be repeated hereafter.

[0160] In the same memory block refresh mode, such as Figure 6 As shown, the counting circuit 111 and the refresh window signal generation circuit 120 sequentially receive the first refresh command Same Bank CMD at times t1, t2, t3, and t4. <0> Same Bank CMD <1> SameBank CMD <2> Same Bank CMD <3> The internal refresh window signal generation circuit 140 outputs the internal refresh window signal Inner ACT Window. The internal refresh window signal Inner ACT Window has falling edges at times t11, t12, t21, t22, t31, t32, t41, and t42. t11 and t12 are between t1 and t2, t21 and t22 are between t2 and t3, t31 and t32 are between t3 and t4, and t41 and t42 are after t4.

[0161] The first latch RS1 responds to the inverted first refresh instruction Same Bank CMD <0> The Bank Counting Signal is output after time t1. <0> The second first latch RS1 responds to the inverted first refresh instruction SameBank CMD <1> The counting signal Bank Counter is output after time t2. <1> The third first latch RS1 responds to the inverted first refresh instruction Same Bank CMD <2> The counting signal BankCouterBankCouter is output after time t3. <2> The fourth latch RS1 responded to the inverted first refresh instruction Same Bank CMD <3> The counting signal Bank Counter is output after time t4. <3> .

[0162] The first third latch RS3 responds to the inverted first refresh instruction Same Bank CMD <0> Output the refresh window sub-signal SBREF_WIN <0> The second and third latches RS3 respond to the inverted first refresh instruction Same Bank CMD <1> Output the refresh window sub-signal SBREF_WIN <1> The third latch RS3 responds to the inverted first refresh instruction Same Bank CMD <2> Output the refresh window sub-signal SBREF_WIN <2> The fourth third latch RS3 responded to the inverted first refresh instruction Same Bank CMD <3> Output the refresh window sub-signal SBREF_WIN <3> Furthermore, the third latch RS3 is reset in response to the Refresh Window Reset signal.

[0163] After passing through the fifth inverter PI5, the fourth delay unit D4, and the fourth AND gate AG4, the precharge signal Inner PRE CMD generates the address command signal SB2 at times t13, t14, t23, t24, t33, t34, t43, and t44. nd ADDR CMD. Address command signal SB 2 nd ADDR CMD generates the address flag signal SB2 via the sixth inverter PI6 and the second latch RS2. nd ADDR flag. Address flag signal SB 2 nd The ADDR flag is transmitted to the fifth AND gate AG5 via the fifth delay unit D5. The fifth AND gate AG5 receives the delayed address flag signal SB2. nd The ADDR flag and the precharge signal Inner PRE CMD, the signal output from the fifth AND gate AG5, are used by the sixth delay D6 and the tenth inverter PI10 to generate the refresh window reset signal Refresh window reset at times t15, t25, t35 and t45.

[0164] The n refresh window signal generation circuits 121 respectively receive Same Bank CMD signals. <0> Same Bank CMD <1> Same Bank CMD <2> Same Bank CMD <3> The refresh window sub-signal processing circuit 122 receives multiple refresh window sub-signals SBREF_WIN sequentially, performs logical operations on them, and outputs the refresh window signal Refresh Window at times t1, t2, t3, and t4.

[0165] The first AND gate AG1 receives the counting signals "Bank Couuter" output from four first latches RS1, and outputs a first intermediate signal at time t4. The second AND gate AG2 receives the first intermediate signal and the inverted refresh window signal "Refersh Window", and outputs a second intermediate signal. The second intermediate signal passes through the first delay unit D1, the third inverter PI3, and the third AND gate AG3, and outputs a first pulse signal at time t5. The first pulse signal passes through the second delay unit D2, the third delay unit D3, and the first OR gate OG1 to generate a second clock signal, which has two pulses. After passing through the fourth inverter PI4, the first pulse signal outputs the counting reset signal "Bank Couuter Reset".

[0166] The second clock signal is transmitted to the address counter 210, which generates a new refresh address in response to the second clock signal. When the second clock signal has two pulses, the address counter 210 can jump between two addresses. For example, if the addresses of the same memory block were previously refreshed (0000 and 0001), where 0000 is the output of the address counter 210 and 0001 is the output of the address processing circuit 220, then upon receiving the second clock signal, the address counter 210 can jump from 0000 to 0010. For example, the first and second clock signals can be... Figure 6 As shown in Same Bank CBR CLK, the first clock signal is low and the second clock signal is a pulse signal.

[0167] The third NOR gate NOG3 receives BankCouter <0> BankCouter <1> BankCouter <2> and BankCouter <3> The output level is valid after time t5. Signals output before time t5 can be masked by the eighth AND gate AG8 and the third NOR gate NOG3. This prevents premature refresh address changes during the same memory block refresh mode, thus maintaining the refresh address during the same memory block refresh.

[0168] It should be noted that, in this embodiment, a refresh operation refers to the period from when the refresh control circuit 100 starts with the first refresh instruction Same Bank CMD until it outputs the count reset signal Bank Count Reset. Furthermore, when the refresh control circuit 100 outputs the count reset signal Bank Count Reset, it is determined that the number of refresh operations has reached a preset value.

[0169] In full memory block refresh mode, the signals received at all four inputs of the counting circuit 111 are low-level signals, and the outputs of the four first latches RS1 are low-level signals. The inputs of the n refresh window sub-signal generation circuits 121 receive the second refresh instruction All Bank CMD.

[0170] The refresh window signal, RefershWindow, passes through the seventh delay D7, the seventh inverter PI7, and the sixth AND gate AG6, outputting the fifth pulse signal Inner 1 at times t1, t2, t3, and t4 respectively. st ACT CMD. Address flag signal SB 2 nd The ADDRflag signal is used by the fifth delay unit D5 and the eighth inverter PI8 to generate the third intermediate signal. This third intermediate signal and the address command signal SB2 are then used together. nd ADDR CMD generates a sixth pulse signal at times t11, t21, t31, and t41 via the seventh AND gate AG7. This sixth pulse signal and the fifth pulse signal, Inner 1, are then processed. st The ACT CMD signal generates a third clock signal through the second NOR gate NOG2 and the ninth inverter PI9.

[0171] In the same memory block refresh mode, the third NOR gate NOG3 continuously outputs a high-level signal, and the first pulse generation sub-circuit 113 continuously outputs a low-level signal. Therefore, the second OR gate OG2 outputs the third clock signal, and the eighth AND gate AG8 outputs the third clock signal. The third clock signal includes four sets of pulse signals, each set of pulse signals including two pulses.

[0172] The third clock signal is transmitted to the address counter 210. The address counter 210 generates a new refresh address in response to the third clock signal. When each group of third clock signals has two pulses, the address counter 210 can jump to two addresses. For example, if the current refresh address is n (output by address counter 210) and n+1 (output by address processing circuit 220), the address counter will change the refresh address to n+2 (output by address counter 210) and n+3 (output by address processing circuit 220) in response to the third clock signal.

[0173] The refresh address generation circuit provided in this embodiment includes a refresh control circuit 100 and an address generator 200. The refresh control circuit 100 sequentially receives multiple first refresh instructions (Same Bank CMD) and performs first refresh operations on each. When the number of first refresh operations is less than a preset value, it outputs a first clock signal. When the number of first refresh operations is equal to the preset value n, it outputs a second clock signal. The address generator 200 is coupled to the refresh control circuit 100, pre-stores a first address, and receives either the first clock signal or the second clock signal. During each first refresh operation, the address generator 200 outputs a first address to be refreshed in response to the first clock signal. The first address to be refreshed includes the first address. The address generator 200 changes the first address in response to the second clock signal. This enables the provision of refresh addresses to the memory in the same memory block refresh mode. Furthermore, when refreshing the same memory block, if multiple memory blocks have not all refreshed their current addresses, the address can be maintained, avoiding address jumps during refresh. The refresh address generation circuit can also provide refresh addresses for the entire memory block refresh mode, enabling the sharing of refresh address generation circuits, which helps save memory layout space and production costs.

[0174] This exemplary embodiment also provides a refresh address generation method for the circuit described above, the method being used in the same memory block refresh mode, such as... Figure 7 As shown, the method for generating the refresh address includes the following steps:

[0175] Step S710: Obtain the number of times the refresh control circuit performs the first refresh operation upon receiving the first refresh command;

[0176] Step S720: When the number of first refresh operations performed by the refresh control circuit is less than a preset number, the control address generator maintains its output address.

[0177] In step S730, when the number of first refresh operations performed by the refresh control circuit is equal to the preset number value, the control address generator changes the address it outputs.

[0178] The refresh address generation method provided in this embodiment obtains the number of first refresh instructions (Same Bank CMD) received by the refresh control circuit 100. When the number of first refresh operations performed by the refresh control circuit 100 is less than a preset value, the control address generator 200 maintains its output address. When the number of first refresh operations performed by the refresh control circuit 100 is equal to the preset value, the control address generator 200 changes its output address. Furthermore, when refreshing the same memory block, address retention can be achieved when multiple memory blocks have not all been refreshed to their current addresses, avoiding address jumps during refresh. The refresh address generation circuit can also provide refresh addresses for a full memory block refresh mode, enabling the sharing of refresh address generation circuitry, which is beneficial for saving memory layout space and production costs.

[0179] Furthermore, such as Figure 8 As shown, the refresh address generation method provided in this embodiment may further include:

[0180] Step S740: When the refresh control circuit receives the second refresh instruction, it controls the address generator to output the full memory block refresh address.

[0181] It should be noted that the implementation method of the refresh address generation circuit in this embodiment has been described in detail in the circuit section, and will not be repeated here.

[0182] The steps of the refresh address generation method provided in this embodiment are described in detail below:

[0183] In step S710, the number of first refresh instructions Same Bank CMD received by refresh control circuit 100 can be obtained.

[0184] The counting of the first refresh instruction can be achieved through a counting circuit, a counting reset signal generation circuit, and a first pulse generation sub-circuit.

[0185] In the same memory block refresh mode, such as Figure 6As shown, the counting circuit 111 and the refresh window signal generation circuit 120 sequentially receive the first refresh command Same Bank CMD at times t1, t2, t3, and t4. <0> Same Bank CMD <1> SameBank CMD <2> Same Bank CMD <3> The internal refresh window signal generation circuit 140 outputs the internal refresh window signal Inner ACT Window. The internal refresh window signal Inner ACT Window has falling edges at times t11, t12, t21, t22, t31, t32, t41, and t42. t11 and t12 are between t1 and t2, t21 and t22 are between t2 and t3, t31 and t32 are between t3 and t4, and t41 and t42 are after t4.

[0186] The first latch RS1 responds to the inverted first refresh instruction Same Bank CMD <0> The Bank Counting Signal is output after time t1. <0> The second first latch RS1 responds to the inverted first refresh instruction SameBank CMD <1> The counting signal Bank Counter is output after time t2. <1> The third first latch RS1 responds to the inverted first refresh instruction Same Bank CMD <2> The counting signal BankCouter is output after time t3. <2> The fourth latch RS1 responded to the inverted first refresh instruction Same Bank CMD <3> The counting signal Bank Counter is output after time t4. <3> .

[0187] The first third latch RS3 responds to the inverted first refresh instruction Same Bank CMD <0> Output the refresh window sub-signal SBREF_WIN <0> The second and third latches RS3 respond to the inverted first refresh instruction Same Bank CMD <1> Output the refresh window sub-signal SBREF_WIN <1> The third latch RS3 responds to the inverted first refresh instruction Same Bank CMD <2> Output the refresh window sub-signal SBREF_WIN <2> The fourth third latch RS3 responded to the inverted first refresh instruction Same Bank CMD <3> Output the refresh window sub-signal SBREF_WIN <3> Furthermore, the third latch RS3 is reset in response to the Refresh Window Reset signal.

[0188] After passing through the fifth inverter PI5, the fourth delay unit D4, and the fourth AND gate AG4, the precharge signal Inner PRE CMD generates the address command signal SB2 at times t13, t14, t23, t24, t33, t34, t43, and t44. nd ADDR CMD. Address command signal SB 2 nd ADDR CMD generates the address flag signal SB2 via the sixth inverter PI6 and the second latch RS2. nd ADDR flag. Address flag signal SB 2 nd The ADDR flag is transmitted to the fifth AND gate AG5 via the fifth delay unit D5D5. The fifth AND gate AG5 receives the delayed address flag signal SB2. nd The ADDR flag and the precharge signal Inner PRE CMD, the signal output from the fifth AND gate AG5, are used by the sixth delay D6 and the tenth inverter PI10 to generate the refresh window reset signal Refresh Window Reset at times t15, t25, t35 and t45.

[0189] The n refresh window signal generation circuits 121 respectively receive Same Bank CMD signals. <0> Same Bank CMD <1> Same Bank CMD <2> Same Bank CMD <3> The refresh window sub-signal processing circuit 122 receives multiple refresh window sub-signals SBREF_WIN sequentially, performs logical operations on them, and outputs the refresh window signal Refresh window at times t1, t2, t3, and t4.

[0190] The first AND gate AG1 receives the counting signals "Bank Couuter" output from four first latches RS1, and outputs a first intermediate signal at time t4. The second AND gate AG2 receives the first intermediate signal and the inverted refresh window signal "Refersh Window", and outputs a second intermediate signal. The second intermediate signal passes through the first delay unit D1, the third inverter PI3, and the third AND gate AG3, and outputs a first pulse signal at time t5. The first pulse signal passes through the second delay unit D2, the third delay unit D3, and the first OR gate OG1 to generate a second clock signal, which has two pulses. After passing through the fourth inverter PI4, the first pulse signal outputs the counting reset signal "Bank Couuter Reset".

[0191] The second clock signal is transmitted to the address counter 210, which generates a new refresh address in response to the second clock signal. When the second clock signal has two pulses, the address counter 210 can jump between two addresses. For example, if the addresses of the same memory block were previously refreshed (0000 and 0001), where 0000 is the output of the address counter 210 and 0001 is the output of the address processing circuit 220, then during the current refresh of the same memory block, the address counter 210 can jump from 0000 to 0010. For example, the first clock signal and the second clock signal can be... Figure 6 As shown in Same Bank CBR CLK, the first clock signal is low and the second clock signal is high.

[0192] In step S720, when the number of first refresh instructions received by the refresh control circuit is less than a preset number, the control address generator maintains its output address.

[0193] Specifically, when the number of first refresh instructions received by the refresh control circuit is less than a preset value, the address counter and address processing circuit are used to maintain the output address.

[0194] For example, when the number of first refresh instructions is less than 4, the refresh control circuit outputs a first clock signal (low-level signal). The address counter responds to the first clock signal and keeps the signal output to the address processing circuit unchanged, so the address output by the address processing circuit remains unchanged.

[0195] In step S730, when the number of first refresh instructions received by the refresh control circuit 100 is equal to a preset number, the control address generator 200 changes its output address.

[0196] Specifically, when the number of first refresh instructions received by the refresh control circuit equals the preset number, the address counter and address processing circuit are used to change the output address.

[0197] For example, when the number of first refresh instructions is less than 4, the refresh control circuit 100 outputs a second clock signal (at least one high-level signal). This second clock signal is transmitted to the address counter, which generates a new refresh address in response to the second clock signal. When the second clock signal has two pulses, the address counter can jump between two addresses. For example, if the addresses of the previous refresh of the same memory block were 0000 and 0001, where 0000 is the output of the address counter and 0001 is the output of the address processing circuit, then during the current refresh of the same memory block, the address counter can jump from 0000 to 0010.

[0198] Third NOR gate receives BankCouter <0> BankCouter <1> BankCouter <2> and BankCouter <3> The output is valid after time t5, and the signals output before time t5 can be shielded by the eighth AND gate and the third NOR gate. This prevents the refresh address from changing prematurely when refreshing the same memory block, thus maintaining the refresh address during the refresh of the same memory block.

[0199] In step S740, when the refresh control circuit 100 receives the second refresh instruction All Bank CMD, the control address generator 200 changes the address it outputs.

[0200] In the full memory block refresh mode, the signals received by the four input terminals of the counting circuit 111 are all low-level signals, and the outputs of the four first latches RS1 are low-level signals. The input terminals of the n refresh window sub-signal generation circuits 121 receive the second refresh instruction All Bank CMD.

[0201] The refresh window signal, RefershWindow, passes through the seventh delay D7, the seventh inverter PI7, and the sixth AND gate AG6, outputting the fifth pulse signal Inner 1 at times t1, t2, t3, and t4 respectively. st ACT CMD. Address flag signal SB 2 nd The ADDRflag signal is used by the fifth delay unit D5 and the eighth inverter PI8 to generate the third intermediate signal. This third intermediate signal and the address command signal SB2 are then used together. nd ADDR CMD generates a sixth pulse signal at times t11, t21, t31, and t41 via the seventh AND gate AG7. This sixth pulse signal and the fifth pulse signal, Inner 1, are then processed. st The ACT CMD signal generates a third clock signal through the second NOR gate NOG2 and the ninth inverter PI9.

[0202] The third clock signal is transmitted to the address counter, which generates a new refresh address in response to the third clock signal. When each set of third clock signals has two pulses, the address counter can jump between two addresses. For example, if the addresses of the previous full memory block refresh were 0000 and 0001, where 0000 is the output of the address counter and 0001 is the output of the address processing circuit, then during the current full memory block refresh, the address counter can jump from 0000 to 0010.

[0203] The refresh address generation method provided in this embodiment obtains the number of first refresh operations performed by the refresh control circuit 100; outputs a first clock signal when the number of first refresh operations is less than a preset number, and outputs a second clock signal when the number of first refresh operations is equal to the preset number. The address generator 200 outputs the address to be refreshed according to the first clock signal and changes the first address according to the second clock signal. This achieves the provision of refresh addresses to the memory in the same memory block refresh mode, and when multiple memory blocks are not all refreshed at their current addresses during the same memory block refresh, it can maintain the address and avoid address jumps during refresh. Furthermore, the refresh address generation circuit can also provide refresh addresses for the full memory block refresh mode, realizing the sharing of the refresh address generation circuit, which is beneficial for saving memory layout space and production costs.

[0204] An exemplary embodiment of this disclosure also provides a memory including the refresh address generation circuit described above.

[0205] The refresh address generation circuit includes a refresh control circuit 100 and an address generator 200. The refresh control circuit 100 sequentially receives multiple first refresh instructions (Same Bank CMD) and performs a first refresh operation on each. When the number of first refresh operations is less than a preset value, it outputs a first clock signal. When the number of first refresh operations is equal to a preset value n, it outputs a second clock signal, where n is a positive integer greater than or equal to 1. The address generator 200 is coupled to the refresh control circuit 100, pre-stores a first address, and receives either the first clock signal or the second clock signal. The address generator 200 outputs a first address to be refreshed in response to the first clock signal. The first address to be refreshed includes a first address. After outputting the first address to be refreshed, the address generator 200 changes the first address in response to the second clock signal.

[0206] Furthermore, the memory provided in this embodiment may further include a memory cell array for storing data. The memory cell array can be connected to a control module 140, which controls the writing of data to the memory cells in the array. The refresh address of the memory cell can be provided by the refresh address generation circuit provided in this embodiment.

[0207] The memory has two refresh modes: a single-block refresh mode and a full-block refresh mode. In the single-block refresh mode, the same address in multiple memory blocks is refreshed sequentially. For example, for address 0000 in N memory blocks, address 0000 in each memory block is refreshed sequentially during the refresh. In the full-block refresh mode, the same address in multiple memory blocks is refreshed simultaneously. For example, for address 0000 in N memory blocks, address 0000 in each memory block is refreshed simultaneously during the refresh.

[0208] The memory provided in this embodiment can be a fifth-generation double-rate synchronous dynamic random access memory. Of course, in practical applications, the memory can also be other types of memory, such as a sixth-generation double-rate synchronous dynamic random access memory or a fourth-generation double-rate synchronous dynamic random access memory. This embodiment is not limited to these.

[0209] The memory provided in this embodiment includes a refresh address generation circuit. A refresh control circuit 100 and an address generator 200 are connected in the refresh address generation circuit. The refresh control circuit 100 receives a first refresh instruction (Same Bank CMD) and executes a first refresh operation. It is configured to output a first clock signal when the number of first refresh operations is less than a preset value, and to output a second clock signal when the number of first refresh operations equals the preset value. The address generator 200 maintains its output address according to the first clock signal and changes its output address according to the second clock signal. This achieves the provision of refresh addresses to the memory in the same memory block refresh mode, and when multiple memory blocks are not fully refreshed during the same memory block refresh, address retention is achieved, avoiding address jumps during refresh. Furthermore, the refresh address generation circuit can also provide refresh addresses for the entire memory block refresh mode, realizing the sharing of the refresh address generation circuit, which is beneficial for saving memory layout space and production costs.

[0210] This disclosure also provides an exemplary embodiment of an electronic device, which includes the aforementioned memory. The electronic device may be a mobile phone, tablet computer, personal computer, server, smartwatch, smart glasses, personal digital assistant, or in-vehicle computer, among other electronic devices.

[0211] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0212] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A refresh address generation circuit configured to provide an address of a memory to be refreshed, the memory being divided into multiple memory block groups, each memory block group containing n memory blocks, characterized in that, The refresh address generation circuit includes: A refresh control circuit is used to sequentially receive multiple first refresh instructions and perform first refresh operations respectively. When the number of first refresh operations is less than a preset number n, a first clock signal is output. When the number of first refresh operations is equal to the preset number n, a second clock signal is output. The n is a positive integer greater than or equal to 1. An address generator is coupled to the refresh control circuit and pre-stores a first address and receives the first clock signal or the second clock signal. During each of the first refresh operations, the address generator outputs a first address to be refreshed in response to the first clock signal. The first address to be refreshed includes the first address. The address generator also changes the first address in response to the second clock signal. The refresh control circuit includes: A refresh window signal generation circuit receives the first refresh instruction and a refresh window reset signal, and is used to generate a refresh window signal according to the first refresh instruction and the refresh window reset signal. The pulse duration of the refresh window signal is the window time for the refresh control circuit to perform one refresh operation. The refresh window reset signal is used to reset the refresh window signal generation circuit after one refresh operation is completed. A clock pulse generation circuit, coupled to the refresh window signal generation circuit, is used to generate the first clock signal before the number of the first refresh instructions received by the clock pulse generation circuit is less than or equal to n and the first refresh operation ends in the nth time, or to generate the second clock signal after the number of the first refresh instructions received by the clock pulse generation circuit is n and the refresh operation ends in the nth time. The clock pulse generation circuit includes: The counting circuit receives the first refresh instruction and the counting reset signal, and is used to count the first refresh instruction and output a counting signal. The counting circuit is reset according to the counting reset signal. A count reset signal generation circuit, coupled to the counting circuit and the refresh window signal generation circuit, is used to generate the count reset signal when there are n first refresh instructions and after the nth first refresh operation is completed. The first pulse generation sub-circuit, coupled to the counting reset signal generation circuit, is used to generate the first clock signal according to the counting signal when the first refresh instruction is less than n, or to generate the second clock signal according to the counting reset signal when the first refresh instruction is equal to n. The refresh window signal generation circuit includes: n refresh window sub-signal generation circuits, each of the refresh window sub-signal generation circuits receives a refresh window reset signal and sequentially receives a plurality of the first refresh instructions, and the refresh window sub-signal generation circuits sequentially output a plurality of refresh window sub-signals according to the first refresh instructions and the refresh window reset signal; A refresh window sub-signal processing circuit, coupled to n refresh window sub-signal generation circuits, is used to sequentially receive multiple refresh window sub-signals and perform logical operations on the refresh window sub-signals to output the refresh window signal; The refresh control circuit also receives a second refresh command to perform a second refresh operation; Among them, the plurality of refresh window sub-signal generation circuits simultaneously receive a second refresh instruction and a refresh window reset signal, and each refresh window sub-signal generation circuit is used to generate the same refresh window sub-signal according to the second refresh instruction and the second refresh window reset signal; The refresh window sub-signal processing circuit receives multiple refresh window sub-signals, performs logical operations on the refresh window sub-signals, and outputs the refresh window signal.

2. The refresh address generation circuit as described in claim 1, characterized in that, The refresh control circuit also includes: The second pulse generation sub-circuit is coupled to the refresh window signal generation circuit. It is used to receive the refresh window signal and the address command signal, generate the first pulse of the third clock signal when the first refresh operation or the second refresh operation begins, and output the second pulse of the third clock signal according to the first pulse of the address command signal, thereby outputting the third clock signal. An internal refresh window signal generation circuit is used to generate the internal refresh window signal according to the third clock signal, wherein the first pulse of the internal refresh window signal is generated after the first pulse of the third clock signal and ends before the second pulse of the third clock signal is generated, and the second pulse of the internal refresh window signal is generated after the second pulse of the third clock signal and ends before the pulse of the refresh window signal ends. The address command signal generation circuit is used to generate a first pulse and a second pulse of the address command signal based on the effective level of the precharge signal. The first pulse of the address command signal is used to generate a second pulse of the internal refresh signal and a second pulse of the third clock signal. The effective level of the precharge signal is an effective level generated in response to the falling edge of the internal refresh window signal. A refresh window reset signal generation circuit receives the precharge signal and generates the pulse of the refresh window reset signal based on the falling edge of the second pulse of the precharge signal.

3. The refresh address generation circuit as described in claim 2, characterized in that, The refresh control circuit also includes: A signal selection circuit, coupled to the counting circuit, the first pulse generation sub-circuit, and the second pulse generation sub-circuit, is used to output the first clock signal or the second clock signal when the refresh control circuit performs the first refresh operation, or to output the third clock signal according to the counting signal when the refresh control circuit performs the second refresh operation.

4. The refresh address generation circuit as described in claim 3, characterized in that, The refresh control circuit also includes: The address flag signal generation circuit is used to generate a rising edge of the address flag signal based on the first rising edge of the address command signal, and to generate a falling edge of the address flag signal based on the falling edge of the refresh window signal. The address generator includes: An address counter, which pre-stores the first address and is coupled to the signal selection circuit, is used to change the first address to a third address according to the second clock signal, or to change the first address according to the third clock signal and output a fourth address and a fifth address in sequence. The first address, the fourth address, and the fifth address are three consecutive addresses. The address processing circuit is connected to the address counter and the refresh window sub-signal generation circuit. It is used to receive the address flag signal and obtain the first address when the refresh control circuit performs the first refresh operation. It outputs the first address before the rising edge of the address flag signal arrives, or outputs the second address after the rising edge of the address flag signal arrives. The address processing circuit is further configured to, when the refresh control circuit performs the second refresh operation, sequentially acquire the fourth address and the fifth address, and sequentially output the fourth address and the fifth address according to the plurality of refresh window sub-signals.

5. The refresh address generation circuit as described in claim 4, characterized in that, The address processing circuit includes: An address arithmetic circuit is coupled to the address counter. The address arithmetic unit is used to perform addition or subtraction operations on the first address to obtain the second address. The address selection circuit is coupled to the address counter, the address calculation circuit and the refresh window sub-signal generation circuit, respectively. It is used to output the first address when the first refresh instruction is received and the address flag signal is low, and to output the second address when the address flag signal is high, or to output the fourth address and the fifth address sequentially according to the multiple refresh window sub-signals when the second refresh instruction is received.

6. The refresh address generation circuit as described in claim 1, characterized in that, The counting circuit includes: There are n first inverters, and each first inverter receives a first refresh instruction. There are n first latches, each with its set terminal connected to a first inverter. The reset terminals of the n first latches are configured to receive a count reset signal, and the output terminals of the n first latches are configured to output the count signal. When the number of the first refresh operation is equal to a preset value, the count reset signal resets the n first latches.

7. The refresh address generation circuit as described in claim 6, characterized in that, The counting reset signal generation circuit includes: A first AND gate, the input of which receives the counting signal; The second inverter, whose input is connected to the refresh window signal generation circuit, inverts the refresh window signal. The second AND gate has its input terminals connected to the output terminals of the first AND gate and the second inverter, respectively. A first delay unit, the input of which is connected to the output of the second AND gate; A third inverter, the input of which is connected to the output of the first delay unit; The third AND gate, the input of which is connected to the output of the second AND gate and the output of the third inverter respectively; A fourth inverter is connected to the output of the third AND gate to output the count reset signal.

8. The refresh address generation circuit as described in claim 7, characterized in that, The first pulse generation sub-circuit includes: A second delay unit, the input of which is connected to the output of the third AND gate; A third delay unit, the input of which is connected to the output of the second delay unit; The first OR gate has its input terminals connected to the output terminals of the third AND gate and the third delay unit, respectively. When the number of the first refresh instructions is less than n, the output terminal of the first OR gate outputs the first clock signal according to the counting signal, or when the number of the first refresh instructions is equal to n, the output terminal of the first OR gate outputs the second clock signal according to the counting reset signal.

9. The refresh address generation circuit as described in claim 4, characterized in that, The second pulse generation sub-circuit includes: A seventh delay unit, the input of which is connected to the refresh window signal generation circuit to receive the refresh window signal; The seventh inverter has its input terminal connected to the output terminal of the seventh delay unit; The input terminals of the sixth AND gate are respectively connected to the refresh window signal generation circuit and the output terminal of the seventh inverter; The eighth inverter, the input of which is connected to the address flag signal generation circuit; The seventh AND gate, the input of which is connected to the output of the eighth inverter and the address command signal generation circuit respectively; The input terminals of the second NOR gate are respectively connected to the output terminals of the sixth AND gate and the seventh AND gate; The ninth inverter has its input terminal connected to the output terminal of the second NOR gate, and its output terminal connected to the signal selection circuit.

10. The refresh address generation circuit as described in claim 9, characterized in that, The internal refresh window signal generation circuit includes: The fourth latch has its set terminal connected to the output terminal of the second NOR gate and its reset terminal connected to the address command signal generation circuit. The fourth latch is used to generate the internal refresh window signal based on the third clock signal.

11. The refresh address generation circuit as described in claim 10, characterized in that, The address command signal generation circuit includes: The fifth inverter receives a pre-charge signal at its input terminal; The fourth delay unit, the input of which is connected to the output of the fifth inverter; The fourth AND gate, whose input is connected to the output of the fifth inverter and the fourth delay, outputs an address command signal.

12. The refresh address generation circuit as described in claim 11, characterized in that, The address flag signal generation circuit includes: The input of the sixth inverter is connected to the output of the fourth AND gate; The second latch has its set terminal connected to the output terminal of the sixth inverter, and it outputs an address flag signal.

13. The refresh address generation circuit as described in claim 12, characterized in that, The refresh window reset signal generation circuit includes: The fifth AND gate receives the signal output by the second latch and the precharge signal at its input terminals, respectively. A sixth delay unit, the input of which is connected to the output of the fifth AND gate; The tenth inverter is connected to the output of the sixth delay unit and outputs the refresh window reset signal.

14. The refresh address generation circuit as described in claim 13, characterized in that, The refresh window sub-signal generation circuit includes: The first NOR gate receives the first refresh instruction and the second refresh instruction at its input terminals, respectively. The third latch has its set terminal connected to the output terminal of the first NOR gate, its reset terminal connected to the output terminal of the tenth inverter, and its output terminal outputs a refresh window sub-signal.

15. The refresh address generation circuit as described in claim 14, characterized in that, The refresh window sub-signal processing circuit includes: The third OR gate, whose input is connected to the output of a plurality of third latches, outputs the refresh window signal.

16. The refresh address generation circuit as described in claim 5, characterized in that, The address selection circuit includes: A ninth AND gate, the input terminals of which are respectively connected to multiple refresh window sub-signal generation circuits; The eleventh inverter has its input terminal connected to an address identifier signal generation circuit to receive the address identifier signal. The fourth NOR gate, the input of which is connected to the output of the ninth AND gate and the output of the eleventh inverter respectively; A multiplexer, connected to the address counter, the address arithmetic circuit, and the fourth NOR gate, is used to respond to the signal output by the fourth NOR gate when performing the first refresh operation with the first address or the second address; or when performing the second refresh operation with the fourth address or the third address.

17. The refresh address generation circuit as described in claim 3, characterized in that, The signal selection circuit includes: The third NOR gate, the input of which receives the counting signal; The second OR gate has its input terminals connected to the first pulse generation circuit and the second pulse generation circuit, respectively. The eighth AND gate has its input terminals connected to the output terminals of the third NOR gate and the second OR gate, respectively, and its output terminal is connected to the address generator.

18. A method for generating a refresh address, characterized in that, For a circuit according to any one of claims 1-17, the method is used in the same memory block refresh mode, the method comprising: The number of times the first refresh operation is performed by the refresh control circuit upon receiving the first refresh command; When the number of times the refresh control circuit performs the first refresh operation is less than a preset number, the control address generator maintains its output address. When the number of times the refresh control circuit performs the first refresh operation equals a preset value, the control address generator changes the address it outputs.

19. The refresh address generation method as described in claim 18, characterized in that, The method further includes: When the refresh control circuit receives the second refresh instruction, it controls the address generator to output the full memory block refresh address.

20. A memory, characterized in that, The memory includes the refresh address generation circuit according to any one of claims 1-17.

21. An electronic device, characterized in that, The electronic device includes the memory as described in claim 20.

Images