Memory device and method of operation thereof

Abstract

This document provides a memory device and a method of operating the same. The memory device may include a plurality of memory cell strings, peripheral circuitry, and an operation controller. The peripheral circuitry is configured to use a plurality of read voltages to perform a read operation to read data stored in selected memory cells, which are included in a selected memory cell string. The operation controller is configured to control the peripheral circuitry to: perform a read operation using a first read voltage; perform a first potential adjustment operation using a second read voltage lower than the first read voltage; and perform the read operation again. The first potential adjustment operation involves: applying a first on-state voltage to an unselected source select line coupled to an unselected memory cell string for a first time period, and thereafter applying a ground voltage to the unselected source select line.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2022-0069740, filed on June 8, 2022, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Various embodiments of this disclosure relate to an electronic device, and more particularly to a memory device and a method of operating the memory device. Background Technology

[0004] Because 3D memory devices are designed with a multi-memory cell string structure to improve memory cell integration, the following problem arises: 3D memory devices are susceptible to read interference, in which the threshold voltage of the memory cells changes during read operations. As a solution to overcome this, an operation to initialize the channel potential is performed between multiple read operations. Another solution is to increase the channel potential before performing a read operation by turning off the transistors coupled to the unselected drain select line and the unselected source select line of the unselected memory cell string before reading the data stored in the memory cell. However, when the channel potential increases, soft erase may occur, in which the charge in the memory cells included in the unselected memory cell string is lost during the read operation. Therefore, it is necessary to decrease the channel potential during the read operation to improve this soft erase phenomenon. Summary of the Invention

[0005] One embodiment of this disclosure may provide a memory device. The memory device may include: a plurality of memory cell strings, each memory cell string including a plurality of memory cells coupled between a drain select line and a source select line; peripheral circuitry configured to perform a read operation using a plurality of read voltages to read data stored in selected memory cells, the selected memory cells being included in a selected memory cell string among the plurality of memory cell strings; and an operation controller configured to control the peripheral circuitry to perform a read operation by using a first read voltage among the plurality of read voltages, performing a first potential adjustment operation after performing the read operation, and performing a read operation by using a second read voltage lower than the first read voltage after performing the first potential adjustment operation, wherein the first potential adjustment operation involves: applying a first on-state voltage to an unselected source select line coupled to an unselected memory cell string among the plurality of memory cell strings for a first time period, and thereafter applying a ground voltage to the unselected source select line.

[0006] One embodiment of this disclosure provides a method for operating a memory device that uses multiple read voltages to perform a read operation on data stored in selected memory cells, the selected memory cells being included in a selected memory cell string among a plurality of memory cell strings. The method may include: performing a read operation using a first read voltage among the multiple read voltages; applying a first on-state voltage to an unselected source select line coupled to an unselected memory cell string among the plurality of memory cell strings for a first time period; subsequently applying a ground voltage to the unselected source select line; and performing a read operation using a second read voltage lower than the first read voltage. Attached Figure Description

[0007] Figure 1 This is a diagram illustrating a memory system including a memory device according to an embodiment of the present disclosure.

[0008] Figure 2 It's a diagram. Figure 1 A diagram of the structure of a memory device.

[0009] Figure 3 It's a diagram. Figure 2 A diagram of one embodiment of a memory cell array.

[0010] Figure 4 It's a diagram. Figure 3 The circuit diagram of any one of the multiple memory blocks BLK1 to BLKz.

[0011] Figure 5 It's a diagram. Figure 4 The circuit diagram shown in the figure depicts a string of memory cells.

[0012] Figure 6 This is a diagram illustrating the read operation of a memory device.

[0013] Figure 7 This is a diagram illustrating a first read operation and a second read operation according to an embodiment of the present disclosure.

[0014] Figure 8 This diagram illustrates a first read operation, a second read operation, and a third read operation according to an embodiment of the present disclosure.

[0015] Figure 9 This is a diagram illustrating examples of a first read operation, a second read operation, and a third read operation according to an embodiment of the present disclosure.

[0016] Figure 10This is a diagram illustrating examples of a first read operation, a second read operation, and a third read operation according to an embodiment of the present disclosure.

[0017] Figure 11 This is a flowchart illustrating a read operation of a memory device according to an embodiment of the present disclosure.

[0018] Figure 12 This is a block diagram illustrating a memory card system that applies a memory system according to an embodiment of the present disclosure.

[0019] Figure 13 This is a block diagram illustrating a solid-state drive (SSD) system that applies a memory system according to an embodiment of the present disclosure.

[0020] Figure 14 This is a block diagram illustrating a user system using a memory system according to an embodiment of the present disclosure. Detailed Implementation

[0021] The specific structural or functional descriptions of the embodiments of this disclosure described in this specification or application are provided as examples to illustrate embodiments based on the concept of this disclosure. Embodiments based on the concept of this disclosure may be practiced in various forms and should not be construed as limited to the embodiments described in the specification or application.

[0022] Various embodiments of this disclosure relate to a memory device capable of mitigating the phenomenon of threshold voltage variation in memory cells during read operations, and a method of operating the memory device.

[0023] Figure 1 This is a diagram illustrating a memory system including a memory device according to an embodiment of the present disclosure.

[0024] refer to Figure 1 The memory system 50 may include a memory device 100 and a memory controller 200. The memory system 50 may be a device that stores data under the control of a host 300, such as a mobile phone, smartphone, MP3 player, laptop computer, desktop computer, game console, TV, tablet PC, or in-vehicle infotainment system.

[0025] The memory system 50 can be manufactured as any of a variety of storage devices depending on the host interface used for communication with the host 300. For example, the memory system 50 can be implemented as any of a variety of storage devices, such as solid-state drives (SSDs), multimedia cards (such as MMC, embedded MMC (eMMC), reduced-size MMC (RS-MMC), or micro-MMC), secure digital cards (such as SD, mini-SD, or micro-SD), universal serial bus (USB) storage devices, universal flash memory (UFS) devices, PCMCIA card-type storage devices, peripheral component interconnect (PCI) card-type storage devices, PCI rapid (PCI-E) card-type storage devices, compact flash (CF) cards, smart media cards, and memory sticks.

[0026] The memory system 50 can be manufactured in any of a variety of package types. For example, the memory system 50 can be manufactured in any of a variety of package types, such as POP, SIP, SOC, MCP, COB, WFP, and WSP.

[0027] The memory device 100 can store data. The memory device 100 can operate under the control of the memory controller 200. The memory device 100 may include a memory cell array (not shown) that includes a plurality of memory cells for storing data.

[0028] Each memory cell can be implemented as a single-level cell (SLC) capable of storing one bit of data, a multi-level cell (MLC) capable of storing two bits of data, a three-level cell (TLC) capable of storing three bits of data, or a four-level cell (QLC) capable of storing four bits of data.

[0029] A memory cell array (not shown) may include multiple memory blocks. Each memory block may include multiple memory cells. A memory block may include multiple pages. In one embodiment, a page may be a unit for storing data in memory device 100 or a unit for reading data stored in memory device 100. A memory block may be a unit for erasing data.

[0030] In one embodiment, memory device 100 may be implemented as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate Generation 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR) SDRAM, Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, Vertical NAND flash memory, NOR flash memory, Resistive RAM (RRAM), Phase Change RAM (PRAM), Magnetoresistive RAM (MRAM), Ferroelectric RAM (FRAM), or Spin-Torque RAM (STT-RAM). For ease of explanation, this specification assumes that memory device 100 is NAND flash memory.

[0031] Memory device 100 can receive commands and addresses from memory controller 200 and can access regions of the memory cell array selected by the addresses. Memory device 100 can perform operations instructed by commands on the regions selected by the addresses. For example, memory device 100 can perform write operations (i.e., programming operations), read operations, and erase operations. During a write operation, memory device 100 can program data into the region selected by the addresses. During a read operation, memory device 100 can read data from the region selected by the addresses. During an erase operation, memory device 100 can erase data stored in the region selected by the addresses.

[0032] In one embodiment, the memory device 100 may include an operation controller 140.

[0033] The operation controller 140 can control programming and reading operations performed on the memory cells. A programming operation can be an operation that stores data in the memory cells. A reading operation can be an operation that retrieves data stored in the memory cells.

[0034] In one embodiment, a read operation may be an operation of applying a read voltage to a word line coupled to a memory cell and sensing data stored in the memory cell. Because the threshold voltage of the memory cell is determined based on the stored data, the read operation may be an operation of identifying a programming state among multiple programming states that corresponds to the threshold voltage of the memory cell. For example, when programming a memory cell according to a TLC scheme, seven read voltages may be applied to identify which of the erase state and the first through seventh programming states corresponds to each of the threshold voltages of the memory cell.

[0035] In one embodiment, the operation controller 140 can control a potential adjustment operation that changes the potential of the channel coupled to the memory cell after a read operation is performed. For example, the operation controller 140 can lower the channel potential by applying a conduction voltage to the drain select line and source select line coupled to the memory cell during the potential adjustment operation. In one example, the operation controller 140 can raise the channel potential by applying a ground voltage to the drain select line and source select line during the potential adjustment operation.

[0036] The memory controller 200 can control the overall operation of the memory system 50.

[0037] When power is applied to the memory system 50, the memory controller 200 can run firmware (FW). When the memory device 100 is a flash memory device, the firmware (FW) may include: a host interface layer (HIL) for controlling communication with the host 300; a flash translation layer (FTL) for controlling communication between the host 300 and the memory device 100; and a flash interface layer (FIL) for controlling communication with the memory device 100.

[0038] In one embodiment, the memory controller 200 may receive data and a logical block address (LBA) from the host 300, and may translate the logical block address (LBA) into a physical block address (PBA), which indicates the address of a memory cell included in the memory device 100 and in which data is to be stored. In this specification, the terms "logical block address (LBA)" and "logical address" are used interchangeably. Similarly, in this specification, the terms "physical block address (PBA)" and "physical address" are used interchangeably.

[0039] The memory controller 200 can control the memory device 100 to perform write, read, or erase operations in response to requests received from the host 300. During a write operation, the memory controller 200 can provide the memory device 100 with a write command, a physical block address, and data. During a read operation, the memory controller 200 can provide the memory device 100 with a read command and a physical block address. During an erase operation, the memory controller 200 can provide the memory device 100 with an erase command and a physical block address.

[0040] In one embodiment, the memory controller 200 may internally generate commands, addresses, and data regardless of whether a request is received from the host 300, and may send them to the memory device 100. For example, the memory controller 200 may provide the memory device 100 with commands, addresses, and data required to perform read and write operations, which are involved in performing wear leveling, read recycling, garbage collection, and other similar operations.

[0041] In one embodiment, the memory controller 200 can control two or more memory devices 100. In this case, the memory controller 200 can control the memory devices 100 according to an interleaving scheme to improve operational performance. The interleaving scheme can be a scheme for controlling the memory devices 100 such that the operation of at least two memory devices 100 overlaps with each other.

[0042] The host 300 can communicate with the memory system 50 using at least one of a variety of communication methods, such as Universal Serial Bus (USB), Serial AT Accessory (SATA), Serial Attached SCSI (SAS), High Speed ​​Interconnect Chip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI Fast (PCIe), Non-Volatile Memory Fast (NVMe), Universal Flash Memory (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Low Load DIMM (LRDIMM).

[0043] Figure 2 It's a diagram. Figure 1 A diagram of the structure of a memory device.

[0044] refer to Figure 2 The memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic 130.

[0045] Memory cell array 110 includes multiple memory blocks BLK1 to BLKz. The multiple memory blocks BLK1 to BLKz can be coupled to address decoder 121 via row lines RL. Memory blocks BLK1 to BLKz can be coupled to page buffer group 123 via bit lines BL1 to BLm. Each of the memory blocks BLK1 to BLKz can include multiple memory cells. In one embodiment, the multiple memory cells can be non-volatile memory cells. Memory cells coupled to the same word line among the multiple memory cells are defined as a page. In other words, memory cell array 110 can be formed from multiple pages. In one embodiment of this disclosure, each of the memory blocks BLK1 to BLKz included in memory cell array 110 can include multiple dummy cells. With respect to dummy cells, one or more dummy cells can be coupled in series between a drain select transistor and a memory cell, and between a source select transistor and a memory cell.

[0046] Each memory cell of the memory device 100 can be implemented as a single-level cell (SLC) capable of storing one bit of data, a multi-level cell (MLC) capable of storing two bits of data, a three-level cell (TLC) capable of storing three bits of data, or a four-level cell (QLC) capable of storing four bits of data.

[0047] Peripheral circuitry 120 can drive memory cell array 110. In one example, peripheral circuitry 120 can drive memory cell array 110 to perform programming, reading, and erasing operations under the control of control logic 130. In one example, peripheral circuitry 120 can apply various drive voltages Vop to row lines RL and bit lines BL1 to BLm or discharge the applied voltage under the control of control logic 130.

[0048] The peripheral circuit 120 may include an address decoder 121, a voltage generator 122, a page buffer group 123, a data input / output circuit 124, and a sensing circuit 125.

[0049] Address decoder 121 can be coupled to memory cell array 110 via row lines RL. Row lines RL may include drain select lines, word lines, source select lines, and common source lines. According to one embodiment of this disclosure, word lines may include ordinary word lines and dummy word lines. According to one embodiment of this disclosure, row lines RL may also include pipe select lines.

[0050] Address decoder 121 can operate under the control of control logic 130. Address decoder 121 can receive address ADDR from control logic 130.

[0051] Address decoder 121 can decode the block address in the received address ADDR. Address decoder 121 can select at least one of the memory blocks BLK1 to BLKz based on the decoded block address. Address decoder 121 can decode the row address RADD in the received address ADDR. Address decoder 121 can select at least one word line of the selected memory block by applying the voltage supplied from voltage generator 122 to at least one word line based on the decoded row address RADD.

[0052] During programming operations, address decoder 121 can apply a programming voltage to the selected word line and can apply a pass voltage with a lower level than the programming voltage to the unselected word line. During programming verification operations, address decoder 121 can apply a verification voltage to the selected word line and can apply a verification pass voltage with a higher level than the verification voltage to the unselected word line.

[0053] During a read operation, the address decoder 121 can apply a read voltage to the selected word line and apply a read voltage with a higher level than the read voltage to the unselected word line.

[0054] The erase operation of memory device 100 can be performed on a memory block basis. During the erase operation, the address ADDR input to memory device 100 may include the block address. Address decoder 121 can decode the block address and select a memory block based on the decoded block address. During the erase operation, address decoder 121 can apply a ground voltage to the word line coupled to the selected memory block.

[0055] Address decoder 121 can decode the column address in the received address ADDR. The decoded column address can be sent to page buffer set 123. In one embodiment, address decoder 121 may include components such as row decoder, column decoder, and address buffer.

[0056] Voltage generator 122 can generate multiple drive voltages Vop using the external power supply voltage supplied to memory device 100. Voltage generator 122 can operate under the control of control logic 130.

[0057] In one embodiment, voltage generator 122 can generate an internal power supply voltage by adjusting an external power supply voltage. The internal power supply voltage generated by voltage generator 122 can be used as the driving voltage of memory device 100.

[0058] In one embodiment, voltage generator 122 can generate various drive voltages Vop for programming, reading, and erasing operations in response to an operation signal OPSIG. Voltage generator 122 can generate multiple drive voltages Vop using either an external or internal power supply voltage. Voltage generator 122 can generate various voltages required by memory device 100. For example, voltage generator 122 can generate multiple erase voltages, multiple programming voltages, multiple programming pass voltages, multiple read voltages, and multiple read pass voltages.

[0059] Voltage generator 122 may include multiple pump capacitors for receiving internal power supply voltages to generate multiple drive voltages Vop with various voltage levels, and multiple drive voltages Vop may be generated by selectively enabling multiple pump capacitors under the control of control logic 130.

[0060] The generated driving voltage Vop can be supplied to the memory cell array 110 through the address decoder 121.

[0061] Page buffer group 123 may include first to m page buffers PB1 to PBm. First to m page buffers PB1 to PBm may be coupled to memory cell array 110 via first to m bit lines BL1 to BLm respectively. First to m page buffers PB1 to PBm may be operated under the control of control logic 130.

[0062] The buffers PB1 to PBm, which are the first to m pages, can send / receive data DATA to / from the data input / output circuit 124. During programming operations, the buffers PB1 to PBm, which are the first to m pages, can receive the data DATA to be stored through the data input / output circuit 124 and the data line DL.

[0063] During programming operations, when a programming pulse is applied to the selected word line, the first to m-th page buffers PB1 to PBm can transmit the data DATA to be stored, received via the data input / output circuit 124, to the selected memory cell via bit lines BL1 to BLm. The memory cell in the selected page can be programmed based on the received data DATA. Memory cells coupled to bit lines to which a programming enable voltage (e.g., ground voltage) is applied can have an increased threshold voltage. The threshold voltage of memory cells coupled to bit lines to which a programming disable voltage (e.g., power supply voltage) is applied can be maintained. During programming verification operations, the first to m-th page buffers PB1 to PBm can read the data DATA stored in the selected memory cell via bit lines BL1 to BLm.

[0064] During a read operation, page buffer group 123 can read data DATA from the memory cell in the selected page via bit lines BL1 to BLm, and can store the read data DATA in the first to m-th page buffers PB1 to PBm.

[0065] During an erase operation, page buffer group 123 may allow bit lines BL1 to BLm to float. In one embodiment, page buffer group 123 may include column select circuitry.

[0066] In one embodiment, when multiple data segments in some of the multiple page buffers included in the page buffer group 123 are programmed into the memory cell array 110, the remaining page buffers can receive new data from the memory controller 200 and then store the new data.

[0067] The data input / output circuit 124 can be coupled to the buffers PB1 to PBm of the first to m pages via the data line DL. The data input / output circuit 124 can operate under the control of the control logic 130.

[0068] The data input / output circuit 124 may include multiple input / output buffers (not shown) for receiving input data DATA. During programming operations, the data input / output circuit 124 receives data DATA to be stored from an external controller (not shown). During read operations, the data input / output circuit 124 outputs data DATA received from the first to the m-th page buffers PB1 to PBm, which are included in the page buffer group 123, to the external controller.

[0069] During a read or verification operation, the sensing circuit 125 can generate a reference current in response to the enable bit signal VRYBIT generated by the control logic 130, and can output a pass signal or a failure signal to the control logic 130 by comparing the sensed voltage VPB received from the page buffer group 123 with the reference voltage generated by the reference current. In one example, when the magnitude of the sensed voltage VPB is less than the magnitude of the reference voltage, the sensing circuit 125 can output a pass signal to the control logic 130. In another example, when the magnitude of the sensed voltage VPB is less than the magnitude of the reference voltage, the sensing circuit 125 can output a failure signal to the control logic 130.

[0070] Control logic 130 can be coupled to address decoder 121, voltage generator 122, page buffer group 123, data input / output circuit 124, and sensing circuit 125. Control logic 130 can control the overall operation of memory device 100. Control logic 130 can operate in response to commands (CMD) transmitted from external devices.

[0071] Control logic 130 can control peripheral circuitry 120 by generating various types of signals in response to command CMD and address ADDR. For example, control logic 130 can generate operation signal OPSIG, row address RADD, page buffer control signal PBSIGNALS, and enable bit VRYBIT in response to command CMD and address ADDR. Control logic 130 can output operation signal OPSIG to voltage generator 122, row address RADD to address decoder 121, page buffer control signal PBSIGNALS to page buffer group 123, and enable bit VRYBIT to sensing circuit 125. Furthermore, control logic 130 can determine whether the verification operation passed or failed in response to pass or fail signals PASS or FAIL output from sensing circuit 125.

[0072] like Figure 1 The operation controller 140 shown in the figure can be included in, for example, Figure 2 The control logic 130 shown in the figure is as follows.

[0073] Operation controller 140 can control peripheral circuitry 120 such that the drive voltage Vop to be used in read operations is applied to row lines RL and bit lines BL1 to BLm. In one example, operation controller 140 can control peripheral circuitry 120 such that during read operations, read voltage and read pass voltage are applied to multiple word lines. Furthermore, operation controller 140 can control peripheral circuitry 120 such that during leveling operations, pass voltage and ground voltage are applied to drain select lines and source select lines coupled to memory cells. Specifically, operation controller 140 can control voltage generator 122 to generate the drive voltage Vop to be used in read and leveling operations. Voltage generator 122 can then provide the generated drive voltage Vop to address decoder 121. Address decoder 121 can then transmit the drive voltage Vop to multiple word lines, drain select lines, and source select lines. During read and voltage adjustment operations, the voltage levels of multiple word lines, drain select lines, and source select lines can be changed according to the magnitude of the drive voltage Vop provided by the address decoder 121.

[0074] Figure 3 It's a diagram. Figure 2 A diagram of one embodiment of a memory cell array.

[0075] refer to Figure 3 The memory cell array 110 may include multiple memory blocks BLK1 to BLKz. Each of the memory blocks may have a three-dimensional (3D) structure. Each of the memory blocks may include multiple memory cells stacked on a substrate. The multiple memory cells are arranged along the +X, +Y, and +Z directions. The structure of each memory block will be referenced below. Figure 4 and Figure 5 To describe in more detail.

[0076] Figure 4 It's a diagram. Figure 3 The circuit diagram of any one of the multiple memory blocks BLK1 to BLKz.

[0077] Figure 5 It's a diagram. Figure 4 The circuit diagram shown in the figure depicts a string of memory cells.

[0078] refer to Figure 4 and Figure 5 Each memory cell string ST can be coupled between bit lines BL1 to BLm and the source line SL. An example of a memory cell string ST coupled between the first bit line BL1 and the source line SL is described below.

[0079] A memory cell string ST may include source selection transistors SST, memory cells F1 to Fn (where n is a positive integer), and drain selection transistors DST, all connected in series between source line SL and first bit line BL1. The gates of source selection transistors SST included in different memory cell strings ST coupled to different bit lines BL1 to BLm may be coupled to a first source selection line SSL0 and a second source selection line SSL1. For example, in source selection transistors SST, source selection transistors adjacent to each other in the second direction Y may be coupled to the same source selection line. For example, assuming the source selection transistors SST are arranged sequentially along the second direction Y, the gates of source selection transistors SST arranged from the first source selection transistor SST along the first direction X and included in different memory cell strings ST, and the gates of source selection transistors SST arranged from the second source selection transistor SST along the first direction X and included in different memory cell strings ST, may be coupled to the first source selection line SSL0. Furthermore, the gates of the source selection transistors SST arranged along the first direction X from the third source selection transistor SST and included in different memory cell strings ST, and the gates of the source selection transistors SST arranged along the first direction X from the fourth source selection transistor SST and included in different memory cell strings ST, can be coupled to the second source selection line SSL1.

[0080] The gates of memory cells F1 to Fn can be coupled to word lines WL1 to WLn, and the gate of drain select transistor DST can be coupled to any one of the first to fourth drain select lines DSL0 to DSL3.

[0081] The gates of transistors arranged along the first direction X in a drain-select transistor (DST) can be commonly coupled to the same drain-select line (e.g., DSL0), but the gates of transistors arranged along the second direction Y can be coupled to different drain-select lines DSL1 to DSL3. For example, assuming the drain-select transistors DST are arranged sequentially along the second direction Y, the gate of a drain-select transistor DST arranged along the first direction X from the first drain-select transistor DST and included in different memory cell strings ST can be coupled to the first drain-select line DSL0. Drain-select transistors DST arranged along the second direction Y from the drain-select transistor DST coupled to the first drain-select line DSL0 can be sequentially coupled to the second to fourth drain-select lines DSL1 to DSL3. Therefore, in a selected memory block, the memory cell string ST coupled to the selected drain-select line may be selected, while the memory cell string ST coupled to the remaining drain-select lines (i.e., the unselected drain-select lines) may not be selected. For example, when the first drain select line DSL0 is selected, the memory cell string coupled to the first drain select line DSL0 is the selected memory cell string, while the memory cell strings coupled to the second to fourth drain select lines DSL1 to DSL3 may be unselected memory cell strings. Furthermore, the first drain select line DSL0 may be the selected drain select line, while the second to fourth drain select lines DSL1 to DSL3 may be unselected drain select lines. Moreover, when the first drain select line DSL0 is selected, the first source select line SSL0 may be the selected source select line, while the second source select line SSL1 may be an unselected source select line.

[0082] Memory cells coupled to the same word line can form a page PG. Here, the term "page" refers to a physical page. For example, in a string of memory cells ST coupled to bit lines BL1 to BLm, a group of memory cells coupled along the first direction X in the same word line can be called a page PG. For example, in a first memory cell F1 coupled to the first word line WL1, memory cells arranged along the first direction X can form a page PG. In a first memory cell F1 commonly coupled to the first word line WL1, memory cells arranged along the second direction Y can be divided into different pages. Therefore, when the first drain select line DSL0 is the selected drain select line and the first word line WL1 is the selected word line, among the multiple page PGs coupled to the first word line WL1, the page PG coupled to the first drain select line DSL0 may be the selected page. Pages commonly coupled to word line WL1 but coupled to the unselected second to fourth drain select lines DSL1 to DSL3 may be unselected pages.

[0083] In one embodiment, when a memory cell is programmed according to a TLC scheme, where three bits of data are stored in each memory cell, the data stored in a page can be multi-page data. For example, multi-page data can include multiple logical pages. Specifically, the multiple logical pages can include a least significant bit (LSB) page, a center significant bit (CSB) page, and a most significant bit (MSB) page.

[0084] Although a source-select transistor (SST) and a drain-select transistor (DST) are illustrated in the accompanying drawings as being included in a memory cell string ST, according to the memory device, multiple source-select transistors (SST) and multiple drain-select transistors (DST) can be included in a memory cell string ST. Furthermore, according to the memory device, dummy cells can be included between the source-select transistors (SST), memory cells F1 to Fn, and drain-select transistors (DST). Dummy cells do not store user data like ordinary memory cells F1 to Fn, but can be used to improve the electrical characteristics of each memory cell string ST.

[0085] Figure 6 This is a diagram illustrating the read operation of a memory device.

[0086] exist Figure 6 In the graph, the horizontal axis indicates the threshold voltage Vth of the memory cell, while the vertical axis indicates the number of memory cells (the number of cells).

[0087] exist Figure 6 The following explanation is based on the assumption that memory cells are programmed according to a TLC scheme, in which three bits of data are stored in one memory cell. (Reference) Figure 6 The threshold voltage of each of the plurality of memory cells can be increased by a programming operation to a threshold voltage corresponding to any one of the erase state E and the first to seventh programming states PV1 to PV7. Thereafter, the memory device 100 can perform a read operation to retrieve data stored in the memory cell. Specifically, when a read voltage is applied to a word line coupled to a selected memory cell among the plurality of memory cells, the memory device 100 can sense the data stored in the selected memory cell by detecting changes in current on the bit line coupled to the selected memory cell. The data stored in the memory cell can vary according to the programming state of the memory cell. Specifically, different data segments can be stored according to any one of the erase state E and the first to seventh programming states PV1 to PV7 corresponding to the threshold voltage of each memory cell.

[0088] In one embodiment, the memory device 100 can perform a read operation on each of a plurality of logical pages using multiple read voltages. The plurality of logical pages may include LSB pages, CSB pages, and MSB pages. For example, as... Figure 6 As illustrated, when the LSB page corresponding to erase state E and the first to seventh programming states PV1 to PV7 is 11100001, a read operation can be performed on the LSB page using the third read voltage Vr3 and the seventh read voltage Vr7 used to distinguish between 1 and 0. Similarly, when the CSB page corresponding to erase state E and the first to seventh programming states PV1 to PV7 is 11001100, a read operation can be performed on the CSB page using the second read voltage Vr2, the fourth read voltage Vr4, and the sixth read voltage Vr6 used to distinguish between 1 and 0. Furthermore, when the MSB page corresponding to erase state E and the first to seventh programming states PV1 to PV7 is 10000111, a read operation can be performed on the MSB page using the first read voltage Vr1 and the fifth read voltage Vr5 used to distinguish between 1 and 0.

[0089] In other embodiments, the bits included in the LSB page, CSB page, and MSB page can be correlated with... Figure 6 Different formats are stored. In this case, the read voltage required to perform read operations on LSB pages, CSB pages, and MSB pages may vary. For example, although in Figure 6 The diagram illustrates a read operation on an LSB page where two read voltages are used. However, a read operation can be performed using three read voltages, depending on the bits included in the LSB page. In other words, the magnitude and number of read voltages used to distinguish between 1s and 0s can vary depending on the bits included in the LSB, CSB, and MSB pages.

[0090] Figure 7 This is a diagram illustrating a first read operation and a second read operation according to an embodiment of the present disclosure.

[0091] refer to Figure 7 The memory device 100 can select any one of a plurality of memory blocks included in the memory cell array in response to a read command and address received from the memory controller, and can select the string of memory cells from which a read operation on the selected memory block is to be performed. Thereafter, the memory device 100 can execute a first read operation Read1 and a second read operation Read2. In one embodiment, the first read operation Read1 and the second read operation Read2 can be performed by using... Figure 6The third read voltage Vr3 and the seventh read voltage Vr7 illustrated in the figure represent read operations performed on LSB pages. In one embodiment, the first read operation Read1 and the second read operation Read2 can be performed by using... Figure 6 The diagram illustrates the read operations performed on the MSB page using the first read voltage Vr1 and the fifth read voltage Vr5. In other words, the first read operation Read1 and the second read operation Read2 can be read operations performed on the logical page using two read voltages.

[0092] In one embodiment, the memory device 100 may perform a potential adjustment operation prior to the first and second read operations Read1 and Read2. The potential adjustment operation may be an operation that changes the channel potential Unsel_channel of an unselected string of memory cells.

[0093] During the time period from t1 to t2, memory device 100 can perform a potential adjustment operation. Specifically, memory device 100 can apply a voltage Vpass to the selected word line Sel_WL, and subsequently apply a first read voltage Vrd1 to the selected word line Sel_WL. The voltage Vpass can be a voltage higher than the first read voltage Vrd1. During the time period from t1 to t2, memory device 100 can apply a voltage Vpass to the unselected word line Unsel_WL. During the time period from t1 to t2, memory device 100 can apply a selection line voltage Vds to the selected drain select line sel_DSL and the selected source select line sel_SSL. The selection line voltage Vds can be a voltage higher than the threshold voltages of the drain select transistor and the source select transistor coupled to the selected drain select line Sel_DSL and the selected source select line Sel_SSL, respectively. During the time period from t1 to t2, memory device 100 may apply a ground voltage to the unselected drain select line Unsel_DSL and the unselected source select line Unsel_SSL. Here, the channel potential Unsel_channel of the unselected memory cell string may rise. In one embodiment, during the time period from t1 to t2, memory device 100 may apply a ground voltage to the unselected source select line Unsel_SSL and may apply a first on-state voltage Von1 to the unselected drain select line Unsel_DSL for a preset time, and thereafter apply a ground voltage. The first on-state voltage Von1 may be a voltage higher than the threshold voltages of the drain select transistor and the source select transistor.

[0094] During the time period from t2 to t3, memory device 100 may perform a first read operation Read1. The first read operation Read1 may be an operation of acquiring data stored in a memory cell using a first read voltage Vrd1. The memory cell to which the first read operation Read1 is performed may be a memory cell programmed to a higher programming state than the memory cell to which the second read operation Read2 is performed.

[0095] During the time period from t2 to t3, memory device 100 may apply a first read voltage Vrd1 to the selected word line Sel_WL. Figure 7 The first read voltage Vrd1 shown in the figure can be Figure 6 The diagram illustrates either the seventh read voltage Vr7 or the fifth read voltage Vr5. During the period from t2 to t3, the memory device 100 can maintain a pass voltage Vpass applied to the unselected word line Unsel_WL. During the period from t2 to t3, the memory device 100 can maintain a select line voltage Vds applied to the selected drain select line Sel_DSL and the selected source select line Sel_SSL. During the period from t2 to t3, the memory device 100 can maintain a ground voltage applied to the unselected drain select line Unsel_DSL and the unselected source select line Unsel_SSL. Here, the channel potential Unsel_channel of the unselected memory cell string can be maintained in the same state as during the period from t1 to t2.

[0096] During the period from t3 to t4, memory device 100 may perform a voltage adjustment operation. Specifically, during the period from t3 to t4, memory device 100 may apply a ground voltage to the selected word line Sel_WL. In one embodiment, memory device 100 may apply the ground voltage to the selected word line Sel_WL for a preset time, and thereafter apply a second read voltage Vrd2, which is lower than the first read voltage Vrd1, to the selected word line Sel_WL. During the period from t3 to t4, memory device 100 may maintain a pass voltage Vpass applied to the unselected word line Unsel_WL. During the period from t3 to t4, memory device 100 may maintain a select line voltage Vds applied to the selected drain select line Sel_DSL and the selected source select line Sel_SSL.

[0097] During the period from t3 to t3-1, memory device 100 may apply a first on-state voltage Von1 to the unselected drain select line Unsel_DSL and the unselected source select line Unsel_SSL. Here, the channel potential Unsel_channel of the unselected memory cell string may be lower than the channel potential Unsel_channel during the period from t1 to t3. In one embodiment, during the period from t3 to t3-1, memory device 100 may apply a ground voltage to the unselected drain select line Unsel_DSL and may apply the first on-state voltage Von1 to the unselected source select line Unsel_SSL. In this case, the degree to which the channel potential Unsel_channel of the unselected memory cell string is reduced may be less than when the first on-state voltage Von1 is applied to the unselected drain select line Unsel_DSL and the unselected source select line Unsel_SSL.

[0098] During the period from t3-1 to t4, memory device 100 may apply a ground voltage to the unselected drain select line Unsel_DSL and the unselected source select line Unsel_SSL. Here, the channel potential Unsel_channel of the unselected memory cell string may be maintained in the same state as during the period from t3 to t3-1.

[0099] In one embodiment, during a potential adjustment operation, the memory device 100 can adjust the channel potential Unsel_channel of the unselected memory cell string by applying a first on-state voltage Von1 to the unselected drain select line Unsel_DSL and the unselected source select line Unsel_SSL for a preset time, and then applying a ground voltage thereafter.

[0100] During the time period from t4 to t5, memory device 100 may perform a second read operation Read2. The second read operation Read2 may be an operation that retrieves data stored in a memory cell using a second read voltage Vrd2. The memory cell to which the second read operation Read2 is performed may be a memory cell programmed to a lower programming state than the memory cell to which the first read operation Read1 is performed.

[0101] During the time period from t4 to t5, memory device 100 may apply a second read voltage Vrd2 to the selected word line Sel_WL. Figure 7 The second read voltage Vrd2 shown in the figure can be Figure 6The diagram illustrates either the third read voltage Vr3 or the first read voltage Vr1. During the period from t4 to t5, the memory device 100 can maintain a pass voltage Vpass applied to the unselected word line Unsel_WL. During the period from t4 to t5, the memory device 100 can maintain a select line voltage Vds applied to the selected drain select line Sel_DSL and the selected source select line Sel_SSL. During the period from t4 to t5, the memory device 100 can maintain a ground voltage applied to the unselected drain select line Unsel_DSL and the unselected source select line Unsel_SSL. Here, the channel potential Unsel_channel of the unselected memory cell string can be maintained in the same state as during the period from t3 to t4.

[0102] After time t5, memory device 100 can discharge the voltages of the selected word line Sel_WL, the unselected word line Unsel_WL, the selected drain select line Sel_DSL, and the selected source select line Sel_SSL to ground voltage.

[0103] According to one embodiment of this disclosure, the channel potential Unsel_channel of the unselected memory cell string can be increased by applying a ground voltage to the unselected drain select line Unsel_DSL and the unselected source select line Unsel_SSL during a potential adjustment operation prior to the first read operation Read1. However, since a low-level read voltage is applied to the selected word line Sel_WL while the channel potential Unsel_channel of the unselected memory cell string is increased, a threshold voltage change of the selected memory cell coupled to the selected word line may occur. Therefore, the threshold voltage change of the selected memory cell can be reduced by applying a first on-state voltage Von1 to the unselected drain select line Unsel_DSL and the unselected source select line Unsel_SSL for a preset time during a potential adjustment operation prior to the second read operation Read2, and then applying a ground voltage thereafter.

[0104] Figure 8 This diagram illustrates a first read operation, a second read operation, and a third read operation according to an embodiment of the present disclosure.

[0105] because Figure 8 The time period from t1 to t5 and Figure 7 The time periods from t1 to t5 are the same, so the pair will be omitted. Figure 7 The configuration is the same as the repeated description of the configuration.

[0106] refer to Figure 8 The memory device 100 can execute a first read operation Read1, a second read operation Read2, and a third read operation Read3. In one embodiment, the first read operation Read1, the second read operation Read2, and the third read operation Read3 can be performed by using... Figure 6 The diagram illustrates the read operations performed on the CSB page using the second read voltage Vr2, the fourth read voltage Vr4, and the sixth read voltage Vr6. In other words, the first read operation Read1, the second read operation Read2, and the third read operation Read3 can be read operations performed using three read voltages.

[0107] In one embodiment, the memory device 100 may perform a potential adjustment operation before the first to third read operations Read1, Read2 and Read3.

[0108] During the period from t5 to t6, memory device 100 may perform a potential adjustment operation. Specifically, during the period from t5 to t6, memory device 100 may apply a ground voltage to the selected word line Sel_WL. In one embodiment, memory device 100 may apply the ground voltage to the selected word line Sel_WL for a preset time, and thereafter apply a third read voltage Vrd3, which is lower than the second read voltage Vrd2, to the selected word line Sel_WL. During the period from t5 to t6, memory device 100 may maintain a pass voltage Vpass applied to the unselected word line Unsel_WL. During the period from t5 to t6, memory device 100 may maintain a select line voltage Vds applied to the selected drain select line Sel_DSL and the selected source select line Sel_SSL.

[0109] During the period from t5 to t5-1, memory device 100 may apply a second on-state voltage Von2 to the unselected drain select line Unsel_DSL and the unselected source select line Unsel_SSL. In one embodiment, the second on-state voltage Von2 may be a voltage higher than the first on-state voltage Von1. In another embodiment, the magnitude of the second on-state voltage Von2 may be equal to the magnitude of the first on-state voltage Von1. Here, the channel potential Unsel_channel of the unselected memory cell string may be lower than the channel potential Unsel_channel during the period from t3 to t5.

[0110] During the period from t5-1 to t6, memory device 100 may apply a ground voltage to the unselected drain select line Unsel_DSL and the unselected source select line Unsel_SSL. Here, the channel potential Unsel_channel of the unselected memory cell string may be maintained in the same state as during the period from t5 to t5-1.

[0111] During the time period from t6 to t7, memory device 100 may perform a third read operation Read3. The third read operation Read3 may be an operation that retrieves data stored in a memory cell using a third read voltage Vrd3. The memory cell to which the third read operation Read3 will be performed may be a memory cell programmed to a lower programming state than the memory cell to which the second read operation Read2 will be performed.

[0112] During the time period from t6 to t7, memory device 100 may apply a third read voltage Vrd3 to the selected word line Sel_WL. The third read voltage Vrd3 may be a negative voltage. Figure 8 The third read voltage Vrd3 shown in the figure can be Figure 6 The second read voltage Vr2 is illustrated in the figure. During the period from t6 to t7, the memory device 100 can maintain a pass voltage Vpass applied to the unselected word line Unsel_WL. During the period from t6 to t7, the memory device 100 can maintain a select line voltage Vds applied to the selected drain select line Sel_DSL and the selected source select line Sel_SSL. During the period from t6 to t7, the memory device 100 can maintain a ground voltage applied to the unselected drain select line Unsel_DSL and the unselected source select line Unsel_SSL. Here, the channel potential Unsel_channel of the unselected memory cell string can be maintained in the same state as during the period from t5 to t6.

[0113] After time t7, memory device 100 can discharge the voltages of the selected word line Sel_WL, the unselected word line Unsel_WL, the selected drain select line Sel_DSL, and the selected source select line Sel_SSL to ground voltage.

[0114] According to one embodiment of this disclosure, since a low-level read voltage is applied to the selected word line Sel_WL while the channel potential Unsel_channel of the unselected memory cell string is raised, the degree of threshold voltage variation of the selected memory cell coupled to the selected word line Sel_WL may be high. Therefore, during the potential adjustment operation prior to the third read operation Read3 using a third read voltage Vrd3 lower than the second read voltage Vrd2 used in the second read operation Read2, the phenomenon of threshold voltage variation of the selected memory cell can be improved by applying a second turn-on voltage Von2, which is higher than the first turn-on voltage Von1, to the unselected drain select line Unsel_DSL and the unselected source select line Unsel_SSL for a preset time, and thereafter applying a ground voltage to the unselected drain select line Unsel_DSL and the unselected source select line Unsel_SSL.

[0115] Figure 9 This is a diagram illustrating examples of a first read operation, a second read operation, and a third read operation according to an embodiment of the present disclosure.

[0116] exist Figure 9 Lieutenant General (omitted) Figure 8 The configuration is the same as the repeated description of the configuration.

[0117] refer to Figure 9 During the period from t3 to t3-1, memory device 100 may apply a first on-state voltage Von1 to the unselected drain select line Unsel_DSL and the unselected source select line Unsel_SSL to achieve a first time init_t1. During the period from t3-1 to t4, memory device 100 may apply a ground voltage to the unselected drain select line Unsel_DSL and the unselected source select line Unsel_SSL.

[0118] During the time period from t5 to t5-1, the memory device 100 may apply a first on-state voltage Von1 to the unselected drain select line Unsel_DSL and the unselected source select line Unsel_SSL for a second time init_t2, which is longer than the first time init_t1. That is, the length of the time period from t5 to t5-1 can be longer than the length of the time period from t3 to t3-1, during which the first on-state voltage Von1 is applied to the unselected drain select line Unsel_DSL and the unselected source select line Unsel_SSL.

[0119] The longer the first on-state voltage Von1 is applied to the unselected drain select line Unsel_DSL and the unselected source select line Unsel_SSL during the potential adjustment operation, the greater the reduction in the channel potential Unsel_channel of the unselected memory cell string. The third read voltage Vrd3 used in the third read operation Read3 can be lower than the second read voltage Vrd2 used in the second read operation Read2. Therefore, the memory device 100 can set the time init_t2 to be longer than the time init_t1, thereby improving the phenomenon of threshold voltage changes in memory cells during the time init_t2, during which the first on-state voltage is applied to the unselected drain select line Unsel_DSL and the unselected source select line Unsel_SSL during the potential adjustment operation prior to the third read operation Read3, and during the time init_t1, during the potential adjustment operation prior to the second read operation Read2.

[0120] Figure 10 This is a diagram illustrating examples of a first read operation, a second read operation, and a third read operation according to an embodiment of the present disclosure.

[0121] exist Figure 10 Lieutenant General (omitted) Figure 8 and Figure 9 The configuration is the same as the repeated description of the configuration.

[0122] refer to Figure 10The memory device 100 can change at least one of the magnitude and application time of the on-state voltage applied to the unselected drain select line Unsel_DSL and the unselected source select line Unsel_SSL during a potential adjustment operation prior to the second read operation Read2 and the third read operation Read3. The magnitude of the second on-state voltage Von2 applied to the unselected drain select line Unsel_DSL and the unselected source select line Unsel_SSL during the time period from t5 to t5-1 can be higher than the magnitude of the first on-state voltage Von1 applied to the unselected drain select line Unsel_DSL and the unselected source select line Unsel_SSL during the time period from t3 to t3-1. Furthermore, time init_t2 can be longer than time init_t1. During time init_t2, a second on-state voltage is applied to the unselected drain select line Unsel_DSL and the unselected source select line Unsel_SSL during the period from t5 to t5-1. During time init_t1, a first on-state voltage is applied to the unselected drain select line Unsel_DSL and the unselected source select line Unsel_SSL during the period from t3 to t3-1.

[0123] In one embodiment, the memory device 100 may vary at least one of the magnitude and application time of the on-state voltage applied to the unselected drain select line Unsel_DSL and the unselected source select line Unsel_SSL during a potential adjustment operation, depending on the number of programming and erasing operations performed on the memory cell. In one example, the memory device 100 may increase the magnitude of the on-state voltage applied to the unselected drain select line Unsel_DSL and the unselected source select line Unsel_SSL during a potential adjustment operation as the number of programming and erasing operations performed on the memory cell increases. In one example, the memory device 100 may increase the time during which the on-state voltage is applied to the unselected drain select line Unsel_DSL and the unselected source select line Unsel_SSL during a potential adjustment operation as the number of programming and erasing operations performed on the memory cell increases.

[0124] In one embodiment, the memory device 100 may vary at least one of the magnitude and application time of the on-state voltage applied to the unselected drain select line Unsel_DSL and the unselected source select line Unsel_SSL during a potential adjustment operation, depending on the number of read operations performed on the memory cell. In one example, the memory device 100 may increase the magnitude of the on-state voltage applied to the unselected drain select line Unsel_DSL and the unselected source select line Unsel_SSL during a potential adjustment operation as the number of read operations performed on the memory cell increases. In one example, the memory device 100 may increase the time during which the on-state voltage is applied to the unselected drain select line Unsel_DSL and the unselected source select line Unsel_SSL during a potential adjustment operation as the number of read operations performed on the memory cell increases.

[0125] In one embodiment, the memory device 100 may include a temperature sensor for measuring the internal temperature of the memory device. Furthermore, the memory device 100 may vary at least one of the magnitude and application time of the on-state voltage applied to the unselected drain select line Unsel_DSL and the unselected source select line Unsel_SSL during a potential adjustment operation, based on the measured temperature of the memory device. In one example, the memory device 100 may increase the magnitude of the on-state voltage applied to the unselected drain select line Unsel_DSL and the unselected source select line Unsel_SSL during a potential adjustment operation due to a lower temperature of the memory device. In another example, the memory device 100 may increase the duration for which it applies the on-state voltage to the unselected drain select line Unsel_DSL and the unselected source select line Unsel_SSL during a potential adjustment operation due to a lower temperature of the memory device.

[0126] Figure 11 This is a flowchart illustrating a read operation of a memory device according to an embodiment of the present disclosure.

[0127] refer to Figure 11 At step S1201, the memory device 100 may perform a read operation by using a first read voltage among a plurality of read voltages. This read operation may be the operation of reading any one of a plurality of logical pages. The first read voltage may be the highest voltage among the plurality of read voltages used to perform the read operation. In one embodiment, the memory device 100 may apply a ground voltage to the unselected drain select line and the unselected source select line before performing the read operation by using the first read voltage.

[0128] At step S1203, the memory device 100 may apply a first on-state voltage to the unselected drain select line and the unselected source select line coupled to the unselected memory cell string among the plurality of memory cell strings for a first time period, and thereafter apply a ground voltage thereto. In one embodiment, the memory device 100 may apply a ground voltage to the unselected drain select line while simultaneously applying the first on-state voltage to the unselected source select line for the first time period.

[0129] At step S1205, the memory device 100 can perform a read operation by using a second read voltage that is lower than the first read voltage.

[0130] At step S1207, the memory device 100 may apply a second turn-on voltage to the unselected source select line and the unselected drain select line for a second time period, and thereafter apply a ground voltage thereto. In one embodiment, the length of the second time period may be equal to or longer than the length of the first time period. In one embodiment, the magnitude of the second turn-on voltage may be equal to or higher than the first turn-on voltage.

[0131] At step S1209, the memory device 100 can perform a read operation by using a third read voltage that is lower than the second read voltage.

[0132] Figure 12 This is a block diagram illustrating a memory card system that applies a memory system according to an embodiment of the present disclosure.

[0133] refer to Figure 12 The memory card system 2000 may include a memory controller 2100, a memory device 2200, and a connector 2300.

[0134] Memory controller 2100 can be coupled to memory device 2200. Memory controller 2100 can access memory device 2200. For example, memory controller 2100 can control read, write, erase, and background operations of memory device 2200. Memory controller 2100 can provide an interface between memory device 2200 and a host. Memory controller 2100 can run firmware for controlling memory device 2200. Memory controller 2100 can be referenced above. Figure 1 The memory controller 200 described herein is implemented in the same manner. The memory device 2200 can be implemented in the same manner as described above. Figure 1 The memory device 100 described is implemented in the same manner.

[0135] In one embodiment, the memory controller 2100 may include components such as RAM, a processor, a host interface, a memory interface, and error correction circuitry.

[0136] The memory controller 2100 can communicate with external devices via connector 2300. The memory controller 2100 can communicate with external devices (e.g., a host) based on a specific communication standard or protocol. In one embodiment, the memory controller 2100 can communicate with external devices via at least one of various communication standards or protocols, such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and Non-Volatile Memory Express (NVMe). In one embodiment, connector 2300 can be defined by at least one of the aforementioned communication standards or protocols.

[0137] In one embodiment, the memory device 2200 may be implemented as any of a variety of non-volatile memory devices, such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase-change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), spin-transfer torque magnetic RAM (STT-MRAM).

[0138] The memory controller 2100 and memory device 2200 can be integrated into a single semiconductor device to configure a memory card. For example, the memory controller 2100 and memory device 2200 can be integrated into a single semiconductor device to configure a memory card such as a PC card (PCMCIA), a compact flash card (CF), a smart media card (SM or SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro, or eMMC), an SD card (SD, miniSD, microSD, or SDHC), or universal flash storage (UFS).

[0139] Figure 13 This is a block diagram illustrating a solid-state drive (SSD) system that applies a memory system according to an embodiment of the present disclosure.

[0140] refer to Figure 13The SSD system 3000 may include a host 3100 and an SSD 3200. The SSD 3200 can exchange signals with the host 3100 through a signal connector 3001 and can receive power through a power connector 3002. The SSD 3200 may include an SSD controller 3210, multiple flash memories 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

[0141] According to one embodiment of this disclosure, the SSD controller 3210 can perform the above-mentioned reference. Figure 1 The functions of the memory controller 200 are described.

[0142] SSD controller 3210 can control multiple flash memories 3221 to 322n in response to signals received from host 3100. In one embodiment, the signal can be based on the interface between host 3100 and SSD 3200. For example, the signal can be defined by at least one of various interfaces, such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Fast (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and Non-Volatile Memory Fast (NVMe).

[0143] Auxiliary power supply 3230 can be coupled to host 3100 via power connector 3002. Auxiliary power supply 3230 can be supplied by the power supply of host 3100 and can be charged. When the power supply from host 3100 is not successfully executed, auxiliary power supply 3230 can supply power to SSD 3200. In one embodiment, auxiliary power supply 3230 can be located inside or outside SSD 3200. For example, auxiliary power supply 3230 can be disposed in the motherboard and can supply auxiliary power to SSD 3200.

[0144] Buffer memory 3240 can function as a buffer memory for SSD 3200. For example, buffer memory 3240 can temporarily store data received from host 3100 or data received from multiple flash memories 3221 to 322n, or it can temporarily store metadata (e.g., mapping tables) of flash memories 3221 to 322n. Buffer memory 3240 can include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0145] Figure 14 This is a block diagram illustrating a user system using a memory system according to an embodiment of the present disclosure.

[0146] refer to Figure 14 The user system 4000 may include an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0147] Application processor 4100 can run user system 4000, operating system (OS), or components included in user programs. In one embodiment, application processor 4100 may include controllers, interfaces, graphics engines, etc., for controlling components included in user system 4000. Application processor 4100 may be provided as a system-on-a-chip (SoC).

[0148] The memory module 4200 can function as the main memory, working memory, buffer memory, or cache memory of the user system 4000. The memory module 4200 may include volatile RAM such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or non-volatile RAM such as PRAM, ReRAM, MRAM, and FRAM. In one embodiment, the application processor 4100 and the memory module 4200 may be packaged based on a stacked package (POP) and then provided as a single semiconductor package.

[0149] Network module 4300 can communicate with external devices. For example, network module 4300 can support wireless communication, such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), Long Term Evolution (LTE), WiMAX, WLAN, UWB, Bluetooth, or Wi-Fi communication. In one embodiment, network module 4300 may be included in application processor 4100.

[0150] Storage module 4400 can store data. For example, storage module 4400 can store data received from application processor 4100. Alternatively, storage module 4400 can send data stored in storage module 4400 to application processor 4100. In one embodiment, storage module 4400 can be implemented as a non-volatile semiconductor memory device, such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, or NAND flash memory with a three-dimensional (3D) structure. In one embodiment, storage module 4400 can be provided as a removable storage medium (i.e., a removable drive), such as a memory card of user system 4000 or an external drive.

[0151] In one embodiment, the storage module 4400 may include a plurality of non-volatile memory devices, each of which may be referenced above. Figure 1 The memory device 100 described herein operates in the same manner. The memory module 4400 can operate in the same manner as described above. Figure 1 The memory system 50 described operates in the same manner.

[0152] User interface 4500 may include an interface for inputting data or instructions to application processor 4100 or outputting data to external devices. In one embodiment, user interface 4500 may include user input interfaces such as a keyboard, keypad, buttons, touch panel, touch screen, touchpad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, and piezoelectric device. User interface 4500 may also include user output interfaces such as liquid crystal display (LCD), organic light-emitting diode (OLED) display device, active matrix OLED (AMOLED) display device, LED, speaker, and monitor.

[0153] According to this disclosure, a memory device is provided that can improve the phenomenon of threshold voltage variation of memory cells during read operations, and a method for operating the memory device is also provided.

Claims

1. A memory device, comprising: Multiple memory cell strings, each of the memory cell strings comprising multiple memory cells coupled between a drain select line and a source select line; The peripheral circuitry is configured to use multiple read voltages to perform a read operation to read data stored in a selected memory cell, the selected memory cell being included in a selected memory cell string among the multiple memory cell strings; as well as The operation controller is configured to control the peripheral circuitry: The read operation is performed by using a first read voltage among the plurality of read voltages; After the read operation is performed, a first potential adjustment operation is performed. as well as After performing the first potential adjustment operation, the read operation is performed using a second read voltage that is lower than the first read voltage. The first potential adjustment operation is as follows: applying a first on-state voltage to an unselected source select line coupled to an unselected memory cell string among the plurality of memory cell strings for a first time period, and thereafter applying a ground voltage to the unselected source select line.

2. The memory device of claim 1, wherein the operation controller is configured to control the peripheral circuitry to: apply the first on-state voltage to an unselected drain select line coupled to the unselected memory cell string for the first time period while the first potential adjustment operation is being performed, and thereafter apply the ground voltage to the unselected drain select line.

3. The memory device of claim 2, wherein the operation controller is configured to control the peripheral circuitry to perform: After performing the read operation using the second read voltage, a second potential adjustment operation is performed, and the read operation is then performed using a third read voltage that is lower than the second read voltage. The second potential adjustment operation is as follows: a second turn-on voltage higher than the first turn-on voltage is applied to the unselected source selection line and the unselected drain selection line for the first time period, and thereafter the ground voltage is applied to the unselected source selection line and the unselected drain selection line.

4. The memory device of claim 2, wherein the operation controller is configured to control the peripheral circuitry to perform: After performing the read operation using the second read voltage, a third potential adjustment operation is performed, and the read operation is performed using a third read voltage that is lower than the second read voltage. The third potential adjustment operation is as follows: applying the first on-state voltage to the unselected source select line and the unselected drain select line for a second period longer than the first period, and thereafter applying the ground voltage to the unselected source select line and the unselected drain select line.

5. The memory device of claim 2, wherein the operation controller is configured to control the peripheral circuitry to perform: After performing the read operation using the second read voltage, a fourth potential adjustment operation is performed, and the read operation is then performed using a third read voltage that is lower than the second read voltage. The fourth potential adjustment operation is as follows: applying a second turn-on voltage higher than the first turn-on voltage to the unselected source select line and the unselected drain select line for a second period longer than the first period, and thereafter applying the ground voltage to the unselected source select line and the unselected drain select line.

6. The memory device of claim 5, wherein the operation controller is configured to control the peripheral circuitry to apply the ground voltage to the unselected source select line and the unselected drain select line before performing the read operation using the first read voltage.

7. The memory device according to claim 6, wherein: The length of each of the first and second time periods increases with the number of programming and erasing operations performed on the selected memory cell, and The magnitude of each of the first and second turn-on voltages increases with the number of times the programming and erasing operations are performed on the selected memory cell.

8. The memory device according to claim 6, wherein: The length of each of the first and second time periods increases with the number of read operations performed on the selected memory cell, and The magnitude of each of the first and second turn-on voltages increases as the number of read operations performed on the selected memory cell increases.

9. The memory device according to claim 6, wherein: The length of each of the first and second time periods decreases as the temperature of the memory device increases, and The magnitude of each of the first and second turn-on voltages decreases as the temperature of the memory device increases.

10. A method of operating a memory device, the memory device using a plurality of read voltages to perform a read operation to read data stored in selected memory cells, the selected memory cells being included in a selected memory cell string among a plurality of memory cell strings, the method comprising: The read operation is performed by using a first read voltage among the plurality of read voltages; A first on-state voltage is applied to an unselected source select line coupled to an unselected memory cell string among the plurality of memory cell strings for a first time period, and thereafter a ground voltage is applied to the unselected source select line. as well as The read operation is performed by using a second read voltage that is lower than the first read voltage.

11. The method of claim 10, further comprising: While applying the first on-state voltage to the unselected source select line for the first time period and subsequently applying the ground voltage to the unselected source select line, the first on-state voltage is also applied to the unselected drain select line coupled to the unselected memory cell string for the first time period and subsequently applying the ground voltage to the unselected drain select line.

12. The method of claim 11, further comprising: After performing the read operation using the second read voltage, a second turn-on voltage higher than the first turn-on voltage is applied to the unselected source select line and the unselected drain select line for the first time period, and thereafter the ground voltage is applied to the unselected source select line and the unselected drain select line. as well as The read operation is performed by using a third read voltage that is lower than the second read voltage.

13. The method of claim 11, further comprising: After performing the read operation using the second read voltage, the first on voltage is applied to the unselected source select line and the unselected drain select line for a second period longer than the first period, and thereafter the ground voltage is applied to the unselected source select line and the unselected drain select line. as well as The read operation is performed by using a third read voltage that is lower than the second read voltage.

14. The method of claim 11, further comprising: After performing the read operation using the second read voltage, a second turn-on voltage higher than the first turn-on voltage is applied to the unselected source select line and the unselected drain select line for a second period longer than the first period. as well as The read operation is performed by using a third read voltage that is lower than the second read voltage.

15. The method of claim 14, further comprising: Before performing the read operation using the first read voltage, the ground voltage is applied to the unselected source select line and the unselected drain select line.

16. The method of claim 15, wherein: The length of each of the first and second time periods increases with the number of programming and erasing operations performed on the selected memory cell, and The magnitude of each of the first and second turn-on voltages increases with the number of times the programming and erasing operations are performed on the selected memory cell.

17. The method of claim 15, wherein: The length of each of the first and second time periods increases with the number of read operations performed on the selected memory cell, and The magnitude of each of the first and second turn-on voltages increases as the number of read operations performed on the selected memory cell increases.

18. The method of claim 15, wherein: The length of each of the first and second time periods decreases as the temperature of the memory device increases, and The magnitude of each of the first and second turn-on voltages decreases as the temperature of the memory device increases.

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