Voltage converter circuit and method of controlling the same, radio frequency switch

Abstract

The application discloses a voltage converter circuit and a control method thereof and a radio frequency switch, which can improve the voltage resistance of the radio frequency switch chip, ensure the reliable work of the radio frequency switch, and meet the miniaturization requirement of the radio frequency switch. The voltage converter circuit comprises a band gap reference voltage circuit, a first LDO circuit, a second LDO circuit, a first voltage dividing unit, a second voltage dividing unit, a first switch unit and a second switch unit. The output ends of the first switch unit are connected with the input ends of the band gap reference voltage circuit and the first LDO circuit respectively. The output end of the second switch unit is connected with the input end of the second LDO circuit. The output end of the band gap reference voltage circuit is connected with the first LDO circuit and the second LDO circuit. The first voltage dividing unit comprises a resistor R1. The second voltage dividing unit comprises a series diode. The first switch unit and the second switch unit are both composed of MOS tubes. The radio frequency switch comprises the voltage converter circuit.

Description

Technical Field

[0001] This invention relates to the field of radio frequency switch technology, specifically to a voltage converter circuit and its control method, and a radio frequency switch. Background Technology

[0002] With the rapid development of mobile communication technology, mobile phones, computers, and other devices have increasingly higher requirements for the performance of radio frequency (RF) switches. RF is a key component of wireless products, and an RF switch includes an RF switch chip. The chip's substrate contains RF switches, amplifiers, duplexers, RF filters, and other components. The RF switch is used to switch between RF signal reception and transmission; the amplifier amplifies the RF signal in the receiving or transmitting channel; and the RF filter filters out signals outside a specific frequency band. The RF switch chip incorporates a bandgap reference voltage circuit, which, as a fundamental module of the RF switch chip, needs to meet a wide voltage range requirement of 2.5V to 5V.

[0003] Currently, in RF front-end WIFI switch chips, the internal bias voltage of RF switches based on GPIO interfaces is typically provided by a voltage source VDD and a control voltage VCTRL, such as... Figure 1 As shown, the voltage source VDD is converted into an internal bias voltage by a voltage converter, and the control voltage VCTRL is converted into an internal control voltage by a level converter. In commonly used RF switch chips, the voltage converter includes a bandgap reference voltage circuit, an LDO circuit, and a MOSFET. The operating voltage of the bandgap reference voltage circuit and the LDO circuit is 2.5V to 5V, and the rated voltage of the MOSFET is 2.5V. For applications such as base stations that require 5V voltage, the MOSFET has poor voltage withstand capability and is easily damaged by exceeding its rated operating voltage. To meet the 5V voltage requirement and improve the voltage withstand performance, at least two MOSFETs need to be stacked in the voltage converter. In order to obtain the same current conduction capability, the two MOSFETs need to be large-size structures. This not only increases the process complexity of the MOSFET and the complexity of the RF switch chip, but also increases the size of the RF switch chip by several times, which cannot meet the miniaturization requirements of RF switches. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a voltage converter circuit that can improve the voltage withstand capability of RF switch chips, ensure reliable operation of RF switch chips, and simultaneously meet the miniaturization requirements of RF switches.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] A voltage converter circuit includes a bandgap reference voltage circuit, a first LDO circuit, and a second LDO circuit. It is characterized by further including a first voltage divider unit, a second voltage divider unit connected in series with the first voltage divider unit, and a first switching unit and a second switching unit connected in parallel. The input terminals of the first voltage divider unit, the first switching unit, and the second switching unit are all connected to a voltage source VDD. The output terminal of the first voltage divider unit is respectively connected to the input terminal of the second voltage divider unit and the control terminals of the first and second switching units. The output terminal of the first switching unit is respectively connected to the input terminal of the bandgap reference voltage circuit and the input terminal of the first LDO circuit. The output terminal of the second switching unit is connected to the input terminal of the second LDO circuit, and the output terminal of the bandgap reference voltage circuit is respectively connected to the first LDO circuit and the second LDO circuit. The first voltage divider unit includes a resistor R1, the second voltage divider unit includes several diodes connected in series, and both the first and second switching units are composed of MOSFETs.

[0007] Its further feature is that,

[0008] The second voltage divider unit includes four diodes D1 to D4 connected in series.

[0009] The first switching unit includes a MOS transistor N1, and the second switching unit includes a MOS transistor N2, wherein both MOS transistors N1 and N2 are NMOS transistors;

[0010] It also includes a filtering unit, which includes resistors R2 and R3. One end of resistors R2 and R3 is connected to the voltage source VDD, the other end of resistor R2 is connected to the input terminal of the first switching unit, and the other end of resistor R3 is connected to the input terminal of the second switching unit.

[0011] Furthermore, one end of each of resistors R1, R2, and R3 is connected to the voltage source VDD and the first input terminal of the first LDO circuit. The other ends of resistors R2 and R3 are connected in series with the sources of MOSFETs N1 and N2, respectively. The other end of resistor R1 is connected to the gates of MOSFETs N1 and N2 and the anode of diode D1, respectively. The drain of MOSFET N1 outputs a bias voltage Vreg_ana, which is connected to the input terminal of the bandgap reference voltage circuit and the second input terminal of the first LDO circuit, respectively. The drain of MOSFET N2 outputs a bias voltage Vreg_dig, which is connected to the first input terminal of the second LDO circuit. The output terminals of the bandgap reference voltage circuit include: the first output terminal to the fourth output terminal. The output terminals, the first output terminal, the second output terminal, and the third output terminal, respectively output a voltage reference voltage Vref and a bias current Ib1 and Ib2. The first output terminal is connected to the first LDO circuit and the second LDO circuit, respectively, to provide a reference voltage Vref to the first LDO circuit and the second LDO circuit. The second output terminal is connected to the first LDO circuit, to provide a bias current Ib1 to the first LDO circuit. The third output terminal is connected to the second LDO circuit, to provide a bias current Ib2 to the second LDO circuit. The cathode of the diode D4, the fourth output terminal of the bandgap reference voltage circuit, the output terminal of the first LDO circuit, and the output terminal of the second LDO circuit are all grounded.

[0012] Furthermore, the voltage source VDD is a high voltage, specifically 5V, and the operating voltages of the MOSFETs N1 and N2 are 1 / 2*VDD, respectively.

[0013] Furthermore, the resistance value of resistor R1 is 500 kΩ, and the resistance values ​​of resistors R2 and R3 are both 1 kΩ to 2 kΩ.

[0014] A voltage converter circuit control method, characterized in that the method includes: S1, powering on the start-up voltage source VDD, turning on the MOS transistors in the first switching unit and the second switching unit, and providing the bandgap reference voltage circuit with start-up voltage and start-up current;

[0015] S2. The bandgap reference voltage circuit generates a reference voltage Vref and bias currents Ib1 and Ib2. The first LDO circuit starts up under the action of the reference voltage Vref and bias current Ib1 and outputs a bias voltage Vreg_ana. The second LDO circuit starts up under the action of the reference voltage Vref and bias current Ib1 and outputs a bias voltage Vreg_dig. At this time, the MOS transistors in the first switching unit and the second switching unit are turned off. The bandgap reference voltage circuit and the first LDO circuit form a first conduction loop, and the bandgap reference voltage circuit and the second LDO circuit form a second conduction loop.

[0016] S3. The bandgap reference voltage circuit is turned off, and the MOS transistors N1 and N2 are restarted.

[0017] A radio frequency (RF) switch includes a housing and an RF switch chip encapsulated within the housing. The RF switch chip includes a substrate, a voltage converter circuit, a level converter, an oscillator and a negative voltage generation circuit, a driver stage, and an RF switch distributed on the substrate. The input terminal of the voltage converter circuit is connected to a voltage source VDD, and the output terminal is connected to the level converter, the oscillator and negative voltage generation circuit, and the driver stage, respectively. The voltage converter circuit is used to convert the voltage source VDD into bias voltages Vreg_ana and Vreg_dig, and to provide bias voltage Vreg_ana to the level converter and the driver stage, respectively, and to the oscillator and the driver stage. A negative voltage generating circuit provides a bias voltage Vreg_dig. The input terminal of the level converter receives a control voltage VCTRL. The level converter is used to convert the control voltage VCTRL and output a control voltage signal BS to control the drive stage. The oscillator and negative voltage generating circuit are used to generate a reference voltage Vneg and provide the reference voltage Vneg to the drive stage. Under the action of the control voltage signal BS and the reference voltage Vneg, the drive stage generates a drive signal to control the opening or closing of the RF switch. The voltage converter circuit is the aforementioned voltage converter circuit.

[0018] The above-described structure of this invention achieves the following beneficial effects: The voltage converter circuit includes a first voltage divider unit and a second voltage divider unit. The first voltage divider unit includes a resistor R1, and the second voltage divider unit includes several diodes connected in series. The voltage source VDD is divided by the first and second voltage divider units to obtain a reference voltage V. This reference voltage V is added to the control terminals of the first and second switching units, reducing the voltage difference between the control terminals and the input terminals of the first and second switching units. This avoids damage to the first and second switching units due to poor voltage withstand capability. Therefore, the inclusion of the first and second voltage divider units increases the overall voltage withstand capability of the RF switching chip, meeting the high-voltage conversion requirements. Furthermore, it achieves the same current conduction capability without increasing the size of the MOS transistors in the first and second switching units, thus simplifying the structural design and reducing the area of ​​the voltage converter.

[0019] When this voltage converter circuit is applied to an RF switch, the area of ​​the voltage converter is greatly reduced after adopting the voltage converter circuit structure of this application. This reduces the area occupied by the voltage converter in the RF switch chip, simplifies the structure of the RF switch chip, and ensures the reliable operation of the RF switch chip, thus meeting the miniaturization requirements of the RF switch. Attached Figure Description

[0020] Figure 1 This is a block diagram of the circuit structure of commonly used RF switch chips.

[0021] Figure 2 This is a block diagram of the circuit structure of the voltage converter in a commonly used RF switch chip.

[0022] Figure 3 This is the circuit schematic of an LDO circuit, which is commonly used in voltage converters.

[0023] Figure 4 To be Figure 2 The circuit schematic shows how to replace the MOSFETs in the circuit with at least two stacked MOSFETs.

[0024] Figure 5 This is a circuit schematic diagram of the radio frequency switch chip of the present invention;

[0025] Figure 6 The simulation diagram shows the bias voltage Vreg_ana, Vreg_dig, and reference voltage Vneg generated by the voltage converter circuit of this invention. Detailed Implementation

[0026] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. It should be noted that the terms "comprising" and "having" and any variations thereof in the specification, claims and the above-mentioned drawings of the present invention are intended to cover non-exclusive inclusion. For example, a process, method, apparatus, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to these processes, methods, products or devices.

[0027] Currently, in RF switch chips, such as Figure 1 As shown, the external power supply voltage VDD is mainly converted into two sets of internal bias voltages, Vreg_ana and Vreg_dig, through a voltage converter. Both sets of voltages must be below 3V to meet the national standard requirement of 2.5V safe operating voltage for MOSFETs. Additionally, the external control voltage signal VCTRL, typically 1.6V to 3.6V high level, also needs to be converted into the internal voltage control signal BS by a level converter. The high level of BS is equal to Vreg_ana. The bias voltage Vreg_dig powers the oscillator and the negative voltage generation circuit, causing it to generate the negative voltage circuit Vneg. The driver stage, used to drive the RF switch to turn on or off, is powered by both Vreg_ana and Vneg, converting the control signal BS into the actual bias voltages Vg1, Vg2, Vb1, and Vb2 of the RF switch stage.

[0028] See Figure 2 Currently, commonly used voltage converters mainly consist of a bandgap voltage reference circuit and an LDO circuit connected in sequence. The input terminals of both the bandgap and LDO circuits are connected to a voltage source VDD. The bandgap generates a reference voltage Vref and provides the reference voltage Vref to the LDO circuit. The LDO circuit outputs a voltage Vout. Both the bandgap and LDO circuits operate at VDD (2.5V~5V). See [link to relevant documentation] Figure 3 Currently, commonly used LDO circuits mainly include an amplifier OPA, a MOSFET M1, and resistors R1 and R2. The voltage sources for the amplifier OPA and the MOSFET M1 are both VDD, with VDD typically ranging from 2.5V to 5V. The MOSFET M1 uses SOI technology with a 2.5V withstand voltage. However, when VDD is a high voltage of 5V, the MOSFET M1 is very prone to damage due to its poor withstand voltage, thus affecting the reliability of the entire RF switch chip.

[0029] Taking the output power transistor PMOS M1 of the LDO circuit as an example, when VDD = 5V and Vout = 2.5V, the output power transistor PMOS operates within its normal withstand range. However, when the entire RF switch chip is in the off state, the LDO circuit is turned off and stops working. At this time, VDD = 5V and Vout = 0V, and the operating voltage of the output power transistor PMOS M1 is 5V, exceeding the normal voltage range (the normal operating rated voltage is 2.5V), leading to device damage. The traditional way to solve the problem of poor voltage withstand capability of the above-mentioned MOS transistors is to stack several MOS transistors, see... Figure 3 The output power transistor PMOS M1 is split into two PMOS transistors, M2 and M3. Vgate is connected to the output of the LDO operational amplifier OPA, and VMID equals VDD / 2. When the RF switch chip is in the off state, the drain voltage of PMOS transistor M2 and the source voltage of PMOS transistor M3 are approximately VDD / 2. Therefore, the operating voltage of both PMOS transistors M2 and M3 is VDD / 2. Thus, even if VDD is as high as 5V, PMOS transistors M2 and M3 will still operate within their normal voltage range.

[0030] However, after splitting PMOS transistor M1 into a stacked structure of two PMOS transistors M2 and M3, in order to obtain the same current conduction capability, the size of PMOS transistors M2 and M3 is twice that of PMOS transistor M1, which increases the area of ​​the RF switch chip by 4 times. Similar high-voltage processing methods for stacked device circuits have appeared in the operational amplifiers of bandgap reference voltage circuits and LDO circuits, which greatly increases the structural complexity of the entire RF switch chip circuit and occupies more chip area.

[0031] To address the problem of poor voltage withstand capability of MOSFETs in existing RF switch chips, which is addressed by stacking two PMOS transistors to improve the voltage withstand capability, this method increases the structural complexity of the entire RF switch chip circuit, occupies more chip area, and fails to meet the miniaturization requirements of RF switch chips. This invention provides a specific embodiment of a voltage converter circuit and an RF switch, see [link to specific embodiment]. Figure 4 The voltage converter circuit includes a bandgap reference voltage circuit 1, a first LDO circuit (LDO_ana) 2, a second LDO circuit (LDO_dig) 3, a first voltage divider unit 4, a second voltage divider unit 5 connected in series with the first voltage divider unit 4, and a first switching unit 6 and a second switching unit 7 connected in parallel. The input terminals of the first voltage divider unit 4, the first switching unit 6, and the second switching unit 7 are all connected to a voltage source VDD. The output terminal of the first voltage divider unit 4 is connected to the input terminal of the second voltage divider unit 7, the control terminals of the first switching unit 6 and the second switching unit 7, respectively. The output terminal of the first switching unit 6 is connected to the input terminal of the bandgap reference voltage circuit 1 and the input terminal of the first LDO circuit 2, respectively. The output terminal of the second switching unit 7 is connected to the input terminal of the second LDO circuit 3, and the output terminal of the bandgap reference voltage circuit 1 is connected to the first LDO circuit 2 and the second LDO circuit 3, respectively. The first voltage divider unit 4 includes a resistor R1, the second voltage divider unit 5 includes several diodes connected in series, and the first switching unit 6 and the second switching unit 7 are both composed of MOSFETs.

[0032] In this embodiment, the second voltage divider unit 5 includes four diodes D1 to D4 connected in series, the first switching unit 6 includes a MOS transistor N1, and the second switching unit 7 includes a MOS transistor N2. Both MOS transistors N1 and N2 are NMOS transistors.

[0033] The voltage converter circuit also includes a filter unit 8, which includes resistors R2 and R3. The voltage source VDD is connected to the input terminal of the first switching unit 6 through resistor R2, and the voltage source VDD is connected to the input terminal of the second switching unit 7 through resistor R3.

[0034] See Figure 4The specific circuit structure of the voltage converter circuit is as follows: one end of resistors R1, R2, and R3 is connected to the voltage source VDD and the first input terminal of the first LDO circuit. The other ends of resistors R2 and R3 are connected in series with the sources of MOSFETs N1 and N2, respectively. The other end of resistor R1 is connected to the gates of MOSFETs N1 and N2 and the anode of diode D1, respectively. The drain of MOSFET N1 outputs a bias voltage Vreg_ana, which is connected to the input terminal of the bandgap reference voltage circuit and the second input terminal of the first LDO circuit, respectively. The drain of MOSFET N2 outputs a bias voltage Vreg_dig, which is connected to the first input terminal of the second LDO circuit. The output terminal of the bandgap reference voltage circuit includes: the first... The circuit has four output terminals. The first, second, and third output terminals output a reference voltage Vref and bias currents Ib1 and Ib2, respectively. The first output terminal is connected to the first LDO circuit and the second LDO circuit, providing a reference voltage Vref to both circuits. The second output terminal is connected to the first LDO circuit, providing a bias current Ib1 to it. The third output terminal is connected to the second LDO circuit, providing a bias current Ib2 to it. The cathode of diode D4, the fourth output terminal of the bandgap reference voltage circuit, the output terminal of the first LDO circuit, and the output terminal of the second LDO circuit are all grounded.

[0035] The voltage converter circuit described above is applied to an RF switch. The RF switch includes a housing, an RF switch chip encapsulated within the housing, and an RF switch chip including a substrate, a voltage converter circuit, a level converter, an oscillator and a negative voltage generation circuit, a driver stage, and an RF switch. The input terminal of the voltage converter circuit is connected to a voltage source VDD, and the output terminals are connected to the level converter, the oscillator and the negative voltage generation circuit, and the driver stage, respectively. The voltage converter circuit converts the voltage source VDD into bias voltages Vreg_ana and Vreg_dig, and provides bias voltages Vreg_ana to the level converter and the driver stage, and Vreg_dig to the oscillator and the negative voltage generation circuit, respectively. The input terminal of the level converter receives a control voltage VCTRL, which is used to convert the control voltage VCTRL and output a control voltage signal BS to control the driver stage. The oscillator and the negative voltage generation circuit generate a reference voltage Vneg and provide the reference voltage Vneg to the driver stage. Under the action of the control voltage signal BS and the reference voltage Vneg, the driver stage generates a drive signal to control the opening or closing of the RF switch. In this embodiment, the voltage converter circuit is... Figure 4 The voltage converter circuit shown is shown.

[0036] In this embodiment, the voltage source VDD is 5V, and the operating voltages of MOSFETs N1 and N2 are 1 / 2*VDD respectively; the resistance value of resistor R1 is 500 kΩ, and the resistance values ​​of resistors R2 and R3 are both 1 kΩ to 2 kΩ. Resistor R1 has a larger resistance value and is used to divide the voltage source VDD, while resistors R2 and R3 have smaller resistance values ​​and are used to filter out noise in the voltage source VDD, thereby improving the electrostatic discharge capability of the RF switch chip and further improving the stability of the RF switch chip.

[0037] The working principle of the voltage converter circuit described above is as follows: S1, the startup voltage source VDD supplies power, and the MOS transistor N1 in the first switching unit 6 is turned on, providing the startup voltage and startup current to the bandgap reference voltage circuit 1, and the bandgap reference voltage circuit 1 starts up. The gate voltage of the MOS transistor N1 is the voltage between the first voltage divider unit and the second voltage divider unit. This voltage is obtained by dividing the 5V voltage source VDD by the first voltage divider unit and the second voltage divider unit. The second voltage divider unit includes four diodes D1 to D4 connected in series. If the forward voltage drop of a single diode is 0.7V, then the forward voltage drop of the four diodes D1 to D4 connected in series is 2.8V. This voltage is the reference voltage V. At this time, the gate-source voltage Vgs1 of the MOS transistor N1 is approximately 2.8V. The threshold voltage Vth of MOSFETs N1 and N2 is 0.4V. Therefore, the bias voltage Vreg_ana = 2.8V - 0.4V = 2.4V. The rated operating voltage of MOSFETs N1 and N2 is 2.5V. Thus, the bias voltage Vreg_ana is less than the rated operating voltage. Similarly, the calculated bias voltage Vreg_dig is 2.4V. Since Vreg_dig is less than the rated operating voltage, the problem of damage to MOSFETs N1 and N2 due to their poor withstand voltage is avoided. At this time, the bandgap reference voltage circuit 1 starts up.

[0038] S2. The bandgap reference voltage circuit 1 generates a reference voltage Vref and bias currents Ib1 and Ib2, and provides the reference voltage Vref and bias currents Ib1 and Ib2 to the first LDO circuit 2 and the second LDO circuit 3, respectively. The first LDO circuit starts under the action of the reference voltage Vref and bias current Ib1, and outputs a bias voltage Vreg_ana. The second LDO circuit starts under the action of the reference voltage Vref and bias current Ib1, and outputs a bias voltage Vreg_dig. At this time, the MOS transistor N1 in the first switching unit and the second switching unit... The gate-source voltage Vgs2 of N2 is the difference between the bias voltage Vreg_ana and Vgs1: 2.4V - 2.8V = -0.4V. Therefore, Vgs2 - Vth = -0.4 - 0.4 = -0.8V < 0, which turns off MOSFETs N1 and N2. At this time, the bandgap reference voltage circuit and the first LDO circuit form the first conduction loop, and the bandgap reference voltage circuit and the second LDO circuit form the second conduction loop. The bandgap reference voltage circuit 1 is established to a steady state, thereby providing reliable bias voltages Vreg_ana and Vreg_dig for subsequent circuits.

[0039] S3. The bandgap reference voltage circuit is turned off, and MOSFETs N1 and N2 are restarted.

[0040] Figure 6 Simulation diagrams of the bias voltage Vreg_ana, Vreg_dig, and reference voltage Vneg generated by the aforementioned voltage converter under the control of the clock signal CLK are presented. Figure 6 The horizontal axis represents time, and the vertical axis represents the bias voltage Vreg_dig, bias voltage Vreg_ana, clock signal CLK, and reference voltage Vneg, respectively. Figure 6 It can be seen that in the initial stage of power supply from the starting voltage source VDD, under the control of the clock signal CLK, the bias voltage Vreg_dig and bias voltage Vreg_ana gradually increase with the clock signal CLK, and the bandgap reference voltage circuit 1 starts up and establishes a steady state, i.e., step S1; after 85 microseconds, when the first conduction loop and the second conduction loop are formed, the bandgap reference voltage circuit 1 establishes a steady state. At this time, the reference voltage Vneg gradually converts to the required voltage of about -2.5V, and the bandgap reference voltage circuit 1 establishes a steady state, thereby providing reliable bias voltages Vreg_ana and Vreg_dig for subsequent circuits.

[0041] The structure and method described in this application have the following advantages:

[0042] (1) The voltage converter circuit in the RF switch chip does not need to stack multiple large-size MOS transistor devices to meet the high voltage conversion requirements, which simplifies the circuit complexity, improves the working reliability, and saves chip area.

[0043] (2) Compared with the existing method of directly supplying power to the bandgap reference voltage circuit by the voltage source VDD, the voltage converter circuit of this application mainly provides bias voltages Vreg_ana and Vreg_dig to the bandgap reference voltage circuit by the first LDO circuit and the second LDO circuit. The bias voltages Vreg_ana and Vreg_dig are obtained by dividing the voltage source VDD. Therefore, the voltage value is less than the voltage source VDD, thereby improving the power supply rejection ratio of the RF switch chip. The improvement of the power supply rejection ratio is beneficial to suppressing noise in the output voltage and further improving the stability and reliability of the RF switch chip.

[0044] A reference voltage V is obtained by dividing the voltage using the first and second voltage divider circuits. This reference voltage V is applied to the gates of MOSFETs N1 and N2, making the operating voltage of MOSFETs N1 and N2 2.8V - 0.4V = 2.4V. This operating voltage is lower than the rated operating voltage of 2.5V. Therefore, the configuration of the first and second voltage divider circuits ensures that MOSFETs N1 and N2 operate within the normal operating voltage range, preventing damage to MOSFETs N1 and N2 due to exceeding the rated operating voltage of 2.5V.

[0045] (3) The dimensions of MOSFETs N1 and N2 are relatively large compared to current... Figure 3 The PMOS transistors M1, M2, and M3 shown are relatively small, thus saving overall chip area. Furthermore, testing shows that when the bandgap reference voltage circuit is off, the leakage current of the entire voltage converter circuit is less than or equal to 5uA, meeting the design requirements of the RF switch chip.

[0046] The above are merely preferred embodiments of this application, and the present invention is not limited to the above embodiments. It is understood that other improvements and variations that are directly derived or conceived by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included within the protection scope of the present invention.

Claims

1. A voltage converter circuit, comprising a bandgap reference voltage circuit, a first LDO circuit, and a second LDO circuit, characterized in that, It also includes a first voltage divider unit, a second voltage divider unit connected in series with the first voltage divider unit, and a first switching unit and a second switching unit connected in parallel. The input terminals of the first voltage divider unit, the first switching unit, and the second switching unit are all connected to a voltage source VDD. The output terminal of the first voltage divider unit is connected to the input terminal of the second voltage divider unit and the control terminals of the first and second switching units, respectively. The output terminal of the first switching unit is connected to the input terminal of the bandgap reference voltage circuit and the output terminal of the first LDO circuit, respectively. The output terminal of the second switching unit is connected to the output terminal of the second LDO circuit, and the output terminal of the bandgap reference voltage circuit is connected to the first LDO circuit and the second LDO circuit, respectively. The first voltage divider unit includes a resistor R1, the second voltage divider unit includes several diodes connected in series, and both the first and second switching units are composed of MOSFETs. The second voltage divider unit includes four diodes D1~D4 connected in series; the voltage source VDD is a high voltage of 5V.

2. The voltage converter circuit according to claim 1, characterized in that, The first switching unit includes a MOS transistor N1, and the second switching unit includes a MOS transistor N2, wherein both MOS transistors N1 and N2 are NMOS transistors.

3. The voltage converter circuit according to claim 2, characterized in that, It also includes a filtering unit, which includes resistors R2 and R3. The voltage source VDD is connected to the input terminal of the first switching unit through resistor R2, and the voltage source VDD is connected to the input terminal of the second switching unit through resistor R3.

4. The voltage converter circuit according to claim 3, characterized in that, One end of each of resistors R1, R2, and R3 is connected to the voltage source VDD and the first input terminal of the first LDO circuit. The other end of resistor R2 is connected in series with the source of MOSFET N1, and the other end of resistor R3 is connected in series with the source of MOSFET N2. The other end of resistor R1 is connected to the gates of MOSFETs N1 and N2 and the anode of diode D1, respectively. The drain of MOSFET N1 outputs a bias voltage Vreg_ana, which is connected to the input terminal of the bandgap reference voltage circuit and the output terminal of the first LDO circuit, respectively. The drain of MOSFET N2 outputs a bias voltage Vreg_dig, which is connected to the output terminal of the second LDO circuit. The output terminal of the bandgap reference voltage circuit includes: a first output terminal~ The fourth output terminal, the first output terminal, the second output terminal, and the third output terminal respectively output a voltage reference voltage Vref and a bias current Ib1 and Ib2. The first output terminal is connected to the first LDO circuit and the second LDO circuit respectively, providing a reference voltage Vref to the first LDO circuit and the second LDO circuit. The second output terminal is connected to the first LDO circuit, providing a bias current Ib1 to the first LDO circuit. The third output terminal is connected to the second LDO circuit, providing a bias current Ib2 to the second LDO circuit. The cathode of the diode D4, the fourth output terminal of the bandgap reference voltage circuit, the ground terminal of the first LDO circuit, and the ground terminal of the second LDO circuit are all grounded.

5. A voltage converter circuit control method, the method being used to control the voltage converter circuit of claim 1, characterized in that, The method includes: S1, powering on the start-up voltage source VDD, turning on the MOS transistors in the first switching unit and the second switching unit, and providing the bandgap reference voltage circuit with start-up voltage and start-up current; S2. The bandgap reference voltage circuit generates a reference voltage Vref and bias currents Ib1 and Ib2. The first LDO circuit starts up under the action of the reference voltage Vref and bias current Ib1 and outputs a bias voltage Vreg_ana. The second LDO circuit starts up under the action of the reference voltage Vref and bias current Ib1 and outputs a bias voltage Vreg_dig. At this time, the MOS transistors in the first switching unit and the second switching unit are turned off. The bandgap reference voltage circuit and the first LDO circuit form a first conduction loop, and the bandgap reference voltage circuit and the second LDO circuit form a second conduction loop. S3. The bandgap reference voltage circuit is turned off, and the MOS transistors N1 and N2 are restarted.

6. A radio frequency (RF) switch, comprising a housing and an RF switch chip encapsulated within the housing, the RF switch chip comprising a substrate, a voltage converter circuit, a level converter, an oscillator and a negative voltage generation circuit distributed on the substrate, a driver stage, and an RF switch, wherein the input terminal of the voltage converter circuit is connected to a voltage source VDD, and the output terminal is connected to the level converter, the oscillator and negative voltage generation circuit, and the driver stage respectively; the voltage converter circuit is used to convert the voltage source VDD into bias voltages Vreg_ana and Vreg_dig, and to provide bias voltage Vreg_ana to the level converter and the driver stage, and bias voltage Vreg_dig to the oscillator and the negative voltage generation circuit respectively; the input terminal of the level converter receives a control voltage VCTRL, the level converter is used to convert the control voltage VCTRL, and outputs a control voltage signal BS to control the driver stage; the oscillator and the negative voltage generation circuit is used to generate a reference voltage Vneg and to provide the reference voltage Vneg to the driver stage; the driver stage generates a drive signal under the action of the control voltage signal BS and the reference voltage Vneg to control the opening or closing of the RF switch, characterized in that… The voltage converter circuit uses the voltage converter circuit described in claim 1.

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