A configurable time domain pipelined analog-to-digital converter

Abstract

The application relates to a configurable time domain pipeline analog-to-digital converter, comprising: a first configurable analog-to-digital converter and a plurality of cascaded second configurable analog-to-digital converters, wherein the first configurable analog-to-digital converter serves as a first stage of the configurable time domain pipeline analog-to-digital converter, is used for converting an input voltage signal into a time signal, and transmitting the quantized time signal to the plurality of cascaded second configurable analog-to-digital converters; the second configurable analog-to-digital converter is used for amplifying and quantizing the input residual time signal stage by stage to generate corresponding digital codes and residual time signals; wherein the first configurable analog-to-digital converter and the second configurable analog-to-digital converter realize the time gain configurable function through a set of discharge and charge switch capacitor arrays. The application adopts the structure of the configurable TA and SA TDC, avoids the use of a voltage amplifier, has high linearity, meets the precision configuration requirements of the ADC, and does not need a time residual generator.

Description

Technical Field

[0001] This invention belongs to the field of analog-to-digital converter technology, and specifically relates to a configurable time-domain pipelined analog-to-digital converter. Background Technology

[0002] With the rapid development of wireless receiving systems and sensor systems, various communication standards have been adopted. Different communication standards require different bandwidths and data transmission rates, while new-generation communication standards also need to be backward compatible with previous generations; for example, 5G needs to be compatible with 4G and 3G. End users need devices that can support multiple application scenarios and communication protocols to reduce manufacturing costs, improve system performance, and minimize chip size. Configurable analog-to-digital converters (ADCs) have emerged in this context, and their high flexibility allows them to be used simultaneously in multiple communication systems such as wireless LANs, Bluetooth transmission, and digital TV receivers.

[0003] Currently, configurable analog-to-digital converters (ADCs) use a voltage-domain pipelined architecture and incorporate multiple parallel voltage amplifiers within the gain-based analog-to-digital converter (MDAC). Different conversion speeds are achieved by turning these amplifiers on and off. However, the design difficulty of high-performance voltage amplifiers in the voltage-domain architecture increases with shrinking process dimensions. Traditional pipelined sub-ADCs suffer from speed limitations or high power consumption, failing to simultaneously meet high-speed and high-precision requirements. Multi-parallel amplifier structures occupy a large area and cannot modify inter-stage gain, limiting accuracy configuration. Traditional time-domain pipelined architectures require the introduction of a time margin generator, reducing ADC operating speed, and the nonlinearity of the margin generator can affect accuracy. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a configurable time-domain pipelined analog-to-digital converter. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] This invention provides a configurable time-domain pipelined analog-to-digital converter (ADC), comprising: a first configurable ADC and a plurality of cascaded second configurable ADCs, wherein,

[0006] The first configurable analog-to-digital converter serves as the first stage of the configurable time-domain pipelined analog-to-digital converter, converting the input voltage signal into a time signal, quantizing the time signal, and transmitting it to the plurality of cascaded second configurable analog-to-digital converters.

[0007] The second configurable analog-to-digital converter is used to amplify and quantize the input margin time signal step by step to generate the corresponding digital code and margin time signal;

[0008] The first configurable analog-to-digital converter and the second configurable analog-to-digital converter achieve configurable time gain through a set switched capacitor array.

[0009] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0010] This invention relates to a configurable time-domain pipelined analog-to-digital converter (ADC) employing a configurable time amplifier (configurable TA) and a successive approximation time-to-digital converter (SA TDC) structure, avoiding the use of voltage amplifiers and making it suitable for advanced manufacturing processes. Furthermore, this invention relies on gate propagation delay quantization, offering advantages such as simple structure, small area, and low power consumption. The time amplifier in this invention has configurable gain and high linearity, meeting the accuracy configuration requirements of the analog-to-digital converter (ADC). The SA TDC naturally generates time margin information after quantization, eliminating the need for a time margin generator.

[0011] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0012] Figure 1 This is a structural block diagram of a configurable time-domain pipelined analog-to-digital converter provided in an embodiment of the present invention;

[0013] Figure 2 This is a schematic diagram of a configurable voltage-time converter provided in an embodiment of the present invention;

[0014] Figure 3 This is a schematic diagram of the structure of a successive approximation time-to-digital converter provided in an embodiment of the present invention;

[0015] Figure 4 This is a schematic diagram of a configurable time amplifier provided in an embodiment of the present invention. Detailed Implementation

[0016] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following detailed description of a configurable time-domain pipelined analog-to-digital converter based on the present invention is provided in conjunction with the accompanying drawings and specific embodiments.

[0017] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.

[0018] Please see Figure 1 , Figure 1 This is a structural block diagram of a configurable time-domain pipelined analog-to-digital converter (ADC) provided in an embodiment of the present invention. The configurable time-domain pipelined ADC of this embodiment includes: a first configurable ADC 100 and multiple cascaded second configurable ADCs 200. The first configurable ADC 100, as the first stage of the configurable time-domain pipelined ADC, is used to convert an input voltage signal into a time signal, quantize the time signal, and transmit it to the multiple cascaded second configurable ADCs. The second configurable ADCs 200 are used to amplify and quantize the input margin time signal stage by stage to generate corresponding digital codes and margin time signals. The first configurable ADC 100 and the second configurable ADC 200 achieve configurable time gain through a switched capacitor array.

[0019] In an optional embodiment, the first configurable analog-to-digital converter 100 includes a cascaded configurable voltage-to-time converter (configurable VTC) and a successive approximation time-to-digital converter (SA TDC). The configurable VTC converts an input voltage signal into a time signal, and during the signal conversion process, the time gain of the configurable VTC is configured by switching the capacitance of the switched capacitor array in the configurable VTC. The successive approximation time-to-digital converter quantizes the time signal successively to generate corresponding digital codes and a margin time signal.

[0020] In an optional embodiment, the second configurable analog-to-digital converter 200 includes a cascaded configurable time amplifier (configurable TA) and a successive approximation time-to-digital converter, wherein the configurable time amplifier is used to amplify the input margin time signal to obtain an amplified time signal; and the successive approximation time-to-digital converter is used to quantize the input amplified time signal successively to generate corresponding digital codes and margin time signals.

[0021] The configurable time-domain pipelined analog-to-digital converter (ADC) of this invention adopts a pipelined architecture to improve speed and accuracy. The SA TDC inherently generates time margins, avoiding the need for time margin generators in traditional pipelined TDCs, and offers advantages such as low power consumption and small size. Furthermore, the proposed configurable ADC features multiple configuration modes and strong scalability, making it suitable for various application scenarios.

[0022] Furthermore, the structure and working principle of each module of the configurable time-domain pipelined analog-to-digital converter in this embodiment will be described in detail.

[0023] Please see Figure 2 The schematic diagram of a configurable voltage-time converter provided by an embodiment of the present invention is shown in the figure. As shown, the configurable voltage-time converter of this embodiment includes two configurable voltage-time conversion units with identical structures. The voltage signal is input to the two configurable voltage-time conversion units and converted to obtain a time signal.

[0024] Optionally, the configurable voltage-time conversion unit includes: a first current source, a first switched capacitor array, and a threshold detection circuit. The first current source has a first terminal connected to a voltage signal via a clock switch, and a second terminal connected to ground. The clock switch is switched on and off according to an external clock signal (CLK1). The upper plate of the capacitors in the first switched capacitor array is connected to the voltage signal, and the lower plate is connected to ground. The number of capacitors connected to the voltage signal in the first switched capacitor array is controlled by an external first selection signal. The threshold detection circuit receives a voltage signal at its first input terminal, a threshold voltage at its second input terminal, and a time signal at its output terminal.

[0025] In this embodiment, a switch is used in the first switched capacitor array to switch the upper plates of the capacitors, changing the number of capacitors connected to the input voltage signals (Vinn, Vinp). When CLK1 arrives, the switch of the first current source (i.e., the discharge current source) closes, and the voltage on the capacitors in the first switched capacitor array begins to decrease. When the voltage decreases to the threshold voltage V of the back-end threshold detection circuit... TH After this, the output of the threshold detection circuit will flip, thus converting the voltage signal into a time signal. Various gain requirements can be achieved by switching the capacitor using different first selection signals (Mode1[M:0]).

[0026] Please see Figure 3 The schematic diagram of a successive approximation time-to-digital converter provided by the embodiment of the present invention is shown in the figure. As shown in the figure, the successive approximation time-to-digital converter of this embodiment includes multiple cascaded time-to-digital conversion units and a switch array. The time-to-digital conversion unit includes: a time comparator, two delay units, and two selectors.

[0027] In this system, the two inputs of the time comparator are connected to the inputs of the two delay units, and the outputs of the two delay units are connected to the inputs of the two selectors. The control signal terminals of the two selectors are connected to the outputs of the time comparator. The inputs of the two delay units of the first time-to-digital converter are connected to the input time signal, and the inputs of the two delay units of the remaining time-to-digital converters are connected to the outputs of the two selectors of the previous time-to-digital converter. The outputs of the two selectors of all time-to-digital converters are connected to a switch array. The switch array is opened and closed by an external control signal (Mode2[M:0]) to output quantized margin time signals (Tresp, Tresn) of different precision modes.

[0028] In this embodiment, SATDC is used to quantize time information and obtain a digital code. The quantization process is as follows: a time comparator is used to quantize the input time signal (T). OP and T ON ) for comparison, while T OP and T ON After passing through different delay units, the data is input into a 2-to-1 multiplexer (MUX). The output of the multiplexer is controlled based on the comparison result of the time comparator, thus obtaining the time margin information and preparing for the next comparison. After quantization, an N-bit digital code B is obtained. <n-1:0>The switch array is controlled by an external control signal (Mode2[M:0]) to select different margin information to be transmitted to the next stage of configurable time amplifier to complete pipeline quantization.

[0029] In this embodiment, the successive approximation time-to-digital converters in the first configurable analog-to-digital converter 100 and the second configurable analog-to-digital converter 200 have the same structure.

[0030] Please see Figure 4 The schematic diagram of a configurable time amplifier provided by the embodiment of the present invention is shown in the figure. As shown, the configurable time amplifier of this embodiment includes a cascaded configurable time-voltage converter (configurable TVC) and a configurable voltage-time converter (configurable VTC).

[0031] The configurable time-voltage converter controls the turn-on time of the current source according to the input margin time signal and converts it into a voltage signal stored on the switched capacitor array; the configurable voltage-time converter converts the input voltage signal into a time signal to obtain an amplified time signal; and during the signal amplification process, the time gain of the configurable time amplifier is configured through the configurable time-voltage converter and the capacitors of the switched capacitor array in the configurable voltage-time converter.

[0032] like Figure 4 As shown, the configurable time-voltage converter includes: a trigger unit, logic gates, a charging current source, a discharging current source, and two second switched capacitor arrays. In this embodiment, the flip-flop unit and logic gate generate corresponding current source control signals based on the input margin time signal. The flip-flop unit includes two flip-flops, and the logic gate is an AND gate. The margin time signal (Tresp, Tresn) corresponds to the clock input of the two flip-flops. The input terminals of the two flip-flops receive external signals, and the output terminals output current source control signals. These current source control signals are input to the input terminals of the AND gate, and the output terminals of the AND gate are connected to the reset terminals of the two flip-flops respectively. The first terminal of the charging current source is connected to the power supply terminal, and the second terminal is connected to the upper plate of a second switched capacitor array through a current source control switch. The first terminal of the discharging current source is connected to the upper plate of another second switched capacitor array through a current source control switch, and the second terminal is connected to the ground terminal. The lower plates of the capacitors in both second switched capacitor arrays are connected to the ground terminal. The number of capacitors connected to the corresponding current source in the second switched capacitor array is controlled by an external second selection signal (Mode3[M:0]). The upper plates of the capacitors in the two second switched capacitor arrays are connected as output terminals to the input terminals of the configurable voltage-time converter.

[0033] In this embodiment, the input margin time signal is converted into a voltage signal stored on the second switched capacitor array by controlling the turn-on time of the configurable TVC discharge / charge current source. The voltage signal is then converted into a time signal (i.e., an amplified time signal) by the configurable VTC. The structure of the configurable VTC is consistent with the structure of the configurable voltage-time converter in the configurable analog-to-digital converter 100, such as... Figure 2 As shown, it will not be elaborated upon here.

[0034] In this embodiment, by designing the transistor size, the current of the current source of the configurable time-to-voltage converter and the configurable voltage-to-time converter in the configurable time amplifier is equal, i.e., I TV =I VT At this point, the gain of the configurable time amplifier depends only on the capacitor value. The time gain can be configured by simply switching the discharge / charge capacitors of the configurable TVC and configurable VTC using external selection signals (Mode1[M:0], Mode3[M:0]). Furthermore, since the gain of the configurable time amplifier depends only on the capacitor value, its linearity is good.

[0035] It should be noted that in this embodiment, the voltage-time converter can be configured as a discharge current source type, while in other embodiments, a charging current source type or a current-starved type can also be used.

[0036] The configurable time-domain pipelined analog-to-digital converter (ADC) of this invention employs a configurable timing amplifier (TA) and a saturable time-delay converter (SA TDC), avoiding the use of voltage amplifiers and making it suitable for advanced manufacturing processes. Furthermore, this invention relies on propagation delay quantization of circuit gates, offering advantages such as simple structure, small area, and low power consumption. The timing amplifier of this invention has configurable gain and high linearity, meeting the accuracy configuration requirements of the ADC. The SA TDC naturally generates time margin information after quantization, eliminating the need for a time margin generator.

[0037] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes said element. Terms such as "connected" or "linked" are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect.

[0038] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A configurable time domain pipelined analog-to-digital converter, comprising: The application relates to a configurable time-domain pipeline analog-to-digital converter. The application comprises: a first configurable analog-to-digital converter and a plurality of cascaded second configurable analog-to-digital converters, the first configurable analog-to-digital converter is used as a first stage of the configurable time-domain pipeline analog-to-digital converter, for converting an input voltage signal into a time signal and transmitting the quantized time signal to the plurality of cascaded second configurable analog-to-digital converters; the second configurable analog-to-digital converter is used for performing step-by-step amplification quantization on the input residual time signal to generate a corresponding digital code and a residual time signal; wherein the first configurable analog-to-digital converter and the second configurable analog-to-digital converter realize the function of time gain configuration through a set of switch capacitor arrays; the first configurable analog-to-digital converter comprises a cascaded configurable voltage-time converter and a successive approximation type time-to-digital converter, the configurable voltage-time converter is used for converting an input voltage signal into a time signal, and the time gain of the configurable voltage-time converter is configured by switching the capacitances of the switch capacitor array in the configurable voltage-time converter during the signal conversion process; the successive approximation type time-to-digital converter is used for performing step-by-step quantization on the time signal to generate a corresponding digital code and a residual time signal; the configurable voltage-time converter comprises two configurable voltage-time conversion units with the same structure, and the voltage signal is input into the two configurable voltage-time conversion units to obtain the time signal; the configurable voltage-time conversion unit comprises a first current source, a first switch capacitor array and a threshold detection circuit, the first end of the first current source is connected to the voltage signal through a clocked switch, and the second end is connected to a ground end; the clocked switch realizes conduction and shutdown according to an external clock signal; the upper plate of the capacitor of the first switch capacitor array is connected to the voltage signal, and the lower plate of the capacitor is connected to the ground end; the number of capacitors connected to the voltage signal in the first switch capacitor array is controlled through an external first selection signal; 2. The configurable time-domain pipelined analog-to-digital converter of claim 1, wherein, the first input end of the threshold detection circuit inputs the voltage signal, the second input end inputs a threshold voltage, and the output end outputs the time signal. the successive approximation type time-to-digital converter comprises a plurality of cascaded time-to-digital conversion units and a switch array, and the time-to-digital conversion unit comprises a time comparator, two delay units and two selectors, the two input ends of the time comparator are connected to the input ends of the two delay units, the output ends of the two delay units are connected to the input ends of the two selectors, and the control signal ends of the two selectors are connected to the output end of the time comparator; the input ends of the two delay units of the first time-to-digital conversion unit input the time signal, and the input ends of the two delay units of the remaining time-to-digital conversion units are connected to the output ends of the two selectors of the previous time-to-digital conversion unit; the output ends of the two selectors of all the time-to-digital conversion units are connected to the switch array. The closing and opening of the switch array are controlled by an external control signal to output a residual time signal quantized in different precision modes.

3. The configurable time-domain pipelined analog-to-digital converter of claim 1, wherein, The second configurable analog-to-digital converter comprises a cascade of a configurable time amplifier and a successive approximation type time-to-digital converter, wherein, The configurable time amplifier is configured to amplify an input residual time signal to obtain an amplified time signal. The successive approximation type time-to-digital converter is configured to quantize the input amplified time signal successively to generate a corresponding digital code and a residual time signal.

4. The configurable time-domain pipelined analog-to-digital converter of claim 3, wherein, The configurable time amplifier comprises a cascade of a configurable time-to-voltage converter and a configurable voltage-to-time converter, wherein, The configurable time-to-voltage converter is configured to control the on-time of a current source according to an input residual time signal, and convert the current source into a voltage signal stored on a switch capacitor array. The configurable voltage-to-time converter is configured to convert an input voltage signal into a time signal to obtain an amplified time signal. In the signal amplification process, the capacitances of the switch capacitor arrays in the configurable time-to-voltage converter and the configurable voltage-to-time converter are configured to configure the time gain of the configurable time amplifier.

5. The configurable time-domain pipelined analog-to-digital converter of claim 4, wherein, The configurable time-to-voltage converter comprises a flip-flop unit, a logic gate, a charging current source, a discharging current source, and two second switch capacitor arrays, wherein, The flip-flop unit and the logic gate generate a corresponding current source control signal according to an input residual time signal. The first end of the charging current source is connected to a power supply end, and the second end is connected to the upper plate of a capacitor of one of the second switch capacitor arrays through a current source control switch. The first end of the discharging current source is connected to the upper plate of a capacitor of the other second switch capacitor array through a current source control switch, and the second end is connected to a ground end. The lower plates of the capacitors of the two second switch capacitor arrays are connected to the ground end. The number of capacitors connected to the corresponding current source in the second switch capacitor array is controlled by an external second selection signal. The upper plates of the capacitors of the two second switch capacitor arrays are connected to the input end of the configurable voltage-to-time converter as an output end.

6. The configurable time-domain pipelined analog-to-digital converter of claim 5, wherein, The currents of the current sources of the configurable time-to-voltage converter and the configurable voltage-to-time converter in the configurable time amplifier are equal.

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