Parallel Computing Method Based on Probabilistic Bit Circuits

Abstract

The present disclosure provides a parallel computing method based on a probabilistic bit circuit. The method includes transforming a problem to be solved to obtain a Hamiltonian relation function corresponding to the problem to be solved; mapping multiple nodes of the Hamiltonian relation function in the probabilistic bit circuit, the probabilistic bit circuit including a plurality of parallel modules, the parallel module including a plurality of probabilistic bits, and one probabilistic bit corresponding to one node; solving the Hamiltonian relation function by using the probabilistic bit circuit to obtain a Hamiltonian; randomly updating the plurality of probabilistic bits in the plurality of parallel modules to obtain a state of a new probabilistic bit circuit; solving the Hamiltonian relation function by using the state of the new probabilistic bit circuit to obtain a new Hamiltonian; and generating a solution to the problem to be solved according to the states of the plurality of probabilistic bits corresponding to the Hamiltonian or the new Hamiltonian when the Hamiltonian or the new Hamiltonian satisfies a preset threshold.

Description

Technical Field

[0001] The present disclosure relates to the technical field of probabilistic bits, and more particularly, to a parallel computing method based on a probabilistic bit circuit. Background Art

[0002] Problems such as optimization, sampling, and back-calculation are usually difficult to solve using traditional digital computers. Although quantum computers based on superconducting qubits are promising to solve the above problems efficiently, they need to operate in a low-temperature environment. Probabilistic bit circuits are a class of circuits inspired by quantum computing and can solve problems such as optimization, sampling, and back-calculation based on randomness at room temperature. However, probabilistic computing usually can only achieve serial computing, which seriously hinders its computing efficiency. Some existing parallel computing methods for probabilistic bit circuits require a large number of auxiliary probabilistic bits and are usually only applicable to solving sparse problems with a density of less than 5%. Their applications are greatly limited, and at the same time, their solving speed and the accuracy of the solving results are less than satisfactory. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a parallel computing method based on a probabilistic bit circuit, including:

[0004] Converting the problem to be solved to obtain a Hamiltonian relation function corresponding to the problem to be solved, where the Hamiltonian relation function includes a plurality of nodes;

[0005] Mapping the plurality of nodes of the Hamiltonian relation function in a probabilistic bit circuit, where the probabilistic bit circuit includes a plurality of parallel modules, the parallel module includes a plurality of probabilistic bits, and one probabilistic bit corresponds to one of the nodes;

[0006] Solving the Hamiltonian relation function using the probabilistic bit circuit to obtain a Hamiltonian;

[0007] In the case that the Hamiltonian does not meet a preset threshold, randomly updating the plurality of probabilistic bits in the plurality of parallel modules to obtain a state of a new probabilistic bit circuit;

[0008] Solving the Hamiltonian relation function using the state of the new probabilistic bit circuit to obtain a new Hamiltonian;

[0009] In the case that the Hamiltonian or the new Hamiltonian meets the preset threshold, generating a solution to the problem to be solved according to the states of the plurality of probabilistic bits corresponding to the Hamiltonian or the new Hamiltonian.

[0010] According to an embodiment of the present disclosure, randomly updating the plurality of nodes in the plurality of parallel modules to obtain a state of a new probabilistic bit circuit includes:

[0011] Randomly shuffle the order of a preset number of probability bits in multiple of the above parallel modules to obtain multiple shuffled probability bits;

[0012] Divide the multiple shuffled probability bits to obtain multiple new parallel modules, where the above new probability bit circuit includes multiple of the above new parallel modules.

[0013] According to an embodiment of the present disclosure, the number of probability bits in different of the above parallel modules is the same or different.

[0014] According to an embodiment of the present disclosure, the above probability bit circuit includes:

[0015] A processor or a controller;

[0016] A digital-to-analog converter, the input end of the digital-to-analog converter is connected to the output end of the processor or the controller;

[0017] A demultiplexer, the input end of the demultiplexer is connected to the output end of the digital-to-analog converter;

[0018] Multiple of the above probability bits, the input end of the probability bits is connected to the output end of the demultiplexer, and the multiple of the above probability bits are divided into multiple of the above parallel modules;

[0019] A multiplexer, the input end of the multiplexer is connected to the output end of the probability bits;

[0020] An analog-to-digital converter, the input end of the analog-to-digital converter is connected to the output end of the multiplexer, and the output end of the analog-to-digital converter is connected to the input end of the processor or the controller.

[0021] According to an embodiment of the present disclosure, the above probability bits include:

[0022] Multiple groups of word lines arranged vertically at intervals, each group of word lines includes a writing word line and a reading word line spaced apart by a preset distance;

[0023] Multiple groups of bit lines arranged horizontally at intervals, where the above bit line group includes a read control bit line, a write control bit line, and a ground line arranged horizontally from top to bottom, the write control bit line and the ground line in one of the above bit line groups, the above writing word line and the above reading word line in each of the above line groups enclose a placement area;

[0024] Multiple magnetic tunnel junctions, one of the above magnetic tunnel junctions is arranged in each of the above placement areas;

[0025] Among them, the first port of the above-mentioned magnetic tunnel junction is connected to the above-mentioned read control bit line, the second port is connected to the above-mentioned read word line, the third port is connected to the above-mentioned write control bit line, the fourth port is connected to the above-mentioned write word line, and the fifth port is connected to the above-mentioned ground wire.

[0026] According to an embodiment of the present disclosure, the above-mentioned magnetic tunnel junction includes:

[0027] A magnetic tunnel structure, wherein the output end of the above-mentioned magnetic tunnel structure is connected to the above-mentioned ground wire;

[0028] A first transistor, the first end of the above-mentioned first transistor is connected to the first surface of the above-mentioned magnetic tunnel structure, the second end of the above-mentioned first transistor is connected to the above-mentioned read control bit line, and the third end of the above-mentioned first transistor is connected to the above-mentioned read word line;

[0029] A second transistor, the first end of the above-mentioned second transistor is connected to the second surface of the above-mentioned magnetic tunnel structure, the second end of the above-mentioned second transistor is connected to the above-mentioned write word line, and the third end of the above-mentioned second transistor is connected to the above-mentioned write control bit line.

[0030] According to an embodiment of the present disclosure, the above-mentioned magnetic tunnel structure includes:

[0031] A spin-orbit coupling layer, one end of the above-mentioned spin-orbit coupling layer is connected to the above-mentioned ground wire, and the other end is connected to the first end of the above-mentioned second transistor;

[0032] A magnetic free layer, disposed on the upper surface of the above-mentioned spin-orbit coupling layer;

[0033] A spacer layer, disposed on the upper surface of the above-mentioned magnetic free layer;

[0034] A top electrode layer, disposed on the upper surface of the above-mentioned spacer layer, and the above-mentioned top electrode layer is connected to the first end of the above-mentioned first transistor.

[0035] According to an embodiment of the present disclosure, the above-mentioned magnetic tunnel structure includes:

[0036] A magnetic reference layer, disposed between the above-mentioned spacer layer and the above-mentioned top electrode layer.

[0037] According to an embodiment of the present disclosure, the above-mentioned magnetic reference layer includes:

[0038] At least one magnetic layer, the material of the above-mentioned magnetic layer includes at least one of ferromagnetic material, ferrimagnetic material, and antiferromagnetic material, and the above-mentioned magnetic layer has perpendicular magnetic anisotropy.

[0039] According to an embodiment of the present disclosure, the material of the above-mentioned spin-orbit coupling layer includes at least one of transition metals and rare earth elements and their alloys, half-metals, topological insulators, or alloys or multi-layer heterostructures composed of transition metals and rare earth elements and their alloys, half-metals, topological insulators;

[0040] The above magnetic free layer has perpendicular magnetic anisotropy, and the material of the above magnetic free layer includes at least one of ferromagnetic materials, ferrimagnetic materials, and antiferromagnetic materials;

[0041] The material of the above spacer layer is a material with a semiconductor or insulator bandgap;

[0042] The material of the above top electrode layer is a conductive metal.

[0043] According to an embodiment of the present disclosure, by mapping multiple nodes of a Hamiltonian relation function corresponding to a problem to be solved onto probability qubits in different parallel modules of a probability qubit circuit, and randomly updating the multiple nodes in the multiple parallel modules during the iterative solution process, the Hamiltonian relation function is iteratively solved using the new probability qubit circuit until the obtained Hamiltonian satisfies a preset threshold, and then the solution to the problem to be solved is generated according to the states of the multiple probability qubits corresponding to the Hamiltonian. By iteratively and randomly updating the nodes in the probability qubit circuit, the present disclosure can obtain a more accurate solution result on the premise of ensuring the solution speed. At the same time, the parallel computing method of the present disclosure does not require adding any auxiliary probability qubits, solving the problem that existing probability calculation methods cannot perform parallel computing or require auxiliary probability qubits for parallel computing. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Through the following description of the embodiments of the present disclosure with reference to the drawings, the above and other objects, features, and advantages of the present disclosure will become clearer. In the drawings:

[0045] Figure 1 Schematically shows a flowchart of a parallel computing method according to an embodiment of the present disclosure;

[0046] Figure 2 Schematically shows a schematic diagram of updating probability qubits according to an embodiment of the present disclosure;

[0047] Figure 3 Schematically shows a schematic structural diagram of a probability qubit circuit according to an embodiment of the present disclosure;

[0048] Figure 4 Schematically shows a schematic structural diagram of a probability qubit according to an embodiment of the present disclosure;

[0049] Figure 5 Schematically shows a schematic structural diagram of a magnetic tunnel junction according to an embodiment of the present disclosure;

[0050] Figure 6 Schematically shows a schematic structural diagram of a magnetic tunnel structure according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0051] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In the following detailed description, for the sake of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. However, it is obvious that one or more embodiments can also be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

[0052] The terms used herein are merely for describing specific embodiments and are not intended to limit the present disclosure. The terms "including", "comprising", etc. used herein indicate the presence of the described features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0053] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0054] In cases where expressions similar to "at least one of A, B, and C, etc." are used, generally, it should be interpreted according to the meaning commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include, but not be limited to, a system having only A, only B, only C, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.). In cases where expressions similar to "at least one of A, B, or C, etc." are used, generally, it should be interpreted according to the meaning commonly understood by those skilled in the art (for example, "a system having at least one of A, B, or C" should include, but not be limited to, a system having only A, only B, only C, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.).

[0055] Embodiments of the present disclosure provide a parallel computing method based on a probabilistic bit circuit. The method includes transforming a problem to be solved to obtain a Hamiltonian relation function corresponding to the problem to be solved, where the Hamiltonian relation function includes a plurality of nodes; mapping the plurality of nodes of the Hamiltonian relation function in a probabilistic bit circuit, where the probabilistic bit circuit includes a plurality of parallel modules, and the parallel module includes a plurality of probabilistic bits, and one probabilistic bit corresponds to one node; using the probabilistic bit circuit to solve the Hamiltonian relation function to obtain a Hamiltonian; in the case where the Hamiltonian does not satisfy a preset threshold, randomly updating the plurality of probabilistic bits in the plurality of parallel modules in random order to obtain a state of a new probabilistic bit circuit; using the state of the new probabilistic bit circuit to solve the Hamiltonian relation function to obtain a new Hamiltonian; in the case where the Hamiltonian or the new Hamiltonian satisfies the preset threshold, generating a solution to the problem to be solved according to the states of the plurality of probabilistic bits corresponding to the Hamiltonian or the new Hamiltonian.

[0056] Figure 1 FIG. schematically shows a flowchart of a parallel computing method according to an embodiment of the present disclosure.

[0057] As Figure 1 shown, the parallel computing method based on the probabilistic bit circuit includes operations S101 to S105.

[0058] In operation S101, transform the problem to be solved to obtain a Hamiltonian relation function corresponding to the problem to be solved, where the Hamiltonian relation function includes a plurality of nodes;

[0059] In operation S102, map the plurality of nodes of the Hamiltonian relation function in a probabilistic bit circuit, where the probabilistic bit circuit includes a plurality of parallel modules, and the parallel module includes a plurality of probabilistic bits, and one probabilistic bit corresponds to one node;

[0060] In operation S103, use the probabilistic bit circuit to solve the Hamiltonian relation function to obtain a Hamiltonian;

[0061] In operation S104, in the case where the Hamiltonian does not satisfy a preset threshold, randomly update the plurality of nodes in the plurality of parallel modules in random order to obtain a state of a new probabilistic bit circuit;

[0062] In operation S105, use the state of the new probabilistic bit circuit to solve the Hamiltonian relation function to obtain a new Hamiltonian;

[0063] In operation S106, in the case where the Hamiltonian or the new Hamiltonian satisfies the preset threshold, generate a solution to the problem to be solved according to the states of the plurality of probabilistic bits corresponding to the Hamiltonian or the new Hamiltonian.

[0064] According to an embodiment of the present disclosure, the probabilistic bit circuit may be a spin transfer torque (STT) probabilistic device, a spin orbit torque (SOT) probabilistic device, a probabilistic bit constructed based on CMOS transistors, etc.

[0065] According to an embodiment of the present disclosure, the problem to be solved is modeled and transformed to obtain a corresponding Hamiltonian relation function. Among them, the problem to be solved may be a combinatorial optimization problem such as a traveling salesman problem, a maximum cut / minimum cut problem, a graph coloring problem, a knapsack problem, a vertex cover problem, a minimum spanning tree, a Boolean satisfiability problem, etc., and an inverse calculation problem such as integer factorization and reversible logic applied to rapid solution. Multiple nodes of the Hamiltonian relation function are mapped in the probabilistic bit circuit. At this time, each probabilistic bit in the probabilistic bit circuit corresponds to a node in the Hamiltonian relation function.

[0066] According to an embodiment of the present disclosure, the initialized probabilistic bit circuit is used to solve the Hamiltonian relation function to obtain a Hamiltonian, and it is determined whether the Hamiltonian satisfies a preset threshold. The preset threshold is determined according to the type of the problem to be solved. For some problems to be solved, the larger the Hamiltonian of the probabilistic bit circuit, the better, while for some problems to be solved, the smaller the Hamiltonian of the probabilistic bit circuit, the better. In some embodiments, the preset threshold may be 1 or 0.01, etc.

[0067] According to an embodiment of the present disclosure, in the case where the Hamiltonian does not satisfy the preset threshold, the nodes in multiple parallel modules are randomly updated in order. For example, the nodes in different parallel modules are swapped, and then the new probabilistic bit circuit after the swap is used to solve the Hamiltonian relation function to obtain a new Hamiltonian. The above operations are iteratively repeated until the Hamiltonian or the new Hamiltonian satisfies the preset threshold. At this time, the solution to the problem to be solved can be generated according to the states of multiple probabilistic bits corresponding to the current iteration. Among them, regarding the states of multiple probabilistic bits as the configurations corresponding to multiple nodes is the solution to the problem to be solved.

[0068] According to an embodiment of the present disclosure, by mapping multiple nodes of a Hamiltonian relation function corresponding to a problem to be solved onto probability qubits of different parallel modules in a probability qubit circuit, randomly updating the multiple nodes in the multiple parallel modules in a random order during the iterative solution process to iteratively solve the Hamiltonian relation function using the new probability qubit circuit until the obtained Hamiltonian satisfies a preset threshold, and generating a solution to the problem to be solved according to the states of the multiple probability qubits corresponding to the Hamiltonian. By iteratively and randomly updating the nodes in the probability qubit circuit in a random order, the present disclosure can obtain a more accurate solution result on the premise of ensuring the solution speed. At the same time, the parallel computing method of the present disclosure does not require adding any auxiliary probability qubits, solving the problem that existing probability calculation methods cannot perform parallel computing or require auxiliary probability qubits for parallel computing.

[0069] Figure 2 Schematically shows a schematic diagram of updating probability qubits according to an embodiment of the present disclosure.

[0070] According to an embodiment of the present disclosure, randomly updating multiple nodes in multiple parallel modules to obtain the state of a new probability qubit circuit includes:

[0071] Randomly shuffling the order of a preset number of probability qubits in the multiple parallel modules to obtain multiple shuffled probability qubits;

[0072] Dividing the multiple shuffled probability qubits to obtain multiple new parallel modules, where the new probability qubit circuit includes multiple new parallel modules.

[0073] According to an embodiment of the present disclosure, the preset number can be adjusted according to actual needs, generally not exceeding 1 / 2 of the total number of probability qubits. The reason is that the smaller the proportion, the lower the solution speed, while too high a proportion will reduce the accuracy of the solution result. If all N probability qubits are updated in parallel, the probability qubit circuit can hardly solve the problem to be solved.

[0074] According to an embodiment of the present disclosure, as Figure 2 shown, the numbers in the grid represent different probability qubits (p 1 , p 2 , …, p N ). In the first iteration, the probability qubits are in order (p 1 , p 2, …) are updated, and multiple probability bits can be updated in parallel each time. Each iteration can include multiple parallel modules, and each parallel module can update multiple probability bits in parallel. The number of probability bits updated by different parallel modules can be the same or different until all the probability bits are updated. In subsequent iterations, before updating the probability bits each time, use a classical shuffling algorithm or any other method of randomly shuffling the order to randomly shuffle the update order of the probability bits, and then perform the update; each iteration can include multiple parallel modules, and each parallel module can update multiple probability bits in parallel. The number of probability bits updated by different parallel modules can be the same or different until all the probability bits are updated. Repeat the above iteration process until the optimal or sub-optimal solution to the problem is obtained.

[0075] Figure 3 Schematically shows a schematic diagram of the probability bit circuit 300 according to an embodiment of the present disclosure.

[0076] According to an embodiment of the present disclosure, the probability bit circuit 300 includes:

[0077] A processor or controller 310;

[0078] A digital-to-analog converter 320, the input end of the digital-to-analog converter 320 is connected to the output end of the processor or controller 310;

[0079] A demultiplexer 330, the input end of the demultiplexer 330 is connected to the output end of the digital-to-analog converter 320;

[0080] Multiple probability bits 340, the input ends of the probability bits 340 are connected to the output end of the demultiplexer 330, and the multiple probability bits 340 are divided into multiple parallel modules;

[0081] A multiplexer 350, the input end of the multiplexer 350 is connected to the output end of the probability bit 340;

[0082] An analog-to-digital converter 360, the input end of the analog-to-digital converter 360 is connected to the output end of the multiplexer 350, and the output end of the analog-to-digital converter 360 is connected to the input end of the processor or controller 310.

[0083] According to an embodiment of the present disclosure, the processor or controller 310 is used to process the digital signal converted by the analog-to-digital converter (ADC) 360, and is used to randomly reset the update order of the probability bits 340.

[0084] According to an embodiment of the present disclosure, the multiple probability bits 340 form a spin-orbit torque probability bit circuit 300 for performing the parallel probability calculation proposed by the present disclosure.

[0085] According to an embodiment of the present disclosure, a multiplexer (MUX) 350 is configured to output a plurality of signals read from a probability bit circuit 300.

[0086] According to an embodiment of the present disclosure, an analog-to-digital converter 360 (ADC) is configured to convert the plurality of signals output by the multiplexer 350 into digital signals; a digital-to-analog converter (DAC) 320 is configured to convert the switching probability value obtained by a processor or a controller 310 into an analog signal.

[0087] According to an embodiment of the present disclosure, a demultiplexer (DEMUX) 330 is configured to perform read and write operations on the probability bits 340 following the analog signal converted by the digital-to-analog converter 320.

[0088] Figure 4 A schematic structural diagram of the probability bits 340 according to an embodiment of the present disclosure is schematically shown.

[0089] According to an embodiment of the present disclosure, the probability bits 340 include:

[0090] A plurality of word line groups arranged vertically at intervals, each word line group including a write word line 341 and a read word line 342 spaced apart by a preset distance;

[0091] A plurality of bit line groups arranged horizontally at intervals, wherein the bit line group includes a read control bit line 343, a write control bit line 344, and a ground line 345 arranged horizontally from top to bottom. The write control bit line 344 and the ground line 345 in one bit line group, and the write word line 341 and the read word line 342 in each word line group enclose a placement area 346;

[0092] A plurality of magnetic tunnel junctions 347, with one magnetic tunnel junction 347 provided in each placement area 346;

[0093] Wherein, the first port of the magnetic tunnel junction 347 is connected to the read control bit line 343, the second port is connected to the read word line 342, the third port is connected to the write control bit line 344, the fourth port is connected to the write word line 341, and the fifth port is connected to the ground line 345. Wherein, the write word line 341, the read word line 342, and the write control bit line 344 are connected to the demultiplexer (DEMUX), and the read control bit line 343 and the ground line 345 are connected to the multiplexer (MUX).

[0094] Figure 5 A schematic structural diagram of the magnetic tunnel junction 347 according to an embodiment of the present disclosure is schematically shown.

[0095] According to an embodiment of the present disclosure, as Figure 5 shown, the magnetic tunnel junction (MTJ) 347 includes:

[0096] A magnetic tunnel structure, wherein the output end of the magnetic tunnel structure is connected to the ground line 345;

[0097] A first transistor 301, a first end of the first transistor 301 is connected to a first surface of the magnetic tunnel structure, a second end of the first transistor 301 is connected to a read control bit line 343, and a third end of the first transistor 301 is connected to a read word line 342;

[0098] A second transistor 302, a first end of the second transistor 302 is connected to a second surface of the magnetic tunnel structure, a second end of the second transistor 302 is connected to a write word line 341, and a third end of the second transistor 302 is connected to a write control bit line 344.

[0099] According to an embodiment of the present disclosure, the first surface may refer to the upper surface of the magnetic tunnel structure, and the second surface may refer to the side surface of the spin-orbit coupling layer 303 in the magnetic tunnel structure.

[0100] Figure 6 A schematic structural diagram of a magnetic tunnel structure according to an embodiment of the present disclosure is schematically shown.

[0101] According to an embodiment of the present disclosure, the magnetic tunnel structure includes:

[0102] A spin-orbit coupling layer 303 (i.e., a bottom electrode layer), one end of the spin-orbit coupling layer 303 is connected to a ground wire 345, and the other end is connected to a first end of the second transistor 302;

[0103] A magnetic free layer 304, disposed on the upper surface of the spin-orbit coupling layer 303;

[0104] A spacer layer 305, disposed on the upper surface of the magnetic free layer 304;

[0105] A top electrode layer 306, disposed on the upper surface of the spacer layer 305, and the top electrode layer 306 is connected to a first end of the first transistor 301.

[0106] According to an embodiment of the present disclosure, the magnetic tunnel structure includes:

[0107] A magnetic reference layer, disposed between the spacer layer 305 and the top electrode layer 306.

[0108] According to an embodiment of the present disclosure, the magnetic reference layer includes:

[0109] At least one magnetic layer, the material of the magnetic layer includes at least one of ferromagnetic material, ferrimagnetic material, and antiferromagnetic material, and the magnetic layer has perpendicular magnetic anisotropy.

[0110] According to an embodiment of the present disclosure, the material of the spin-orbit coupling layer 303 includes at least one of transition metals and rare earth elements and their alloys, half-metals, topological insulators, or alloys or multilayer heterostructures composed of transition metals and rare earth elements and their alloys, half-metals, topological insulators;

[0111] The magnetic free layer 304 has perpendicular magnetic anisotropy, and the material of the magnetic free layer 304 includes at least one of ferromagnetic materials, ferrimagnetic materials, and antiferromagnetic materials;

[0112] The material of the spacer layer 305 is a material having a semiconductor or insulator band gap;

[0113] The material of the top electrode layer 306 is a conductive metal.

[0114] According to embodiments of the present disclosure, the transition metal elements may include Pt, Ir, W, Ta, Hf, Zr, Mo, Ru, Rh, Pd, Cd, Ti, V, Cr, Mn, Zn, etc., and the rare earth elements may include La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, etc. The half-metals may include Mn 3 Pt, Mn 3 Pd, Mn 3 Sn, Mn 3 Ge, FeGe, FeSn, Fe 3 Sn 2 , Co 3 Sn 2 S 2 , TbMn 6 Sn 6 , two-dimensional WTe 2 etc. The topological insulators may include BiSb, BiSe, BiSbTe, etc.

[0115] According to embodiments of the present disclosure, the ferromagnetic materials may include Fe, Co, Ni, CoFe, CoFeB, Co 3 Sn 2 S 2 , Fe 3 Sn 2 , two-dimensional FeGeTe, two-dimensional FeGaTe, etc. The ferrimagnetic materials may include CoGd, CoTb, CoDy, CoHo, GdFeCo, FeTb, TbMn 6 Sn 6 etc. The antiferromagnetic materials may include IrMn 3 , PtMn, Mn 3 Pt, Mn 3 Pd, Mn 3 Sn, Mn 3 Ge, FeGe, FeSn, RuO 2 , two-dimensional TaCoTe 2 etc.

[0116] According to an embodiment of the present disclosure, the material of the spacer layer 305 is a material having a semiconductor or insulator bandgap, such as AlO x , MgO, TiO 2 , BN, GaSe, InSe, WSe 2 , WS 2 , MoTe 2 , MoSe 2 and so on.

[0117] According to an embodiment of the present disclosure, the material of the top electrode layer 306 is a conductive metal, such as Al, Cu, Ag, Au, Pt, Ti, etc.

[0118] According to an embodiment of the present disclosure, the method proposed by the present disclosure can effectively solve the problem that the solution result of the probabilistic bit circuit 300 deteriorates due to parallel computing during sequential update. According to the probabilistic bit circuit parallel computing method of the present disclosure, compared with the completely serial probabilistic bit circuit computing method, there is almost no difference in the solution result, and the solution result is far better than the scheme without updating the probabilistic bit 340, and it can solve the problem that the computing speed of the completely serial probabilistic bit circuit is too slow. The probabilistic bit circuit parallel computing method proposed by the present disclosure can greatly improve the computing speed, and as the problem scale increases, the higher the parallelism, the higher the improved computing speed. For example, for a problem with only 10 p-bits, compared with the completely serial method, a maximum computing acceleration of 5 times can be achieved (each iteration contains at least two parallel branches); while for a problem with 1000 p-bits, compared with the completely serial method, a maximum computing acceleration of 500 times can be achieved.

[0119] According to an embodiment of the present disclosure, the probabilistic bit circuit parallel computing method proposed by the present disclosure does not require adding any auxiliary probabilistic bits, solving the problem that the existing probabilistic computing methods cannot perform parallel computing or require auxiliary probabilistic bits for parallel computing. It can be applied to solving problems of any density, while the existing parallel computing methods can only solve sparse problems with a density of less than 5%. As the problem scale increases, the parallelism is higher, which is beneficial to faster and more efficient probabilistic computing.

[0120] The above describes the embodiments of the present disclosure. However, these embodiments are only for illustrative purposes and not for limiting the scope of the present disclosure. Although the embodiments are described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present disclosure.

Claims

1. A parallel computing method based on a probabilistic bit circuit, comprising: transforming the problem to be solved to obtain a Hamiltonian relation function corresponding to the problem to be solved, wherein the Hamiltonian relation function includes a plurality of nodes; mapping the plurality of nodes of the Hamiltonian relation function in a probabilistic bit circuit, wherein the probabilistic bit circuit includes a plurality of parallel modules, the parallel module includes a plurality of probabilistic bits, and one probabilistic bit corresponds to one of the nodes; solving the Hamiltonian relation function by using the probabilistic bit circuit to obtain a Hamiltonian; in the case where the Hamiltonian does not satisfy a preset threshold, randomly updating the plurality of probabilistic bits in the plurality of parallel modules to obtain a state of a new probabilistic bit circuit; solving the Hamiltonian relation function by using the state of the new probabilistic bit circuit to obtain a new Hamiltonian; in the case where the Hamiltonian or the new Hamiltonian satisfies the preset threshold, generating a solution to the problem to be solved according to the states of the plurality of probabilistic bits corresponding to the Hamiltonian or the new Hamiltonian; wherein, randomly updating the plurality of nodes in the plurality of parallel modules to obtain a new probabilistic bit circuit includes: randomly shuffling the order of a preset number of probabilistic bits in the plurality of parallel modules to obtain a plurality of shuffled probabilistic bits; dividing the plurality of shuffled probabilistic bits to obtain a plurality of new parallel modules, wherein the new probabilistic bit circuit includes the plurality of new parallel modules.

2. The method according to claim 1, wherein, the number of probabilistic bits in different parallel modules is the same or different.

3. The method according to claim 1, wherein, the probabilistic bit circuit includes: a processor or a controller; a digital-to-analog converter, an input end of the digital-to-analog converter is connected to an output end of the processor or the controller; a multiplexer, an input end of the multiplexer is connected to an output end of the digital-to-analog converter; a plurality of the probabilistic bits, an input end of the probabilistic bit is connected to an output end of the multiplexer, and the plurality of probabilistic bits are divided into a plurality of the parallel modules; a demultiplexer, an input end of the demultiplexer is connected to an output end of the probabilistic bit; an analog-to-digital converter, an input end of the analog-to-digital converter is connected to an output end of the demultiplexer, and an output end of the analog-to-digital converter is connected to an input end of the processor or the controller.

4. The method according to claim 3, wherein, the probabilistic bit includes: a plurality of word line groups arranged vertically at intervals, each word line group includes a write word line and read word lines spaced apart by a preset distance; a plurality of bit line groups arranged horizontally at intervals, wherein the bit line group includes a read control bit line, a write control bit line, and a ground line arranged horizontally from top to bottom, and the write control bit line and the ground line in one bit line group, and the write word line and the read word lines in each word line group enclose a placement area; a plurality of magnetic tunnel junctions, and one magnetic tunnel junction is arranged in each of the placement areas; Among them, the first port of the magnetic tunnel junction is connected to the read control bit line, the second port is connected to the read word line, the third port is connected to the write control bit line, the fourth port is connected to the write word line, and the fifth port is connected to the ground wire.

5. The method according to claim 4, wherein, the magnetic tunnel junction includes: a magnetic tunnel structure, wherein the output end of the magnetic tunnel structure is connected to the ground wire; a first transistor, the first end of the first transistor is connected to the first surface of the magnetic tunnel structure, the second end of the first transistor is connected to the read control bit line, and the third end of the first transistor is connected to the read word line; a second transistor, the first end of the second transistor is connected to the second surface of the magnetic tunnel structure, the second end of the second transistor is connected to the write word line, and the third end of the second transistor is connected to the write control bit line.

6. The method according to claim 5, wherein, the magnetic tunnel structure includes: a spin-orbit coupling layer, one end of the spin-orbit coupling layer is connected to the ground wire, and the other end is connected to the first end of the second transistor; a magnetic free layer, disposed on the upper surface of the spin-orbit coupling layer; a spacer layer, disposed on the upper surface of the magnetic free layer; a top electrode layer, disposed on the upper surface of the spacer layer, and the top electrode layer is connected to the first end of the first transistor.

7. The method according to claim 6, the magnetic tunnel structure includes: a magnetic reference layer, disposed between the spacer layer and the top electrode layer.

8. The method according to claim 7, wherein, the magnetic reference layer includes: at least one magnetic layer, the material of the magnetic layer includes at least one of ferromagnetic material, ferrimagnetic material, and antiferromagnetic material, and the magnetic layer has perpendicular magnetic anisotropy.

9. The method according to claim 6, wherein, the material of the spin-orbit coupling layer includes at least one of transition metals and rare earth elements and their alloys, half-metals, topological insulators, or alloys or multi-layer heterostructures composed of transition metals and rare earth elements and their alloys, half-metals, topological insulators; the magnetic free layer has perpendicular magnetic anisotropy, and the material of the magnetic free layer includes at least one of ferromagnetic material, ferrimagnetic material, and antiferromagnetic material; the material of the spacer layer is a material with a semiconductor or insulator band gap; the material of the top electrode layer is a conductive metal.

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