Display panel, driving method thereof and display device

Abstract

The application discloses a display panel and a driving method thereof and a display device. The display panel comprises a plurality of data lines configured to provide a data signal to enable the display panel to display an original picture based on the data signal; a plurality of feedback circuits comprising a first detection circuit, a second detection circuit and a compensation circuit, wherein the first detection circuit is configured to sample a data expected voltage on the data line in a first time period of the original picture; the second detection circuit is configured to sample a data reference voltage on the data line in a second time period of the original picture; the compensation circuit is connected with the first detection circuit and the second detection circuit, and is configured to obtain a compensation voltage based on the data expected voltage and the data reference voltage; and the display panel is enabled to display a compensation picture based on the compensation voltage, the compensation picture being a next frame picture adjacent to the original picture.

Description

Technical Field

[0001] This application generally relates to the field of display technology, and specifically to a display panel and its driving method, and a display device. Background Technology

[0002] Typically, a display panel includes multiple scan lines, multiple data lines, and multiple pixels, which are formed at the intersections of the data lines and scan lines. The driving circuit of the display panel includes a gate driving circuit and a data driving circuit. The gate driving circuit outputs a scan gate signal to the scan lines, and the data driving circuit outputs a data voltage to the data lines.

[0003] Because the screen gate signal typically has a short signal drop time and a large voltage drop when it is turned off, and there is a coupling capacitor between the scan lines and the data lines, the data voltage is pulled down during the gate signal turn-off process and cannot be recovered when the TFT is completely turned off, thus causing display abnormalities. Summary of the Invention

[0004] In view of the above-mentioned defects or deficiencies in the prior art, it is desirable to provide a display panel and its driving method and display device that can improve the display effect.

[0005] In a first aspect, this application provides a display panel, including: Multiple data lines are configured to provide data signals so that the display panel displays the original image based on the data signals; Multiple feedback circuits, each of which is connected to one of the data lines, wherein each feedback circuit includes a first detection circuit, a second detection circuit, and a compensation circuit, wherein... The first detection circuit is configured to sample the expected voltage of the data on the data line during a first time period of the original image; The second detection circuit is configured to sample the data reference voltage on the data line during a second time period of the original image; The compensation circuit is connected to the first detection circuit and the second detection circuit. The compensation circuit is configured to obtain a compensation voltage based on the expected data voltage and the reference data voltage, so that the display panel displays a compensation image based on the compensation voltage. The compensation image is the next frame adjacent to the original image.

[0006] Optionally, it also includes: Multiple scan lines, configured to provide scan signals, so that the display panel displays the original image based on the scan signals and the data signals; wherein... The first time period is configured as a first preset time before the current scan signal is turned off; the second time period is configured as a second preset time after the current scan signal is turned off and before the next scan signal is turned on, wherein the current scan signal and the next scan signal are both scan signals corresponding to the original image displayed on the display panel.

[0007] Optionally, the first detection circuit includes: A first sampling control sub-circuit, wherein a first terminal of the first sampling control sub-circuit is connected to the data line, and a control terminal of the first sampling control sub-circuit is connected to a first sampling signal; A sample storage circuit is connected to the second terminal of the first sampling control sub-circuit and the compensation circuit. The sample storage circuit is configured to store the expected data voltage during the first time period and provide the expected data voltage to the compensation circuit during the second time period.

[0008] Optionally, the first sampling control sub-circuit includes a first transistor, a first terminal of the first transistor is connected to the data line, and a control terminal of the first transistor is connected to the first sampling signal; The storage transistor circuit includes a first amplifier, a storage capacitor, a first diode, and a second diode. The non-inverting input terminal of the first amplifier is connected to the second terminal of the first transistor, the negative input terminal of the first amplifier is connected to the first terminal of the storage capacitor and the anode of the first diode, the output terminal of the first amplifier is connected to the cathode of the first diode and the anode of the second diode, and the second terminal of the storage capacitor is grounded.

[0009] Optionally, the second detection circuit includes: The second sampling control sub-circuit has its control terminal connected to the second sampling signal, its first terminal connected to the data line, and its second terminal connected to the compensation circuit.

[0010] Optionally, the second sampling control sub-circuit includes a second transistor, the first terminal of which is connected to the data line, and the control terminal of which is connected to the second sampling signal.

[0011] Optionally, the compensation circuit includes a second amplifier, the non-inverting input terminal of the second amplifier being connected to the first terminal of the storage capacitor and the negative terminal of the second diode, and the negative-inverting input terminal of the second amplifier being connected to the second terminal of the second transistor and the output terminal of the second amplifier.

[0012] Optionally, it also includes: A data driving circuit, connected to the plurality of data lines and the compensation circuit, is configured to provide the data signal and the compensation voltage to the data lines; A gate driving circuit, which is connected to a plurality of scan lines, is configured to provide scan signals to the scan lines.

[0013] Secondly, this application provides a driving method for a display panel, optionally employing a display panel as described in any of the above descriptions, the method comprising: The display panel displays the original image based on the data signal; The expected voltage of the data on the data line is sampled during the first time period of the original image; The data reference voltage on the data line is sampled during the second time period of the original image; A compensation voltage is obtained based on the expected data voltage and the reference data voltage; so that the display panel displays a compensation image based on the compensation voltage, the compensation image being the next frame adjacent to the original image.

[0014] Thirdly, this application provides a display device including a display panel as described in any of the above.

[0015] The technical solutions provided by the embodiments of this application may include the following beneficial effects: The display panel provided in this embodiment samples the highest, lowest, and final values ​​of the Data voltage during the Gate signal shutdown process using a first and second detection circuit on the data line. The compensation circuit calculates the compensation grayscale, thereby preprocessing the original image and inserting frames after the original image for compensation. This increases the number of display grayscale levels, achieves the desired grayscale brightness, and improves the display effect. Attached Figure Description

[0016] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This is a schematic diagram of the existing coupling between Gate and Data signals; Figure 2 A schematic diagram of the structure of a display panel provided for an embodiment of this application; Figure 3 A schematic diagram of a feedback circuit provided for an embodiment of this application; Figure 4 A timing diagram of a display panel provided for an embodiment of this application; Figure 5 This is a schematic diagram illustrating the compensation principle of a display panel, provided as an embodiment of this application. Detailed Implementation

[0017] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0018] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0019] Research has revealed that current mobile and notebook products use both positive and negative gate voltages, with a typical voltage difference between 14V and 30V and a fall time of 1µs. Furthermore, under the existing panel design architecture, the coupling between the data line (DL) and the scan line (GL) is virtually unavoidable. Large voltage changes in the gate signal within a short period can severely impact the data level. Figure 1 As shown. For example, in a liquid crystal display panel, when the Gate signal drops to the TFT turn-off voltage, the internal voltage difference of the liquid crystal locks, and the Data voltage has no recovery time, which will cause the Data voltage to deviate from the Source IC output voltage.

[0020] For example, in OLED display panels, OLEDs are positively charged self-emissive devices, and a deviation in the Data voltage will result in a lower overall OLED organic light-emitting voltage. If compensation is made by increasing the Gamma voltage by a fixed value during Gamma Tuning, the actual offset value will vary depending on the panel load, coupling capacitance, and displayed grayscale values. Even within the same batch of products, manufacturing errors can cause differences in the required compensation value. Furthermore, with current low-power consumption demands leading to a general reduction in Data voltage, the difference between adjacent grayscale levels is as small as 2mV. Under the requirements of high transmittance and color accuracy, fixed-value compensation is insufficient to meet the need for accurate grayscale color display.

[0021] Please see details. Figure 2-3 This application provides a display panel, including: Multiple data lines DL are configured to provide a data signal Data, so that the display panel displays the original image based on the data signal Data; Multiple feedback circuits 100, each of which is connected to one of the data lines DL, each feedback circuit 100 includes a first detection circuit 11, a second detection circuit 12, and a compensation circuit 13, wherein... The first detection circuit 11 is configured to sample the expected data voltage Vs on the data line DL during a first time period T1 of the original image; The second detection circuit 12 is configured to sample the data reference voltage Vo on the data line DL during the second time period T2 of the original image; The compensation circuit 13 is connected to the first detection circuit 11 and the second detection circuit 12. The compensation circuit 13 is configured to obtain a compensation voltage OUT based on the expected data voltage Vs and the reference data voltage Vo, so that the display panel displays a compensation screen based on the compensation voltage OUT, and the compensation screen is the next frame adjacent to the original screen.

[0022] The display panel provided in this embodiment of the application samples the highest, lowest and final values ​​of the Data voltage during the Gate signal turn-off process through the first detection circuit 11 and the second detection circuit 12 set on the data line DL, respectively. The compensation circuit 13 calculates the compensation grayscale, thereby preprocessing the original image and inserting frames after the original image for compensation, which increases the number of display grayscale levels, achieves the desired grayscale brightness, and improves the display effect.

[0023] In this embodiment of the application, the display panel has multiple pixel units P arranged in an array to form multiple pixel rows and multiple pixel columns. Figure 2 In the example, multiple pixel units are arranged in multiple rows along a first direction (X direction in the figure) and in multiple columns along a second direction (Y direction in the figure). The first direction and the second direction intersect each other. In the embodiment of this application, the first direction and the second direction intersect perpendicularly, and the first direction and the second direction can be interchanged.

[0024] In this embodiment, the display panel includes multiple data lines DL and multiple scan lines GL, which intersect to define multiple pixel units P. The data lines DL extend along the column direction, and the scan lines GL extend along the row direction. Each scan line GL corresponds to a pixel row, and each data line DL corresponds to a pixel column. Each data line DL connects to a column of pixel units P, and each scan line GL connects to a row of pixel units P. The multiple data lines DL write data voltage into the pixel units P row by row.

[0025] In this embodiment, the display panel further includes a data driving circuit 200 and a gate driving circuit 300. The gate driving circuit 300 outputs a scan signal Gate, which performs a row-by-row scan of the pixel array via scan lines GL. The data driving circuit 200 outputs a data signal Data, which is transmitted to the corresponding pixel unit P via data lines DL to achieve image grayscale. Specifically, during the display stage, the gate driving circuit 300 outputs scan signals Gate to multiple scan lines GL row by row to activate the pixel unit P connected to each scan line GL row by row. Then, the required data signal Data is written to the activated sub-pixel units row by row via all column data lines DL, thereby achieving display.

[0026] In this embodiment of the application, the gate driving circuit 300 and the data driving circuit 200 provide signals to the display panel to display the original image and the compensated image. The scan line GL is configured to provide a scan signal Gate, so that the display panel displays the original image based on the scan signal Gate and the data signal Data, and displays the compensated image based on the scan signal Gate and the compensation voltage OUT. The data driving circuit 200 is connected to the plurality of data lines DL and the compensation circuit 13, and is configured to provide the data signal Data and the compensation voltage OUT to the data lines DL. The gate driving circuit 300 is connected to the plurality of scan lines GL and is configured to provide the scan signal Gate to the scan lines GL.

[0027] In the embodiments of this application, such as Figure 4 As shown, the first time period T1 is configured as a first preset time t1 before the current scan signal Gate is turned off; the second time period T2 is configured as a second preset time t2 after the current scan signal Gate is turned off and before the next scan signal Gate is turned on, wherein the current scan signal Gate and the next scan signal Gate are both the scan signal Gate corresponding to the original image displayed on the display panel.

[0028] It should be noted that, in this embodiment, the specific values ​​of the first preset time t1 and the second preset time t2 are not limited, and can be adjusted as needed in different embodiments. In this embodiment, within the first preset time t1 before the current scan signal Gate is turned off, the voltage value corresponding to the data signal Data on the data line DL is the highest voltage of the Data signal. Within the second preset time t2 after the current scan signal Gate is turned off and before the next scan signal Gate is turned on, the data reference voltage Vo on the data line DL is the actual voltage of the original image.

[0029] In this embodiment of the application, the first detection circuit 11 includes: A first sampling control sub-circuit 101, the first terminal of the first sampling control sub-circuit 101 is connected to the data line DL, and the control terminal of the first sampling control sub-circuit 101 is connected to the first sampling signal S1. The sample storage circuit 102 is connected to the second terminal of the first sampling control sub-circuit 101 and the compensation circuit 13. The sample storage circuit 102 is configured to store the expected data voltage Vs during the first time period T1 and provide the expected data voltage Vs to the compensation circuit 13 during the second time period T2.

[0030] The second detection circuit 12 includes: The second sampling control sub-circuit 103 has its control terminal connected to the second sampling signal, its first terminal connected to the data line DL, and its second terminal connected to the compensation circuit 13.

[0031] In a specific configuration, the first sampling control sub-circuit 101 includes a first transistor M1, the first terminal of which is connected to the data line DL, and the control terminal of which is connected to the first sampling signal S1; the sample storage circuit 102 includes a first amplifier X1, a storage capacitor C1, a first diode D1, and a second diode D2, the non-inverting input terminal of the first amplifier X1 is connected to the second terminal of the first transistor M1, the negative-inverting input terminal of the first amplifier X1 is connected to the first terminal of the storage capacitor C1 and the anode of the first diode D1, the output terminal of the first amplifier X1 is connected to the cathode of the first diode D1 and the anode of the second diode D2, and the second terminal of the storage capacitor C1 is grounded.

[0032] The second sampling control sub-circuit 103 includes a second transistor M2, the first terminal of the second transistor M2 is connected to the data line DL, and the control terminal of the second transistor M2 is connected to the second sampling signal.

[0033] The compensation circuit 13 includes a second amplifier X2. The positive input terminal of the second amplifier X2 is connected to the first terminal of the storage capacitor C1 and the negative terminal of the second diode D2. The negative input terminal of the second amplifier X2 is connected to the second terminal of the second transistor M2 and the output terminal of the second amplifier X2.

[0034] It is understood that, in order to improve the accuracy of the circuit in acquiring voltage and calculating compensation voltage OUT in this embodiment of the application, the feedback circuit 100 may also include other electronic components, such as resistors, inductors, etc. Exemplarily, a first resistor R1 is provided between the first transistor M1 and the non-inverting input terminal of the first amplifier X1; a second resistor R2 is provided between the anode of the first diode D1 and the cathode of the second diode D2; a third resistor R3 is provided between the second diode D2 and the non-inverting input terminal of the second amplifier X2; a fourth resistor R4 is provided between the storage capacitor C1 and the cathode of the second diode D2; a fifth resistor R5 is provided between the second terminal of the second transistor M2 and the negative input terminal of the second amplifier X2; a sixth resistor R6 is provided between the negative input terminal and the output terminal of the second amplifier X2; and a seventh resistor R7 is also provided on the non-inverting input terminal of the second amplifier X2, with the other end of the seventh resistor R7 grounded.

[0035] In this embodiment, the negative terminal of the second diode D2 is connected to the second terminal of the second resistor R2, the first terminal of the third resistor R3, and the second terminal of the fourth resistor R4 at the first node U1. The first terminal of the second resistor R2 is connected to the negative input terminal of the first amplifier X1 and the positive terminal of the first diode D1. The second terminal of the third resistor R3 is connected to the positive input terminal of the second amplifier X2 and the first terminal of the seventh resistor R7. The first terminal of the fourth resistor R4 is connected to the first terminal of the storage capacitor C1.

[0036] It should be noted that the transistors used in all embodiments of this invention are thin-film transistors, field-effect transistors, or other devices with the same characteristics. Since the source and drain of the transistors used here are symmetrical, there is no difference between their source and drain. In the embodiments of this application, in order to distinguish the two poles of the transistor other than the gate, one pole is called the first terminal and the other pole is called the second terminal.

[0037] Furthermore, transistors can be classified into N-type and P-type based on their characteristics. The following embodiments use N-type transistors as examples. When using an N-type transistor, the first terminal can be the source, and the second terminal can be the drain. It is conceivable that using a P-type transistor is easily conceived by those skilled in the art without inventive effort, and therefore falls within the scope of protection of this invention. As is known in the art, an N-type transistor is turned on by a high-level control signal and turned off by a low-level control signal; a P-type transistor is turned on by a low-level control signal and turned off by a high-level control signal.

[0038] It is understood that the transistors used in the circuit of this application can be MOS transistors (metal-oxide-semiconductor field-effect transistors), TFT transistors (thin film transistors), or other types of transistors. The specific choice can be made according to the actual situation. The alternative solutions are still within the protection scope of this application. The connection method of TFT transistors or other types of transistors can be referred to the connection method of MOS transistors, which will not be repeated here.

[0039] The first detection circuit 11 mainly samples during the first time period T1 after the Data stabilizes. The output voltage of this detection period is the highest voltage of the Data signal during the entire sampling period. Since the Data voltage is pulled down as a whole during the coupling process (Gate voltage pull-down), the sampled voltage can be determined as the expected voltage Vs of the Data.

[0040] During the first time period T1, S1 is at a high level, the first transistor M1 is turned on, and C1 is charged through the non-inverting input of the first amplifier X1 and D2. Since the resistance of R4 is very small, the current in the path X1-D2-C1 is large, and C1 can quickly rise to the maximum level. When the Data voltage decreases, the discharge path of C1 is the R2-D1 path. The large resistance of R2 limits the current, and the discharge speed of C1 is extremely slow, so that the voltage of node U1 connected to the first end of C1 remains at Vs during the sampling time and is output to X2.

[0041] In this embodiment, the entire sampling period includes a first time period T1, a gate off time period t0, and a second time period T2. The first detection circuit 11 is used for sampling during the first time period T1. The gate off time period t0 is the gate signal off pull-down process until the TFT controlled by the gate signal is completely turned off. The second detection circuit 12 is used for sampling during the second time period T2.

[0042] The first sampling signal S1 remains at a high level during the first time period T1, the Gate off time period, and the second time period T2. The first transistor M1 remains in the on state throughout the entire sampling period. The pull-down of the Data voltage does not affect the voltage of node U1.

[0043] For example, the first sampling signal S1 needs to include sampling of the stable voltage after the Source is charged. Therefore, it needs to be within the stable charging time of the Source before the Gate is turned off. Thus, the turn-on time of the first sampling signal S1 can be t1=1us ​​before the clock signal CLK starts to fall.

[0044] It should be noted that, in this embodiment of the application, when the CLK signal is high, the Gate signal is enabled during the scanning period of the current pixel row; when the CLK signal is low, the current pixel row is closed and the next pixel row is charged; the Gate signal is turned off at the falling edge of CLK. The display panel described in this application is equipped with a counter. When the falling edge of CLK is detected by the counter, the S1 signal is generated by the timing controller (Tcon).

[0045] The second sampling control sub-circuit 103 is used to detect the data reference voltage Vo when the actual Data signal is charging while the Gate signal is turned off. Therefore, the sampling time (second time period T2) of the second sampling control sub-circuit 103 is after the current row's Gate signal is completely turned off and before the next row's Gate signal is turned on.

[0046] For example, the second sampling signal S2 needs to include the voltage of the Data signal after the Gate signal is completely turned off to obtain the data reference voltage Vo. Therefore, the turn-on time of S2 is designed to be t2 = 1.5us after CLK starts to fall (CLK falling edge).

[0047] In this embodiment, the compensation circuit 13 is a subtraction circuit. The two ends of the second amplifier X2 are input Vs and Vo. According to the virtual short and virtual open circuit of the second amplifier X2, the potentials at the input terminals of the second amplifier X2 are equal:

[0048] When R5=R6=R3=R7=10kΩ Therefore, the difference between the coupled Data signal and the required value can be calculated. .

[0049] It should be noted that, in this embodiment of the application, the compensation circuit 13 may also include other voltage processing units to obtain the compensation voltage OUT. For example, the compensation circuit 13 may output to a voltage ADC unit for sampling, convert the sampled analog voltage into a digital voltage, and transmit the digital voltage to the timing controller Tcon or AP terminal, and calculate the compensation through an internal grayscale-voltage lookup table.

[0050] Based on the same concept, this application provides a driving method for a display panel, optionally employing a display panel as described above, the method comprising: The display panel displays the original image based on the data signal Data; The expected voltage Vs on the data line DL is sampled during the first time period T1 of the original image. The data reference voltage Vo on the data line DL is sampled during the second time period T2 of the original image. A compensation voltage OUT is obtained based on the expected data voltage Vs and the reference data voltage Vo; so that the display panel displays a compensation screen based on the compensation voltage OUT, the compensation screen being the next frame adjacent to the original screen.

[0051] It is worth noting that, such as Figure 5 As shown, there is a coupling phenomenon between the scan lines GL and the data lines DL when the display panel displays the image. This phenomenon exists not only when displaying the original image but also when displaying the compensated image. Therefore, in this embodiment, when displaying the compensated image, the data voltage on the data line DL corresponding to the compensated image is twice the value of the compensation voltage OUT. The original image and the compensated image are compensated by using twice the compensation voltage OUT. By adjusting the data voltage of the compensated image, the image that the display panel can display can be the image corresponding to the expected data voltage Vs.

[0052] For example, the output of a normal data voltage will be lower than normal after being coupled. For instance, the original voltage grayscale might be 127, but after being pulled down by the falling edge of the gate, the actual voltage grayscale becomes 123 (in the original image). Therefore, when obtaining... After the voltage is equal to 4 grayscale voltages, it needs to be multiplied by 2 during compensation. The compensation is applied to the image, which is then output as 135 gray levels. During display, the display frequency is doubled. The original 60Hz 127 gray level image is split into two images: 120Hz 127 gray level and 135 gray level. The actual display of 120Hz 123 gray level (original image) and 131 gray level (compensated image) is equivalent to the actual 127 gray level display effect, achieving a precise improvement in display gray levels.

[0053] Display frequency refers to the number of times an image is refreshed per second. In the embodiments of this application, the provided display scheme can improve the display effect by increasing the display frequency.

[0054] This application provides a display device, including a display panel as described in any of the above descriptions.

[0055] The display device provided in this application embodiment can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0056] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention.

[0057] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0058] Unless otherwise defined, the technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used herein is for descriptive purposes only and is not intended to limit the invention. Terms such as “setup” appearing herein can refer to either a component being directly attached to another component or a component being attached to another component via an intermediary. A feature described in one embodiment herein may be applied, alone or in combination with other features, to another embodiment, unless that feature is not applicable in that other embodiment or is otherwise stated.

[0059] The present invention has been described through the above embodiments; however, it should be understood that the above embodiments are for illustrative purposes only and are not intended to limit the present invention to the described embodiments. Those skilled in the art will understand that many variations and modifications can be made based on the teachings of the present invention, and all such variations and modifications fall within the scope of protection claimed by the present invention.

Claims

1. A display panel, characterized in that, include: Multiple data lines are configured to provide data signals so that the display panel displays the original image based on the data signals; Multiple feedback circuits, each of which is connected to one of the data lines, wherein each feedback circuit includes a first detection circuit, a second detection circuit, and a compensation circuit, wherein... The first detection circuit is configured to sample the expected voltage of the data on the data line during a first time period of the original image; The second detection circuit is configured to sample the data reference voltage on the data line during a second time period of the original image; The compensation circuit is connected to the first detection circuit and the second detection circuit, and the compensation circuit is configured to obtain a compensation voltage based on the expected data voltage and the data reference voltage; so that the display panel displays a compensation image based on the compensation voltage, and the compensation image is the next frame adjacent to the original image; Multiple scan lines, configured to provide scan signals, so that the display panel displays the original image based on the scan signals and the data signals; wherein... The first time period is configured as a first preset time before the current scan signal is turned off; the second time period is configured as a second preset time after the current scan signal is turned off and before the next scan signal is turned on, wherein the current scan signal and the next scan signal are both scan signals corresponding to the original image displayed on the display panel.

2. The display panel according to claim 1, characterized in that, The first detection circuit includes: A first sampling control sub-circuit, wherein a first terminal of the first sampling control sub-circuit is connected to the data line, and a control terminal of the first sampling control sub-circuit is connected to a first sampling signal; A sample storage circuit is connected to the second terminal of the first sampling control sub-circuit and the compensation circuit. The sample storage circuit is configured to store the expected data voltage during the first time period and provide the expected data voltage to the compensation circuit during the second time period.

3. The display panel according to claim 2, characterized in that, The first sampling control sub-circuit includes a first transistor, a first terminal of the first transistor is connected to the data line, and a control terminal of the first transistor is connected to the first sampling signal; The storage transistor circuit includes a first amplifier, a storage capacitor, a first diode, and a second diode. The non-inverting input terminal of the first amplifier is connected to the second terminal of the first transistor, the negative input terminal of the first amplifier is connected to the first terminal of the storage capacitor and the anode of the first diode, the output terminal of the first amplifier is connected to the cathode of the first diode and the anode of the second diode, and the second terminal of the storage capacitor is grounded.

4. The display panel according to claim 3, characterized in that, The second detection circuit includes: The second sampling control sub-circuit has its control terminal connected to the second sampling signal, its first terminal connected to the data line, and its second terminal connected to the compensation circuit.

5. The display panel according to claim 4, characterized in that, The second sampling control sub-circuit includes a second transistor, the first terminal of which is connected to the data line, and the control terminal of which is connected to the second sampling signal.

6. The display panel according to claim 5, characterized in that, The compensation circuit includes a second amplifier, the positive input terminal of which is connected to the first terminal of the storage capacitor and the negative terminal of the second diode, and the negative input terminal of which is connected to the second terminal of the second transistor and the output terminal of the second amplifier.

7. The display panel according to claim 1, characterized in that, Also includes: A data driving circuit, connected to the plurality of data lines and the compensation circuit, is configured to provide the data signal and the compensation voltage to the data lines; A gate driving circuit, which is connected to a plurality of scan lines, is configured to provide scan signals to the scan lines.

8. A driving method for a display panel, characterized in that, The method, employing a display panel as described in any one of claims 1-7, comprises: The display panel displays the original image based on the data signal; The expected voltage of the data on the data line is sampled during the first time period of the original image; The data reference voltage on the data line is sampled during the second time period of the original image; A compensation voltage is obtained based on the expected data voltage and the reference data voltage; so that the display panel displays a compensation image based on the compensation voltage, the compensation image being the next frame adjacent to the original image.

9. A display device, characterized in that, Includes the display panel as described in any one of claims 1-7.

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