A display panel, control circuit, method and device thereof

Abstract

The application discloses a display panel and a control circuit, method and device thereof, comprising: a level conversion module, the level conversion module is used for receiving an overcurrent protection signal and generating a black screen GOA output signal based on the overcurrent protection signal; the black screen GOA output signal is used for providing a GOA effective signal for the display panel to control each pixel row to be in an open state, so that the display panel is blackened based on the black screen GOA output signal. When the level conversion module receives the overcurrent protection signal, the black screen GOA output signal is generated, and the GOA effective signal generated by the black screen GOA output signal is the gate effective level, so that the TFT on the display panel pixel circuit is opened, each pixel row on the display panel is in the open state, and when the overcurrent protection is executed, the display panel is quickly blackened, the problem of picture difference after the OCP triggering in the prior art is solved, the charge in the panel is discharged, the service life of the display panel is improved, and the user experience and product quality are improved.

Description

TECHNICAL FIELD

[0001] The present application generally relates to the technical field of display, and in particular to a display panel and a control circuit, method and device thereof. BACKGROUND

[0002] Liquid crystal display panel adopts GOA architecture (Gate Drive On Array), that is, the gate drive IC is integrated on the thin film transistor array substrate, so as to realize driving the liquid crystal panel by row-by-row scanning.

[0003] In order to prevent the short circuit between clock signals caused by floating particles in the GOA architecture liquid crystal display panel, an over current protection circuit (OCP) is usually used, which aims to prevent the panel temperature from rising due to excessive current after the panel short circuit, and to prevent burns and the like.

[0004] However, in the prior art, when the OCP over current protection mechanism is executed, the GOA is directly disconnected, which causes the charge in the pixel electrode to be lost through the TFT leakage current, the picture is frozen and slowly blackened, and in the eyes of the user, the screen is damaged, which raises doubts about the product quality and affects the user experience. SUMMARY

[0005] In view of the above defects or deficiencies in the prior art, it is desirable to provide a display panel and a control circuit, method and device thereof, which can solve the problem of picture difference after OCP triggering, improve user experience and product quality.

[0006] In a first aspect, the present application provides a control circuit of a display panel, comprising:

[0007] a level conversion module, configured to receive an over current protection signal and generate a black screen GOA output signal based on the over current protection signal; the black screen GOA output signal is used to provide a GOA effective signal for the display panel to control each pixel row to be in an open state, so that the display panel is black screened based on the black screen GOA output signal.

[0008] Optionally, the control circuit further comprises:

[0009] a power management module, connected with the level conversion module, the level conversion module is configured to generate a control signal based on the over current protection signal; the power management module is configured to power off a power line based on the received control signal, the power line is used to provide a power signal for the display panel and the level conversion module.

[0010] Optionally, the power supply signals include one or more of a VGH signal, an AVDD signal, and a VCOM signal, and each of the power supply signals corresponds to a power supply line that is synchronized to be powered off based on the received control signal.

[0011] Optionally, the display panel further comprises:

[0012] a power supply module connected to the power management module and the level conversion module, the level conversion module configured to generate a control signal based on the overcurrent protection signal, and the power supply module configured to control a backlight module of the display panel to be turned off based on the received control signal.

[0013] Optionally, the power supply module is configured to generate a power-on signal, and the power management module and the power supply module are configured to exit an overcurrent protection state based on the power-on signal.

[0014] Optionally, the display panel further comprises:

[0015] a timing control module connected to the level conversion module, the timing control module configured to provide a timing signal to the level conversion module.

[0016] Optionally, the timing control module is connected to the power management module and configured to synchronize the timing signal and the power supply signal to be powered off based on the control.

[0017] Optionally, the display panel further comprises:

[0018] a data driving module connected to the level conversion module, the level conversion module configured to generate a control signal based on the overcurrent protection signal, and the data driving module configured to synchronize an output data voltage and a voltage of a VCOM signal based on the control signal.

[0019] Optionally, the display panel comprises a pixel electrode and a common electrode, the common electrode is connected to a common power supply line, the common power supply line is configured to provide a VCOM signal to the common electrode, and the pixel electrode is connected to the data driving module, the data driving module is configured to provide a data voltage to the pixel electrode.

[0020] In a second aspect, the present application provides a display panel applied to the control circuit of any of the display panels described above, the display panel comprising an array substrate and a counter substrate.

[0021] Optionally, the array substrate comprises a pixel electrode, and the counter substrate comprises a common electrode, the common electrode is connected to a common power supply line, the common power supply line is configured to provide a VCOM signal to the common electrode, and the pixel electrode is connected to a data driving module, the data driving module is configured to provide a data voltage to the pixel electrode.

[0022] Thirdly, this application provides a control method for a display panel, applied to a control circuit of a display panel as described above, the method comprising:

[0023] Receive overcurrent protection signal;

[0024] A black screen GOA output signal is generated based on the overcurrent protection signal; the black screen GOA output signal is used to provide a valid GOA signal to the display panel to control each pixel row to be in the open state, so that the display panel goes black based on the black screen GOA output signal.

[0025] Fourthly, this application provides a display device, including a display panel as described in any of the above descriptions, and a circuit board electrically connected to the display panel, wherein the circuit board is provided with the level conversion module.

[0026] The technical solutions provided by the embodiments of this application may include the following beneficial effects:

[0027] The control circuit of the display panel provided in this application generates a control signal and a black screen GOA output signal when the level conversion module receives the overcurrent protection signal. The control signal controls the power management module to synchronously power down the power signals of each power line. The black screen GOA output signal generates an output GOA effective signal with a gate effective level, which turns on the TFTs on the pixel circuit of the display panel. Each pixel row on the display panel is in the on state. When the display panel performs overcurrent protection, the panel quickly goes black, which solves the problem of abnormal image display after OCP triggering in the existing technology. The charge in the panel is released, which improves the service life of the display panel and enhances the user experience and product quality. Attached Figure Description

[0028] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0029] Figure 1 A schematic diagram of the structure of a display panel provided for an embodiment of this application;

[0030] Figure 2 A schematic diagram of the structure of a control circuit for a display panel provided in an embodiment of this application;

[0031] Figure 3 A circuit diagram of a level conversion module provided for an embodiment of this application;

[0032] Figure 4 A timing diagram of a control circuit for a display panel provided for an embodiment of this application;

[0033] Figure 5 Another structural schematic diagram of a control circuit of a display panel provided for an embodiment of the present application is provided.

[0034] Figure 6 Another structural schematic diagram of a control circuit of a display panel provided for an embodiment of the present application is provided.

[0035] Figure 7 A circuit schematic diagram of a gate driving module provided for an embodiment of the present application is provided. DETAILED DESCRIPTION

[0036] The present application will be further described below in conjunction with the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the related application, and not to limit the application. In addition, it should be noted that only the parts related to the application are shown in the drawings for ease of description.

[0037] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings and embodiments.

[0038] For ease of description, the driving device and driving method of the display panel provided by the embodiments are applied to the display panel as shown in Figure 1 for example. Referring to Figure 1 , the display panel 100 includes a plurality of pixel units, a plurality of data lines D and a plurality of gate lines G. The plurality of pixel units are arranged in an array, the plurality of data lines D extend along the column direction, the plurality of gate lines G extend along the row direction, and the data lines D and the gate lines G are staggered to define the pixel units. Each data line D is connected to a column of pixel units, each gate line G is connected to a row of pixel units, and the plurality of data lines D write data voltages into the pixel units row by row.

[0039] GOA (Gate On Array) is a technology of integrating the gate driving circuit 200 on the TFT substrate. Each GOA unit serves as a shift register to sequentially transmit the scanning signal to the next GOA unit, to open the TFT switch row by row and complete the data signal input of the pixel unit. In the embodiments of the present application, the GOA unit is arranged on one side of the display panel 100, and the GOA is connected to the plurality of gate lines G, and the GOA inputs the scanning voltage to the gate lines G.

[0040] The application is not limited to the type of display panel, which can be a vertical electric field type liquid crystal display panel, such as a twisted nematic (TN) type liquid crystal display panel, a vertical alignment (VA) type liquid crystal display panel, or a horizontal electric field type liquid crystal display panel, such as a fringe field switching (FFS) type liquid crystal display panel or an in-plane switching (IPS) type liquid crystal display panel.

[0041] For details, please refer to Figure 2 The application provides a control circuit of a display panel 100, which comprises:

[0042] A level conversion module 10 is configured to receive an overcurrent protection signal OT and generate a black screen GOA output signal based on the overcurrent protection signal OT; the black screen GOA output signal is configured to provide a GOA effective signal for the display panel 100 to control each pixel row to be in an open state, so that the display panel 100 is blackened based on the black screen GOA output signal.

[0043] The control circuit of the display panel 100 provided in the embodiments of the application generates a black screen GOA output signal through the level conversion module 10 when the overcurrent protection signal OT is received, and generates a GOA effective signal for the gate effective level through the black screen GOA output signal after output, so that the TFT on the pixel circuit of the display panel 100 is opened, each pixel row on the display panel 100 is in an open state, and the display panel 100 is quickly blackened when overcurrent protection is performed, thereby solving the problem of picture difference after OCP triggering in the prior art, discharging the charge in the panel, improving the service life of the display panel 100, and improving user experience and product quality.

[0044] In the embodiments of the application, as shown in Figure 3 The level conversion module 10 comprises an OCP detection circuit 110, which amplifies the GOA input signal input into the display panel 100 in the GOA circuit to obtain a GOA output signal and input into the display panel 100, detects the GOA output signal through the OCP detection circuit 110, and performs overcurrent protection control based on the detection result of the GOA output signal.

[0045] The OCP detection circuit 110 comprises a signal input end and a signal output end, and is configured to convert the level of the GOA input signal provided by the signal input end IN and output through the signal output end OUT.

[0046] In the embodiment of the present application, the signal output end is connected with the gate drive circuit 200 on the display panel 100100, and the present application does not limit the type of signal input into the signal input end. According to the difference of the gate drive circuit 200, the level conversion module 10 can access different GOA signals, such as various clock signals or start frame signals. In the embodiment of the present application, in the non-OCP protection state, the signal input end and the signal output end are used to output the GOA signal for normal display of the display panel 100. Taking the example that the signal input end is connected with the GOA input signal and the signal output end is the GOA output signal for illustration.

[0047] It can be understood that when the over-current protection state is exited, the display panel 100 is in normal display, the GOA input signal is further boosted and amplified by the OCP detection circuit 110, and the boosted signal is input into each pixel row. The GOA output signal of the signal output end includes an effective level and an ineffective level. The effective level refers to the level for turning on the corresponding switching element (TFT), and the ineffective level refers to the level for turning off the corresponding switching element. The effective level and the ineffective level only represent two states of the level of the signal, and do not represent that the effective level or the ineffective level has a specific value in the whole text.

[0048] In the embodiment of the present application, the level conversion module 10 outputs the black screen GOA output signal after receiving the over-current protection signal OT. The black screen GOA output signal is an effective level, and the black screen GOA output signal is used to provide the GOA effective signal for the display panel 100 to control each pixel row to be in the on state.

[0049] In the present application, the level conversion module 10 further includes an over-current protection unit 120 (OCP), which is used to generate an over-current protection signal OT and input the over-current protection signal OT into the signal input end. The over-current protection signal OT outputs the black screen GOA output signal through the OCP detection circuit 110. That is, the over-current protection signal is connected with the signal input end, and the black screen GOA output signal is connected with the signal output end.

[0050] In the setting, the over-current protection unit 120 (OCP) is connected with the OCP detection circuit 110, and is used to perform over-current protection based on the monitoring result of the OCP detection circuit 110. For example, the over-current protection unit 120 (OCP) is used to control the GOA input signal of the signal input end to be a high-level signal when the control signal is received.

[0051] Specifically, the OCP detection circuit 110 comprises a first transistor M1, a control end of the first transistor M1 is connected with the signal input end, a first end of the first transistor M1 is connected with the first power supply end VGH, and a second end of the first transistor M1 is connected with the gate drive circuit 200200.

[0052] The OCP detection circuit 110 is used for detecting the signal of the signal output end OUT under the control of the GOA input signal provided by the signal input end IN and outputting the detection result of the GOA signal; specifically, the OCP detection circuit 110 comprises:

[0053] A third transistor M3, a first resistor RS1 and a first comparator T1, a control end of the third transistor M3 is connected with the signal input end, a first end of the third transistor M3 is connected with the first power supply end VGH, and a second end of the third transistor M3 and a first end of the first resistor RS1 are connected with a first input end of the first comparator T1; a second end of the first resistor RS1 is grounded; a second input end of the first comparator T1 is connected with a first reference signal Vref1, and an output end of the first comparator T1 is connected with an overcurrent protection unit.

[0054] A fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a second resistor RS2 and a second comparator T2, a control end of the fourth transistor M4 is connected with the signal input end, a first end of the fourth transistor M4 is connected with the second power supply end VGL, and a second end of the fourth transistor M4 is connected with a control end of the fifth transistor M5, a second end of the fifth transistor M5 and a control end of the sixth transistor M6.

[0055] A first end of the fifth transistor M5 and a first end of the sixth transistor M6 are connected with a third power supply end VDD, a second end of the sixth transistor M6 is connected with a first input end of the second comparator T2; a second end of the second resistor RS2 is grounded; a second input end of the second comparator T2 is connected with a second reference signal Vref2, and an output end of the second comparator T2 is connected with the overcurrent protection unit.

[0056] In addition, according to different transistor semiconductor characteristics, the transistor can be divided into an N-type transistor and a P-type transistor. Among them, when the transistor is used as a switching transistor, the N-type switching transistor is turned on under the control of a high-level switching control signal and is turned off under the control of a low-level switching control signal; the P-type switching transistor is turned on under the control of a low-level switching control signal and is turned off under the control of a high-level switching control signal.

[0057] The “control end” specifically refers to the gate of the transistor, the “first end” specifically refers to the source of the transistor, and the “second end” specifically refers to the drain of the transistor. Of course, it should be known by those skilled in the art that the “first end” and the “second end” can be interchanged, that is, the “first end” specifically refers to the drain of the transistor, and the “second end” specifically refers to the source of the transistor.

[0058] In the embodiment of the present application, the first transistor M1 and the third transistor M3 are the same type of PMOS tube and NMOS tube, the second transistor M2 and the fourth transistor M4 are the other type of PMOS tube and NMOS tube, and the fifth transistor M5 and the sixth transistor M6 are NMOS. Exemplarily, the first transistor M1, the third transistor M3, the fifth transistor M5 and the sixth transistor M6 are NMOS tubes, and the second transistor M2 and the fourth transistor M4 are PMOS tubes.

[0059] In order to sample the working currents of the first transistor M1 and the second transistor M2 according to a certain ratio in the present application, the working current of the first transistor M1 is greater than the working current of the third transistor M3; the working current of the second transistor M2 is greater than the working current of the fourth transistor M4, and the working current of the fifth transistor M5 is equal to the working current of the sixth transistor M6.

[0060] The first power supply end VGH is a high-voltage end, the second power supply end VGL is a low-voltage end, and the third power supply end VDD is a high-voltage end.

[0061] In the embodiment, when the GOA input signal is high, M1 / M3 is turned on, the gate drive GOA output signal is connected to the VGH voltage, and the high level is output. At the same time, the working current of M3 is smaller than the working current of M1 and is in a fixed ratio, and the purpose is that when the output end is connected to VGH, a certain proportion of the current passing through M1 is sampled, for example, the current passing through M1 is 200 mA, and the current passing through M3 and RS1 is 10 mA. According to the resistance voltage division principle, the input voltage of the first comparator T1 is RS1*10 mA, and this voltage is compared with the RVEF1 of the first comparator T1. If it is higher than Vref1, the OCP is triggered, and if it is lower than Vref1, it is not triggered. Vref1 is the voltage threshold or current threshold set by the OCP; optionally, the width-length ratio of the third transistor M3 is smaller than the width-length ratio of the first transistor M1.

[0062] When the GOA input signal is low, M2 / M4 is turned on, the gate driving GOA output signal is connected to the VGL voltage, and a low level is output. Meanwhile, the working current of M4 is smaller than that of M2 and is in a fixed ratio, and the purpose is that when the output end is connected to VGL, a certain proportion of the current passing through M2 is sampled, such as 200 mA passing through M2 and 10 mA passing through M4. Since VGL is connected at this time, the current is negative, and in order to convert it to a positive current, 5V is pulled up in series with M5, and M6+RS2 which is the same size as M5 is connected in parallel. The role of M6+RS2 is to copy the current of 10 mA passing through M5 and M4. According to the resistance voltage division principle, the voltage at the input end of the second comparator T2 is RS2*10mA, and the second comparator T2 has Vref2. When it is higher than Vref2, OCP is triggered, and when it is lower than Vref2, it is not triggered. Vref2 is the voltage threshold or current threshold set by OCP; alternatively, the width-length ratio of the fourth transistor M4 is smaller than that of the second transistor M2.

[0063] The voltage value of the first power supply end VGH is greater than the first driving signal voltage value of the GOA input signal, and the voltage value of the second power supply end VGL is greater than the second driving signal voltage value of the GOA input signal. It can be understood that the high voltage and low voltage of the timing control signal are set according to the needs, and the high voltage switching signal of the GOA is used as the reference.

[0064] In this embodiment, when a certain proportion of the current passing through M1(or M2) is sampled, the result obtained is higher than Vref1(or Vref2) to trigger OCP, and the overcurrent protection unit outputs an overcurrent protection signal(high level), so that the signal at the signal input end is high, M1 / M3 is turned on, the gate driving GOA output signal is connected to the VGH voltage, and the black screen GOA output signal is output(high level). The gate driving circuit of the display panel is connected through the GOA output signal, so that each pixel row on the display panel is in an open state to control the display panel to be black.

[0065] It should be noted that when the display panel 100 is normally displayed, the gate driving circuit 200 can be in a line-by-line scanning mode or an interlaced scanning mode in the scanning mode, and can be scanned from top to bottom or from bottom to top in the scanning direction. The specific pixel scanning mode can refer to various different modes in the prior art, and will not be described in detail herein. When the display panel 100 enters the overcurrent protection, the black screen GOA output signal makes the gate driving units connected to each pixel row of the gate driving circuit 200 can output the GOA effective signal at the same time, so that each pixel row can be turned on at the same time, realizing the display panel 100 to display a black picture, realizing the release of the residual charge of the display panel 100, and avoiding display abnormalities.

[0066] In the embodiment of the present application, the control circuit of the display panel 100 further comprises:

[0067] A power management module 20 connected with the level conversion module, the power management module 20 is used to provide working voltage for each IC and provide various power signals for each module.

[0068] A power module 30 used to power the display panel 100 and the system, the power module 30 generates working voltage of various ICs and the like through the power management module 20.

[0069] A timing control module 40 connected with the level conversion module 10 and the data driving module 50, used to provide timing signals for the level conversion module 10 and the data driving module 50.

[0070] A data driving module 50 connected with the timing control module 40, the power management module 20 and the display panel 100, the data driving module 50 outputs data signals and transmits them to corresponding pixel units through data lines D to realize image gray scale.

[0071] In the embodiment of the present application, the level conversion module 10 is used to generate a control signal FN based on the over-current protection signal OT.

[0072] In the setting, the level conversion module 10 is provided with a control pin FN, the power management module 20 is provided with an enable pin EN, the control pin FN is connected with the enable pin EN, the connection mode of the control pin FN and the enable pin EN is not limited in the embodiment of the present application, which can be directly connected by copper wire, bonding and the like, and can also be indirectly connected by other intermediate elements. The control pin FN is in high level (normal signal) in the non-over-current protection state, and is in low level (over-current protection signal OT) in the over-current protection state.

[0073] Embodiment one

[0074] The power management module 20 is used to power off the power line based on the received control signal FN, the power line is used to provide power signal for the display panel 100 and the level conversion module 10.

[0075] The enable pin EN receives the over-current protection signal OT received through the control pin FN, and the signal on the enable pin EN is defined as an enable signal EN in the present application. The power management module 20 enters an over-current protection state based on the enable signal EN, in which mode, on the one hand, the power management module 20 powers off the power lines based on the received control signal FN (enable signal EN).

[0076] The signal type of the power lines is not limited in the embodiments of the present application, and is selected as required. Optionally, the power signals include one or more of a VGH signal, an AVDD signal, and a VCOM signal, and the power lines corresponding to the power signals are synchronously powered off based on the received control signal FN, as shown in Figure 4

[0077] In the embodiments of the present application, the AVDD signal is a gamma main voltage AVDD for a pixel voltage on a data line, and is about 5-16V; a reference voltage required by a data driving module 50 generated by a gray scale circuit, i.e., a gamma reference voltage AVDD, is synchronously powered off through the AVDD signal, so that a gray scale voltage of a black picture can be quickly generated, and a black screen of the display panel 100 is realized.

[0078] The VGH signal is a maximum on-state voltage VGH for opening a TFT on a scan line, and is about 20V, and is up to 40V, and the VGH signal can be connected with a first power terminal VGH on the OCP detection circuit 110. The VCOM signal is a common voltage VCOM of a common electrode on the display panel 100, and ranges from 5V to 6V.

[0079] In a conventional control circuit, the circuit output is immediately cut off to protect the panel after the OCP is triggered, but there is no pixel discharge action, which causes picture abnormalities and liquid crystal polarization flicker, and affects user experience. In the present application, the pixel electrode is discharged through the synchronous power-off mode of the power signals, so that the OCP protection effect is improved, and the service life of the display panel 100 and user experience are improved.

[0080] It can be understood that the synchronous power-off mode of the signal lines is not limited in the embodiments of the present application, and for example, related circuits can be selected to realize, and exemplarily, the VCOM signal can be obtained by resistance voltage division from the AVDD signal generation circuit through resistance voltage division, so that the VCOM signal is synchronously powered off while the AVDD signal is powered off; of course, other modes can also be used to realize synchronous power-off, and the present application does not limit this.

[0081] ​It should be further explained that in this application, VGH can be powered down synchronously with other power signals. However, the signal output terminal of the level conversion module 10 is connected to the gate drive circuit 200. At least one capacitor is connected in parallel with the VGH signal on the gate drive circuit 200. The power signals of each power line on the power management module 20 are powered down synchronously. When the voltages of the AVDD and VCOM signals drop to 0V, the black screen GOA output signal can still keep each pixel row in the on state. Therefore, by synchronously powering down the aforementioned power signals, a black screen display can be achieved, the charge in the display panel 100 can be discharged, a rapid black screen can be achieved, and the user experience can be improved.

[0082] It should also be noted that, in this embodiment, the voltage generated by the power management module 20 includes not only the voltage signal on the power line, but also the operating voltage of each IC, such as the operating voltage of the timing control module 40, the data drive module 50, and the level conversion module 10. This operating voltage VDD can be approximately 3.3V. In this embodiment, after the power management module 20 receives the control signal FN, it only performs a synchronous power-down of the signals on the power line, while the operating voltage remains unchanged to ensure the normal operation of various ICs.

[0083] Optionally, the timing control module 40 is connected to the power management module 20 and is used to synchronously power down based on controlling the timing signal and the power signal. The data driving circuit converts the signal related to display data from the timing control module 40 into an analog voltage and outputs it to the pixel electrode to form the voltage required for liquid crystal deflection. By synchronously powering down the timing signal and the power signal, it is possible to prevent the IC from being accidentally triggered and causing the panel to display abnormal images.

[0084] Example 2

[0085] like Figure 5 As shown, in one embodiment of this application, the power module 30 is connected to the power management module 20 and the level conversion module 10. The level conversion module 10 is used to generate a control signal FN based on the overcurrent protection signal OT. The power module 30 is used to control the backlight module 60 of the display panel 100 to turn off based on the received control signal FN.

[0086] In this embodiment, the display panel 100 can be a liquid crystal display panel 100, which includes a backlight module 60. The power module 30 supplies power to the backlight module 60. In order to improve the black screen effect, the power module 30 is used to directly turn off the backlight module to achieve a rapid black screen and improve the user experience.

[0087] In the setting, the level conversion module 10 is provided with a control pin FN, and the power module 30 is provided with a feedback pin FB, the control pin FN is connected with the control pin FN, and the connection mode of the control pin FN and the control pin FN is not limited in the embodiment of the application, and can adopt direct electrical connection mode such as copper wire, bonding, and can also adopt indirect electrical connection mode formed by other intermediate elements. The control pin FN (feedback pin FB) is at a high level (normal signal) in a non-overcurrent protection state, and is at a low level (overcurrent protection signal OT) in an overcurrent protection state.

[0088] In addition, the power module 30 is used for generating a power-on signal, and the power management module 20 and the power module 30 exit the overcurrent protection state based on the power-on signal. In the embodiment of the application, when the total power supply is restarted, each module including the backlight module 60, the power management module 20 and the like is restarted, the level conversion module 10 exits the overcurrent protection state, normal display is realized, and the protection effect and the service life of the display panel 100 are improved.

[0089] Embodiment three

[0090] Please continue to refer to Figure 1 The application provides a display panel 100 applied to the control circuit of the display panel 100 as described in any of the above, and the display panel 100 includes an array substrate and a counter substrate.

[0091] The array substrate includes a pixel electrode P1, and the counter substrate includes a common electrode P2, the common electrode P2 is connected with a common power line VCOM, and the common power line VCOM is used for providing a VCOM signal for the common electrode; the pixel electrode P1 is connected with the data driving module 50, and the data driving module 50 is used for providing a data voltage for the pixel electrode.

[0092] The data driving module 50 is connected with the level conversion module 10, and the level conversion module 10 is used for generating a control signal FN based on the overcurrent protection signal OT; and the data driving module 50 is used for synchronizing the output data voltage with the voltage of the VCOM signal based on the control signal FN. When the pixel electrode inputs a common voltage signal, there is no voltage difference between the two sides of the liquid crystal layer, the liquid crystal layer does not flip, and the liquid crystal display panel 100 displays a black picture.

[0093] For example, for a VA product, since the TFT on the gate driving circuit 200 adopts ICZO material, the discharge is relatively slow, and only the synchronous power-down mode is adopted, which leads to slow discharge of the pixel electrode. In the embodiment, the pixel electrode is connected to the VCOM signal, and when the pixel is in an open state, the voltage difference between the pixel electrode and the common electrode is 0V, and the charge in the pixel electrode is discharged.

[0094] During setup, such as Figure 6 As shown, the level conversion module 10 is provided with a control pin FN, and the data driving module 50 is provided with a conversion pin XN. The control pin FN is connected to the control pin XN. In this embodiment, the connection method between the control pins FN and XN is not limited. Direct electrical connection methods such as copper wire or bonding can be used, or indirect electrical connection methods can be formed by other intermediate components. The control pin FN (conversion pin XN) is at a high level (normal signal) in the non-overcurrent protection state, and is pulled low (overcurrent protection signal OT) when entering the overcurrent protection state.

[0095] In this embodiment, the data driving module 50 adds a control circuit to the existing circuit. The control circuit includes a control transistor DT. The control terminal of the control transistor DT is connected to the control signal FN. The first terminal of the control transistor is connected to the VCOM voltage terminal of the VCOM signal. The second terminal of the control transistor is connected to the data voltage output terminal.

[0096] Furthermore, the VCOM signal is powered down synchronously with other power signals, so that the voltage on the pixel electrode can be simultaneously powered down to 0V. The charge on the pixel electrode can be quickly discharged through the power line, improving the discharge effect, achieving rapid blackout, improving overcurrent protection and user experience.

[0097] Based on the same concept, this application provides a control method for a display panel 100, applied to the control circuit of the display panel 100 as described above, the method comprising:

[0098] Receive overcurrent protection signal OT;

[0099] A black screen GOA output signal is generated based on the overcurrent protection signal OT; the black screen GOA output signal is used to provide a valid GOA signal to the display panel 100 to control each pixel row to be in the open state, so that the display panel 100 goes black based on the black screen GOA output signal.

[0100] Based on the same inventive concept, the application provides a display device, comprising the display panel 100 according to any one of the above and a circuit board, the circuit board is electrically connected with the display panel 100, and the circuit board is provided with the level conversion module 10. In one or more embodiments of the application, the display device can be applied to any product or component with display function such as mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator and the like. Other essential components of the display device should be understood by those skilled in the art, and are not described here in detail, nor should they be regarded as a limitation on the application.

[0101] It should be understood that the terms "length", "width", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the application.

[0102] In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second" can include one or more of the features explicitly or implicitly. In the description of the application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0103] Unless otherwise defined, the technical and scientific terms used herein have the same meaning as understood by those skilled in the art of the technology of the application. The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the application. The terms such as "provided" appearing in this document can mean that one component is directly attached to another component, or that one component is attached to another component through an intermediate component. The features described in one embodiment herein can be applied to another embodiment alone or in combination with other features, unless the features are not applicable in the other embodiment or are otherwise stated.

[0104] The application has been described by the above embodiments, but it should be understood that the above embodiments are only for the purpose of example and illustration, and are not intended to limit the application to the described embodiments. Those skilled in the art can understand that more variations and modifications can be made according to the teachings of the application, and these variations and modifications all fall within the scope of the application claimed.

Claims

1. A control circuit for a display panel, characterized in that, It includes a level conversion module and a power management module, wherein the power management module is connected to the level conversion module. The level conversion module is used to receive an overcurrent protection signal and generate and control a black screen GOA output signal based on the overcurrent protection signal; the black screen GOA output signal is used to provide a valid GOA signal to the display panel to control each pixel row to be in the on state, so that the display panel goes black based on the black screen GOA output signal. The power management module is used to power off the power line based on the received control signal, and the power line is used to provide power signals to the display panel and the level conversion module.

2. The control circuit for the display panel according to claim 1, characterized in that, The power signal includes one or more of the following: VGH signal, AVDD signal, and VCOM signal. The power lines corresponding to each power signal are synchronously powered down based on the received control signal.

3. The control circuit for the display panel according to claim 1, characterized in that, Also includes: A power module, which is connected to the power management module and the level conversion module, wherein the level conversion module is used to generate a control signal based on the overcurrent protection signal; The power module is used to control the backlight module of the display panel to turn off based on the received control signal.

4. The control circuit for the display panel according to claim 3, characterized in that, The power module is used to generate a power-on signal, and the power management module and the power module exit the overcurrent protection state based on the power-on signal.

5. The control circuit for the display panel according to claim 1, characterized in that, Also includes: A timing control module is provided, which is connected to the level conversion module, and is used to provide timing signals to the level conversion module.

6. The control circuit for the display panel according to claim 5, characterized in that, The timing control module is connected to the power management module and is used to synchronously power down based on the timing signal and the power signal.

7. The control circuit for the display panel according to claim 1, characterized in that, Also includes: A data-driven module is connected to the level conversion module, which is used to generate a control signal based on the overcurrent protection signal. The data driving module is used to synchronize the output data voltage with the voltage of the VCOM signal based on the control signal.

8. A display panel, characterized in that, A control circuit for a display panel as described in any one of claims 1-7, wherein the display panel includes an array substrate and an opposing substrate.

9. The display panel according to claim 8, characterized in that, The array substrate includes pixel electrodes, and the opposing substrate includes a common electrode. The common electrode is connected to a common power line, which provides a VCOM signal to the common electrode. The pixel electrode is connected to a data driving module, which provides a data voltage to the pixel electrode.

10. A method for controlling a display panel, characterized in that, The method, applied to the control circuit of the display panel as described in any one of claims 1-7, comprises: Receive overcurrent protection signal; Based on the overcurrent protection signal, a control signal and a black screen GOA output signal are generated; the control signal is used to control the power management module of the display panel to cut off the power to the power line, and the black screen GOA output signal is used to provide a valid GOA signal to the display panel to control each pixel row to be in the on state, so that the display panel goes black based on the black screen GOA output signal.

11. A display device, characterized in that, The display panel as described in any one of claims 8-9 is further comprising a circuit board electrically connected to the display panel, the circuit board being provided with a level conversion module.

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