Improved Method for Chip Manufacturing Process, Chip, Electronic Device, and Electronic Equipment

Abstract

The present disclosure provides an improved method for chip manufacturing process, a chip, an electronic device and an electronic equipment. The improved method includes: analyzing test results of chip yield testing to obtain process conditions corresponding to each circuit module of the chip; the process conditions include the optimal process parameters of each process of each circuit module; when each circuit module executes each process, manufacturing each circuit module according to the corresponding optimal process parameters; and generating a chip based on the circuit modules after manufacturing is completed. During the process of manufacturing each circuit module, determining the optimal process parameters of each process of each circuit module based on the test results of chip yield testing can make adaptive process parameter adjustments for each process of different circuit modules, thereby realizing the disassembly and improvement of each link of chip manufacturing by module and process, so as to achieve the purpose of improving chip performance and product yield.

Description

Technical Field

[0001] The present disclosure relates to the field of chip manufacturing technologies, and in particular, to an improved method for a chip manufacturing process, a chip, an electronic device, and an electronic equipment. Background Art

[0002] In the manufacturing process of traditional logic integrated circuit chips, due to the relatively large device size (above 65 nm) of logic integrated circuit chips and the small total number of devices in logic integrated circuit chips, the circuit modules of logic integrated circuit chips are relatively simple. Therefore, in the manufacturing process of traditional logic integrated circuit chips, for the same type of devices under different usage scenarios, by using different working voltages for process differentiation, the requirements for chip usage and yield optimization can be met. However, with the evolution of chip technologies and the improvement of circuit integration, the traditional chip manufacturing methods cannot meet the design requirements of each module circuit of current chips, and cannot ensure that each circuit module is in the optimal performance and yield conditions. Summary of the Invention

[0003] The purpose of the present disclosure is to provide an improved method for a chip manufacturing process, a chip, an electronic device, and an electronic equipment, so as to improve the performance and product yield of the chip.

[0004] According to one aspect of the present disclosure, there is provided an improved method for a chip manufacturing process, the method comprising:

[0005] Analyzing the test results of chip yield testing to obtain the process conditions corresponding to each circuit module of the chip; the process conditions include the optimal process parameters of each process of each circuit module;

[0006] When each process is executed for each circuit module, manufacturing each circuit module according to the corresponding optimal process parameters;

[0007] Generating a chip based on each circuit module after manufacturing is completed.

[0008] Further, the test results include CP test results and FT test results.

[0009] Further, before each process is executed for each circuit module, the improved method for a chip manufacturing process further comprises:

[0010] Dividing the photomask area according to the process conditions to obtain different photomask areas.

[0011] Further, the step of dividing the photomask area according to the process conditions to obtain different photomask areas comprises:

[0012] Dividing the circuit modules with the same process conditions into the same photomask area;

[0013] Circuit modules with different process conditions are divided into different photomask regions.

[0014] Furthermore, during the process of each circuit module performing each process, the method for improving the chip manufacturing process further includes:

[0015] Before a circuit module performs a target process, adjust the photomask region according to the target process parameters of each circuit module to obtain an adjusted photomask region; the target process is the next process that the circuit module will perform, and the target process parameter is the optimal process parameter corresponding to the target process.

[0016] Furthermore, the step of adjusting the photomask region according to the target process parameters of each circuit module before the circuit module performs the target process to obtain an adjusted photomask region includes:

[0017] Adjust circuit modules with the same target process parameters to the same photomask region;

[0018] Adjust circuit modules with different target process parameters to different photomask regions.

[0019] According to another aspect of the present disclosure, there is provided an apparatus for improving a chip manufacturing process, including:

[0020] A process condition generation module, configured to analyze the test results of chip yield testing to obtain the process conditions corresponding to each circuit module of the chip; the process conditions include the optimal process parameters of each process of each circuit module;

[0021] A process execution module, configured to manufacture each circuit module according to the corresponding optimal process parameter when each circuit module performs each process;

[0022] A chip generation module, configured to generate a chip based on the circuit modules after manufacturing is completed.

[0023] Furthermore, the test results include CP test results and FT test results.

[0024] Furthermore, the improvement apparatus further includes:

[0025] A photomask division module, configured to divide photomask regions according to the process conditions to obtain different photomask regions.

[0026] Furthermore, the photomask division module is configured to divide circuit modules with the same process conditions into the same photomask region and divide circuit modules with different process conditions into different photomask regions.

[0027] Furthermore, the improvement apparatus further includes:

[0028] A photomask adjustment module, which is configured to adjust the photomask area according to the target process parameters of each circuit module before the circuit module executes the target process, so as to obtain an adjusted photomask area; the target process is the next process to be executed by the circuit module, and the target process parameters are the optimal process parameters corresponding to the target process.

[0029] Further, the photomask adjustment module is configured to adjust the circuit modules with the same target process parameters in the same photomask area, and adjust the circuit modules with different target process parameters in different photomask areas.

[0030] According to another aspect of the present disclosure, there is provided a chip, including a circuit module manufactured by the improved method of the chip manufacturing process described in any one of the above embodiments.

[0031] According to another aspect of the present disclosure, there is provided an electronic device, including the chip described in any one of the above embodiments.

[0032] According to another aspect of the present disclosure, there is provided an electronic equipment, including the electronic device described in any one of the above embodiments. Description of the Drawings

[0033] Figure 1 It is a schematic flowchart of an improved method for a chip manufacturing process provided by an embodiment of the present disclosure;

[0034] Figure 2 It is a schematic manufacturing flowchart of an improved method for a chip manufacturing process provided by an embodiment of the present disclosure;

[0035] Figure 3 It is a schematic structural diagram of an improved device for a chip manufacturing process provided by an embodiment of the present disclosure;

[0036] Figure 4 It is a schematic structural diagram of an improved device for a chip manufacturing process provided by another embodiment of the present disclosure. Detailed Embodiments

[0037] Before introducing the embodiments of the present disclosure, it should be noted that:

[0038] Some embodiments of the present disclosure are described as processing flows. Although the various operation steps of the flow may be labeled with sequential step numbers, the operation steps therein can be implemented in parallel, concurrently, or simultaneously.

[0039] In the embodiments of the present disclosure, terms such as "first" and "second" may be used to describe various features, but these features should not be limited by these terms. These terms are only used to distinguish one feature from another.

[0040] In the embodiments of the present disclosure, the term "and / or" may be used, and "and / or" includes any and all combinations of one or more of the listed associated features.

[0041] It should be understood that when describing the connection relationship or communication relationship between two components, unless it is clearly specified that the two components are directly connected or directly communicate, otherwise, the connection or communication between the two components can be understood as direct connection or communication, or can be understood as indirect connection or communication through an intermediate component.

[0042] In order to make the technical solutions and advantages in the embodiments of the present disclosure more clearly understood, the following further details the exemplary embodiments of the present disclosure with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than an exhaustive list of all embodiments. It should be noted that, without conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other.

[0043] The purpose of the present disclosure is to provide an improved method for chip manufacturing process, aiming to analyze the process conditions corresponding to each circuit module of the chip according to the test results of chip yield testing. The process conditions include the optimal process parameters of each process of each circuit module. When each circuit module executes each process, each circuit module is manufactured according to the corresponding optimal process parameters, and a chip is generated based on the circuit modules after manufacturing is completed. During the process of manufacturing each circuit module, the optimal process parameters of each process of each circuit module are determined based on the test results of chip yield testing, and adaptive process parameter adjustment can be made for each process of different circuit modules, so as to realize the disassembly and improvement of each link of chip manufacturing by module and process, thereby achieving the purpose of improving chip performance and product yield.

[0044] An embodiment of the present disclosure provides an improved method for chip manufacturing process, as Figure 1 shown, the improved method for chip manufacturing process includes the following steps:

[0045] S110, analyzing the process conditions corresponding to each circuit module of the chip based on the test results of chip yield testing, where the process conditions are used to characterize the optimal process parameters of each process of each circuit module.

[0046] S120, when each circuit module executes each process, manufacturing each circuit module according to the corresponding optimal process parameters.

[0047] S130, generating a chip based on the circuit modules after manufacturing is completed.

[0048] Among them, chip yield testing includes CP testing (Chip Probing, wafer testing) and FT testing (Final Test, finished product testing). CP testing is between wafer manufacturing and packaging in the entire chip manufacturing process. The test object is each Die in the whole wafer. The purpose is to ensure that each Die in the whole wafer can basically meet the device characteristics or design specifications, usually including verification of voltage, current, timing, and function. The test object of FT testing is the packaged chip. After CP testing, packaging is carried out, and then FT testing is carried out. FT testing is used to perform performance testing on the packaged chip and can be used to detect the process level of the packaging factory.

[0049] Since there can be up to thousands of test items in CP testing and FT testing, with the support of CP testing and FT testing, the process conditions corresponding to each circuit module of the chip are very reliable and accurate.

[0050] The test results of the present disclosure correspond to CP test results and FT test results. The test results can include voltage requirements, density, device turn-on speed, leakage current magnitude, drive current voltage magnitude, etc. that each circuit module can withstand.

[0051] Each circuit module of the chip can include a storage module, an oscillation circuit module, an IO drive circuit module, and a THERMdiode (thermal diode) module, etc.; the storage module can be an SRAM (Static Random-Access Memory) module, and the SRAM module is mainly composed of three different types of MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), namely PD (Pull-down transistor), PG (Pass-gate transistor), and PU (Pull-up transistor); the oscillation circuit module can be an RO (Ring Oscillator) module.

[0052] The chip can be a GPU (Graphics Processing Unit), a CPU (central processing unit), etc.

[0053] The processes include well implantation process, gate oxide preparation process, lightly doped drain (LDD) process, gate size process, source / drain (S / D) ion implantation process, silicide process, spacer process, germanium silicon stress process, epitaxial growth process, etching process, photolithography process, channel stress process, etc.

[0054] The optimal process parameters in the present disclosure can be the original process parameters or the adjusted process parameters. It can be understood that if it is obtained based on the analysis of the test results of the chip yield test for each chip that a certain circuit module can ensure the best performance and yield when manufactured based on the original process parameters of a certain process, then the original process parameters of this process are the optimal process parameters and do not need to be adjusted; if it is obtained based on the analysis of the test results of the chip yield test for each chip that a certain circuit module cannot achieve the best performance and yield when manufactured based on the original process parameters of a certain process, then the original process parameters of this process need to be adjusted based on the test results before they can become the optimal process parameters.

[0055] The present disclosure can obtain the test results based on the big data feedback of the chip yield test, and analyze the process conditions corresponding to each circuit module from the test results based on the optimal condition solution of statistics. It can be compatible with the existing manufacturing production lines of integrated circuit chips, upgrade the advanced control systems connected to the production lines, and realize the fully automatic mass production optimization process.

[0056] Now, taking the circuit module as the storage module as an example, it is illustrated how to analyze the process conditions corresponding to the storage module based on the test results of the chip yield test:

[0057] Based on the analysis of the CP test results and FT test results of each chip, it can be obtained that the storage module has performance requirements of high density, low voltage requirements that can be tolerated, and speed.

[0058] Due to the high-performance requirement of the storage module for density, it is necessary to reduce the channel lengths of PD, PU, and PG. However, reducing the channel lengths of PD, PU, and PG will lead to an enhancement of the DIBL (Drain Induce Barrier Low) effect, resulting in the degradation of device performance. Therefore, in order to suppress the DIBL effect, it is determined that a Halo inversion source species is introduced in the lightly doped drain process for the storage module, and different thicknesses are introduced in the spacer process in the PG, PD, and PU regions to control the spacing of the active regions, so as to effectively suppress the DIBL effect and ensure the performance of the device. At the same time, due to the high density of the storage module, it is easily affected by layout effects such as LOD and WPE, resulting in a decrease in the performance of the storage module. Therefore, in the S / D ion implantation process, the performance of the storage module is appropriately compensated by increasing the carrier concentration; correspondingly, the optimal process parameters of the storage module in the lightly doped drain process are the adjusted process parameters, and the process parameters that need to be adjusted include introducing a Halo inversion source species and introducing different thicknesses in the PG, PD, and PU regions; the optimal process parameters of the storage module in the S / D ion implantation process are the adjusted process parameters, and the process parameters that need to be adjusted include the carrier concentration.

[0059] Due to the performance requirement of the storage module for speed, the speed of the storage module is related to the areas of the effective channels of PG, PD, and PU, and is also associated with the turn-on threshold voltages and saturation currents of PG, PD, and PU. Therefore, it is determined that in the well ion implantation process for the storage module, corresponding adjustments are made to the ion implantation process parameters in the PG, PD, and PU regions respectively. For example, by adjusting parameters such as the implantation energy, source species type, or implantation concentration, the read / write window of the storage module can be increased, achieving the purpose of improving the yield and performance of the storage module; in the gate size process, the gate sizes of PG, PD, and PU are adjusted to adjust the channel lengths of PG, PD, and PU, so as to increase the read / write window of the storage module, and thus effectively improve the yield and performance of the storage module. Correspondingly, the optimal process parameters of the storage module in the well ion implantation process are also the adjusted process parameters, and the process parameters that need to be adjusted include the implantation energy, source species type, or implantation concentration, etc.; the optimal process parameters of the storage module in the gate size process are also the adjusted process parameters, and the process parameters that need to be adjusted include the gate size; and the specific values of the adjusted process parameters can be set according to the actual situation and are not limited herein.

[0060] Due to the performance requirement of the storage module for a relatively low withstand voltage, the storage module can meet its voltage requirement by adopting the original process parameters in the gate oxide preparation process, and there is no need to adjust the original process parameters in the gate oxide preparation process. The original process parameters are the optimal process parameters of the storage module in the gate oxide preparation process.

[0061] Since, in the process of manufacturing each circuit module, the optimal process parameters for each process of each circuit module are determined based on the test results of chip yield testing, adaptive process parameter adjustment can be made for each process of different circuit modules, thereby realizing the disassembly and improvement of each link of chip manufacturing by module and process, so as to achieve the purpose of improving chip performance and product yield.

[0062] In order to further save costs and production time, before each circuit module executes each process, the photomask area is divided according to process conditions to obtain different photomask areas.

[0063] It should be understood that circuit modules with the same process conditions are divided into the same photomask area; circuit modules with different process conditions are divided into different photomask areas.

[0064] It can be understood that based on the analysis of the test results of chip yield testing, the process conditions of each circuit module in the first process can be obtained. If the process conditions of circuit module A and circuit module B in the first process are the same, then circuit module A and circuit module B are divided into the first photomask area. If the process conditions of circuit module C and circuit module D in the first process are the same, and the process conditions of circuit module C and circuit module D in the first process are different from those of circuit module A and circuit module B in the first process, then circuit module C and circuit module D are divided into the second photomask area. Within the first photomask area, circuit module A and circuit module B are jointly manufactured based on the process conditions of the first process of circuit module A and circuit module B; within the second photomask area, circuit module C and circuit module D are jointly manufactured based on the process conditions of the first process of circuit module C and circuit module D.

[0065] Circuit modules within the same photomask area can be jointly manufactured in processes with the same process conditions because they have the same process conditions; while circuit modules in different photomask areas cannot be jointly manufactured because they have different process conditions, and different circuit modules are manufactured based on their respective process conditions. Dividing circuit modules with the same process conditions into the same photomask area for joint manufacturing can effectively save costs and production time.

[0066] In order to further save costs and production time, during the process of each circuit module executing each process, before the circuit module executes the target process, the photomask area is adjusted according to the target process parameters of each circuit module to obtain the adjusted photomask area; the target process is the next process that the circuit module will execute, and the target process parameter is the optimal process parameter corresponding to the target process.

[0067] In the present disclosure, circuit modules with the same target process parameters are adjusted in the same mask area, and circuit modules with different target process parameters are adjusted in different mask areas.

[0068] It can be understood that if the third manufacturing process is currently in progress, then the target process is the fourth process, and the target process parameters are the optimal process parameters of the fourth process, that is, the process conditions of the fourth process. Based on the analysis of the test results of the chip yield test, the process conditions of each circuit module in the fourth process can be obtained. Before performing the fourth process, the mask area is adjusted according to the process conditions of each circuit module in the fourth process. If the process conditions of circuit module A and circuit module C in the fourth process are the same, then circuit module A and circuit module C are adjusted in the first mask area. If the process conditions of circuit module B and circuit module D in the fourth process are the same, and the process conditions of circuit module B and circuit module D in the fourth process are different from those of circuit module A and circuit module C in the fourth process, then circuit module B and circuit module D are adjusted in the second mask area. In the first mask area, circuit module A and circuit module C are jointly manufactured based on the process conditions of circuit module A and circuit module C in the fourth process. In the second mask area, circuit module B and circuit module D are jointly manufactured based on the process conditions of circuit module B and circuit module D in the fourth process.

[0069] That is to say, in the present disclosure, before each process is executed, the mask area is adjusted based on the process conditions corresponding to each process of each circuit module. That is, before the first process is executed, the mask area is divided according to the process conditions of each circuit module in the first process. Before the second process is executed, the mask area is adjusted according to the process conditions of each circuit module in the second process. Before the third process is executed, the mask area is adjusted again according to the process conditions of each circuit module in the third process. To ensure that during the manufacturing process of each process, the lowest production cost and production time are achieved.

[0070] Since 70% to 80% of the functions of the chip are realized by the storage module, the oscillation circuit module, and the IO drive circuit module, the present disclosure takes the manufacturing of the storage module, the oscillation circuit module, and the IO drive circuit module in the potential well ion implantation process, the gate oxide preparation process, the lightly doped drain process, the gate size process, the S / D ion implantation process, and the metal silicidation process as an example for description based on the improved method of the chip manufacturing process of the present disclosure. The other circuit modules of the chip are also manufactured based on the optimal process parameters obtained from the analysis of the test results of the chip yield test. However, the performance requirements of different circuit modules are different, and there will be differences in the optimal process parameters of each process. And in other processes, each circuit module is also manufactured according to the corresponding optimal process parameters, which will not be elaborated one by one here.

[0071] As Figure 2 shown, it is a schematic diagram of the manufacturing process of the improved method for the chip manufacturing process of the present disclosure. The manufacturing process of the chip of the present disclosure is as follows:

[0072] First, perform chip yield testing on each chip to obtain the test results of each chip; analyze the test results of each chip to obtain the optimal process parameters of the storage module, oscillator circuit module, and IO driver module under the well ion implantation process, gate oxide preparation process, lightly doped drain process, gate size process, S / D ion implantation process, and metal silicidation process; based on the optimal process parameters of the storage module, oscillator circuit module, and IO driver module under the well ion implantation process, divide the photomask area, and divide the storage module, oscillator circuit module, and IO driver module into different photomask areas; under different photomask areas, manufacture the storage module, oscillator circuit module, and IO driver module respectively according to the optimal process parameters under the well ion implantation process; based on the optimal process parameters of the storage module, oscillator circuit module, and IO driver module under the gate oxide preparation process, adjust the photomask area, and adjust the storage module and oscillator circuit module to the same photomask area, while keeping the photomask area of the IO driver module unchanged; under the adjusted photomask area, manufacture the storage module, oscillator circuit module, and IO driver module respectively according to the optimal process parameters under the gate oxide preparation process; based on the optimal process parameters of the storage module, oscillator circuit module, and IO driver module under the lightly doped drain process, adjust the photomask area, and adjust the storage module, oscillator circuit module, and IO driver module to different photomask areas; under the adjusted photomask area, manufacture the storage module, oscillator circuit module, and IO driver module respectively according to the optimal process parameters under the lightly doped drain process; based on the optimal process parameters of the storage module, oscillator circuit module, and IO driver module under the gate size process, adjust the photomask area, and keep the photomask areas of the storage module, oscillator circuit module, and IO driver module unchanged; under the adjusted photomask area, manufacture the storage module, oscillator circuit module, and IO driver module respectively according to the optimal process parameters under the gate size process; based on the optimal process parameters of the storage module, oscillator circuit module, and IO driver module under the S / D ion implantation process, adjust the photomask area, and keep the photomask areas of the storage module, oscillator circuit module, and IO driver module unchanged; under the adjusted photomask area, manufacture the storage module, oscillator circuit module, and IO driver module respectively according to the optimal process parameters under the S / D ion implantation process; based on the optimal process parameters of the storage module, oscillator circuit module, and IO driver module under the metal silicidation process, adjust the photomask area, and adjust the storage module and oscillator circuit module to the same photomask area, and adjust the IO driver module to another photomask area; under the adjusted photomask area, manufacture the storage module, oscillator circuit module, and IO driver module respectively according to the optimal process parameters under the metal silicidation process to obtain the generated storage module, oscillator circuit module, and IO driver module; interconnect the storage module, oscillator circuit module, and IO driver module based on the backend metal copper to generate a chip.

[0073] Among them, in the potential well ion implantation process, based on the analysis of test results, it is found that the storage module has performance requirements for speed. The speed of the storage module is related to the effective channel areas of PG, PD, and PU, and is also associated with the turn-on threshold voltages and saturation currents of PG, PD, and PU. The original process parameters of the storage module in the potential well ion implantation process can be optimized (for example, adjusting parameters such as implantation energy, source species type, or implantation concentration), which can increase the read / write window of the storage module, achieve the purpose of improving the yield and performance of the storage module, and use the optimized process parameters as the optimal process parameters of the storage module in the potential well ion implantation process. In the potential well ion implantation process, N-well ion implantation of PG and PD, as well as P-well ion implantation of PU, are carried out based on the optimal process parameters to generate the N and P poles of the storage module. Based on the analysis of test results, it is found that the oscillator circuit module has requirements for a faster device turn-on speed and a smaller substrate leakage current. The original process parameters of the oscillator circuit module in the potential well ion implantation process can be optimized, and the optimized process parameters are used as the optimal process parameters of the oscillator circuit module in the potential well ion implantation process. In the potential well ion implantation process, N-well ion implantation and P-well ion implantation are carried out based on the optimal process parameters to generate the N and P poles of the oscillator circuit module. Based on the analysis of test results, it is found that the IO driver module has requirements for a higher voltage tolerance. The original process parameters of the IO driver module in the potential well ion implantation process can be optimized to achieve the purpose of increasing the threshold voltage and breakdown voltage of the IO driver module, and the optimized process parameters are used as the optimal process parameters of the IO driver module in the potential well ion implantation process. In the potential well ion implantation process, N-well ion implantation and P-well ion implantation are carried out based on the optimal process parameters to generate the N and P poles of the IO driver module.

[0074] In the gate oxide preparation process, based on the analysis of test results, it is found that the memory module and the oscillator circuit module have performance requirements with relatively low voltage tolerance. Since the gate oxide requirements of the memory module and the oscillator circuit module are roughly the same, the memory module and the oscillator circuit module are adjusted to the same mask area for mask area merging processing, which can achieve the purpose of reducing costs and increasing production capacity. Moreover, due to the performance requirements of the memory module and the oscillator circuit module with relatively low voltage tolerance, the memory module and the oscillator circuit module can meet their voltage requirements by using the original process parameters in the gate oxide preparation process, and there is no need to adjust the original process parameters in the gate oxide preparation process. The original process parameters are the optimal process parameters of the memory module and the oscillator circuit module in the gate oxide preparation process. Based on the analysis of test results, it is found that the IO driver module has application requirements for withstanding high voltage and large current. The gate oxide requirements of the IO driver module are different from those of the memory module and the oscillator circuit module, and the IO driver module is adjusted to a separate mask area. Moreover, due to the application requirements of the IO driver module for withstanding high voltage and large current, it is necessary to optimize the original process parameters in the gate oxide preparation process, such as increasing the gate oxide growth thickness, and use the optimized process parameters as the optimal process parameters of the IO driver module in the gate oxide preparation process.

[0075] In the lightly doped drain process, based on the analysis of test results, it is found that the memory module has performance requirements for high density, and it is necessary to reduce the channel lengths of PD, PU, and PG. However, reducing the channel lengths of PD, PU, and PG will lead to an enhancement of the DIBL effect and a degradation of device performance. Therefore, in order to suppress the DIBL effect, the original process parameters of the memory module in the lightly doped drain process can be optimized (such as introducing a Halo inversion source species) to effectively suppress the DIBL effect and ensure device performance, and the optimized process parameters are used as the optimal process parameters of the memory module in the lightly doped drain process. Based on the analysis of test results, it is found that the oscillator circuit module has performance requirements for a relatively high device turn-on speed. The original process parameters of the oscillator circuit module in the lightly doped drain process can be optimized (such as increasing the injection concentration of the effective carrier type) to achieve the purpose of accelerating the device switching speed, and the optimized process parameters are used as the optimal process parameters of the memory module in the lightly doped drain process. Based on the analysis of test results, it is found that the IO driver module has the characteristic of a relatively wide channel length, and the effect of the lightly doped drain process is limited. Therefore, the lightly doped drain process of the IO driver module can be carried out based on the original process parameters. Since the optimal process parameters of the memory module, the oscillator circuit module, and the IO driver module in the lightly doped drain process are different, the memory module, the oscillator circuit module, and the IO driver module are adjusted to different mask areas before the lightly doped drain process.

[0076] In the gate size process, based on the analysis of the test results, it is found that the storage module needs PD and PU to form a matching structure, and the PD and PU are misaligned due to the difference in mobility and actual process manufacturing. By adjusting the gate size, the channel length of the device can be adjusted. The PG device can also make targeted size adjustments based on the test results to improve the yield and performance of the storage module. Based on the analysis of the test results, it is found that the oscillation circuit module also needs to solve the matching problem of NMOS and PMOS. Therefore, adjusting the gate size can also improve the yield and performance of the oscillation circuit module. Based on the analysis of the test results, it is found that the IO driver module mainly bears the driving role and has the performance requirements of the ability to withstand large driving current and voltage, but is not sensitive to the matching of NMOS and PMOS and the short channel effect of the device. Therefore, the gate size process of the IO driver module can be based on the original process parameters. Since the optimal process parameters of the storage module, oscillation circuit module and IO driver module in the gate size process are different, the storage module, oscillation circuit module and IO driver module are adjusted to different mask areas before the gate size process.

[0077] In the S / D ion implantation process, based on the analysis of the test results, it is found that the storage module has a high-density performance requirement and is easily affected by layout effects such as LOD and WPE, resulting in a decrease in the performance of the storage module. The original process parameters of the storage module in the S / D ion implantation process can be optimized (such as increasing the carrier concentration), and the performance of the storage module can be appropriately compensated. The optimized process parameters are used as the optimal process parameters of the storage module in the S / D ion implantation process. Based on the analysis of the test results, it is found that the oscillation circuit module has a high device opening speed performance requirement, and the original process parameters of the oscillation circuit module in the S / D ion implantation process can be optimized, and the optimized process parameters are used as the optimal process parameters of the oscillation circuit module in the S / D ion implantation process. Based on the analysis of the test results, it is found that the IO driver module has a large driving current and voltage performance requirement, and the original process parameters of the IO driver module in the S / D ion implantation process can be optimized, and the optimized process parameters are used as the optimal process parameters of the IO driver module in the S / D ion implantation process. Since the optimal process parameters of the storage module, oscillation circuit module and IO driver module in the S / D ion implantation process are different, the storage module, oscillation circuit module and IO driver module are adjusted to different mask areas before the S / D ion implantation process.

[0078] In the metal silicon chemical process, based on the analysis of test results, it is found that the storage module and the oscillation circuit module have the effect of reducing their ohmic contact resistance, thereby reducing energy consumption. Therefore, before the metal silicon chemical process, the storage module and the oscillation circuit module are adjusted to the same photomask area, and in the metal silicon chemical process, the original process parameters of the storage module and the oscillation circuit module in the metal silicon chemical process are optimized, and the optimized process parameters are used as the best process parameters of the storage module and the oscillation circuit module in the metal silicon chemical process. Based on the analysis of test results, it is found that some circuits of the IO driver module need to increase their contact resistance due to special circuit design requirements, such as circuits that require ESD protection, while the remaining circuits do not need to increase their contact resistance. Therefore, the IO driver module can be further split, and some circuits and the remaining circuits of the IO driver module are respectively divided into different photomask areas. For the part of the circuit that needs to increase the contact resistance, it is manufactured based on the optimized best process parameters in the metal silicon chemical process; while the remaining part of the circuit that does not need to increase the contact resistance undergoes the metal silicon chemical process based on the original process parameters to meet the circuit design and yield requirements of the IO driver module.

[0079] It should be understood that the above content only describes the manufacturing processes of the storage module, the oscillation circuit module, and the IO driver circuit module in the potential well ion implantation process, the gate oxide preparation process, the lightly doped drain process, the gate size process, the S / D ion implantation process, and the metal silicon chemical process; while the manufacturing principles of other circuit modules of the chip are the same as those of the storage module, the oscillation circuit module, and the IO driver circuit module, and they are all manufactured based on the best process parameters obtained from the analysis of the test results of the chip yield test; and the potential well ion implantation process, the gate oxide preparation process, the lightly doped drain process, the gate size process, the S / D ion implantation process, and the metal silicon chemical process are only part of the manufacturing processes of the chip. There are also other processes between the potential well ion implantation process, the gate oxide preparation process, the lightly doped drain process, the gate size process, the S / D ion implantation process, and the metal silicon chemical process, and in other processes, each circuit module is also manufactured according to the corresponding best process parameters.

[0080] Based on the same inventive concept, an embodiment of the present disclosure also provides an improved device for a chip manufacturing process, as Figure 3 shown. The improved device 200 includes:

[0081] A process condition generation module 210, configured to obtain the process conditions corresponding to each circuit module of the chip based on the analysis of the test results of the chip yield test; the process conditions include the best process parameters of each process of each circuit module.

[0082] It should be understood that the process condition generation module 210 is used to execute the content of the above S110.

[0083] The process execution module 220 is configured to manufacture each circuit module according to the corresponding optimal process parameters when each circuit module executes various processes.

[0084] It should be understood that the process execution module 220 is used to execute the content of S120 described above.

[0085] The chip generation module 230 is configured to generate a chip based on each circuit module after manufacturing is completed.

[0086] It should be understood that the chip generation module 230 is used to execute the content of S130 described above.

[0087] Furthermore, as Figure 4 shown, the improved device 200 further includes:

[0088] The photomask division module 240 is configured to divide the photomask area according to process conditions to obtain different photomask areas.

[0089] It should be understood that the photomask division module 240 is used to divide the circuit modules with the same process conditions into the same photomask area and divide the circuit modules with different process conditions into different photomask areas.

[0090] The photomask adjustment module 250 is configured to adjust the photomask area according to the target process parameters of each circuit module before the circuit module executes the target process to obtain the adjusted photomask area; the target process is the next process that the circuit module will execute, and the target process parameters are the optimal process parameters corresponding to the target process.

[0091] It should be understood that the photomask adjustment module 250 is used to adjust the circuit modules with the same target process parameters into the same photomask area and adjust the circuit modules with different target process parameters into different photomask areas.

[0092] Based on the same inventive concept, an embodiment of the present disclosure also provides a chip, which includes a circuit module manufactured by the improved method of the chip manufacturing process described in any of the above embodiments.

[0093] Based on the same inventive concept, an embodiment of the present disclosure also provides an electronic device, which includes the chip described in any of the above embodiments. In some usage scenarios, the product form of the electronic device is a graphics card; in some other usage scenarios, the product form of the electronic device is a CPU motherboard.

[0094] Based on the same inventive concept, an embodiment of the present disclosure also provides an electronic device, which includes the above electronic device. In some usage scenarios, the product form of the electronic device is a portable electronic device, such as a smart phone, a tablet computer, a VR device, etc.; in some usage scenarios, the product form of the electronic device is a personal computer, a game console, etc.

[0095] Although the preferred embodiments of the present disclosure have been described, additional changes and modifications can be made to these embodiments by those skilled in the art once they learn the basic inventive concept. Therefore, the appended claims are intended to be construed to include the preferred embodiments as well as all changes and modifications that fall within the scope of the present disclosure.

[0096] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure is also intended to include these modifications and variations.

Claims

1. An improved method for chip manufacturing process, characterized in that, Including: Analyzing the test results based on the chip yield test to obtain the process conditions corresponding to each circuit module of the chip; The process conditions include the optimal process parameters for each process of each circuit module; the test results include the voltage requirements, density, device turn-on speed, leakage current magnitude, and drive current voltage magnitude that each circuit module can withstand; the circuit modules include a storage module, an oscillation circuit module, and an IO drive module, and the processes include a potential well ion implantation process, a gate oxide preparation process, a lightly doped drain process, a gate size process, an S / D ion implantation process, and a metal silicidation process; Before the circuit module executes the target process, adjusting the photomask area according to the target process parameters of each circuit module to obtain the adjusted photomask area; the target process is the next process that the circuit module will execute, and the target process parameters are the optimal process parameters corresponding to the target process; When each circuit module executes each process, manufacturing each circuit module according to the corresponding optimal process parameters; The step of manufacturing each circuit module according to the corresponding optimal process parameters when each circuit module executes each process includes: The storage module, the oscillation circuit module, and the IO drive module are respectively manufactured based on the optimal process parameters under different processes in the potential well ion implantation process, the gate oxide preparation process, the lightly doped drain process, the gate size process, the S / D ion implantation process, and the metal silicidation process; Generating the chip based on each circuit module after manufacturing is completed.

2. The method according to claim 1, characterized in that, The test results include CP test results and FT test results.

3. The method according to claim 1, characterized in that, Before each circuit module executes each process, the method further includes: Dividing the photomask area according to the process conditions to obtain different photomask areas.

4. The method according to claim 3, characterized in that, The step of dividing the photomask area according to the process conditions to obtain different photomask areas includes: Dividing the circuit modules with the same process conditions into the same photomask area; Dividing the circuit modules with different process conditions into different photomask areas.

5. The method according to claim 1, characterized in that, The step of adjusting the photomask area according to the target process parameters of each circuit module before the circuit module executes the target process to obtain the adjusted photomask area includes: Adjusting the circuit modules with the same target process parameters into the same photomask area; Adjusting the circuit modules with different target process parameters into different photomask areas.

6. An improved device for chip manufacturing process, characterized in that, Including: A process condition generation module for analyzing the test results based on the chip yield test to obtain the process conditions corresponding to each circuit module of the chip; The process conditions include the optimal process parameters for each process of each circuit module; the test results include the voltage requirements, density, device turn-on speed, leakage current magnitude, and drive current voltage magnitude that each circuit module can withstand; the circuit modules include a storage module, an oscillation circuit module, and an IO drive module, and the processes include a potential well ion implantation process, a gate oxide preparation process, a lightly doped drain process, a gate size process, an S / D ion implantation process, and a metal silicidation process; A photomask adjustment module, configured to adjust the photomask area according to the target process parameters of each circuit module before the circuit module executes the target process, so as to obtain an adjusted photomask area; the target process is the next process to be executed by the circuit module, and the target process parameters are the optimal process parameters corresponding to the target process; A process execution module, configured to manufacture each circuit module according to the corresponding optimal process parameters when each circuit module executes each process; The process execution module is further configured to manufacture the storage module, the oscillation circuit module, and the IO drive module respectively based on the optimal process parameters under different processes in the processes of well ion implantation, gate oxide preparation, lightly doped drain, gate size, S / D ion implantation, and metal silicidation; A chip generation module, configured to generate the chip based on each circuit module after manufacturing is completed.

7. The improved device for chip manufacturing process according to claim 6, characterized in that, The test results include CP test results and FT test results.

8. The improved device for chip manufacturing process according to claim 6, characterized in that, The improvement device further includes: A photomask division module, configured to divide the photomask area according to the process conditions to obtain different photomask areas.

9. The improved device for chip manufacturing process according to claim 8, characterized in that, The photomask division module is configured to divide the circuit modules with the same process conditions into the same photomask area, and divide the circuit modules with different process conditions into different photomask areas.

10. The improved device for chip manufacturing process according to claim 6, characterized in that, The photomask adjustment module is configured to adjust the circuit modules with the same target process parameters into the same photomask area, and adjust the circuit modules with different target process parameters into different photomask areas.

11. A chip, characterized in that,Including circuit modules manufactured and generated by the improvement method of the chip manufacturing process according to any one of claims 1-5.

12. An electronic device, characterized in that, Including the chip of claim 11.

13. An electronic device, characterized in that, Including the electronic device of claim 12.

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