Four-port chip with built-in clock encoding mode, system and data interaction method

Abstract

This invention provides a four-port chip with a built-in clock encoding method, comprising: a clock module for generating a synchronous clock based on an external clock input from a main clock port, and for multiplying the synchronous clock to generate a multiplied clock; a data input module connected to the output of the clock module for receiving and storing configuration information input from the main data port under the control of the synchronous clock; a main module connected to the output of the data input module for reading the configuration information and configuring the chip, and for generating data to be transmitted under the control of the system clock; and a data output module connected to the outputs of the clock module and the main module for embedding the multiplied clock into the data to be transmitted to generate transmitted data, and outputting the transmitted data through the main data port. The four-port chip with a built-in clock encoding method provided by this invention solves the problem that existing image sensor chips cannot transmit data at a stable and controllable clock frequency.

Description

Technical Field

[0001] This invention relates to the field of image sensor technology, and in particular to a four-port chip with a built-in clock encoding method, a chip system, and a data interaction method. Background Technology

[0002] Image sensors are widely used in digital cameras, mobile phones, medical devices, automobiles and other applications to capture and identify optical image information of people or scenes and convert the optical image information into electrical signals.

[0003] Traditional image sensor chips often suffer from difficulties in effectively controlling transmission stability. Because both clock and data transmission are single-ended, their anti-interference capabilities are poor. Furthermore, since the sensor lacks a reference clock, the clock signal frequency is significantly affected by factors such as manufacturing process, temperature, and power supply voltage, failing to provide a stable clock and thus making it impossible to transmit data at a stable and controllable clock frequency. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a four-port chip, chip system and data interaction method with built-in clock encoding, which solves the problem that existing image sensor chips cannot transmit data at a stable and controllable clock frequency.

[0005] To achieve the above and other related objectives, the present invention provides a four-port chip with a built-in clock encoding method, powered by a main power port and a main ground port, and interacting with data through a main clock port and a main data port; the four-port chip includes:

[0006] The clock module is used to generate a synchronous clock based on the external clock input from the main clock port, and to multiply the synchronous clock to generate a multiplied clock.

[0007] The data input module is connected to the output terminal of the clock module and is used to receive and store the configuration information input from the main data port under the control of the synchronization clock.

[0008] The main module is connected to the output of the data input module and is used to read the configuration information and configure the chip, and to generate the data to be transmitted under the control of the system clock.

[0009] The data output module connects the output terminal of the clock module and the output terminal of the main module. It is used to embed the frequency multiplier clock into the data to be transmitted to generate transmission data, and output the transmission data through the main data port.

[0010] Optionally, the data output module performs an XOR operation between the frequency-doubled clock and the data to be transmitted, so as to embed the frequency-doubled clock into the data to be transmitted.

[0011] Optionally, the data output module is further configured to convert the transmitted data into differential data and output it differentially through the master clock port and the master data port.

[0012] Optionally, the data output module uses the frequency multiplier clock to sample and output the transmitted data.

[0013] Optionally, the clock module is implemented using an adjustable frequency-multiplying phase-locked loop circuit; wherein, before the configuration information transmission is completed, the phase-locked loop circuit operates in a phase-locked state; after the configuration information transmission is completed, the phase-locked loop circuit operates in a voltage-locked state.

[0014] Optionally, the main module is also connected to the output of the clock module to form the system clock based on the synchronization clock.

[0015] Optionally, the four-port chip includes an image sensor chip, and the data to be transmitted includes image data in the form of digital signals.

[0016] The present invention also provides a chip system, the chip system comprising:

[0017] The main chip is a four-port chip with a built-in clock encoding method as described in any of the above items;

[0018] The slave chip has a slave clock port and a slave data port, and the slave clock port and the slave data port are connected to the master clock port and the master data port respectively to perform data interaction. It is used to provide the external clock and the configuration information to the master chip, and to receive the transmission data output by the master chip and obtain the data to be transmitted.

[0019] Optionally, when the master chip outputs the differential data, the slave chip receives the differential data output by the master chip and obtains the data to be transmitted.

[0020] Optionally, the slave chip includes:

[0021] A clock generation module is used to generate the external clock and output it through the clock port.

[0022] The data generation module is used to generate the configuration information and output it through the data port;

[0023] The data processing module is used to receive the differential data through the slave clock port and the slave data port, convert the differential data into the transmission data and perform clock recovery, and then sample the transmission data according to the recovered clock to obtain the data to be transmitted.

[0024] Optionally, when the main chip includes an image sensor chip, the slave chip includes a processor chip.

[0025] This invention also provides a data interaction method for a chip system, the chip system including a master chip and a slave chip, wherein the master clock port and master data port of the master chip are correspondingly connected to the slave clock port and slave data port of the slave chip for data interaction; the data interaction method includes:

[0026] The main chip receives the external clock sent by the slave chip through the main clock port and forms a synchronous clock;

[0027] Under the control of the synchronous clock, the master chip receives configuration information sent by the slave chip through the master data port;

[0028] The main chip is configured according to the configuration information;

[0029] The main chip generates a frequency multiplier clock based on the synchronous clock;

[0030] The master chip embeds the frequency multiplier clock into the data to be transmitted to generate the transmitted data, and outputs the transmitted data to the slave chip through the master data port;

[0031] The slave chip receives the transmitted data through the slave data port, restores the clock of the transmitted data, and then samples the transmitted data according to the restored clock to obtain the data to be transmitted.

[0032] Optionally, the main chip performs an XOR operation between the frequency multiplier clock and the data to be transmitted, so as to embed the frequency multiplier clock into the data to be transmitted.

[0033] Optionally, the main chip uses the frequency multiplier clock to sample and output the transmitted data.

[0034] Optionally, the main chip generates the frequency-doubled clock based on an adjustable frequency-doubled phase-locked loop circuit; before the configuration information transmission is completed, the phase-locked loop circuit operates in a phase-locked state; after the configuration information transmission is completed, the phase-locked loop circuit operates in a voltage-locked state.

[0035] Optionally, after the chip sends the external clock, it sends the configuration information after a set time.

[0036] Optionally, after the master chip receives the frame start field sent by the slave chip, the master chip switches from receive mode to send mode, and at this time, the slave chip switches from send mode to receive mode; after the slave chip receives the frame end field sent by the master chip, the slave chip switches from receive mode to send mode, and at this time, the master chip switches from send mode to receive mode.

[0037] Optionally, the data interaction method further includes:

[0038] After the transmission data is generated, the master chip converts the transmission data into differential data and outputs the differential data differentially to the slave chip through the master clock port and the master data port; and the slave chip receives the differential data through the slave clock port and the slave data port and converts the differential data into the transmission data.

[0039] As described above, the present invention provides a four-port chip, chip system, and data interaction method with a built-in clock encoding method. This method embeds clock information into the data information for transmission, enabling the chip to transmit data at a stable and controllable clock frequency. Simultaneously, it transforms single-ended data transmission into dual-ended data transmission, improving anti-interference capabilities during data transmission and giving the chip the advantages of low power consumption and high performance. The four-port chip of the present invention can stably output images with a controllable frame rate without increasing the number of ports. Attached Figure Description

[0040] Figure 1 The diagram shown is a schematic of the four-port chip of the present invention.

[0041] Figure 2 The diagram shows a four-port chip of the present invention performing XOR processing.

[0042] Figure 3 The diagram shown is a schematic of the chip system of the present invention.

[0043] Figure 4 The flowchart shown is a data interaction method of the present invention.

[0044] Component designation explanation

[0045] 100 Quad-Port Chip / Main Chip

[0046] 101 Clock Module

[0047] 102 Data Input Module

[0048] 103 Main Module

[0049] 104 Data Output Module

[0050] 200 from chips

[0051] 201 Clock Generation Module

[0052] 202 Data Generation Module

[0053] 203 Data Processing Module Detailed Implementation

[0054] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0055] Please see Figures 1 to 4 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation, the shape, quantity and proportion of each component in the actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.

[0056] Example 1

[0057] like Figure 1 As shown, this embodiment provides a four-port chip 100 with a built-in clock encoding method, which is powered by the main power port VDD1 and the main ground port GND1, and performs data interaction through the main clock port SCL1 and the main data port SDA1; the four-port chip 100 includes: a clock module 101, a data input module 102, a main module 103 and a data output module 104.

[0058] The clock module 101 is used to form a synchronous clock SYN_CLK based on the external clock EXT_CLK input to the master clock port SCL1, and to multiply the synchronous clock SYN_CLK to generate a multiplied clock MUL_CLK.

[0059] Specifically, the clock module 101 is implemented using an adjustable frequency-multiplying phase-locked loop (PLL) circuit. Before the configuration information transmission is completed, the PLL circuit operates in a phase-locked state, maintaining a constant frequency by keeping the phase difference constant, thereby obtaining a stable clock signal. After the configuration information transmission is completed, the charge pump (CP) in the PLL circuit is turned off, and the phase-frequency detector (PFD) is placed in a reset state, thereby switching the PLL circuit from a phase-locked state to a voltage-locked state. This ensures that the control voltage of the voltage-controlled oscillator (VCO) remains unchanged, and the PLL circuit can still output a stable clock signal.

[0060] In practical applications, the frequency of the synchronization clock SYN_CLK is the same as the frequency of the external clock EXT_CLK, and the frequency of the multiplied clock MUL_CLK is m times the frequency of the synchronization clock SYN_CLK, where m is a positive number greater than 1. In one example, it can be assumed that the initial multiplication value of the phase-locked loop (PLL) circuit is 1. At this time, the PLL circuit multiplies the external clock EXT_CLK by 1 to generate the synchronization clock SYN_CLK. After the chip configuration is completed, the multiplication value of the PLL circuit is configured to m. At this time, the PLL circuit multiplies the synchronization clock SYN_CLK by m to generate the multiplied clock MUL_CLK. The clock module can be implemented using any PLL circuit capable of frequency adjustment in the existing technology.

[0061] The data input module 102 is connected to the output of the clock module 101 and is used to receive and store the configuration information input from the main data port SDA1 under the control of the synchronization clock SYN_CLK. The data input module may include a control register bank, and data input is implemented based on the control register bank.

[0062] The main module 103 is connected to the output of the data input module 102, and is used to read the configuration information and configure the chip, as well as generate data to be transmitted under the control of the system clock SYS_CLK. Furthermore, the main module 103 is also connected to the output of the clock module 101 to generate the system clock SYS_CLK based on the synchronization clock SYN_CLK. In practical applications, the frequency of the system clock SYS_CLK and the frequency of the multiplier clock MUL_CLK can be the same. Of course, they can also be different; the required frequency of the system clock SYS_CLK can be generated based on the multiplier clock MUL_CLK according to actual needs, for use by the main module.

[0063] Specifically, the main module 103 includes a clock / control unit and a data unit. The clock / control unit is connected to the output of the clock module 101 and the output of the data input module 102, and is used to generate the system clock SYS_CLK based on the synchronization clock SYN_CLK, and to read the configuration information and perform chip configuration, so as to generate a control signal based on the system clock SYS_CLK after the chip configuration is completed. The data unit is connected to the output of the clock / control unit and is used to generate the data to be transmitted based on the control signal. In another example, the system clock SYS_CLK can be generated based on the clock module, and the main module can directly receive the system clock SYS_CLK to generate image data, etc. Of course, the main module can also adopt other conventional modules of the prior art.

[0064] More specifically, when the four-port chip 100 includes an image sensor chip, the data unit includes: a pixel circuit and a quantization circuit; the pixel circuit is connected to the output of the clock / control unit and is used to perform photoelectric conversion according to the control signal to generate a pixel signal; the quantization circuit is connected to the output of the pixel circuit and is used to quantize the pixel signal and generate the data to be transmitted; wherein, the pixel signal is image data in analog signal form, and the data to be transmitted is image data in digital signal form.

[0065] In practical applications, the pixel circuit corresponds to a number of pixels arranged in rows and columns. Each pixel includes at least a photodiode, a transmission transistor, a reset transistor, a source follower transistor, and a selection transistor. The anode of the photodiode is grounded, and its cathode is connected to the first terminal of the transmission transistor. The control terminal of the transmission transistor receives a transmission control signal, and its second terminal is connected to a floating diffused active region. The control terminal of the reset transistor receives a reset control signal, its first terminal receives a power supply voltage, and its second terminal is connected to the floating diffused active region. The gate terminal of the source follower transistor is connected to the floating diffused active region, its drain terminal receives a power supply voltage, and its source terminal is connected to the first terminal of the selection transistor. The control terminal of the selection transistor receives a selection control signal, and its second terminal generates a pixel signal.

[0066] The quantization circuit includes a comparator and a counter. The comparator compares the pixel signal and the ramp signal, while the counter starts counting. When the ramp signal is greater than the pixel signal, the output of the comparator flips, and the counter stops counting. The counting result at this time is the digital code value of the quantized pixel signal.

[0067] The data output module 104 is connected to the output terminal of the clock module 101 and the output terminal of the main module 103. It is used to embed the frequency multiplier clock MUL_CLK into the data to be transmitted to generate transmission data, and output the transmission data through the main data port SDA1.

[0068] Specifically, the data output module 104 performs a XOR operation on the frequency multiplier clock MUL_CLK and the data to be transmitted to embed the frequency multiplier clock MUL_CLK into the data to be transmitted. This can be implemented using an existing XOR processing circuit. Alternatively, other circuits can be used to embed the frequency multiplier clock MUL_CLK into the data to be transmitted to generate the transmitted data. The specific XOR logic is as follows: Figure 2 As shown.

[0069] Specifically, the data output module 104 uses the multiplied clock MUL_CLK to sample and output the transmitted data; the data transmission rate and the clock sampling frequency can be the same or different, which does not affect this example. In practical applications, to save ports and reduce the number of clock signal transmissions, the data transmission rate can be set to be the same as the clock sampling frequency; of course, to reduce power consumption, the data transmission rate can be set to be different from the clock sampling frequency.

[0070] Furthermore, the data output module 104 is also used to convert the transmitted data into differential data and output it differentially through the master clock port SCL1 and the master data port SDA1; by converting single-ended data transmission into dual-ended data transmission, the anti-interference capability during data transmission can be improved.

[0071] Specifically, the data output module 104 includes: a built-in clock circuit and a single-ended to differential converter circuit; the built-in clock circuit is connected to the output terminal of the clock module 101 and the output terminal of the main module 103, and is used to embed the multiplied clock MUL_CLK into the data to be transmitted to generate transmitted data; the single-ended to differential converter circuit is connected to the output terminal of the built-in clock circuit, and is used to convert the transmitted data into differential data, and output it differentially through the main clock port SCL1 and the main data port SDA1. More specifically, the built-in clock circuit is implemented using an XOR logic circuit.

[0072] In practical applications, the main chip 100 has three paths: path ①, path ②, and path ③. Only one path is open at a time to ensure that data transmission or reception does not conflict. Specifically, when the main chip 100 starts working, path ① opens first to transmit the external clock EXT_CLK and closes after transmission. Then, path ② opens to receive configuration information and closes after transmission. Finally, path ③ opens to output differential data and closes after transmission. In other words, in one embodiment, before the chip starts working, the slave end (slave chip) transmits data and clock to the master end (the main chip in this embodiment). At this time, paths ① and ② open first to receive configuration information. Input data is sampled and transmitted to the register via the input clock, thus configuring the chip internally. After transmission is complete, paths ① and ② are closed. At this point, the clock module is locked to a multiple of the input clock frequency. Then, the charge pump in the PLL (clock module) is also turned off, and the PFD (phase-frequency detector) is set to reset state. This ensures that the control voltage of the VCO (voltage-controlled oscillator) remains unchanged, and the PLL can still output a stable frequency. The PLL then outputs a corresponding multiplied clock frequency according to the configuration information for data transmission. Furthermore, embedding the clock signal into the Master output signal facilitates the normal operation of the slave chip's Clock Recovery system. The encoding method can be as follows... Figure 2 As shown, the data to be transmitted is XORed with the clock signal to achieve the transition from level to edge.

[0073] Correspondingly, such as Figure 3 As shown, this embodiment also provides a chip system, which includes a master chip 100 and a slave chip 200. The master chip 100 is a four-port chip with a built-in clock encoding method as described above. The slave chip 200 has a slave clock port SCL2 and a slave data port SDA2, and the slave clock port SCL2 and the slave data port SDA2 are correspondingly connected to the master clock port SCL1 and the master data port SDA1 for data interaction. This allows the slave chip 200 to provide the external clock EXT_CLK and the configuration information to the master chip 100, and to receive the transmission data output by the master chip 100 and obtain the data to be transmitted. It should be noted that the slave chip 200 also has a slave power supply port VDD2 and a slave ground port GND2 to supply power to the slave chip 200.

[0074] Furthermore, when the main chip 100 outputs the differential data, the slave chip 200 receives the differential data output by the main chip 100 and obtains the data to be transmitted.

[0075] Specifically, the slave chip 200 includes a clock generation module 201, a data generation module 202, and a data processing module 203. The clock generation module 201 generates the external clock EXT_CLK and outputs it through the slave clock port SCL2. The clock generation module 201 can be an existing clock generation module, such as one based on a phase-locked loop circuit. The data generation module 202 generates the configuration information and outputs it through the slave data port SDA2. The data generation module 202 can be any module capable of generating configuration information, such as one based on registers. The data processing module 203 receives the differential data through the slave clock port SCL2 and the slave data port SDA2, converts the differential data into the transmission data, performs clock recovery, and then samples the transmission data according to the recovered clock to obtain the data to be transmitted. In practical applications, the master chip 100 includes an image sensor chip, and the slave chip 200 includes a processor chip.

[0076] More specifically, the data processing module 203 includes: a differential-to-single-ended circuit, a clock data recovery circuit, a data to be transmitted recovery circuit, and a data processing circuit. The differential-to-single-ended circuit receives the differential data through the slave clock port SCL2 and the slave data port SDA2, and converts the differential data into single-ended data (i.e., transmission data). The clock data recovery circuit is connected to the differential-to-single-ended circuit and performs clock recovery on the transmission data to obtain a recovered clock, wherein the recovered clock is the frequency multiplier clock, such as using a CDR clock recovery circuit. The data to be transmitted recovery circuit is connected to the output of the differential-to-single-ended circuit and the output of the clock data recovery circuit, and is used to sample the transmission data according to the recovered clock to obtain the data to be transmitted. Existing data recovery circuits can be used to obtain the data to be transmitted, improving the accuracy of data transmission. The data processing circuit is connected to the output of the data to be transmitted recovery circuit and is used to perform subsequent data processing on the data to be transmitted to generate an image. Existing processing circuits can be selected to process the obtained data to be transmitted based on actual needs.

[0077] Example 2

[0078] like Figure 4 As shown, this embodiment provides a data interaction method for a chip system, the data interaction method including: steps 1), 2), 3), 4), 5), and 6); wherein, the chip system includes a master chip 100 and a slave chip 200, the master clock port SCL1 and master data port SDA1 of the master chip 100 are correspondingly connected to the slave clock port SCL2 and slave data port SDA2 of the slave chip 200 for data interaction. In practical applications, the chip system can be the chip system described in Embodiment 1.

[0079] Step 1) The main chip 100 receives the external clock EXT_CLK sent by the slave chip 200 through the main clock port SCL1 and forms a synchronization clock SYN_CLK.

[0080] Step 2) Under the control of the synchronization clock SYN_CLK, the master chip 100 receives the configuration information sent by the slave chip 200 through the master data port SDA1.

[0081] Step 3) The main chip 100 performs chip configuration according to the configuration information.

[0082] Step 4) The main chip 100 generates a frequency multiplier clock MUL_CLK according to the synchronization clock SYN_CLK.

[0083] Specifically, after the slave chip 200 sends the external clock EXT_CLK, it sends the configuration information after a set time. During this set time, the master chip 100 receives the external clock EXT_CLK and generates the synchronization clock SYN_CLK based on it. By setting the external clock and configuration information to be sent in a time-sharing manner, the waiting time is prioritized, which is beneficial for smooth and stable subsequent operations.

[0084] Specifically, the main chip 100 generates the synchronous clock SYN_CLK and the frequency-multiplied clock based on an adjustable frequency-multiplied phase-locked loop circuit; wherein, before the configuration information transmission is completed, the phase-locked loop circuit operates in a phase-locked state; after the configuration information transmission is completed, the phase-locked loop circuit operates in a voltage-locked state.

[0085] In practical applications, the frequency of the synchronization clock SYN_CLK is the same as the frequency of the external clock EXT_CLK, and the frequency of the multiplied clock MUL_CLK is m times the frequency of the synchronization clock SYN_CLK, where m is a positive number greater than 1. Initially, the frequency multiplication value of the phase-locked loop (PLL) circuit is 1. At this time, the PLL circuit multiplies the external clock EXT_CLK by 1 to generate the synchronization clock SYN_CLK. After chip configuration, the frequency multiplication value of the PLL circuit is configured to m. At this time, the PLL circuit multiplies the synchronization clock SYN_CLK by m to generate the multiplied clock MUL_CLK.

[0086] Step 5) The master chip 100 embeds the frequency multiplier clock MUL_CLK into the data to be transmitted to generate transmission data, and outputs the transmission data to the slave chip 200 through the master data port SDA1.

[0087] Specifically, the main chip 100 performs an XOR operation between the frequency multiplier clock MUL_CLK and the data to be transmitted, so as to embed the frequency multiplier clock MUL_CLK into the data to be transmitted, thereby realizing the transformation of the transmitted data from level to edge.

[0088] Specifically, the main chip 100 uses the multiplied clock MUL_CLK to sample and output the transmitted data; the data transmission rate and the clock sampling frequency can be the same or different, which does not affect this example. In practical applications, to save ports and reduce the number of clock signal transmissions, the data transmission rate can be set to be the same as the clock sampling frequency; of course, to reduce power consumption, the data transmission rate can also be set to be different from the clock sampling frequency.

[0089] Step 6) The chip 200 receives the transmission data through the slave data port SDA2, restores the clock of the transmission data, and then samples the transmission data according to the restored clock to obtain the data to be transmitted; the data to be transmitted is obtained by sampling the transmission data using the restored clock, thereby ensuring the correctness of data transmission.

[0090] Furthermore, the data interaction method further includes: after the transmission data is formed, the master chip 100 converts the transmission data into differential data, and outputs the differential data differentially to the slave chip 200 through the master clock port SCL1 and the master data port SDA1; and the slave chip 200 receives the differential data through the slave clock port SCL2 and the slave data port SDA2, and converts the differential data into the transmission data.

[0091] In practical applications, when the master chip 100 and the slave chip 200 interact with each other, after the master chip 100 receives the start-of-frame field sent by the slave chip 200, the master chip 100 switches from receiving mode to sending mode, and at this time, the slave chip 200 switches from sending mode to receiving mode; after the slave chip 200 receives the end-of-frame field sent by the master chip 100, the slave chip 200 switches from receiving mode to sending mode, and at this time, the master chip 100 switches from sending mode to receiving mode.

[0092] In one example, when the master chip 100 sends data to be transmitted to the slave chip 200 based on a set frame format, the data is transmitted in the set frame format, which includes several row fields. Each row field has the same format, including {start of row field, clock synchronization field, data field, clock synchronization field, end of row field}.

[0093] The data field comprises n bits; the frame start field comprises 10n bits; the frame end field comprises 10n bits; the line start field comprises 3n bits; the line end field comprises 3n bits; and the clock synchronization field comprises 8n bits, where n is an integer greater than 1.

[0094] In this example, n = 10. The frame start field includes 100 bits, which are 10 sets of cyclic {1111100000}; the frame end field includes 100 bits, which are 10 sets of cyclic {0000011111}; the line start field includes 30 bits, which are 3 sets of cyclic {0000000000}; the line end field includes 30 bits, which are 3 sets of cyclic {1111111111}; the clock synchronization field includes 80 bits, which are 8 sets of cyclic {0101010101}; and the data field includes 10 bits.

[0095] In practical applications, after the master chip 100 receives the frame start field sent by the slave chip 200, it begins to send a frame of data to the slave chip 200. This frame of data usually includes several lines of data, where the line start field is a marker that a line begins to be transmitted and the line end field is a marker that a line ends to be transmitted. Each line is transmitted sequentially until the slave chip 200 detects the frame end field, which indicates that the data transmission of this frame has ended.

[0096] In summary, the four-port chip, chip system, and data interaction method of the present invention, which utilizes a built-in clock encoding method to embed clock information into the data information for transmission, thereby enabling the chip to transmit data at a stable and controllable clock frequency. Simultaneously, it transforms single-ended data transmission into dual-ended data transmission, improving the anti-interference capability during data transmission and giving the chip the advantages of low power consumption and high performance. The four-port chip of the present invention can stably output images with a controllable frame rate without increasing the number of ports. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0097] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A four-port chip with a built-in clock encoding method, characterized in that, Powered by the main power port and the main ground port, and for data exchange via the main clock port and the main data port; the four-port chip includes: The clock module is used to generate a synchronous clock based on the external clock input from the main clock port, and to multiply the synchronous clock to generate a multiplied clock. The data input module is connected to the output terminal of the clock module and is used to receive and store the configuration information input from the main data port under the control of the synchronization clock. The main module is connected to the output of the data input module and is used to read the configuration information and configure the chip, and to generate the data to be transmitted under the control of the system clock. The data output module connects the output terminal of the clock module and the output terminal of the main module. It is used to embed the frequency multiplier clock into the data to be transmitted to generate transmission data, and also to convert the transmission data into differential data and output it differentially through the main clock port and the main data port.

2. The four-port chip with built-in clock encoding method according to claim 1, characterized in that, The data output module performs an XOR operation between the frequency-doubled clock and the data to be transmitted, so as to embed the frequency-doubled clock into the data to be transmitted.

3. The four-port chip with built-in clock encoding method according to claim 1, characterized in that, The data output module uses the frequency multiplier clock to sample and output the transmitted data.

4. The four-port chip with built-in clock encoding method according to claim 1, characterized in that, The clock module is implemented using an adjustable frequency-multiplying phase-locked loop circuit; wherein, before the configuration information transmission is completed, the phase-locked loop circuit operates in a phase-locked state; after the configuration information transmission is completed, the phase-locked loop circuit operates in a voltage-locked state.

5. The four-port chip with built-in clock encoding method according to claim 4, characterized in that, The main module is also connected to the output of the clock module to form the system clock based on the synchronization clock.

6. The four-port chip with built-in clock encoding method according to claim 1, characterized in that, The four-port chip includes an image sensor chip, and the data to be transmitted includes image data in digital signal form.

7. A chip system, characterized in that, The chip system includes: The main chip is a four-port chip with a built-in clock encoding method as described in any one of claims 1-6; The slave chip has a slave clock port and a slave data port, and the slave clock port and the slave data port are connected to the master clock port and the master data port respectively to perform data interaction. It is used to provide the external clock and the configuration information to the master chip, and to receive the differential data output by the master chip and obtain the data to be transmitted.

8. The chip system according to claim 7, characterized in that, The slave chip includes: A clock generation module is used to generate the external clock and output it through the clock port. The data generation module is used to generate the configuration information and output it through the data port; The data processing module is used to receive the differential data through the slave clock port and the slave data port, convert the differential data into the transmission data and perform clock recovery, and then sample the transmission data according to the recovered clock to obtain the data to be transmitted.

9. The chip system according to claim 7, characterized in that, When the main chip includes an image sensor chip, the slave chip includes a processor chip.

10. A data interaction method for a chip system, characterized in that, The chip system includes a master chip and a slave chip. The master clock port and master data port of the master chip are connected to the slave clock port and slave data port of the slave chip respectively to perform data interaction. The data interaction method includes: The main chip receives the external clock sent by the slave chip through the main clock port and forms a synchronous clock; Under the control of the synchronous clock, the master chip receives configuration information sent by the slave chip through the master data port; The main chip is configured according to the configuration information; The main chip generates a frequency multiplier clock based on the synchronous clock; The master chip embeds the frequency multiplier clock into the data to be transmitted to generate the transmitted data, and also converts the transmitted data into differential data and outputs it differentially to the slave chip through the master clock port and the master data port. The slave chip receives the differential data through the slave clock port and the slave data port and converts it into the transmission data. It also restores the clock of the transmission data and samples the transmission data according to the restored clock to obtain the data to be transmitted.

11. The data interaction method for a chip system according to claim 10, characterized in that, The main chip performs an XOR operation between the frequency multiplier clock and the data to be transmitted, thereby embedding the frequency multiplier clock into the data to be transmitted.

12. The data interaction method for a chip system according to claim 10, characterized in that, The main chip uses the frequency multiplier clock to sample and output the transmitted data.

13. The data interaction method for a chip system according to claim 10, characterized in that, The main chip generates the frequency-doubled clock based on an adjustable frequency-doubled phase-locked loop circuit; before the configuration information transmission is completed, the phase-locked loop circuit operates in a phase-locked state; after the configuration information transmission is completed, the phase-locked loop circuit operates in a voltage-locked state.

14. The data interaction method for a chip system according to claim 10, characterized in that, After the chip sends the external clock, the configuration information is sent after a set time.

15. The data interaction method for a chip system according to claim 10, characterized in that, After the master chip receives the start-of-frame field sent by the slave chip, the master chip switches from receive mode to send mode, and at this time, the slave chip switches from send mode to receive mode; after the slave chip receives the end-of-frame field sent by the master chip, the slave chip switches from receive mode to send mode, and at this time, the master chip switches from send mode to receive mode.

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