Semiconductor structure and method of forming the same
By constructing a DRAM with a three-dimensional array structure, using horizontal capacitors and vertical bit lines, the problems of low semiconductor structure integration and storage density are solved, achieving higher storage capacity and smaller structure size.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-05-30
- Publication Date
- 2026-07-03
AI Technical Summary
Existing semiconductor structures such as DRAM have low storage density and integration, making it difficult to meet the storage capacity requirements of different fields.
A three-dimensional array structure is constructed by forming stacked layers on the top surface of the substrate, including multiple semiconductor layers spaced apart along directions perpendicular to and parallel to the substrate. Horizontal word lines and vertical bit lines are formed in the transistor region, and horizontal capacitors are formed in the capacitor region, thereby enabling transistors to share bit lines.
This improves the integration and storage density of semiconductor structures, increases storage capacity, simplifies manufacturing processes, and reduces the size of semiconductor structures.
Smart Images
Figure CN117222223B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology
[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor device in computers and other electronic devices. It consists of multiple memory cells, each of which typically includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor. The word line voltage on the word line can control the transistor to turn on and off, thereby allowing data information stored in the capacitor to be read or written to the capacitor via the bit line.
[0003] DRAM and other semiconductor structures mostly adopt two-dimensional structures, which results in low storage density and integration, making it difficult to meet the semiconductor storage capacity requirements of different fields.
[0004] Therefore, how to improve the integration level of semiconductor structures, thereby improving their performance, is a technical problem that urgently needs to be solved. Summary of the Invention
[0005] This disclosure provides semiconductor structures and methods for forming the same in some embodiments, which are used to solve the problem of low integration of semiconductor structures, so as to improve the performance of semiconductor structures and expand the application fields of semiconductor structures.
[0006] According to some embodiments, this disclosure provides a method for forming a semiconductor structure, including the following steps:
[0007] A stacked layer is formed on the top surface of a substrate. The stacked layer includes a plurality of semiconductor layers spaced apart along a first direction. The stacked layer includes a transistor region and a capacitor region and a bit line region distributed on opposite sides of the transistor region along a second direction. The semiconductor layer includes semiconductor pillars spaced apart along a third direction. The first direction is perpendicular to the top surface of the substrate. The second direction and the third direction are both parallel to the top surface of the substrate, and the second direction intersects the third direction.
[0008] A capacitor extending along the second direction is formed within the capacitor region;
[0009] A word line is formed in the transistor region, the word line extending along the third direction and continuously covering the semiconductor pillars spaced apart along the third direction;
[0010] A bit line is formed within the bit line region, the bit line extending along the first direction and being electrically connected to the semiconductor pillars arranged at intervals along the first direction.
[0011] In some embodiments, the specific steps of forming the stacked layer on the top surface of the substrate include:
[0012] Semiconductor layers and a first sacrificial layer are alternately deposited on the top surface of the substrate along the first direction to form the stacked layer;
[0013] The stacked layers are etched to form a first trench that exposes the substrate, the first trench dividing the semiconductor layers into semiconductor pillars spaced apart along the third direction.
[0014] In some embodiments, the semiconductor pillar includes a conductive pillar located in the capacitance region; the specific steps of forming a capacitor extending along the second direction in the capacitance region include:
[0015] Remove the first sacrificial layer in the capacitor region to form a first gap between two adjacent semiconductor layers in the capacitor region;
[0016] A conductive layer covering the conductive pillar, a dielectric layer covering the conductive layer, an upper electrode layer covering the dielectric layer, and a common electrode layer covering the upper electrode layer are formed within the first gap, thereby forming a capacitor including the conductive pillar, the conductive layer, the dielectric layer, the upper electrode layer, and the common electrode layer.
[0017] In some embodiments, the specific steps for forming a capacitor including the conductive pillar, the conductive layer, the dielectric layer, the upper electrode layer, and the common electrode layer include:
[0018] A conductive layer is formed that continuously covers the inner wall of the first gaps that are spaced apart along the first direction.
[0019] A dielectric layer is formed covering the surface of the conductive layer;
[0020] An upper electrode layer is formed covering the surface of the dielectric layer;
[0021] A common electrode layer is formed covering the surface of the upper electrode layer;
[0022] The conductive layer, dielectric layer, upper electrode layer, and common electrode layer on the sidewall of the first sacrificial layer covering the transistor region are removed, and a first opening is formed between two adjacent semiconductor layers in the capacitor region. The conductive pillar and the conductive layer, dielectric layer, upper electrode layer, and common electrode layer remaining in the first gap form the capacitor.
[0023] In some embodiments, the semiconductor pillar includes an active pillar located in the transistor region. The active pillar includes a channel region and a source region and a drain region distributed on opposite sides of the channel region along the second direction. The drain region is adjacent to the capacitor region, and the source region is adjacent to the bit line region. The specific steps for forming a word line in the transistor region include:
[0024] Remove the first sacrificial layer in the transistor region and the stacked layer in the bit line region, form a second void in the transistor region that at least exposes the channel region, and form a second trench in the bit line region that exposes the substrate;
[0025] The word lines are formed within the second gap, extending along the third direction and continuously covering the channel area that is spaced apart along the third direction.
[0026] In some embodiments, the specific steps of forming a second gap in the transistor region that at least exposes the channel region and forming a second trench in the bit line region that exposes the substrate include:
[0027] A capacitor isolation layer is formed that fills the first opening;
[0028] Remove the stacked layer in the bit line region and form a second trench in the bit line region to expose the substrate;
[0029] The first sacrificial layer of the transistor region is removed along the second trench, and a second gap is formed between two adjacent semiconductor layers in the transistor region to expose the channel region, the drain region, and the source region.
[0030] In some embodiments, the bottom of the second trench exposes the top surface of the substrate; or,
[0031] The second trench extends into the interior of the substrate.
[0032] In some embodiments, the stacked layer includes two transistor regions distributed along the second direction on opposite sides of a bit line region, and the side of each transistor region facing away from the bit line region has a capacitor region; the specific steps of removing the first sacrificial layer of the transistor region along the second trench include:
[0033] The first sacrificial layer of both transistor regions is removed simultaneously along the second trench.
[0034] In some embodiments, the specific steps of forming the word lines extending along the third direction and continuously covering the channel regions spaced apart along the third direction within the second gap include:
[0035] An initial word line layer is formed to cover the inner wall of the second gap and the inner wall of the second groove, the initial word line layer continuously covering the active columns spaced apart along the third direction;
[0036] An isolation layer is formed that covers the surface of the initial word line layer and fills the second gap and the second trench;
[0037] Remove the initial word line layer and the isolation layer inside the second trench, above the source region, and above the drain region to form a second opening between two adjacent drain regions and a third opening between two adjacent source regions. The initial word line layer remaining above the channel region serves as the word line, and the isolation layer remaining between two adjacent word lines serves as the word line isolation layer.
[0038] In some embodiments, the stacked layer includes the semiconductor layer and the first sacrificial layer alternately stacked along the first direction, the semiconductor pillar includes an active pillar located in the transistor region, and the active pillar includes a channel region;
[0039] The thickness of the first sacrificial layer in the first direction is greater than four times the gap width between two adjacent channel regions in the third direction of the semiconductor layer.
[0040] In some embodiments, the specific steps of forming an initial word line layer covering the inner wall of the second gap and the inner wall of the second groove include:
[0041] An initial word line layer covering the inner wall of the second void and the inner wall of the second trench is formed using a lateral atomic layer deposition process.
[0042] In some embodiments, before forming a bit line in the bit line region, the following steps are further included:
[0043] Remove the capacitor isolation layer;
[0044] A dielectric layer is formed that fills the first opening, the second opening, the third opening, and the second trench;
[0045] Remove the dielectric layer within the second trench.
[0046] In some embodiments, the specific steps of forming the word lines extending along the third direction and continuously covering the channel regions spaced apart along the third direction within the second gap include:
[0047] A gate material is deposited along the second trench on the inner wall of the second gap and the inner wall of the second trench to form an initial gate layer covering the active pillar. Two adjacent initial gate layers along the third direction are independent of each other.
[0048] Initial word line material is deposited along the second trench to form an initial word line layer covering the surface of the initial gate layer, wherein the initial word line layer continuously covers at least the active pillars spaced apart along the third direction;
[0049] An isolation layer is formed that covers the surface of the initial word line layer and fills the second gap and the second trench;
[0050] The initial gate layer, the initial word line layer, and the isolation layer are removed from the second trench, above the source region, and above the drain region to form a second opening between two adjacent drain regions and a third opening between two adjacent source regions. The initial gate layer remaining above the channel region serves as the gate layer, the initial word line layer remaining above the gate layer and between two adjacent gate layers along the third direction serves as the word line, and the isolation layer remaining between two adjacent word lines serves as the word line isolation layer.
[0051] In some embodiments, the semiconductor layer is made of silicon material including doped ions.
[0052] According to other embodiments, this disclosure also provides a semiconductor structure formed using the semiconductor structure formation method described in any of the preceding embodiments.
[0053] The semiconductor structure and its formation method disclosed herein involve forming a stacked layer on the top surface of a substrate, wherein the stacked layer includes multiple semiconductor layers spaced apart along a direction perpendicular to the top surface of the substrate, and each semiconductor layer includes multiple semiconductor pillars spaced apart along a direction parallel to the top surface of the substrate. This results in a three-dimensional array of semiconductor pillars in the stacked layer. Subsequently, by forming horizontal capacitors, horizontal word lines, and vertical bit lines, the traditional two-dimensional semiconductor structure is transformed into a three-dimensional semiconductor structure. This improves the integration density of the semiconductor structure, increases its storage density, and enhances its performance. Furthermore, this disclosure enables two transistors to share a single bit line, thereby helping to further reduce the size of the semiconductor structure and increase its storage capacity. Attached Figure Description
[0054] Appendix Figure 1 This is a flowchart of a method for forming a semiconductor structure according to a specific embodiment of this disclosure;
[0055] Appendix Figure 2-23 This is a schematic diagram of the main process structure in the formation of the semiconductor structure according to the specific embodiments of this disclosure. Detailed Implementation
[0056] The specific embodiments of the semiconductor structure and its formation method provided in this disclosure will be described in detail below with reference to the accompanying drawings.
[0057] This specific embodiment provides a method for forming a semiconductor structure, with appended... Figure 1 This is a flowchart illustrating the method for forming a semiconductor structure according to a specific embodiment of this disclosure, with appended... Figure 2-23 This is a schematic diagram of the main process structure during the formation of the semiconductor structure in a specific embodiment of this disclosure. The semiconductor structure described in this embodiment can be, but is not limited to, DRAM. For example... Figures 1-23 As shown, the method for forming the semiconductor structure includes the following steps:
[0058] Step S11: A stacked layer 21 is formed on the top surface of the substrate 20. The stacked layer 21 includes a plurality of semiconductor layers 212 spaced apart along a first direction D1. The stacked layer 21 includes a transistor region and a capacitor region and a bit line region distributed on opposite sides of the transistor region along a second direction D2. The semiconductor layers 212 include semiconductor pillars 26 spaced apart along a third direction D3. The first direction D1 is perpendicular to the top surface of the substrate 20, and the second direction D2 and the third direction D3 are both parallel to the top surface of the substrate 20. The second direction D2 intersects the third direction D3. Figure 5 As shown, where, Figure 5 (a) in the diagram is a top view of the structure. Figure 5 (b) in the middle is Figure 5 (a) is a cross-sectional view at position AA.
[0059] Specifically, the substrate 20 may be, but is not limited to, a silicon substrate. This specific embodiment uses a silicon substrate as an example for illustration. In other examples, the substrate 20 may be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. The substrate 20 is used to support the semiconductor device placed on it. The top surface of the substrate 20 refers to the surface of the substrate 20 used to form the stacked layer 21.
[0060] In some embodiments, the specific steps of forming the stacked layer 21 on the top surface of the substrate 20 include:
[0061] Semiconductor layers 212 and first sacrificial layers 211 are alternately deposited along the first direction D1 on the top surface of the substrate 20 to form the stacked layer 21, as follows. Figure 2 As shown, where, Figure 2 (a) in the diagram is a top view of the structure. Figure 2 (b) in the middle is Figure 2 (a) is a cross-sectional view at position AA.
[0062] The stacked layer 21 is etched to form a first trench 25 exposing the substrate 20. The first trench 25 divides the semiconductor layer 212 into semiconductor pillars 26 spaced apart along the third direction D3, such as... Figure 5 As shown.
[0063] Specifically, the first sacrificial layer 211 and the semiconductor layer 212 can be alternately formed along the first direction D1 on the top surface of the substrate 20 using epitaxial growth to form the stacked layer 21, such as... Figure 2 As shown. The specific number of alternating layers of the first sacrificial layer 211 and the semiconductor layer 212 in the stacked layer 21 can be selected by those skilled in the art according to actual needs. The more alternating layers of the first sacrificial layer 211 and the semiconductor layer 212 in the stacked layer 21, the larger the storage capacity of the formed semiconductor structure. In some embodiments, the material of the semiconductor layer 212 is silicon material including doped ions, and the material of the first sacrificial layer 211 is silicon germanide. The doped ions can be, but are not limited to, phosphorus ions. By using silicon material including doped ions to form the semiconductor layer 212, subsequent doping is not required when forming the channel region, source region, and drain region in the transistor, thereby simplifying the semiconductor structure formation process. The silicon material including doped ions and the silicon germanide material have a high etching selectivity ratio, which facilitates the selective removal of the first sacrificial layer 211 without damaging the semiconductor layer 212.
[0064] Then, a second sacrificial layer is deposited on the top surface of the stacked layer 21. The second sacrificial layer can be a single-layer structure or a multi-layer structure. In one embodiment, the second sacrificial layer includes a first padding layer 22 covering the top surface of the stacked layer 21, and a second padding layer 23 located on the top surface of the first padding layer 22, such as... Figure 3 As shown, where, Figure 3 (a) in the diagram is a top view of the structure. Figure 3 (b) in the middle is Figure 3 (a) is a cross-sectional schematic diagram at position AA. The material of the first padding layer 22 can be, but is not limited to, an oxide material (e.g., silicon dioxide), and the material of the second padding layer 23 can be, but is not limited to, a nitride material (e.g., silicon nitride). In this specific embodiment, "multiple" refers to two or more.
[0065] A patterned first photoresist layer 24 is formed on the surface of the second pad layer 23, and the first photoresist layer 24 has a first etched window 241 exposing the second pad layer 23, such as... Figure 4 As shown, where, Figure 4 (a) in the diagram is a top view of the structure. Figure 4(b) in the middle is Figure 4 (a) is a cross-sectional view at position AA. The second pad layer 23, the first pad layer 22, and the stacked layer 21 are etched downwards along the first etching window 241 to form a plurality of first trenches 25 exposing the substrate 20. The plurality of first trenches 25 are spaced apart along the third direction D3, thereby dividing each semiconductor layer 212 into a plurality of semiconductor pillars 26 spaced apart along the third direction D3, and dividing each first sacrificial layer 211 into a plurality of sacrificial pillars 27 spaced apart along the third direction D3, as shown. Figure 5 As shown. The first pad layer 22 and the second pad layer 23 are used to improve the morphology of the first trench and to prevent the process of patterning the first photoresist layer 24 from damaging the top semiconductor layer 212 of the stacked layer 21.
[0066] Step S12, a capacitor extending along the second direction D2 is formed within the capacitor region, such as... Figure 12 As shown, where, Figure 12 (a) in the diagram is a top view of the structure. Figure 12 (b) in Figure 12 is a cross-sectional view of (a) at position AA.
[0067] In some embodiments, the semiconductor pillar 26 includes a conductive pillar 261 located in the capacitor region; the specific steps of forming a capacitor extending along the second direction D2 in the capacitor region include:
[0068] The first sacrificial layer 211 in the capacitor region is removed to form a first gap 29 between two adjacent semiconductor layers 212 in the capacitor region, such as... Figure 8 As shown, where, Figure 8 (a) in the diagram is a top view of the structure. Figure 8 (b) in the middle is Figure 8 (a) is a cross-sectional view at position AA.
[0069] A conductive layer 301 covering the conductive pillar 261, a dielectric layer 302 covering the conductive layer 301, an upper electrode layer 303 covering the dielectric layer 302, and a common electrode layer 304 covering the upper electrode layer 303 are formed within the first gap 29, thereby forming a capacitor including the conductive pillar 261, the conductive layer 301, the dielectric layer 302, the upper electrode layer 303, and the common electrode layer 304.
[0070] In some embodiments, the specific steps for forming a capacitor including the conductive pillar 261, the conductive layer 301, the dielectric layer 302, the upper electrode layer 303, and the common electrode layer 304 include:
[0071] A conductive layer 301 is formed to continuously cover the inner wall of the first gaps 29 that are spaced apart along the first direction D1.
[0072] A dielectric layer 302 is formed covering the surface of the conductive 301;
[0073] An upper electrode layer 303 is formed covering the surface of the dielectric layer 302, such as... Figure 9 As shown, in Figure 9(a), it is a top view of the structure. Figure 9 (b) in the middle is Figure 9 (a) is a cross-sectional view at position AA.
[0074] A common electrode layer 304 is formed covering the surface of the upper electrode layer 303, such as... Figure 10 As shown, where, Figure 10 (a) in the diagram is a top view of the structure. Figure 10 (b) in the middle is Figure 10 (a) is a cross-sectional view at position AA;
[0075] The conductive layer 301, dielectric layer 302, upper electrode layer 303, and common electrode layer 304 are removed from the sidewall of the first sacrificial layer 211 covering the transistor region. A first opening 31 is formed between two adjacent semiconductor layers 212 in the capacitor region. The conductive pillar 261, and the remaining conductive layer 301, dielectric layer 302, upper electrode layer 303, and common electrode layer 304 in the first gap 29 form the capacitor. Figure 12 As shown.
[0076] Specifically, a third sacrificial layer 28 is formed on the surface of the second liner layer 23, such as Figure 6 As shown, where, Figure 6 (a) in the diagram is a top view of the structure. Figure 6 (b) in the middle is Figure 6 (a) is a cross-sectional schematic diagram at position AA. The material of the third sacrificial layer 28 may be, but is not limited to, an oxide material (e.g., silicon dioxide). Next, a patterned second photoresist layer is formed on the surface of the third sacrificial layer 28, the second photoresist layer having a second etch window exposing the third sacrificial layer 28. The third sacrificial layer 28 is etched downward along the second etch window to expose the second pad layer 23 above the transistor region, as shown. Figure 7 As shown, where, Figure 7(a) in the diagram is a top view of the structure. Figure 7 (b) in the middle is Figure 7 (a) is a cross-sectional view at position AA. The remaining third sacrificial layer 28 covers the stacked layer 21 of the transistor region and the bit line region. Then, the first sacrificial layer 211 of the capacitor region can be removed using a lateral etching process, forming a first gap 29 between two adjacent semiconductor layers 212 within the capacitor region, as shown in Figure 28. Figure 8 As shown. Using a lateral etching process to form the first gap 29 simplifies the manufacturing process of the semiconductor structure and avoids damage to the stacked layer 21 of the transistor region and the bit line region.
[0077] A conductive layer 301 is formed by continuously depositing conductive materials such as tungsten or TiN onto the inner walls of a plurality of first voids 29 spaced apart along the first direction D1 using a lateral atomic layer deposition process, thereby continuously covering the surfaces of the plurality of conductive pillars 261 spaced apart along the first direction D1. Next, a material with a high dielectric constant (HK) is deposited onto the surface of the conductive layer 301 to form the dielectric layer 302. A conductive material such as tungsten or TiN is then deposited onto the surface of the dielectric layer 302 to form the upper electrode layer 303, as shown below. Figure 9 As shown. A conductive material such as polycrystalline silicon is deposited within the first void 29 to form the common electrode layer 304, which covers the upper electrode layer 303 and fills the first void 29, as shown. Figure 10 As shown. After removing the first pad layer 22, the second pad layer 23, the third sacrificial layer 28, the conductive layer 301, the dielectric layer 302, the upper electrode layer 303, and the common electrode layer 304 from the top surface of the stacked layer 21, the following is obtained: Figure 11 The structure shown, wherein, Figure 11 (a) in the diagram is a top view of the structure. Figure 11 (b) in the middle is Figure 11 (a) is a cross-sectional view at position AA.
[0078] Subsequently, a patterned third photoresist layer is formed above the stacked layer 21, and the third photoresist layer has a third etching window that exposes portions of the conductive layer 301, the dielectric layer 302, the upper electrode layer 303, and the common electrode layer 304. The conductive layer 301, the dielectric layer 302, the upper electrode layer 303, and the common electrode layer 304 are etched downwards along the third etching window, removing the conductive layer 301, the dielectric layer 302, the upper electrode layer 303, and the common electrode layer 304 covering the sidewalls of the first sacrificial layer 211 in the transistor region. A first opening 31 is formed between two adjacent semiconductor layers 212 in the capacitor region. The conductive pillar 261 and the remaining conductive layer 301, the dielectric layer 302, the upper electrode layer 303, and the common electrode layer 304 in the first gap 29 form the capacitor. Figure 12 As shown. The conductive pillar 261 and the conductive layer 301 together serve as the lower electrode layer of the capacitor. An insulating dielectric material such as oxide is deposited within the first opening 31 to form a capacitor isolation layer 32, such as... Figure 13 As shown, Figure 13(a) is a top view of the structure. Figure 13 (b) in the middle is Figure 13 (a) is a cross-sectional view at position AA.
[0079] In this specific embodiment, by making the length of the first gap 29 along the second direction D2 greater than the length of the capacitor along the second direction D2, it is easier to form the capacitor isolation layer 32 to isolate the capacitor and the transistor region, and avoid damage to the already formed capacitor caused by the subsequent word line forming process.
[0080] Step S13: A word line 40 is formed in the transistor region. The word line 40 extends along the third direction D3 and continuously covers the semiconductor pillars 26 spaced apart along the third direction D3, as shown below. Figure 18 As shown, where, Figure 18 (a) in the diagram is a top view of the structure. Figure 18 (b) in Figure 18 is a cross-sectional view of (a) at position AA. Figure 18 (c) in the middle is Figure 18 (a) is a cross-sectional view at position BB.
[0081] In some embodiments, the semiconductor pillar 26 includes an active pillar 36 located in the transistor region (see...). Figure 18The active pillar 36 includes a channel region and a source region and a drain region distributed on opposite sides of the channel region along the second direction D2. The drain region is adjacent to the capacitor region, and the source region is adjacent to the bit line region. The specific steps for forming the word line 40 in the transistor region include:
[0082] The first sacrificial layer 211 in the transistor region and the stacked layer 21 in the bit line region are removed, and a second gap 35 is formed in the transistor region to at least expose the channel region, and a second trench 34 is formed in the bit line region to expose the substrate 20. Figure 15 As shown, Figure 15(a) is a top view of the structure. Figure 15 (b) in the middle is Figure 15 (a) is a cross-sectional view at position AA.
[0083] Within the second gap 35, word lines 40 are formed extending along the third direction D3 and continuously covering the channel area spaced apart along the third direction D3, such as... Figure 18 As shown.
[0084] In some embodiments, the specific steps of forming a second gap 35 in the transistor region that at least exposes the channel region and forming a second trench 34 in the bit line region that exposes the substrate include:
[0085] A capacitor isolation layer 32 is formed that fills the first opening 31;
[0086] Remove the stacked layer 21 in the bit line region and form a second trench 34 in the bit line region to expose the substrate 20, such as Figure 14 As shown, where, Figure 14 (a) in the diagram is a top view of the structure. Figure 14 (b) in the middle is Figure 14 (a) is a cross-sectional view at position AA.
[0087] The first sacrificial layer 211 of the transistor region is removed along the second trench 34, and a second gap 35 is formed between two adjacent semiconductor layers 212 within the transistor region, exposing the channel region, the drain region, and the source region. Figure 15 As shown.
[0088] In some embodiments, the bottom of the second trench 34 exposes the top surface of the substrate 20, that is, the substrate 20 is used as an etching stop layer during the etching process, thereby accurately controlling the etching endpoint and avoiding damage to the substrate 20.
[0089] In other embodiments, the second trench 34 extends into the interior of the substrate 20 to increase the contact area between the bit line subsequently formed in the second trench 34 and the substrate 20.
[0090] In some embodiments, the stacked layer 21 includes two transistor regions distributed along the second direction D2 on opposite sides of a bit line region, and the side of the transistor region facing away from the bit line region has a capacitor region; the specific steps of removing the first sacrificial layer 211 of the transistor region along the second trench 34 include:
[0091] The first sacrificial layer 211 of both transistor regions is removed simultaneously along the second trench 34.
[0092] Specifically, by setting a bit line region in the stacked layer 21, and setting a transistor region on each side of the bit line region along the second direction D2, and setting a capacitor region on the side of each transistor region away from the bit line region, it is possible for two transistors formed subsequently to share a bit line, thereby further reducing the volume of the semiconductor structure and improving the integration of the semiconductor structure.
[0093] In some embodiments, the specific steps of forming the word lines 40 extending along the third direction D3 and continuously covering the channel regions spaced apart along the third direction D3 within the second gap 35 include:
[0094] An initial word line layer 37 is formed, covering the inner wall of the second gap 35 and the inner wall of the second groove 34. This initial word line layer 37 continuously covers at least the active pillars 36 spaced apart along the third direction D3. Figure 16 As shown, where, Figure 16 (a) in the diagram is a top view of the structure. Figure 16 (b) in the middle is Figure 16 (a) is a cross-sectional view at position AA. Figure 16 (d) in the middle is Figure 16 Enlarged view within the dashed box in (c) of the diagram;
[0095] An isolation layer 39 is formed, covering the surface of the initial word line layer 37 and filling the second gap 35 and the second trench 34, as shown. Figure 17 As shown, where, Figure 17 (a) in the diagram is a top view of the structure. Figure 17 (b) in the middle is Figure 17 (a) is a cross-sectional view at position AA.
[0096] The initial word line layer 37 and the isolation layer 39 are removed from the second trench 34, above the source region, and above the drain region, forming a second opening between two adjacent drain regions and a third opening between two adjacent source regions. The initial word line layer 37 remaining above the channel region serves as the word line 40, and the isolation layer 39 remaining between two adjacent word lines 40 serves as the word line isolation layer 41. Figure 18 As shown.
[0097] In some embodiments, the specific steps of forming an initial letter line layer 37 covering the inner wall of the second gap 35 and the inner wall of the second groove 34 include:
[0098] An initial word line layer 37 is formed by using a lateral atomic layer deposition process to cover the inner wall of the second void 35 and the inner wall of the second trench 34.
[0099] Specifically, after forming the second gap 35, an in-situ water vapor oxidation or lateral deposition process can be used to form a gate dielectric layer 38 covering the surface of the active pillar 36, such as... Figure 16 As shown. Next, a lateral atomic layer deposition process is used to deposit conductive materials such as tungsten or TiN onto the surface of the gate dielectric layer 38, forming an initial word line layer 37 covering the inner walls of the second void 35 and the second trench 34. The lateral deposition process ensures that the initial word line layer 37 fully covers the inner walls of the second void 35, thereby further improving the electrical performance of the semiconductor structure.
[0100] In some embodiments, the stacked layer 21 includes the semiconductor layer 212 and the first sacrificial layer 211 alternately stacked along the first direction D1, and the semiconductor pillar 26 includes an active pillar 36 located in the transistor region, the active pillar 36 including a channel region;
[0101] The thickness A of the first sacrificial layer 211 in the first direction D1 is greater than 4 times the gap width B between two adjacent channel regions in the semiconductor layer 212 along the third direction D3, i.e., A > 4B.
[0102] Specifically, by setting the thickness A of the first sacrificial layer 211 in the first direction D1 to be greater than 4 times the gap width B between two adjacent channel regions in the semiconductor layer 212 along the third direction D3, the word line material is first connected into a line along the third direction D3 when depositing the word line material for forming the initial word line layer 37. This ensures that the final word line 40 extends along the third direction D3 and can fully and completely continuously cover all the channel regions in the semiconductor layer 212 that are spaced apart along the third direction D3.
[0103] In other embodiments, the specific steps of forming the word lines 40 within the second gap 35 that extend along the third direction D3 and continuously cover the channel regions spaced apart along the third direction D3 include:
[0104] Gate material is deposited along the second trench 34 on the inner wall of the second gap 35 and the inner wall of the second trench 34 to form an initial gate layer 50 covering the active pillar 36. Two adjacent initial gate layers 50 along the third direction D3 are independent of each other. Figure 22 As shown, where, Figure 22 (c) in the diagram is a schematic diagram of the cross-sectional structure. Figure 22 (d) in the middle is Figure 22 Enlarged view within the dashed box (c) in the diagram;
[0105] Initial word line material is deposited along the second trench 34 to form an initial word line layer 37 covering the surface of the initial gate layer 50. The initial word line layer 37 at least continuously covers the active pillars 36 spaced apart along the third direction D3. Figure 23 As shown, where, Figure 23 (c) in the diagram is a schematic diagram of the cross-sectional structure. Figure 23 (d) in the middle is Figure 23 Enlarged view within the dashed box (c) in the diagram;
[0106] An isolation layer is formed that covers the surface of the initial word line layer 37 and fills the second gap 35 and the second trench 34;
[0107] The initial gate layer 50, the initial word line layer 37, and the isolation layer are removed from the second trench 34, above the source region, and above the drain region to form a second opening between two adjacent drain regions and a third opening between two adjacent source regions. The initial gate layer 50 remaining above the channel region serves as the gate layer, the initial word line layer 37 remaining above the gate layer and between two adjacent gate layers along the third direction D3 serves as the word line, and the isolation layer remaining between two adjacent word lines serves as the word line isolation layer.
[0108] Specifically, after forming the second trench 34 and the second gap 35, an in-situ water vapor oxidation or lateral deposition process can be used to form a gate dielectric layer covering the surface of the active pillar 36. Then, a conductive material such as TiN is deposited on the surface of the gate dielectric layer using a lateral atomic layer deposition process to form the initial gate layer 50 located above the gate dielectric layer. Multiple initial gate layers 50 are located above multiple channel regions, and any two adjacent initial gate layers 50 are independent of each other. Next, a conductive material such as tungsten is deposited on the surface of the initial gate layer 50 using a lateral atomic layer deposition process to form the initial word line layer 37, which at least continuously covers the active pillars 36 spaced along the third direction D3. By forming the initial gate layer 50 first, on the one hand, it can be further ensured that the subsequently formed initial word line layer 37 can fully and continuously cover the channel regions spaced along the third direction D3; on the other hand, it can also enhance the adhesion between the initial word line layer 37 and the initial gate layer 50.
[0109] Step S14: A bit line 44 is formed in the bit line region. The bit line 44 extends along the first direction D1 and is electrically connected to the semiconductor pillars 26 arranged at intervals along the first direction D1. Figure 21 As shown, where, Figure 21 (a) in the diagram is a top view of the structure. Figure 21 (b) in the middle is Figure 21 (a) is a cross-sectional view at position AA.
[0110] In some embodiments, before forming a bit line in the bit line region, the following steps are further included:
[0111] Remove the capacitor isolation layer 32, such as Figure 19 As shown, where, Figure 19 (a) in the diagram is a top view of the structure. Figure 19 (b) in the middle is Figure 19 (a) is a cross-sectional view at position AA.
[0112] A dielectric layer 43 is formed that fills the first opening 31, the second opening, the third opening, and the second trench 34, as shown below. Figure 20 As shown, where, Figure 20 (a) in the diagram is a top view of the structure. Figure 20 (b) in the middle is Figure 20 (a) is a cross-sectional view at position AA.
[0113] Remove the dielectric layer 43 within the second trench 34.
[0114] Specifically, after removing the dielectric layer 43 in the second trench 37, a conductive material such as tungsten can be deposited in the second trench 37 to form a bit line 44 that extends along the first direction D1 and is electrically connected to the source regions in the semiconductor pillars 26 that are spaced apart along the first direction D1. One bit line 44 is simultaneously electrically connected to two source regions located on opposite sides of the bit line 44 along the second direction D2.
[0115] This specific embodiment also provides a semiconductor structure, which can be adopted as shown in Figure 1- Figure 23 The semiconductor structure is formed by the method described above. A schematic diagram of the semiconductor structure provided in this specific embodiment can be found in [reference needed]. Figure 21 .
[0116] The semiconductor structure and its formation method provided in this specific embodiment form a stacked layer on the top surface of a substrate. The stacked layer includes multiple semiconductor layers spaced apart along a direction perpendicular to the top surface of the substrate, and each semiconductor layer includes multiple semiconductor pillars spaced apart along a direction parallel to the top surface of the substrate. This results in a three-dimensional array of semiconductor pillars in the stacked layer. Subsequently, by forming horizontal capacitors, horizontal word lines, and vertical bit lines, the traditional two-dimensional semiconductor structure is transformed into a three-dimensional semiconductor structure. This improves the integration density of the semiconductor structure, increases its storage density, and enhances its performance. Furthermore, this specific embodiment allows two transistors to share a single bit line, which helps to further reduce the size of the semiconductor structure and increase its storage capacity.
[0117] The above description is only a preferred embodiment of this disclosure. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principles of this disclosure, and these improvements and modifications should also be considered within the scope of protection of this disclosure.
Claims
1. A method for forming a semiconductor structure, characterized in that, Includes the following steps: A stacked layer is formed on the top surface of a substrate. The stacked layer includes a plurality of semiconductor layers spaced apart along a first direction. The stacked layer includes a transistor region and a capacitor region and a bit line region distributed on opposite sides of the transistor region along a second direction. The semiconductor layer includes semiconductor pillars spaced apart along a third direction. The first direction is perpendicular to the top surface of the substrate. The second direction and the third direction are both parallel to the top surface of the substrate, and the second direction intersects the third direction. The stacked layer includes the semiconductor layer and the first sacrificial layer that are alternately stacked along the first direction, and the semiconductor pillar includes an active pillar located in the transistor region, the active pillar including a channel region; The thickness of the first sacrificial layer in the first direction is greater than four times the gap width between two adjacent channel regions in the third direction of the semiconductor layer; A capacitor extending along the second direction is formed within the capacitor region; A word line is formed within the transistor region, the word line extending along the third direction and continuously covering the semiconductor pillars spaced apart along the third direction; A bit line is formed within the bit line region, the bit line extending along the first direction and being electrically connected to the semiconductor pillars arranged at intervals along the first direction.
2. The method for forming a semiconductor structure according to claim 1, characterized in that, The specific steps for forming the stacked layer on the top surface of the substrate include: Semiconductor layers and a first sacrificial layer are alternately deposited on the top surface of the substrate along the first direction to form the stacked layer; The stacked layers are etched to form a first trench that exposes the substrate, the first trench dividing the semiconductor layers into semiconductor pillars spaced apart along the third direction.
3. The method for forming a semiconductor structure according to claim 2, characterized in that, The semiconductor pillar includes a conductive pillar located in the capacitor region; the specific steps of forming a capacitor extending along the second direction in the capacitor region include: Remove the first sacrificial layer in the capacitor region to form a first gap between two adjacent semiconductor layers in the capacitor region; A conductive layer covering the conductive pillar, a dielectric layer covering the conductive layer, an upper electrode layer covering the dielectric layer, and a common electrode layer covering the upper electrode layer are formed within the first gap, thereby forming a capacitor including the conductive pillar, the conductive layer, the dielectric layer, the upper electrode layer, and the common electrode layer.
4. The method for forming a semiconductor structure according to claim 3, characterized in that, The specific steps for forming a capacitor including the conductive pillar, the conductive layer, the dielectric layer, the upper electrode layer, and the common electrode layer include: A conductive layer is formed that continuously covers the inner wall of the first gaps that are spaced apart along the first direction. A dielectric layer is formed covering the surface of the conductive layer; An upper electrode layer is formed covering the surface of the dielectric layer; A common electrode layer is formed covering the surface of the upper electrode layer; The conductive layer, dielectric layer, upper electrode layer, and common electrode layer on the sidewall of the first sacrificial layer covering the transistor region are removed, and a first opening is formed between two adjacent semiconductor layers in the capacitor region. The conductive pillar and the conductive layer, dielectric layer, upper electrode layer, and common electrode layer remaining in the first gap form the capacitor.
5. The method for forming a semiconductor structure according to claim 4, characterized in that, The semiconductor pillar includes an active pillar located in the transistor region. The active pillar includes a channel region and a source region and a drain region distributed on opposite sides of the channel region along the second direction. The drain region is adjacent to the capacitor region, and the source region is adjacent to the bit line region. The specific steps for forming word lines within the transistor region include: Remove the first sacrificial layer in the transistor region and the stacked layer in the bit line region, form a second void in the transistor region that at least exposes the channel region, and form a second trench in the bit line region that exposes the substrate; The word lines are formed within the second gap, extending along the third direction and continuously covering the channel area that is spaced apart along the third direction.
6. The method for forming a semiconductor structure according to claim 5, characterized in that, The specific steps of forming a second gap in the transistor region that at least exposes the channel region and forming a second trench in the bit line region that exposes the substrate include: A capacitor isolation layer is formed that fills the first opening; Remove the stacked layer in the bit line region and form a second trench in the bit line region to expose the substrate; The first sacrificial layer of the transistor region is removed along the second trench, and a second gap is formed between two adjacent semiconductor layers in the transistor region to expose the channel region, the drain region, and the source region.
7. The method for forming a semiconductor structure according to claim 5, characterized in that, The bottom of the second trench exposes the top surface of the substrate; or, The second trench extends into the interior of the substrate.
8. The method for forming a semiconductor structure according to claim 6, characterized in that, The stacked layer includes two transistor regions distributed along the second direction on opposite sides of a bit line region, and the side of the transistor region away from the bit line region has a capacitor region; The specific steps for removing the first sacrificial layer of the transistor region along the second trench include: The first sacrificial layer of both transistor regions is removed simultaneously along the second trench.
9. The method for forming a semiconductor structure according to claim 6, characterized in that, The specific steps for forming the word lines extending along the third direction and continuously covering the channel regions spaced apart along the third direction within the second gap include: An initial word line layer is formed to cover the inner wall of the second gap and the inner wall of the second groove, the initial word line layer continuously covering the active columns spaced apart along the third direction; An isolation layer is formed that covers the surface of the initial word line layer and fills the second gap and the second trench; Remove the initial word line layer and the isolation layer inside the second trench, above the source region, and above the drain region to form a second opening between two adjacent drain regions and a third opening between two adjacent source regions. The initial word line layer remaining above the channel region serves as the word line, and the isolation layer remaining between two adjacent word lines serves as the word line isolation layer.
10. The method for forming a semiconductor structure according to claim 9, characterized in that, The specific steps for forming the initial letter line layer covering the inner wall of the second gap and the inner wall of the second groove include: An initial word line layer covering the inner wall of the second void and the inner wall of the second trench is formed using a lateral atomic layer deposition process.
11. The method for forming a semiconductor structure according to claim 9, characterized in that, Before forming a bit line within the bit line region, the following steps are also included: Remove the capacitor isolation layer; A dielectric layer is formed that fills the first opening, the second opening, the third opening, and the second trench; Remove the dielectric layer within the second trench.
12. The method for forming a semiconductor structure according to claim 6, characterized in that, The specific steps for forming the word lines extending along the third direction and continuously covering the channel regions spaced apart along the third direction within the second gap include: Gate material is deposited along the second trench on the inner wall of the second gap and the inner wall of the second trench to form an initial gate layer covering the active pillar. Two adjacent initial gate layers along the third direction are independent of each other. Initial word line material is deposited along the second trench to form an initial word line layer covering the surface of the initial gate layer, wherein the initial word line layer continuously covers at least the active pillars spaced apart along the third direction; An isolation layer is formed that covers the surface of the initial word line layer and fills the second gap and the second trench; The initial gate layer, the initial word line layer, and the isolation layer are removed from the second trench, above the source region, and above the drain region to form a second opening between two adjacent drain regions and a third opening between two adjacent source regions. The initial gate layer remaining above the channel region serves as the gate layer, the initial word line layer remaining above the gate layer and between two adjacent gate layers along the third direction serves as the word line, and the isolation layer remaining between two adjacent word lines serves as the word line isolation layer.
13. The method for forming a semiconductor structure according to claim 1, characterized in that, The semiconductor layer is made of silicon material containing doped ions.
14. A semiconductor structure, characterized in that, The semiconductor structure is formed using the method described in any one of claims 1-13.