DRAM-aware cache

Abstract

Data caching may include storing data associated with DRAM transaction requests in a data storage structure organized in a manner corresponding to the DRAM memory bank, memory bank group, and bank organization. Data may be selected for transfer to the DRAM by selecting in the data storage structure.

Description

Background Art

[0001] A computing device may include multiple subsystems that communicate with each other via a bus or other interconnections. For example, such a computing device may be a portable computing device ("PCD"), such as a laptop or PDA, a cellular phone or smart phone, a portable digital assistant, a portable game console, etc. The communication subsystem may be included in the same integrated circuit chip or in different chips. "System on chip" or "SoC" is an example of such a chip that integrates many components to provide system-level functions. For example, an SoC may include one or more types of processors, such as a central processing unit ("CPU"), a graphics processing unit ("GPU"), a digital signal processor ("DSP"), and a neural processing unit ("NPU"). The SoC may include other subsystems, such as a transceiver or "modem" that provides wireless connectivity, a main memory or system memory, one or more cache memories, etc. Some subsystems may include a processing engine that can perform memory transactions with the system memory. The system memory in PCDs and other computing devices typically includes dynamic random access memory ("DRAM").

[0002] DRAM is organized into an array of rows and columns. A row must be opened before its data can be accessed. Only one row in the array can be open at any time. To help reduce latency, DRAM can be organized into multiple banks, each of which includes an array of the type described above. The DRAM controller can initiate an access to one bank while waiting for a previous access to another bank to complete. To provide further performance benefits, banks can be organized into multiple bank groups. Additionally, DRAM can be organized into multiple ranks, each with multiple bank groups.

[0003] One of the tasks of a DRAM controller is to schedule or direct transactions between banks, groups of banks, and banks. The term "DRAM-aware" scheduling is sometimes used to describe how a DRAM controller performs such scheduling in a way that exploits the efficiencies provided by the organization of the DRAM. For example, a DRAM controller may randomize its selection of banks to access so that sequential accesses are less likely to be directed to different rows in the same bank. In addition, for example, a DRAM controller may direct as many accesses as possible to one bank before switching to another bank, because switching banks incurs a high latency penalty.

[0004] A cache memory system can be inserted into the memory transaction path between the processing engine requesting the transaction and the DRAM controller. When the cache memory is full or becomes "dirty", the cache memory controller writes back or "evicts" some dirty cache lines to the DRAM to free up space in the cache memory. The DRAM-aware scheduling techniques employed by the DRAM controller may not be sufficient to maximize efficiency in some cases. Summary of the invention

[0005] Systems, methods, computer-readable media, and other examples are disclosed for controlling data caching in a DRAM-aware manner.

[0006] An exemplary system for controlling a data cache may include a plurality of data storage structures collectively having an organization corresponding to the structural organization of a DRAM. The exemplary system may also include a cache controller system. The cache controller system may be configured to receive a plurality of transaction requests. The cache controller system may also be configured to store data associated with the transaction requests in one or more data storage structures selected from the plurality of data storage structures based on a memory address associated with each transaction request. The cache controller system may also be configured to control data transfer to the DRAM using the plurality of data storage structures.

[0007] An exemplary method for controlling a data cache may include receiving a plurality of transaction requests. The exemplary method may also include storing data associated with the transaction requests in one or more data storage structures selected from a plurality of data storage structures based on a memory address associated with each transaction request. The exemplary method may also include controlling data transfer to a DRAM using the plurality of data storage structures. The plurality of data storage structures collectively have an organization corresponding to the structural organization of the DRAM.

[0008] Another exemplary system for controlling a data cache may include means for receiving a plurality of transaction requests. The exemplary system may also include means for storing data associated with the transaction requests in one or more data storage structures selected from a plurality of data storage structures based on a memory address associated with each transaction request. The exemplary system may also include means for controlling data transfer to a DRAM using the plurality of data storage structures. The plurality of data storage structures collectively have an organization corresponding to the structural organization of the DRAM.

[0009] An exemplary computer-readable medium for controlling a data cache may include a non-transitory computer-readable medium having instructions in a computer-executable form stored thereon. The instructions, when executed by a processor, may configure the processor to receive a plurality of transaction requests. The instructions may also configure the processor to store data associated with the transaction requests in one or more data storage structures selected from a plurality of data storage structures based on a memory address associated with each transaction request. The instructions may also configure the processor to control data transfer to a DRAM using the plurality of data storage structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In the accompanying drawings, unless otherwise noted, like reference numerals refer to like parts in the various views. For reference numerals with alphabetic character designations (such as "102A" or "102B"), the alphabetic character designations may distinguish between two similar components or elements in the same figure. The alphabetic character designations of a reference numeral may be omitted when a reference numeral is intended to encompass all components having the same reference numeral in all figures.

[0011] Figure 1 is a block diagram illustrating a system for controlling data cache in a DRAM-aware manner according to an exemplary embodiment.

[0012] Figure 2 is a block diagram of a memory system including a system for controlling data caching in a DRAM-aware manner according to an exemplary embodiment.

[0013] Figure 3 is a block diagram of a system for controlling data caching in a DRAM-aware manner according to an exemplary embodiment.

[0014] Figure 4 is a block diagram of data structures and selection logic configured for controlling eviction of cache data to DRAM according to an exemplary embodiment.

[0015] Figure 5 is a flow chart of a method for controlling aspects of a data cache associated with a DRAM write transaction request according to an exemplary embodiment.

[0016] Figure 6 is a data structure diagram illustrating a linked list configured to store cache address information and page hit bits according to an exemplary embodiment.

[0017] Figure 7 According to an exemplary embodiment Figure 3 Block diagram of the tag processor.

[0018] Figure 8is a flow chart of a method for regulating cache hints in transaction requests according to an exemplary embodiment.

[0019] Fig.9A is a flow chart of a method for allocating a cache line based on a write request and storing associated information in a selected linked list queue according to an exemplary embodiment.

[0020] Fig. 9B yes Fig.9A Continuation of the flowchart.

[0021] Fig.10 is a flow chart of a method for searching a victim cache line for replacement according to an exemplary embodiment.

[0022] Fig.11 is a flow chart of a method for selecting a linked list queue from a set of linked list queues according to an exemplary embodiment.

[0023] Fig.12 is a flow chart of a method for selecting among two sets of linked list queues corresponding to two DRAM memory banks according to an exemplary embodiment.

[0024] Fig.13 is a flow chart of a method for activating and deactivating eviction of cache data using a linked list queue to maintain cache dirtiness within a window according to an exemplary embodiment.

[0025] Fig.14 is a flow chart of a method for controlling aspects of a data cache associated with a DRAM transaction request according to an exemplary embodiment.

[0026] Fig.15 is a block diagram of a portable computing device or PCD according to an exemplary embodiment. DETAILED DESCRIPTION

[0027] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." The word "illustrative" may be used synonymously with "exemplary" herein. Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0028] like Figure 1As shown, a system 100 for controlling various aspects of data caching can be provided. The system 100 can be configured to control various aspects of the cache of data associated with a memory transaction between a client device (not shown) and a DRAM (not shown). Although in the exemplary embodiments described herein, write transactions are used as examples of memory transactions, various aspects of the systems, methods, and other embodiments described herein can also be applied to other types of transactions. The system 100 may include a plurality of data storage structures 102. The plurality of data storage structures 102 may collectively have an organization corresponding to the organization of DRAM. For example, as described below, the DRAM may be organized into a repository, a repository group, a memory bank, and the like. The plurality of data storage structures 102 may have an organization corresponding to one or more of a repository organization of DRAM, a repository group organization of DRAM, a memory bank organization of DRAM, and the like.

[0029] The system 100 may also include a cache controller system 104. The cache controller system 104 may be configured to receive DRAM transaction requests from one or more client devices (not shown). The client device may be any type capable of initiating a bus transaction, such as a CPU or other processor. The transaction request may include a read transaction request and a write transaction request (also referred to herein as a read request and a write request for simplicity). Figure 1 The arrows in indicate the logic flow associated with a transaction, and more specifically, the logic flow associated with the request-related aspects of a transaction; for clarity, the response-related aspects are shown in Figure 1 There are no arrows to indicate aspects such as the return flow of data in response to a request. It should also be understood that Figure 1 The arrows in the diagram indicate logical flow in a conceptual manner and are not intended to indicate specific physical interconnections, such as specific signal lines, buses, etc. In addition, references to "indications" in this disclosure may be broadly interpreted to include any type or combination of signals, bits, commands, instructions, etc.

[0030] The transaction request may include a target memory (i.e., DRAM) address and may also include other information as described below. The cache controller system 104 may also be configured to store data associated with the transaction request in a selected one of the data storage structures 102. The data storage structure 102 in which the data is stored may be selected from the data storage structures based on information such as the target memory address associated with the transaction request. For example, in the case of a write request, the information or data stored in the selected data structure 102 may be in the form of a cache address. As described below, such a cache address may indicate a location in the payload cache ( Figure 1 ), the data that is the subject of the write request is cached in this location.

[0031] The cache controller system 104 may also be configured to control data transfer to the DRAM using the data storage structure 102. For example, as described below, data stored in the data storage structure 102 may be used to indicate the location or address of cache data to be evicted to the DRAM. The cache controller system 104 may be configured to control data transfer by selecting in the data storage structure 102 based on a sequence. The sequence may be based on, for example, a round-robin selection between the data storage structures 102. The sequence may be based on, for example, selecting between a first subset of the data storage structure 102 associated with a first bank of DRAM and a second subset of the data storage structure 102 associated with a second bank of DRAM. The sequence may be based on, for example, whether an entry in the data storage structure indicates a DRAM page hit. These aspects related to selecting in the data storage structure 102 are further described below.

[0032] like Figure 2 As shown, system 200 may include client device 202 (i.e., a processor or other processing engine), cache system 204, memory controller 206, and DRAM 208. Client device 202 may issue DRAM transaction requests, which may include read requests (i.e., requests to read data from DRAM 208), and write requests (i.e., requests to store data in DRAM 208). DRAM transaction requests may also be referred to as requests to access DRAM 208. Each DRAM transaction request may include a target address in DRAM 208, a size or amount of data to be accessed, and other information. A write request also includes data that memory controller 206 will store in DRAM 208 in response to the write request, which may be referred to as a payload.

[0033] The cache system 204 may include the system 100 ( Figure 1) features and modes of operation. The cache system 204 may also include conventional features. For example, in some aspects, the cache system 204 may operate in the manner of a conventional write-back cache, which is well known to those of ordinary skill in the art. For example, the cache memory system 204 may temporarily store or "cache" data requested to be written to the DRAM 208 in response to a write request or data read from the DRAM 208 in response to a read request. As understood by those of ordinary skill in the art, data that has been stored in the cache system 204 but has not yet been written to the DRAM 208 is generally referred to as "dirty" data. Conventionally, dirty data is periodically written to the DRAM 208, a process generally referred to as eviction or cleaning. Instead of or in addition to conventional eviction methods, the eviction-related methods described herein may be included. Cleaning the cache may also be colloquially referred to as "washing". Although not shown separately for clarity, the cache system 204 may include one or more processors (configurable by software or firmware) or other logic that can be configured to operate in the manner described herein, including according to the methods described below.

[0034] The memory controller 206 may have a conventional structure and operate in a conventional manner. For example, the memory controller 206 may convert transaction requests into DRAM commands and physical DRAM addresses, among other functions. Since the memory controller 206 and its operation are well known to those of ordinary skill in the art, these aspects of the memory controller 206 are not described herein.

[0035] DRAM 208 may have a conventional structure and operate in a conventional manner. DRAM 208 may be of any type not consistent with the description herein. For example, DRAM 208 may be a double data rate synchronous DRAM ("DDR-SDRAM"), sometimes referred to as "DDR" for brevity. As DDR technology has evolved, DDR versions such as the fourth generation low power DDR ("LPDDR4") and the fifth generation low power DDR ("LPDDR5") have been developed. DRAM 208 may be, for example, LPDDR4, LPDDR4X, LPDDR5, LPDDR5X, and the like. Although the structure and operation of DRAM 208 are fully understood by those of ordinary skill in the art, the following brief description is provided as background.

[0036] DRAM 208 may include two memory banks 210, which may be referred to as Rank_0 and Rank_1. Since the two memory banks 210 are identical to each other, the following description applies to each memory bank 210. Memory bank 210 includes two or more ("M") memory banks 212, which may be referred to as Bank_0 through Bank_M-1. Each memory bank 212 is organized as a two-dimensional array 213 of cells or storage locations, where a storage location in array 213 is accessed by selecting a row and a column. Exemplary rows and exemplary columns are shown in FIG. Figure 2 The cross-hatching in the figure is highlighted for illustration purposes. In addition, although not shown in the figure for clarity, Figure 2 2, but DRAM 208 may be further organized into memory bank groups. For example, each memory bank 210 may be composed of four memory bank groups (not shown), and each of these memory bank groups may include four memory banks. In such an embodiment, DRAM 208 is therefore composed of 32 different (i.e., individually addressable) memory banks 212. Although in the exemplary embodiment described herein, DRAM 208 has two memory banks 210, each memory bank 210 has four memory bank groups, and each of the four memory bank groups has four memory banks 212, in other embodiments, such DRAM may be organized in any other manner, including more or fewer memory banks, memory banks, memory bank groups, etc. than in the exemplary embodiment.

[0037] The physical address used by the memory controller 206 to access the DRAM 208 may include a row address, a column address, a bank group address, and a bank address. In addition, although not shown for the purpose of clarity, in response to a bank address provided by the memory controller 206 (e.g., a chip select bit included in a read or write command), the bank address decoding logic may select one of the banks 210. Although also not shown for the purpose of clarity, in response to a bank address provided by the memory controller 206, the bank address decoding logic may select one of the banks 212 in the selected bank group of the selected bank 210. In response to a row address provided by the memory controller 206, the row address decoder 214 may select one of the rows of the selected bank 212 of the selected bank group in the selected bank 210. Similarly, in response to a column address provided by the memory controller 206, the column address decoder 216 may select one of the columns of the selected bank 212 of the selected bank group in the selected bank 210.

[0038] Each memory bank 210 may have a read latch 218 for buffering read data and a write latch 220 for buffering write data. Each memory bank 210 may also have input / output ("I / O") logic 222 that is configured to direct read and write data from and to selected memory locations.

[0039] Each memory bank 212 may have a row buffer 224. The row buffer 224 stores the contents of a selected row (also referred to as a "page"). A row must be selected or "opened" before it can be written to or read from. Once a row is opened, the DRAM 208 can read from or write to any number of columns in the row buffer 224 in response to a read or write command. Following a read or write command, data is transferred serially between the memory controller 206 and the DRAM 208 in units called "bursts," which may be eight bits per data signal line, for example. After writing to or reading from the row buffer 224, the row must be restored or "closed."

[0040] A read or write transaction to an opened row is called a "page hit". A read or write transaction to a row that is not opened (and therefore needs to be opened) is called a "page miss". Page misses have greater latency than page hits. It is desirable to perform multiple sequential transactions (i.e., sequential page hits) on the same open row, rather than having to close one row and open another, because this can reduce latency. In addition, sequential transactions directed to the same repository incur more latency than sequential transactions directed to different repositories. The structure or organization of the repository groups and DRAM208 in the repository enables the DRAM controller 206 to initiate access to a row in one repository while waiting for a previous access to a row in another repository to complete. This time overlap helps minimize transaction latency. The DRAM controller 206 can use a conventional repository hashing algorithm to help randomize its selection of the repository to be accessed, so that sequential accesses are less likely to be directed to the same repository. This randomization effect is often referred to as "expansion" of adding repositories and / or repository groups. DRAM controller 206 may employ other algorithms to attempt to reduce other sources of latency, such as read-to-write switching, write-to-read switching, or bank-to-bank switching. Cache system 204 may include features as described below that may further increase repository expansion, increase page hit rates, and reduce read-to-write switching, write-to-read switching, or bank-to-bank switching, with the goal of further reducing latency.

[0041] like Figure 3 As shown, a system 300 for controlling various aspects of a data cache may be provided. The system 300 may be the system 100 ( Figure 1) example. The system 300 may be configured as described above with respect to Figure 1-Figure 2 Describes the way to receive data from a client device ( Figure 3 ), which is directed to the DRAM ( Figure 3 300 may include a scrubber 302. The scrubber 302 may include a plurality of queues 304. The queues 304 may be the data storage structure 102 ( Figure 1 ). As further described below, queues 304 can be organized in a manner corresponding to the organization of DRAM. For example, each queue 304 can correspond to a bank of DRAM.

[0042] The system 300 may also include a cache data (or "payload") memory 306. The cache data memory 306 may be configured to store (i.e., cache) data that is the subject of a DRAM transaction request. The data stored in the cache data memory 306 may be referred to as cache data. The data may be stored in the cache data memory 306 in units commonly referred to as cache lines. The cache data memory 306 may be organized as a set associative cache. Although set associative caches are well understood by those of ordinary skill in the art, the following brief description is provided as background.

[0043] A set associative cache may be addressed using address portions generally referred to as a "set" and a "way." Conceptually, a set is a row in the cache. Each DRAM address maps to one of the sets. An "N-way set associative cache" consists of a certain number (N) of ways, and each DRAM address may map to (or select from) any one of the N ways in a set. References herein to a lookup tag mean reading the contents of all N paths (e.g., from a tag memory 310 described below), and checking the tag of each path, as well as a valid flag for each path, to determine if a cache hit occurs in one of the ways in the set. A hit in one of the paths indicates that the data is cached at a location associated with that path (e.g., in cache data memory 306). Cache data memory 306 may be implemented in static RAM ("SRAM").

[0044] The system 300 may also include a tag processor 308, which may be the cache controller system 104 ( Figure 1 ) or a portion thereof. Although for clarity purposes Figure 3, but the tag processor 308 may include a processor (e.g., configurable by software or firmware) or other logic (e.g., a finite state machine, etc.) that is configurable to provide the functionality described below. As further described below, when data that is the subject of a write request is stored in the cache data memory 306 (at a cache address) but has not yet been written to the DRAM, that is, when the cache data is "dirty," the tag processor 308 may store the cache address of the dirty data in a selected queue in the queue 304. In other words, the queue 304 may be used to store cache addresses (e.g., sets and ways) of dirty cache lines. A reference to a cache line "registered" in the queue 304 indicates that the cache address at which the cache data is stored in the cache data memory 306 is stored in the queue 304. The queue 304 storing the data (i.e., the cache address) may be selected based on, for example, which DRAM memory bank corresponds to the target memory address associated with the write request. Although in Figure 3 In the exemplary embodiment shown, queue 304 is used by tag processor 308 to store cache addresses of dirty cache lines, but in other embodiments (not shown), such a queue may be used to store other types of information or data associated with a transaction request.

[0045] The system 300 may include a tag memory 310. The tag memory 310 may be configured to store tags associated with cache data. As understood by one of ordinary skill in the art, the tag may be derived from a portion of a target address in a memory transaction request and may be used to identify the cache data. Each tag stored in the tag memory 310 may identify a cache line stored in the cache data memory 306. The tag memory 310 may be implemented using SRAM. Since addressing cache memories (e.g., by sets and paths), using stored tags to identify cache data, and other such data caching principles are well understood by one of ordinary skill in the art, such aspects are not described in further detail herein.

[0046] The tag memory 310 may be configured to store not only the tags themselves, but also information associated with the tags. Such information may include one or more flags associated with each tag, which may indicate various states of the cache line identified by the tag. For example, a "valid" flag may indicate whether the cache line identified by the tag is valid (i.e., the "valid" flag is true) or invalid (i.e., the "valid" flag is false). A dirty flag may indicate whether the cache line identified by the tag is dirty (i.e., the dirty flag is true) or clean (i.e., the dirty flag is false). A "cleanable" flag may indicate whether the cache line identified by the tag is registered in the queue 304 (i.e., the "cleanable" flag is true) or not registered in the queue 304 (e.g., the "cleanable" flag is false). A "stall" flag may indicate whether the cache line identified by the tag is older than a predetermined threshold time length (i.e., the "stall" flag is true) or not older than a threshold time length (e.g., the "stall" flag is false). Aspects related to cache line age are described below.

[0047] The system 300 may also include an arbitrator 312, which in the illustrated embodiment may be included in the scrubber 302. However, more generally, the arbitrator 312 may be a cache controller system 104 ( Figure 1 ) is an example of a portion of the arbiter 312 related to the control of the eviction of dirty cache lines to DRAM. Because the arbiter 312 may include selection logic (not separately shown) based on the DRAM bank, memory bank group, and memory bank organization, the arbiter 312 may be referred to as having a "DDR-aware" feature. Although for clarity purposes, Figure 3 312 , but the selection logic of the arbiter 312 may include a processor (e.g., configurable by software or firmware) or other logic (e.g., a finite state machine, etc.) configurable according to a selection algorithm or method (such as the exemplary method described below). As further described below, based on such a selection method, the arbiter 312 can select from the queues 304. The selected queues 304 are used to control which dirty cache lines are evicted from the cache data memory 306 to the DRAM. The system 300 may include a cache service processor 314, which, among other functions, may control the transmission of cache lines evicted from the cache data memory 306. The result or output provided by the arbiter 312 identifying the cache lines to be evicted or cleaned can be referred to as a "clean" transaction request. The tag processor 308 can direct the "clean" transaction request to the cache service processor 314. The memory controller (e.g., as described above with respect to Figure 2 The ) can receive evicted cache line data from the cache service processor 314 and control how the data is ultimately written to the DRAM.

[0048] The system 300 may also include a transaction buffer 316 configured to receive and buffer (eg, in a transaction pool) transactions from a client device ( Figure 3 316 and 317. The system 300 may also include an input arbiter 318 configured to select from any transactions that may be in the buffer 316 and any clean transactions that may be provided by the arbiter 312, and provide the selected transaction request to the tag processor 308. The input arbiter 318 may base the selection on various factors, which may include, for example, a priority associated with each transaction, a length of time associated with each transaction request (e.g., how long the write transaction request has been in the transaction buffer 316), or other factors.

[0049] Incoming transaction requests received by system 300 may include not only the target address, data, length, etc., but also additional information. The additional information may include cache "hints". A client may include a cache hint in a write request to indicate, for example, whether the client prefers to cache the transaction (a "write allocate" hint) or prefer to pass the transaction through system 300 without caching (a "write don't allocate") hint. A transaction request may also include an indication identifying a sub-cache. Although for purposes of clarity, the cache "hint" may be used to indicate whether the client prefers to cache the transaction (a "write allocate" hint) or to pass the transaction through system 300 without caching (a "write don't allocate" hint). Figure 3 Not shown, system 300 may include multiple sub-caches, and different sub-caches may correspond to different priorities, where transactions directed to one sub-cache are processed relative to transactions directed to another sub-cache.

[0050] It should be noted that Figure 3 The arrows in the figure indicate the flow associated with the request-related aspects of a write transaction; for clarity, the response-related aspects are not shown. Figure 3 The arrows in , such as in response to a request, indicate a return flow of data. In addition, in addition to being configured to process write requests in the manner described herein, the system 300 may also be configured to process read requests. The system 300 may be configured to process read requests in any manner, including in a conventional manner. It should also be understood that Figure 3 The arrows in the indicate the flow of information in a conceptual manner and are not intended to indicate specific physical interconnections, such as specific signal lines, buses, etc.

[0051] like Figure 4 As shown, the scrubber structure 402 may include a linked list queue ("LLQ") 404 and selection logic 406. The LLQ 404 may be a Figure 3 The example of queue 304 described above and the Figure 1An example of a data storage structure 102 is described. The LLQ 404 can be organized in a manner corresponding to the bank, memory bank group, and memory bank organization of a DRAM (not shown). Thus, in an embodiment where the DRAM has two banks (Rank_0 and Rank_1), wherein each bank consists of four memory bank groups (BG0, BG1, BG2, and BG3), each memory bank group consists of four memory banks (32 memory banks in total), the LLQ 404 can be organized into a first subgroup 404A of 16 LLQs 404 corresponding to the 16 memory banks of one of the banks (e.g., Rank_0), and a second subgroup 404B of 16 LLQs 404 corresponding to the 16 memory banks of the other bank (e.g., Rank_1).

[0052] In each subgroup 404A and 404B, the LLQ 404 can be organized by banks and bank groups. According to an exemplary pattern or organization, the bank groups can be incremented from one LLQ 404 to the next LLQ 404 through each bank: the first LLQ 404 in each subgroup 404A and 404B can correspond to Bank_0 in BG_0; the second LLQ 404 in each subgroup 404A and 404B can correspond to Bank_0 in BG_1; the third LLQ 404 in each subgroup 404A and 404B can correspond to Bank_0 in BG_2; and the fourth LLQ 404 in each subgroup 404A and 404B can correspond to Bank_0 in BG_3. This pattern or organization continues for the next memory bank (i.e., Bank_1): the fifth LLQ 404 in each subgroup 404A and 404B may correspond to Bank_1 in BG_0; the sixth LLQ 404 in each subgroup 404A and 404B may correspond to Bank_1 in BG_1; the seventh LLQ 404 in each subgroup 404A and 404B may correspond to Bank_1 in BG_2, and the eighth LLQ 404 in each subgroup 404 may correspond to Bank_1 in BG_3. This pattern or organization may continue for Bank_2 and Bank_3. According to this pattern or organization, the 16th LLQ 404 corresponds to Bank_3 in BG3.

[0053] Each LLQ 404 may be implemented as a linked list (data structure). Although an exemplary linked list structure is described below, it may be noted that each entry in each LLQ 404 identifies a dirty cache line. The head entry in each LLQ 404 identifies a dirty cache line that may be a candidate for cleaning (i.e., evicting) before the next entry in that LLQ 404 becomes a candidate.

[0054] The selection logic 406 may be used to select a cache line for cleaning from the candidate dirty cache lines. That is, the selection logic 406 may be used to select one LLQ from the 32 LLQs 404 and thereby select or identify the dirty cache line at the head of the selected queue (LLQ) 404. It should be understood that the selection logic 406 may be used to select a cache line for cleaning from the candidate dirty cache lines. Figure 4 406 is shown conceptually in FIG. 406 and may include, for example, a processor (eg, configurable by software or firmware), a finite state machine, or other logic. Figure 3 312 described above.

[0055] Conceptually, the selection logic 406 may include a first queue selection logic 408A and a second queue selection logic 408B, the first queue selection logic 408A being configured to select an LLQ 404 from the 16 LLQs 404 of the first subgroup 404A corresponding to the memory bank of Rank_0, and the second queue selection logic 408B being configured to select an LLC 404 from the 16 LLCs 404 of the second subgroup 404B corresponding to the memory bank of Rank_1. Conceptually, the results produced by the first queue selection logic 408A and the second queue selection logic 408B may operate multiplexers or queue selectors 414A and 414B, respectively. Each of the first queue selection logic 408A and the second queue selection logic 408B may operate independently of each other, but according to the same queue selection method described below. The selection logic 406 may also conceptually include a bank selection logic 410 that is configured to select between the LLQ 404 selected by the first queue selection logic 408A and the LLQ 404 selected by the second queue selection logic 408B. The bank selection logic 410 may operate according to a bank selection method described below. Conceptually, the result produced by the bank selection logic 410 may operate a multiplexer or bank selector 416. The output of the bank selector 416 identifies a selected LLQ 404. Another method described below may control whether the selection logic 406 outputs an indication of a selected LLQ 404 (i.e., an indication that a cache line has been identified for eviction) or does not output a selection (i.e., an indication that no cache line has been identified for eviction at the time). The method of controlling whether the bank selector 416 outputs an indication of a selected LLQ 404 (and therefore an indication identifying a cache line) may be referred to as a scrubber enable or scrubber activation method. Selectively enabling the output of the bank selector 416 at Figure 4 4 is conceptually represented by a 2-input logic-AND 412 having one input representing an indication of the selected LLQ 404 and another input representing the control determination made by the scrubber activation method.

[0056] Again briefly reference Figure 3 , the output of the selection logic 406 forms the scrubber output 320. The scrubber output 320 is provided to the input arbiter 318. As described above, if a cache line has been identified for eviction, the input arbiter 318 may choose to proceed with evicting the identified cache line. If no cache line has been identified for eviction at the time, the input arbiter 318 may select an incoming transaction from the transaction buffer 316. The input arbiter 318 may select a clean request provided by the scrubber output 320 or a transaction from the transaction buffer 316 based on priority. In one embodiment, the clean request provided by the scrubber output 320 may have the lowest priority and may only be serviced if no transactions are pending in the transaction buffer 316. In another embodiment, the priority of the clean request provided by the scrubber output 320 may be dynamically changed based on the fullness of the scrubber LLQ.

[0057] exist Figure 5 In the embodiment of the present invention, a method 500 for controlling a data cache is depicted in the form of a flowchart. For example, the method 500 may represent the system 300 ( Figure 3 ) of the above operations. Figure 5 (as well as Figure 8-Figure 14 ) indicate the order between various blocks, but it should be understood that the blocks are depicted in order for ease of description and to guide the reader to understand the method, and the operations or actions indicated by the blocks are not limited to such order. On the contrary, in other exemplary methods, such actions can be performed in various orders or occur in other ways. In addition, some operations can occur simultaneously with other operations. For example, with respect to Figure 5 , actions associated with receiving a transaction, storing information in a queue, etc., can occur substantially simultaneously with actions associated with selecting from a queue and using the information stored in the selected queue to evict cache data. Figure 3 , the operation of the tag processor 308 and related elements may occur substantially simultaneously with the operation of the scrubber 302. Furthermore, in other exemplary methods, some of the actions or operations may be omitted or combined with other actions.

[0058] As shown in block 502, a write request may be received. The write request may be received by, for example, a tag processor ( Figure 3 ) is received. As shown in block 504, data associated with the write request may be cached (e.g., as described above with respect to Figure 3 306).

[0059] As shown in block 506, a queue can be selected based on the DRAM bank corresponding to the write request, and information associated with the write request can be stored in the selected queue. For example, the linked list LLQ 404( Figure 4 ) can be selected by the scrubber 302( Figure 3 ), and cache address information (e.g., set and way) indicating the location in the cache data memory 306( Figure 3 ) where data associated with the write request is cached can be stored in the selected LLQ 404( Figure 4 ), as described above with respect to Figure 4 .

[0060] Although not shown for clarity purposes, the actions described above with respect to blocks 502 - 506 can be performed substantially continuously, independent of other actions. Thus, the LLQ 404( Figure 4 ) can be populated as additional write requests are received and information associated with the additional write requests is stored in the queue. In the exemplary embodiments described herein, the information associated with the write request can include not only cache address information (e.g., way and set), but also a page hit indication, as described below.

[0061] In Figure 6 , a linked list queue or LLQ 600 is shown, which can be an example of each of the above data storage structures 102( Figure 1 ), queue 304( Figure 3 ), or LLQ 404( Figure 4 ). The LLQ 600 can include any number of entries 602 (or sometimes referred to as linked list "nodes") from a first or "tail" entry 602A to a last or "head" entry 602N. Since the linked list principle is well known to those of ordinary skill in the art, details such as pointers to link nodes are not shown in Figure 6 . Each entry 602 can include cache address information (e.g., way and set) and page hit information (e.g., bit). The page hit bit indicates whether the entry 602 is a page hit with respect to a previous entry in the LLQ 600.

[0062] Referring again to Figure 3, the processing of the write request by the tag processor 308 may include controlling (e.g., via the cache traffic processor 314) the storage of the data (payload) that is the subject of the write request in the cache data memory 306. The processing of the write request by the tag processor 308 may also include deriving a tag, a path, and a set from the target address of the write request. As will be appreciated by one of ordinary skill in the art, the tag processor 308 may derive this cache address information in a conventional manner. The path and set determine the location (i.e., cache line) in the cache data memory 306 where the data is stored or cached. The tag may be stored in the tag memory 360 and used with the target address of a subsequent transaction request (e.g., a read request) to uniquely identify whether the subsequent transaction request is directed to the same cache data.

[0063] When the data that is the subject of the write request is stored in a certain location in the cache data memory 306, the scrubber 302 (or alternatively, the tag processor 308) may also determine whether the write request is directed to the same DRAM page, i.e., the same row in the same memory bank in the same memory bank group in the same memory bank, as indicated by the tail of the queue 304 to which the write request is directed. If two consecutive write requests are directed to the same DRAM page, the second write request may be referred to as a page hit relative to the first write request because corresponding accesses to the DRAM row may occur continuously while the DRAM row remains open.

[0064] Based on the target address, scrubber 302 (or alternatively, tag processor 308) can determine the DRAM row, memory bank, memory bank group, and bank address. When the data that is the subject of the write request is stored in a location in cache data memory 306, tag processor 308 can provide a path and set that collectively indicate the location to scrubber 302. Scrubber 302 can select a corresponding queue in queue 304 and add a new entry (or Figure 6 , selects one of the LLQ 602 and adds a new (tail) entry or node). The scrubber 302 may store in the new entry a way and set, and a bit indicating whether the cache line data at the way and set is a page hit relative to the previous entry.

[0065] return Figure 5 Another part of method 500 may involve controlling data transfer to the DRAM. Figure 3 ), data transfer from the cache data memory 306 to the DRAM may be controlled using the queue 304.

[0066] As indicated at block 508, controlling data transfer may include selecting among queues 304. For example, referring again to Figure 3 , the arbitrator 312 can select among the queues 304. The arbitrator 312 can select the queues 304 in a repetitive or iterative manner, i.e., each consecutive or next queue 304 is selected after the previous queue 304 is selected. The arbitrator 312 can make the queue selection based in part on information obtained from the head entry of the linked list queue (e.g., page hit (bit) information). Note that references to the selection of the queue 304 herein still refer to selecting an entry in the queue 304, and therefore still refer to selecting the dirty cache line identified by the entry. The arbitrator 312 can select the queue 304 in this manner based on, for example, one or more of the following: sequence; page hit information; a threshold level of cache dirtiness; a selected memory body; etc. These aspects of the operation of the arbitrator 312 are described below with respect to Figure 11-13 Give a description.

[0067] As shown in block 510 ( Figure 5 ), method 500 may include evicting cache data indicated by the selected queue. For example, queue 304 ( Figure 3 ) may be selected by the arbiter 312. The dirty cache line in the location identified by the selected (hereinafter also referred to as the "winner") queue entry in the cache data memory 306 may be evicted. The scrubber output 320 may identify the selected dirty cache line to the tag processor 308 (via the input arbiter 318). The tag processor 308, in turn, may identify the selected dirty cache line to the cache traffic processor 314. The cache traffic processor 314 may then control the transfer of the dirty cache line from the cache data memory 306.

[0068] like Figure 7 As shown, tag processor 702 may include features related to storing or caching data that is the subject of a write request. Tag processor 702 may be the tag processor 308 ( Figure 3 In the example shown, such features may include write hint change logic 704, stall logic 706, victim search logic 708, and tag lookup and cleanable row search logic 710.

[0069] Write hint change logic 704 relates to a feature by which a client's write request may include a cache "hint" indicating whether the data associated with the write request is to be cached (an "allocate" hint) or pass through the system 300 without a cache (a "don't allocate") hint. Exemplary embodiments may address client use of cache hints by changing a "don't allocate" hint to an "allocate" hint in most circumstances.

[0070] like Figure 8 As shown, the above write hint change logic 704 ( Figure 7 ) can be configured to control method 800. Incoming transactions (e.g., from arbitrator 318 ( Figure 3 )) may be provided to the write hint change logic 704 and processed in the following manner.

[0071] As shown in block 802, it may be determined whether the incoming transaction request is for a write transaction. The exemplary embodiments described herein relate to write transactions. However, aspects of the embodiments described herein may be applied in other embodiments to read transactions. If it is determined (block 802) that the incoming transaction is not a write request, the remainder of method 800 is not performed.

[0072] If it is determined (block 802) that the incoming transaction is a write request, then the selected queue (e.g., Figure 4 404 is full, or there is no remaining space in the LLQ 404 to store a new entry, as shown in block 804. In the exemplary embodiments described herein, each queue may not have a predetermined size or capacity, and new entries may be added to the queue only when the storage capacity used by the LLQ 404 is not full. However, in other embodiments, the queue may have a predetermined size. As described above, the queue may be selected based on, for example, which DRAM memory bank corresponds to the target memory address associated with the transaction request. If it is determined (block 804) that the selected queue is full, the remainder of the method 800 is not performed.

[0073] If it is determined (block 804) that the selected queue has room for the new entry, it may be determined whether the write request includes a "don't allocate" cache hint, as shown in block 806. If it is determined (block 806) that the write request does not include a "don't allocate" cache hint, the remainder of method 800 is not performed. For example, if the write request includes an "allocate" cache hint, method 800 does not change the cache hint for the transaction, so the cache hint remains "allocate".

[0074] If it is determined (block 806) that the write request includes a "don't allocate" cache hint, the cache hint may be changed to "allocate". However, whether the "don't allocate" cache hint is changed to "allocate" may depend on the attributes of the sub-cache to which the write request is directed. As described above, a transaction request may include an indication identifying a sub-cache in a certain number of sub-caches into which the cache system may be divided. One such sub-cache (which may be referred to as a write sub-cache or "WRSC") may be used to cache payloads whose locations are registered in LLQ 404. Each sub-cache may have an attribute referred to herein as a "write buffer" attribute, and the write buffer attributes of some sub-caches may be different from the write buffer attributes of other sub-caches. The write buffer attribute may have one of two values: true or false. As shown in block 808, it may be determined whether the write buffer attribute of the sub-cache to which the write request is directed is true. If it is determined that the write buffer attribute is true, the write request with the "don't allocate" hint may be assigned to the WRSC sub-cache, and the associated information may be registered (i.e., stored) in a queue as described above. If it is determined (block 808) that the write buffer attribute of the sub-cache to which the write request is directed is not true, i.e., is false, then the write request with the "allocate" hint may be forwarded to the sub-cache at a later time (block 810). Figure 8 ) when cache data is stalled and is detected by tag lookup and cleanable line search logic 710 ( Figure 7 ) is registered in the selected queue when selected. A method by which cache data can be marked with a "stall" indication is described below, referred to as a "stall" method. If it is determined (block 808) that the write buffer attribute is true, the "do not allocate" cache hint of the write request can be replaced with an "allocate" cache hint, as shown in block 810. Also as shown in block 810, the indication of the sub-cache to which the write transaction is directed can be replaced with an indication of writing to the sub-cache.

[0075] Again briefly reference Figure 7 , the tag lookup and cleanable row search logic 710 involves executing the above method 800 ( Figure 8 ) and then further processes the write request. As described below, such processing may include looking up a tag associated with the write request, searching for a location for storing or caching data associated with the write request, etc.

[0076] like Figure 9A-9B As shown, tag lookup and cleanable row search logic 710 ( Figure 7 ) may be configured to control method 900. Alternatively or additionally, scrubber 302 ( Figure 3 ) can be configured as part of control method 900.

[0077] although Figure 9A-9B , but before performing a tag lookup (described below), stall logic 706 ( Figure 7 ) may be operable to check the age of each cache line in the set accessed by the tag lookup operation. If the age of the cache line exceeds a predetermined threshold, the stall flag may be set to true. The age of the cache line may be calculated by comparing the current time with a timestamp associated with the cache line when the cache line was allocated in the cache. Each sub-cache may have its own current time, which is performed on each new allocation in that sub-cache.

[0078] As shown in block 902, a determination may be made as to whether the write request resulted in a cache hit. (Note that a "cache hit" is different from the DRAM "page hit" described above.) Whether a write request resulted in a cache hit may be determined in a conventional manner. For example, as will be appreciated by one of ordinary skill in the art, for an N-way set associative cache, each set contains N paths or degrees of associativity. Each path includes a data block, a tag, and the valid, dirty, cleanable, and stalled flags described above. The set and path may be determined based on a portion of the target address associated with the write request. In an exemplary embodiment, the cache hit may then be determined from the tag memory 310 ( Figure 3 ) reads the tag and associated flag. (In an exemplary embodiment, the cache data (line) may be stored separately in cache data memory 306.) For each way in the set, the tag read from tag memory 310 is compared with the tag bits of the target address of the write request, and if they match, and if the valid flag is true, then it is determined that the write request resulted in a cache hit. Note that the target address decoding described above may also identify the DRAM bank, memory bank group, and memory bank to which the write request is directed, thereby identifying or selecting one of LLQs 404 (which may be referred to herein as LLQ 404 or selected LLQ 404).

[0079] If it is determined (block 902) that the write request did not result in a cache hit, further processing may be performed to determine if the cache data memory 306 ( Figure 3 ) where data can be stored, and an entry indicating that the location contains dirty data is added to LLQ 404. Prior to this further processing, it can be determined whether the write request includes an "allocate" cache hint, as shown in block 904.

[0080] If it is determined (block 904) that the write request includes an "allocate" cache hint, then a victim search method may be performed. Block 906 indicates performing a victim search method, which is described further below. The result of performing the victim search method may be a cache data memory 306 ( Figure 3 ) in the memory. However, another possible result of the victim search method may be that no victim cache line is found. In addition, the victim search method may be more inclined to select a clean victim line to minimize the occurrence of dirty line evictions that would pollute the DRAM-aware write-back flow that is continuous with the scrubber operation.

[0081] As shown in block 908, it may be determined whether a victim cache line is found. If it is determined (block 910) that a victim cache line is found, the cache line may be allocated for the data associated with the write request. Thus, the data associated with the write request is stored in the allocated cache line in the cache data memory 306. Additionally, as described below, the tag memory 310 may be updated and an entry may be added to the LLQ 404. Adding an entry to the LLQ 404 may be conditional on some additional conditions, one of which is that the LLQ 404 is not full, as shown in block 912.

[0082] Returning to block 902, if it is determined that the write request resulted in a hit, it may be determined whether the hit was on a "clean" line (i.e., the "dirty" flag has a false state) as indicated by block 914. If it is determined that the hit was on a clean line, the method 900 may return to block 912 described above, where it may be determined whether the LLQ 404 is full. If it is determined (block 912) that the LLQ 404 is full, the method 900 ends with respect to processing of the write request, and no entry is added to the LLQ 404.

[0083] If it is determined (block 912) that the LLQ 404 is not full, another combination of conditions may be determined, as shown in block 916: the cache line is dirty (i.e., the dirty flag has a true state), and the cache line is purgeable (i.e., the purgeable flag has a true state), and the above-described write buffer attribute has a true state. As described above, a true purgeable flag indicates that the cache line has not been registered in the LLQ 404.

[0084] If the above combination of conditions is determined (block 916) to be true, an entry may be added to the LLQ 404, as indicated by block 918. A new "head" of the LLQ 404 (including the set of allocated cache lines and the way address) may be "pushed" or added to the LLQ 404, effectively placing the entry that was previously the head after the new head. The line information of the new head may be compared with the line information of the previous head to determine if the page hit flag is true. The page hit flag is also pushed into the queue. The cleanable flag in the location associated with the allocated cache line in the tag memory 310 may be set to a false state. A write request that has been processed in the manner described above may indicate the end of the method 900 with respect to that write request.

[0085] However, if it is determined according to block 914 above that the cache hit is not on a clean line, or if it is determined according to block 904 above that the cache hint is not "allocate", or if it is determined according to block 908 above that no victim cache line is found, or if it is determined that the combination of conditions described above with respect to block 916 does not hold, then method 900 may continue (see Fig. 9B ), as shown in box 920.

[0086] It may then be determined (block 920) whether the LLQ 404 is full. If it is determined that the LLQ 404 is full, then processing of the method 900 for the write request ends, and no entry is added to the LLQ 404.

[0087] If it is determined (block 920) that the LLQ 404 is not full, then as indicated at block 922, it may be determined whether the set has any cache lines that have the following combination of conditions: dirty, cleanable, and stalled (i.e., the dirty, cleanable, and stalled flags are all true). If the combination of conditions is determined to be true, then one of those cache lines (e.g., the first such cache line found) may be selected to be added to the list of dirty cache lines in the LLQ 404, as indicated at block 924. Returning to block 918 ( Fig.9A ), and then the entry for the cache line can be added to LLQ 404.

[0088] like Fig.10 As shown, the “sacrificial search” method 1000 may be a method 900 ( Fig.9A ). As shown in block 1002, it may be determined whether there are one or more invalid rows in the set (i.e., the "valid" flag is false). If it is determined (block 1002) that there are one or more invalid rows in the set, one of the invalid rows may be selected as a victim row, as shown in block 1004. If more than one such row is found, the first such row found may be selected according to block 1004.

[0089] However, if it is determined (block 1002) that there are no invalid lines in the set, then it may be determined whether there are one or more clean stalled lines in the set (i.e., the "clean and stalled" flag is true), as indicated by block 1006. If it is determined (block 1006) that there are one or more clean stalled lines in the set, then one of these clean stalled lines may be selected as a victim line, as indicated by block 1008. If more than one such line is found, then the first such line found may be selected according to block 1008. It will be appreciated that the probability of finding a clean stalled line is high because the scrubber ensures that the level of dirty lines in the cache is low, and the stalling process ensures that the probability of finding a stalled line in each set is high.

[0090] However, if it is determined (block 1006) that there are no clean stalled rows in the set, it may be determined if there are one or more dirty stalled rows in the set (as shown in block 1010). If it is determined (block 1010) that there are one or more dirty stalled rows in the set, one of these dirty stalled rows may be selected as a victim row, as shown in block 1012. If more than one such row is found, the first such row found may be selected according to block 1012. It will be appreciated that selecting a dirty victim will result in a dirty eviction and therefore contaminate the DRAM-aware write-back flow that is continuous with the scrubber operation.

[0091] However, if it is determined (block 1010) that there are no clean, stalled lines in the set, it may be determined whether there are one or more clean lines in the set that have a lower priority than the incoming line (i.e., the priority of the write request being processed), as shown in block 1014. As described above, the "priority" of a write request may refer to the priority of the sub-cache to which the write request is directed, as each sub-cache may have a predetermined priority relative to the other sub-caches. If it is determined (block 1014) that there are one or more clean lines in the set that have a lower priority than the incoming line, one of those lines with the lowest priority may be selected as a victim line, as shown in block 1016. If two or more lines each have the lowest priority, the first such line found may be selected according to block 1016.

[0092] If, however, it is determined (block 1014) that there are no clean rows in the set with a lower priority than the incoming row, then a determination may be made as to whether there are one or more dirty rows in the set with a lower priority than the incoming row, as indicated at block 1018. If it is determined (block 1018) that there are one or more dirty rows in the set with a lower priority than the incoming row, then one of these rows may be selected as a victim row, as indicated at block 1020. If more than one such row is found, then the first such row found may be selected according to block 1020. If, however, it is determined (block 1018) that there are no clean rows in the set with a lower priority than the incoming row, then the result of method 1000 may be that no victim row was found.

[0093] An alternative sacrificial search method (not shown) may be similar to method 1000 described above ( Fig.10 ), except that the dirty row can be omitted as a victim row candidate. Therefore, in an alternative method, blocks 1010, 1012, 1018, and 1020 can be omitted. That is, the method flow can proceed directly to block 1014 from the "no" determination in block 1006.

[0094] The above method 800( Figure 8 )、900( Figure 9A-9B ) and 1000( Fig.10 ) involves caching data associated with an incoming transaction request and in LLQ 404 ( Figure 4 ) in registering dirty cache lines. Therefore, methods 800, 900 and 1000 can also represent the above method 500 ( Figure 5 )'s blocks 502, 504, and 506 illustrate an example of the processing described herein.

[0095] like Fig.11 As shown, a flowchart is depicted in the form of a flowchart related to using LLQ 404 ( Figure 4 ) is related to the control of transferring cache data to DRAM. Method 1100 may represent the above method 500 ( Figure 5 ) of blocks 508 and 510. Method 1100 may represent a method for performing a sequence-based Figure 4 ) in the LLQ 404. The method 1100 may control Figure 4 The selections conceptually represented by queue selection logic 408A and 408B in FIG. 408A and 408B. Figure 4) can operate independently of each other. In other words, two instances of method 1100 can operate independently of each other and concurrently, with the first instance of method 1100 controlling the selection represented by first queue selection logic 408A and the second instance of method 1100 controlling the selection represented by second queue selection logic 408B. Selection logic 406 ( Figure 4 ) can be configured as two instances of control method 1100.

[0096] As shown in block 1102, it may be determined whether a page hit list count (Page_Hit_List_Count) is greater than or equal to a predetermined threshold number (LLQ_PH_TH). The page hit list count is the number of LLQs 404 (indicated by the header entry (page hit bit) in the page hit) that are in the page hit list. Figure 4 ). If it is determined (block 1102) that the page hit list count is greater than or equal to the threshold number, a determination may be made as to whether there are one or more LLQs 404 having header entries indicating page hits in a different repository group than the “last winner” (i.e., the LLQ 404 most recently selected by method 1100), as shown in block 1104. If there is no “last winner” because the determination in block 1104 is the first iteration after initially starting method 1100, the determination in block 1104 may default to a result of “yes”. If it is determined (block 1104) that there are one or more LLQs 404 having header entries indicating page hits in a different repository group than the “last winner” (or the determination defaults to “yes”), the current list (Current_list) may be incremented. Method 1100 maintains a list or LLQ 404 (which may be referred to as the “current list”) of pages that have been hit in a different repository group than the “last winner”. Figure 4 ) is a record or pointer to one of the .

[0097] Incrementing the current list indicates that the next LLQ 404 in the sequence becomes the new current list. For example, if the current list is the LLQ 404 of Bank 0 in BG0, then the next list in the sequence is the LLQ 404 of Bank 0 in BG1. In other words, when the LLQ 404 of Bank_0 in BG0 is referred to as the first LLQ 404 and the LLQ 404 of Bank_3 in BG3 is referred to as the 16th LLQ 404, then the list may be incremented from the first LLQ 404 to the second LLQ 404, and so on, to the 16th LLQ 404. The incrementing performed according to block 1106 is modulo 16. That is, if the 16th LLQ 404 (i.e., Bank_3 in BG3) is the current list, then incrementing the current list indicates that the first LLQ 404 (i.e., Bank_0 in BG0) becomes the new current list. It may be noted that the sequence represented by method 1100 is based on a round-robin sequence in LLQ 404. While a conventional round-robin sequence would advance from each LLQ 404 to the next LLQ 404 without regard to other conditions, method 1100 represents a modification of the conventional round-robin sequence based on page hit information.

[0098] As shown in block 1108, after incrementing the current list, it may then be determined whether the current list (head entry) indicates a page hit and whether the page hit is in a different bank group than the last winner. If it is determined that the current list indicates a page hit and is in a different bank group than the last winner, the current list is selected, as shown in block 1110. Figure 4 , the information identifying the first selected list is conceptually the output of the first selection logic 408A, and the information identifying the second selected list is conceptually the output of the second selection logic 408B. The method flow iterates from block 1110 back to block 1102. Note that for purposes of blocks 1104, 1108, etc., the selected list also becomes the new "final winner."

[0099] If it is determined (box 1102) that the page hit list count is not greater than or equal to the threshold number, that is, the page hit list count is less than the threshold number, the value of the saved list (Saved_List) can be assigned to the current list. That is, the saved list will become the new current list. If there is no "saved list" because the method flow has reached box 1112 in the first iteration of method 1100, the saved list can be the same as the current list. That is, when method 1100 starts operation, the saved list can initially be set to the same list as the current list. In addition, returning to box 1104, if it is determined that there is no LLQ 404 with a header entry indicating a page hit in a different storage library group than the last winner, method 1100 continues as described above with respect to box 1112.

[0100] After the saved list becomes the new current list (block 1112), the current list may be incremented, as shown in block 1114. Then, as shown in block 1116, it may then be determined whether the current list is empty. If it is determined that the current list is empty, the current list may be incremented (block 1114) until the current list is not empty.

[0101] As shown in box 1118, if it is determined (box 1116) that the current list is not empty, it can be determined whether there are one or more lists in a different repository group than the last winner, or whether the current list is in a different repository group than the last winner. If it is determined that there are no lists in a different repository group than the last winner, or the current list is in a different repository group than the last winner, the current list can become a saved list (i.e., the current list is saved for the next iteration of method 1100), as shown in box 1120. However, if it is determined that there are one or more lists in a different repository group than the last winner and the current list is not in a different repository group than the last winner, the current list can be incremented, and method 1100 can continue, as described above with respect to box 1114.

[0102] like Fig.12 As shown, a method 1200 related to the selection of a storage body is depicted in the form of a flowchart. The method 1200 may represent the method 500 ( Figure 5 ) is part of the processing described in block 508 of FIG. Figure 4 , selection logic 406 may be configured to control method 1200. Method 1200 selects a memory bank (eg, Rank_0 or Rank_1 in an exemplary embodiment). Memory bank selection logic 410 may be configured according to method 1200. Memory bank selection logic 410 is thus configured to select a memory bank. Fig.12 In the method 1200, any one of Rank_0 and Rank_1 previously selected at the start of the determination indicated by block 1202 is referred to as the "current memory bank" (Current_Rank), and any one of Rank_0 and Rank_2 that is not the current memory bank is referred to as the "other memory bank" (Other_Rank). The current memory bank may be initialized to any memory bank before the first iteration through the method 1200. Fig.12 In the description, the term "list spread" (List_Spread) refers to the number of LLQs 404 in a non-empty bank. The term "minimum list spread" refers to a threshold number that may be predetermined or fixed.

[0103] As shown in block 1202, a first condition may be determined: whether the list extension of the current storage body is less than the minimum list extension, and whether the list extension of another storage body is greater than or equal to the minimum list extension. Also as shown in block 1202, a second condition may be determined: the list extension of the current storage body is equal to zero. And the list extension of another storage body is not equal to zero. If it is determined that either the first condition or the second condition is true, the current storage body may be changed or switched to another storage body, as shown in block 1204. That is, the current storage body becomes another storage body, and vice versa. After block 1204, method 1200 may return to block 1202. However, if it is determined (block 1202) that both the first condition and the second condition are not established, method 1200 may return to block 1202 without changing the current storage body. That is, as long as both the first condition and the second condition are not established, the determination indicated by block 1202 may be substantially continuously repeated without changing the storage body.

[0104] Again briefly reference Figure 4 , the output of the bank selection logic 410 is an indication identifying the LLQ 404 in Rank_0 selected by the first queue selection logic 408A or the LLQ 404 in Rank_1 selected by the second queue selection logic 408B. In the illustrated embodiment, the output of the bank selection logic 410 becomes the output of the selection logic 406 (conceptually represented by Figure 4 ); if the selection enable logic 412 is not enabled, the output of the selection logic 406 is an indication that the LLQ 404 is not currently selected. Fig.13 The scrubber enable or scrubber activation method described may control whether the select enable logic 412 is enabled. However, it should be understood that such a scrubber enable or activation method may enable any of the above-described logic and methods related to controlling the transfer of cache data to DRAM using the LLQ 404; enabling the output of the select logic 406 after queue selection by the queue selection logic 408A and 408B and bank selection by the bank selection logic 410 as the final action immediately before the output is intended only as an example.

[0105] Method 1300( Fig.13 ) can control the scrubber 302 ( Figure 3 ) is active or inactive because, in an exemplary embodiment, selection logic 406 ( Figure 4) effectively controls scrubber operation. When the scrubber 302 is active, it identifies dirty cache data for eviction to DRAM. Eviction (or "cleaning") can reduce the dirtiness of the cache. The method 1300 attempts to regulate the level of scrubber activity to keep the level of cache dirtiness within a range or window between a high threshold (HT) and a low threshold (LT). This feature can be beneficial in operating examples where read and write traffic competes for memory controller bandwidth. For example, in a PCD, write request traffic from a camera client can compete with read request traffic from a display client.

[0106] Selection logic 406 ( Figure 4 ) or scrubber 302( Figure 3 ) can be configured to monitor the total number of linked list entries in all LLQs 404 as a measure of cache dirtiness. For example, a count of the total number of entries in all LLQs 404 can be incremented when entries are added (or "pushed") and can be decremented when entries are removed (or "popped") in conjunction with eviction. In method 1300, this measure of cache dirtiness is referred to as the "LLQ level."

[0107] Although for the sake of clarity, Fig.13 or other flowcharts herein are not shown for initialization, but the scrubber 302 ( Figure 3) may be initialized to an inactive state. As shown in block 1302, it may be determined whether the LLQ level is greater than or equal to a predetermined minimum threshold (i.e., a "bottommost threshold" or RBT). The minimum threshold may be determined empirically. For example, it may be statistically determined that if the pool of candidate cache lines for eviction in a bank remains above 80 candidates, the result is likely to be a bank expansion of approximately 16. The determination indicated by block 1302 may be repeated until it may be determined that the LLQ level is greater than or equal to the minimum threshold. If it is determined that the LLQ level is greater than or equal to the minimum threshold, it may be determined whether the scrubber is active, as shown in block 1304. If it is determined that the scrubber is not active, it may be determined whether the LLQ level is greater than or equal to a high threshold, or whether the number of pending read requests in the memory controller (MCreadOT) is less than a predetermined or fixed threshold (readOTthreshold), as shown in block 1306. If it is determined that the LLQ level is greater than or equal to the high threshold, or the number of outstanding read requests in the memory controller (MCreadOT) is less than a predetermined or fixed threshold (readOTthreshold), the scrubber may be activated or enabled, as shown in block 1308. The method 1300 may then return to the above block 1302. If it is determined that the LLQ level is not greater than or equal to the high threshold, and the number of outstanding read requests in the memory controller (MCreadOT) is not less than a predetermined fixed threshold (readOTthreshold), the method 1300 may return to the above block 1302.

[0108] If it is determined (block 1304) that the scrubber is active, it may be determined whether the LLQ level is less than a low threshold or the number of outstanding read requests in the memory controller (MCreadOT) is greater than or equal to a predetermined fixed threshold, as shown in block 1310. If it is determined that the LLQ level is less than the low threshold or the number of outstanding read requests in the memory controller (MCreadOT) is greater than or equal to a predetermined or fixed threshold (readOTthreshold), the scrubber may be deactivated or disabled, as shown in block 1312. The method 1300 may then return to block 1302 described above. If it is determined that the LLQ level is not less than the low threshold and the number of outstanding read requests in the memory controller (MCreadOT) is not greater than or equal to a predetermined or fixed threshold (readOTthreshold), the method 1300 may return to block 1302 described above.

[0109] The method 500 ( Figure 5 )、800( Figure 8 )、900( Figure 9A-9B )、1000( Fig.10 )、1100( Fig.11 ) and 1200( Fig.12 ) may be referred to as "DRAM-aware" because they take advantage of the latency-reducing organization of DRAM. Similar methods may be provided for DRAM-aware processing of other types of memory transactions. For example, to process a read prefetch request, instead of storing information identifying cache locations of dirty data in a selected LLQ or other data storage structure as described above with respect to, for example, method 500, the read prefetch request may be stored. And, instead of evicting cache lines identified by contents stored in a selected LLQ or other data storage structure in a DRAM-aware order as described above with respect to, for example, method 500, the prefetch request may be sent from the LLQ or other data storage structure to the DRAM (via a memory controller) in such a DRAM-aware order.

[0110] like Fig.14 As shown, a method 1400 for controlling a data cache is shown in the form of a flow chart. As shown in block 1402, the method 1400 may include receiving a DRAM transaction request. As shown in block 1404, the method may also include storing information associated with the transaction request in a data storage structure organized in a manner corresponding to the DRAM organization. As shown in block 1406, the method 1400 may also include using the data storage structure to control data transfer to the DRAM.

[0111] like Fig.15 As shown, an exemplary embodiment of a system and method for controlling data cache in a DRAM-aware manner may be provided in a portable computing device ("PCD") 1500. For clarity, a data bus or other data communication interconnect is shown in FIG. Fig.15 Some exemplary interconnects are described for context, some of which may represent communication via such buses or interconnects. However, it should be understood that, more generally, the various elements described below may communicate with each other via one or more buses or system interconnects.

[0112] PCD 1500 may include SoC 1502. SoC 1502 may include CPU 1504, GPU 1506, DSP 1507, analog signal processor 1508, or other processors. CPU 1504 may include multiple cores, such as first core 1504A, second core 1504B, and so on, up to Nth core 1504N.

[0113] The CPU 1504 may include a display controller 1510 and a touch screen controller 1512. A touch screen display 1514 external to the SoC 1502 may be coupled to the display controller 1510 and the touch screen controller 1512. The PCD 1500 may also include a video decoder 1516 coupled to the CPU 1504. A video amplifier 1518 may be coupled to the video decoder 1516 and the touch screen display 1514. A video port 1520 may be coupled to the video amplifier 1518. A universal serial bus (“USB”) controller 1522 may also be coupled to the CPU 1504, and a USB port 1524 may be coupled to the USB controller 1522. A subscriber identity module (“SIM”) card 1526 may also be coupled to the CPU 1504.

[0114] One or more memories may be coupled to CPU 1504. The one or more memories may include volatile memory and non-volatile memory. Examples of volatile memory include static random access memory ("SRAM") 1528 and dynamic RAM ("DRAM") 1530 and 1531. Such memory may be external to SoC 1502, such as DRAM 1530, or internal to SoC 1502, such as DRAM 1531. A DRAM controller 1532 coupled to CPU 1504 may control writing data to and reading data from DRAM 1530 and 1531. In other embodiments, such a DRAM controller may be included within a processor, such as CPU 1504. DRAM 1530 and 1531 may be DRAM 208 ( Figure 2 ), or more generally, the example above with reference to Figure 1-Figure 14 Any DRAM is an example of a cache system 204 ( Figure 2 )'s example cache system 1533 can be coupled to the DRAM controller 1532.

[0115] A stereo audio CODEC 1534 may be coupled to the analog signal processor 1508. In addition, an audio amplifier 1536 may be coupled to the stereo audio CODEC 1534. A first stereo speaker 1538 and a second stereo speaker 1540 may be coupled to the audio amplifier 1536, respectively. In addition, a microphone amplifier 1542 may be coupled to the stereo audio CODEC 1534, and a microphone 1544 may be coupled to the microphone amplifier 1544. A frequency modulation ("FM") radio tuner 1546 may be coupled to the stereo audio CODEC 1534. An FM antenna 1548 may be coupled to the FM radio tuner 1546. In addition, a stereo headset 1550 may be coupled to the stereo audio CODEC 1534. Other devices that may be coupled to the CPU 1504 include one or more digital (e.g., CCD or CMOS) cameras 1552.

[0116] A modem or RF transceiver 1554 may be coupled to the analog signal processor 1508 and the CPU 1504. An RF switch 1556 may be coupled to the RF transceiver 1554 and the RF antenna 1558. Additionally, a keypad 1560, a mono headset 1562 with a microphone, and a vibrator device 1564 may be coupled to the analog signal processor 1508.

[0117] SoC 1502 may have one or more internal or on-chip thermal sensors 1570A and may be coupled to one or more external or off-chip thermal sensors 1570B. An analog-to-digital converter ("ADC") controller 1572 may convert the voltage drop produced by thermal sensors 1570A and 1570B into a digital signal. A power supply 1574 and a power management integrated circuit ("PMIC") 1576 may provide power to SoC 1502.

[0118] The firmware or software may be stored in any of the above-described memories, such as DRAM 1530 or 1531, SRAM 1528, etc., or may be stored in local memory that is directly accessible by the processor hardware executing the software or firmware. The execution of such firmware or software may control aspects of any of the above-described methods, or configure aspects of any of the above-described systems. Any such memory or other non-transitory storage medium in which firmware or software is stored in a computer-readable form for execution by processor hardware may be an example of a "computer-readable medium," as that term is understood in the patent dictionary.

[0119] Alternative embodiments will become apparent to those skilled in the art to which the present invention pertains.Thus, while selected aspects have been shown and described in detail, it will be appreciated that various substitutions and changes may be made thereto.

[0120] Implementation examples are described in the following numbered clauses:

[0121] 1. A system for controlling a data cache, comprising:

[0122] a plurality of data storage structures, collectively having an organization corresponding to the structural organization of a dynamic random access memory (DRAM); and

[0123] A cache controller system configured to:

[0124] receiving multiple transaction requests;

[0125] storing data associated with the transaction requests in one or more data storage structures selected from a plurality of data storage structures based on a memory address associated with each transaction request; and

[0126] A number of data storage structures are used to control data transfer to the DRAM.

[0127] 2. The system of clause 1, wherein each of the plurality of data storage structures is a linked list.

[0128] 3. The system of clause 1, wherein each of the plurality of data storage structures corresponds to one of the plurality of memory banks of DRAM.

[0129] 4. A system according to clause 3, wherein the cache controller system is configured to:

[0130] receiving a plurality of DRAM write requests having associated memory addresses; and

[0131] Cache address information associated with the plurality of DRAM write requests is stored in corresponding selected data storage structures selected based on memory bank addresses associated with the DRAM write requests.

[0132] 5. The system of clause 4, wherein the cache controller system is configured to control data transfer to the DRAM by being configured to:

[0133] Selecting among multiple data storage structures; and

[0134] Cache data is evicted to DRAM from a location in the data cache indicated by data stored in the selected data storage structure.

[0135] 6. The system of clause 5, wherein the cache controller system is configured to select among the plurality of data storage structures based on a sequence.

[0136] 7. A system according to clause 6, wherein the sequence is based on round robin selection.

[0137] 8. A system according to clause 7, wherein the sequence is also based on DRAM page hit information stored in the data storage structure.

[0138] 9. The system of clause 5, wherein the cache controller system is configured to select between a first subset of the plurality of data storage structures associated with a first bank of DRAM and a second subset of the plurality of data storage structures associated with a second bank of DRAM.

[0139] 10. The system of clause 5, wherein the cache controller system is configured to selectively enable eviction of cache data based on at least one threshold level of cache dirtiness.

[0140] 11. A method for controlling a data cache, comprising:

[0141] receiving multiple transaction requests;

[0142] storing data associated with the transaction requests in one or more data storage structures selected from a plurality of data storage structures based on a memory address associated with each transaction request; and

[0143] Data transfer to a dynamic random access memory (DRAM) is controlled using a plurality of data storage structures, wherein the plurality of data storage structures collectively have an organization corresponding to the structural organization of the DRAM.

[0144] 12. The method of clause 11, wherein storing the data associated with the transaction request comprises storing the data associated with the transaction request in a plurality of linked lists.

[0145] 13. The method of clause 11, wherein each of the plurality of data storage structures corresponds to one of a plurality of memory banks of DRAM.

[0146] 14. A method according to clause 13, wherein:

[0147] Receiving a plurality of transaction requests includes receiving a plurality of DRAM write requests having associated memory addresses; and

[0148] Storing data associated with the transaction request includes storing cache address information associated with the plurality of DRAM write requests in corresponding selected data storage structures selected based on memory bank addresses associated with the DRAM write requests.

[0149] 15. The method of clause 14, wherein controlling data transfer to the DRAM comprises:

[0150] Selecting among multiple data storage structures; and

[0151] Cache data is evicted to DRAM from a location in the data cache indicated by data stored in the selected data storage structure.

[0152] 16. The method of clause 15, wherein selecting among the plurality of data storage structures is based on a sequence.

[0153] 17. A method according to clause 16, wherein the sequence is based on round robin selection.

[0154] 18. The method of clause 17, wherein the sequence is further based on DRAM page hit information stored in the data storage structure.

[0155] 19. The method of clause 15, wherein selecting among the plurality of data storage structures comprises selecting between a first subset of the plurality of data storage structures associated with a first memory bank of the DRAM and a second subset of the plurality of data storage structures associated with a second memory bank of the DRAM.

[0156] 20. The method of clause 15, wherein controlling data transfer to the DRAM comprises selectively enabling eviction of cache data based on at least one threshold level of cache dirtiness.

[0157] 21. A system for controlling a data cache, comprising:

[0158] means for receiving a plurality of transaction requests;

[0159] means for storing data associated with the transaction requests in one or more data storage structures selected from a plurality of data storage structures based on a memory address associated with each transaction request; and

[0160] Apparatus for controlling data transfer to a dynamic random access memory (DRAM) using a plurality of data storage structures, wherein the plurality of data storage structures collectively have an organization corresponding to the structural organization of the DRAM.

[0161] 22. The system of clause 21, wherein the means for storing data associated with the transaction request comprises means for storing the data associated with the transaction request in a plurality of linked lists.

[0162] 23. The system of clause 21, wherein each of the plurality of data storage structures corresponds to one of the plurality of memory banks of DRAM.

[0163] 24. A system according to clause 23, wherein:

[0164] The means for receiving a plurality of transaction requests comprises means for receiving a plurality of DRAM write requests having associated memory addresses; and

[0165] Means for storing data associated with a transaction request include means for storing cache address information associated with a plurality of DRAM write requests in corresponding selected data storage structures selected based on memory bank addresses associated with the DRAM write requests.

[0166] 25. The system of clause 24, wherein the means for controlling data transfer to the DRAM comprises:

[0167] means for selecting among a plurality of data storage structures; and

[0168] Means for evicting cache data from a location in the data cache indicated by the data stored in the selected data storage structure to the DRAM.

[0169] 26. The system of clause 25, wherein the means for selecting among the plurality of data storage structures is based on a sequence.

[0170] 27. A system according to clause 26, wherein the sequence is based on round robin selection.

[0171] 28. A system according to clause 27, wherein the sequence is also based on DRAM page hit information stored in the data storage structure.

[0172] 29. A system according to clause 25, wherein the means for selecting among a plurality of data storage structures comprises means for selecting between a first subset of a plurality of data storage structures associated with a first memory bank of DRAM and a second subset of a plurality of data storage structures associated with a second memory bank of DRAM.

[0173] 30. The system of clause 25, wherein the means for controlling data transfer to the DRAM comprises means for selectively enabling eviction of cache data based on at least one threshold level of cache dirtiness.

[0174] 31. A computer readable medium for controlling a data cache, comprising a non-transitory computer readable medium having stored thereon instructions in computer executable form, the instructions, when executed by a processor, configuring the processor to:

[0175] receiving multiple transaction requests;

[0176] storing data associated with the transaction requests in one or more data storage structures selected from a plurality of data storage structures based on a memory address associated with each transaction request; and

[0177] Data transfer to a dynamic random access memory (DRAM) is controlled using a plurality of data storage structures, each of the plurality of data storage structures corresponding to one of a plurality of memory banks of the DRAM.

[0178] 32. The computer-readable medium of clause 31, wherein the processor is configured to store data associated with the transaction requests by being configured to store the data associated with the transaction requests in a plurality of linked lists.

Claims

1. A system for controlling a data cache, comprising: a plurality of data storage structures collectively having an organization corresponding to the structural organization of a dynamic random access memory DRAM, wherein each of the plurality of data storage structures is a linked list queue organized in a manner corresponding to the bank, memory bank group, and memory bank organization of the DRAM; and each linked list queue corresponds to a memory bank of the plurality of memory banks of the DRAM; as well as A cache controller system configured to: receiving multiple transaction requests; storing data associated with each transaction request in one or more of the data storage structures selected from the plurality of data storage structures based on a memory address associated with the transaction request; controlling data transfer to the DRAM using the plurality of data storage structures; selecting among the plurality of data storage structures according to a sequence, wherein the sequence is based on at least one of round-robin selection and DRAM page hit information stored in the data storage structure; as well as Cache data is evicted from a location in the data cache indicated by the data stored in the selected data storage structure to the DRAM.

2. The system of claim 1, wherein each linked list queue has a data field for a bank, a data field for a memory bank group, and a data field for a memory bank corresponding to the DRAM.

3. The system of claim 1, wherein the linked list queue is organized by subsets, wherein each subset corresponds to a memory bank of the DRAM.

4. The system of claim 1 , wherein the cache controller system is configured to: receiving a plurality of DRAM write requests having associated memory addresses; and Cache address information associated with the plurality of DRAM write requests is stored in a corresponding selected data storage structure selected based on a memory bank address associated with the DRAM write requests.

5. The system of claim 1 , wherein the cache controller system is configured to select between a first subset of the plurality of data storage structures associated with a first memory bank of the DRAM and a second subset of the plurality of data storage structures associated with a second memory bank of the DRAM. 6 . The system of claim 1 , wherein the cache controller system is configured to selectively enable eviction of cache data based on at least one threshold level of cache dirtiness.

7. A method for controlling a data cache, comprising: receiving multiple transaction requests; storing data associated with each transaction request in one or more data storage structures selected from a plurality of data storage structures based on a memory address associated with the transaction request; Controlling data transfer to a dynamic random access memory DRAM using the plurality of data storage structures, wherein the plurality of data storage structures collectively have an organization corresponding to the structural organization of the DRAM, wherein each of the plurality of data storage structures is a linked list queue organized in a manner corresponding to the bank, memory bank group, and memory bank organization of the DRAM; and each linked list queue corresponds to one of the plurality of memory banks of the DRAM; selecting among the plurality of data storage structures according to a sequence, wherein the sequence is based on at least one of round-robin selection and DRAM page hit information stored in the data storage structure; as well as Cache data is evicted from a location in the data cache indicated by the data stored in the selected data storage structure to the DRAM.

8. The method of claim 7, wherein each linked list queue has a data field for a bank, a data field for a memory bank group, and a data field for a memory bank corresponding to the DRAM.

9. The method of claim 7, wherein the linked list queue is organized by subsets, wherein each subset corresponds to a memory bank of the DRAM.

10. The method according to claim 7, wherein: Receiving a plurality of transaction requests includes receiving a plurality of DRAM write requests having associated memory addresses; as well as Storing data associated with the transaction requests includes storing cache address information associated with the plurality of DRAM write requests in corresponding selected data storage structures selected based on memory bank addresses associated with the DRAM write requests.

11. The method of claim 7, wherein selecting among the plurality of data storage structures comprises selecting between a first subset of the plurality of data storage structures associated with a first memory bank of the DRAM and a second subset of the plurality of data storage structures associated with a second memory bank of the DRAM.

12. The method of claim 7, wherein controlling data transfer to the DRAM comprises selectively enabling eviction of cache data based on at least one threshold level of cache dirtyness.

13. A system for controlling a data cache, comprising: means for receiving a plurality of transaction requests; means for storing data associated with each transaction request in one or more data storage structures selected from a plurality of data storage structures based on a memory address associated with the transaction request; means for controlling data transfer to a dynamic random access memory DRAM using the plurality of data storage structures, wherein the plurality of data storage structures collectively have an organization corresponding to the structural organization of the DRAM, each of the plurality of data storage structures is a linked list queue organized in a manner corresponding to the bank, memory bank group, and memory bank organization of the DRAM; and each linked list queue corresponds to one of the plurality of memory banks of the DRAM; means for selecting among the plurality of data storage structures according to a sequence, wherein the sequence is based on at least one of round-robin selection and DRAM page hit information stored in the data storage structure; as well as Means for evicting cache data from a location in the data cache indicated by the data stored in the selected data storage structure to the DRAM.

14. The system of claim 13, wherein each linked list queue has a data field for a bank, a data field for a memory bank group, and a data field for a memory bank corresponding to the DRAM.

15. The system of claim 13, wherein the linked list queue is organized by subsets, wherein each subset corresponds to a bank of the DRAM.

16. The system of claim 13, wherein: The means for receiving a plurality of transaction requests includes means for receiving a plurality of DRAM write requests having associated memory addresses; as well as The means for storing data associated with the transaction request includes means for storing cache address information associated with the plurality of DRAM write requests in corresponding selected data storage structures selected based on memory bank addresses associated with the DRAM write requests.

17. A system according to claim 13, wherein the device for selecting among the plurality of data storage structures includes a device for selecting between a first subset of the plurality of data storage structures associated with a first memory bank of the DRAM and a second subset of the plurality of data storage structures associated with a second memory bank of the DRAM.

18. The system of claim 13, wherein the means for controlling data transfer to the DRAM comprises means for selectively enabling eviction of cache data based on at least one threshold level of cache dirtiness.

19. A computer readable medium for controlling a data cache, comprising a non-transitory computer readable medium having stored thereon instructions in a computer executable form, the instructions, when executed by a processor, configuring the processor to: receiving multiple transaction requests; storing data associated with each transaction request in one or more data storage structures selected from a plurality of data storage structures based on a memory address associated with the transaction request; controlling data transfer to a dynamic random access memory DRAM using the plurality of data storage structures, each of the plurality of data storage structures corresponding to one of a plurality of memory banks of the DRAM, wherein each of the plurality of data storage structures is a linked list queue organized in a manner corresponding to the bank, memory bank group, and memory bank organization of the DRAM; and each linked list queue corresponds to one of a plurality of memory banks of the DRAM; selecting among the plurality of data storage structures according to a sequence, wherein the sequence is based on at least one of round-robin selection and DRAM page hit information stored in the data storage structure; as well as Cache data is evicted from a location in the data cache indicated by the data stored in the selected data storage structure to the DRAM.

20. The computer-readable medium of claim 19, wherein each linked list queue has a data field for a bank, a data field for a memory bank group, and a data field for a memory bank corresponding to the DRAM.

21. The computer-readable medium of claim 19, wherein the processor is further configured to: receiving a plurality of DRAM write requests having associated memory addresses; and Cache address information associated with the plurality of DRAM write requests is stored in corresponding selected data storage structures selected based on the bank addresses associated with the DRAM write requests.

22. The computer-readable medium of claim 19, wherein the processor is further configured to: A selection is made between a first subset of the plurality of data storage structures associated with a first memory bank of the DRAM and a second subset of the plurality of data storage structures associated with a second memory bank of the DRAM.

23. The computer-readable medium of claim 19, wherein the processor is further configured to: Eviction of cache data is selectively enabled based on at least one threshold level of cache dirtiness.

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