Aggregating multiple data streams over a communication link

Abstract

A host device establishes a wireless communication link with a client device and implements a wired communication standard over the link to transmit a first data stream. To increase data throughput in compliance with the standard, the host device replaces synchronization information in packets to be transmitted during a first synchronization frame with configuration information indicating packet-switched data of a second data stream to be transmitted or received during a second synchronization frame. The host device transmits or receives the packet-switched data of the second data stream to or from the client device via the wireless communication link during the second synchronization frame. The host device can transmit or receive the packet-switched data of the second data stream during a delay or idle period between transmission and / or reception of packets of the first data stream via the wireless communication link in accordance with the wired communication standard.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 180,958, filed April 28, 2021, entitled “AGGREGATING MULTIPLE DATA STREAMSON A COMMUNICATION LINK,” the entire contents of which are incorporated herein by reference for all purposes. Background Technology

[0003] This disclosure relates in general to data communication, and more specifically to increasing data throughput on communication links between communication devices.

[0004] Electronic devices can communicate with each other by sending and / or receiving data streams over a communication link using communication standards. To increase data throughput, electronic devices can communicate with each other by sending and / or receiving multiple bidirectional data streams over a link using multiple communication standards. However, using multiple communication standards over a communication link to implement multiple bidirectional data streams may increase hardware complexity in electronic devices, require the use of higher-order modulation and / or higher frequency bandwidth, use of complex protocol adapter layers and / or dedicated software drivers, and / or increase resource consumption (e.g., current). Summary of the Invention

[0005] The following outlines some of the embodiments disclosed herein. It should be understood that these aspects are presented merely to provide the reader with a concise overview of these particular embodiments, and are not intended to limit the scope of this disclosure. In fact, this disclosure may cover many aspects that may not be set forth below.

[0006] In one embodiment, a method includes: establishing a wireless communication link with an electronic device; transmitting data of a first data stream to the electronic device via the wireless communication link using a wired communication standard; and generating packets to be transmitted during a first synchronization frame of the wired communication standard by replacing synchronization information with configuration information indicating packet-switched data of a second data stream to be transmitted or received during a second synchronization frame of the wired communication standard. The method also includes transmitting packets to the electronic device via the wireless communication link, receiving acknowledgments from the electronic device via the wireless communication link, and transmitting or receiving packet-switched data of the second data stream from the electronic device via the wireless communication link.

[0007] In another embodiment, an electronic device includes: one or more antennas, a transmitting circuit that transmits signals via the one or more antennas, a receiving circuit that receives signals from the one or more antennas, and at least one processor coupled to the transmitting circuit and the receiving circuit. The at least one processor establishes a wireless communication link with another electronic device, causing the receiving circuit to receive data of a first data stream from the other electronic device via the wireless communication link using a wired communication standard, and causing the receiving circuit to receive a first packet from the other electronic device via the wireless communication link during a first synchronization frame of the wired communication standard. The at least one processor also generates and processes a second packet according to the wired communication standard in response to determining that the first packet has configuration information associated with packet-switched data of a second data stream to be transmitted or received during a second synchronization frame of the wired communication standard, and causes the receiving circuit to receive packet-switched data of the second data stream from the other electronic device or causes the transmitting circuit to transmit packet-switched data of the second data stream during the second synchronization frame of the wired communication standard.

[0008] In yet another embodiment, an electronic device includes: one or more antennas, a transmitting circuit for transmitting signals from the one or more antennas, a receiving circuit for receiving signals from the one or more antennas, and at least one processor coupled to the transmitting circuit and the receiving circuit. The at least one processor determines a delay between transmitting a first packet of a first data stream via a wireless communication link according to a wired communication standard and transmitting or receiving a second packet of the first data stream. The at least one processor also instructs packet-swapping data to be transmitted during the delay period for the second data stream, and causes the transmitting circuit to transmit the first packet of the first data stream via the wireless communication link using the wired communication standard. The at least one processor also causes the transmitting circuit to transmit packet-swapping data of the second data stream via the wireless communication link during the delay period, and causes the transmitting circuit to transmit the second packet of the first data stream via the wireless communication link using the wired communication standard or causes the receiving circuit to receive the second packet of the first data stream.

[0009] Various modifications to the features described above may exist with respect to various aspects of this disclosure. Other features may also be incorporated into these aspects. These modifications and additional features may exist individually or in any combination. For example, the various features discussed below relating to one or more of the illustrated embodiments may be incorporated individually or in any combination into any of the foregoing aspects of this disclosure. The brief summary presented above is intended only to familiarize the reader with specific aspects and context of embodiments of this disclosure and does not limit the claimed subject matter. Attached Figure Description

[0010] Various aspects of this disclosure can be better understood by reading the following detailed description and referring to the accompanying drawings, wherein similar figures refer to similar parts.

[0011] Figure 1 This is a block diagram of an electronic device according to an embodiment of the present disclosure;

[0012] Figure 2 The feasibility of the implementation scheme according to this disclosure Figure 1 Functional block diagram of electronic device components;

[0013] Figure 3 This describes the transmission and reception of multiple data streams on a wireless communication link according to an embodiment of this disclosure. Figure 2 A schematic diagram of an electronic device;

[0014] Figure 4 It is based on the implementation scheme of this disclosure. Figure 1 A schematic diagram of a transmitter for an electronic device that can wirelessly transmit packet-switched data in synchronous packets;

[0015] Figure 5 It is based on the implementation scheme of this disclosure. Figure 1 A schematic diagram of a receiver for an electronic device that can wirelessly receive packet-switched data in synchronous packets;

[0016] Figure 6 It is a timing diagram of replacing the synchronization information of the first data stream with the configuration information and / or packet-switched data of the second data stream according to the implementation scheme of this disclosure;

[0017] Figure 7 It is for use in accordance with the embodiments of this disclosure Figure 1 A flowchart of a method for an electronic device (e.g., a host device) to wirelessly transmit and / or receive a second data stream in an SOF packet;

[0018] Figure 8 It is for use in accordance with the embodiments of this disclosure Figure 1 A flowchart of a method for an electronic device (e.g., a client device) to wirelessly receive and / or transmit a second data stream in an SOF packet;

[0019] Figure 9 It is based on the implementation scheme of this disclosure. Figure 1 A schematic diagram of a transmitter of an electronic device that can wirelessly transmit packet-switched data of a second data stream during the delay between transmitting or receiving packets of a first data stream;

[0020] Figure 10 It is based on the implementation scheme of this disclosure. Figure 1 A schematic diagram of a receiver for an electronic device that can wirelessly receive packet-switched data of a second data stream during the delay between receiving or transmitting packets of a first data stream;

[0021] Figure 11It is based on the implementation scheme of this disclosure. Figure 1 Timing diagram of packet-switched data sent and / or received during the delay period of sending a first data stream using USB 2.0 bulk, interrupt, or control outgoing or write transfer types;

[0022] Figure 12 It is based on the implementation scheme of this disclosure. Figure 1 A timing diagram of packet-switched data transmission and / or reception of a second data stream during the delay period when an electronic device (e.g., a host device) uses USB 2.0 or similar outgoing transmission type to transmit the first data stream;

[0023] Figure 13 It is based on the implementation scheme of this disclosure. Figure 1 Timing diagram of packet-switched data sent and / or received by electronic devices (e.g., host devices) using USB 2.0 bulk, interrupt, or control incoming transfer types during the delay period of receiving a first data stream;

[0024] Figure 14 It is based on the implementation scheme of this disclosure. Figure 1 Timing diagram of packet-switched data transmission and / or reception of a second data stream during the delay period of receiving a first data stream when an electronic device (e.g., a host device) uses USB 2.0 or similar transmission type;

[0025] Figure 15 It is a table indicating the bus allocation according to the USB 2.0 standard;

[0026] Figure 16 This is a table indicating the maximum amount of latency available according to the USB 2.0 standard;

[0027] Figure 17 This is a table of commutation delays and / or maximum packet-switched data throughput during idle time for scenarios that maximize the use of the wireless communication link for USB 2.0 data, according to the instructions of the embodiments of this disclosure;

[0028] Figure 18 This is a table of inter-packet delay and commutation delay, as well as maximum packet-switched data throughput during idle time, for scenarios that maximize the use of the wireless communication link for USB 2.0 data, according to the instructions of the embodiments of this disclosure.

[0029] Figure 19A and Figure 19B It is for use in accordance with the embodiments of this disclosure Figure 1 A flowchart of a method for an electronic device (e.g., a host device) to wirelessly transmit and / or receive a second data stream during a delay between packets of a first data stream;

[0030] Figure 20 It is for use in accordance with the embodiments of this disclosure Figure 1 A flowchart of a method for an electronic device (e.g., a client device) to wirelessly receive and / or transmit a second data stream during a delay between packets of receiving or transmitting a first data stream;

[0031] Figure 21A and Figure 21B It is for use in accordance with the embodiments of this disclosure Figure 1 A flowchart of a method for an electronic device (e.g., a host device) to extend the delay between packets transmitting a first data stream, thereby enabling the transmission or reception of more packets of a second data stream during the extended delay;

[0032] Figure 22 It is for use in accordance with the embodiments of this disclosure Figure 1 A flowchart of a method for an electronic device (e.g., a client device) to receive or transmit additional packets of a second data stream during an extended delay between receiving packets of a first data stream;

[0033] Figure 23 It is based on the implementation scheme of this disclosure. Figure 9 A more detailed schematic diagram of the transmitter; and

[0034] Figure 24 It is based on the implementation scheme of this disclosure. Figure 10 A more detailed schematic diagram of the receiver. Detailed Implementation

[0035] One or more specific implementations will be described below. To provide a brief description of these implementations, not all characteristics of the actual implementations are described in this specification. It should be understood that in the development of any such actual implementation, as in any engineering or design project, decisions must be made specific to many implementations to achieve the developer's specific objectives, such as compliance with system-related and business-related constraints that may vary from one implementation to another. Furthermore, it should be understood that such development work can be complex and time-consuming, but will still be routine work of design, fabrication, and manufacturing for those skilled in the art who benefit from this disclosure.

[0036] When describing elements of various embodiments of this disclosure, the articles “an” and “the” are intended to refer to the presence of one or more of the elements. The terms “comprising,” “including,” and “having” are intended to be included and to indicate the presence of additional elements besides those listed. Additionally, it should be understood that reference to “an embodiment” or “an embodiment” of this disclosure is not intended to be construed as excluding the existence of additional embodiments also incorporating the cited features. Furthermore, specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. The use of the terms “generally,” “closely,” “about,” and / or “substantially” should be understood to mean including close to the target (e.g., design, value, quantity), such as within limits of any suitable or conceivable error (e.g., within 0.1% of the target, within 1% of the target, within 5% of the target, within 10% of the target, within 25% of the target, etc.).

[0037] This disclosure relates to increasing data throughput on communication links (e.g., wired or wireless) between communication devices. Electronic devices can communicate with each other by sending and / or receiving data streams via a communication link using communication standards. To increase data throughput (e.g., data transmission or signaling), electronic devices can communicate with each other by sending and / or receiving multiple bidirectional data streams using one or more communication standards on a radio frequency link. For example, a first electronic device (e.g., a host device) can establish a wireless communication link with a second electronic device (e.g., a client device) using any suitable radio frequency communication technology, including non-standard millimeter-wave (mmWave) technologies operating in extremely high frequency (EHF) bands as specified by the International Telecommunication Union (ITU). The EHF band can include radio frequencies in the electromagnetic spectrum from 30 GHz to 300 GHz, such as 60 GHz. Thus, the wireless communication link may be referred to herein as an EHF wireless communication link. Additionally, the host device can send or receive a first data stream, such as a Universal Serial Bus (USB) 2.0 data stream, on the wireless communication link. That is, the wireless communication link can replicate or virtualize the USB 2.0 communication link, even if USB 2.0 is a wired communication standard. Therefore, the host device and client device can send and / or receive the first data stream, making it compliant with the USB 2.0 standard.

[0038] It may be desirable to implement the USB 2.0 standard on a wireless communication link because of its ability to achieve high data throughput. To aggregate additional data streams to be transmitted on the wireless communication link, the USB 2.0 endpoint may terminate at the transmitter of the host device. The USB 2.0 data stream may then be packetized with other data streams (e.g., including USB 2.0 data streams, other USB generated data streams, Universal Asynchronous Receiver / Transmitter (UART) data streams, Serial Wire Debug (SWD) data streams, Serial Peripheral Interface (SPI) data streams, and Inter-Integrated Circuit (I2C) data streams, etc.) and transmitted as packets to the receiver of the client device on the wireless communication link. The receiver may then decompose the packet data into corresponding data streams and process these data streams. For example, the extracted USB 2.0-related data may be forwarded to the USB 2.0 host controller in the receiver, which may reconstruct the USB 2.0 interface. While this disclosure illustrates an implementation of a USB 2.0 data stream on an EHF wireless communication link 38, it should be understood that the implementation may also be applied to other communication standards or technologies (e.g., wired or wireless). For example, the wireless communication link 38 may be... The link and / or may contain one or more different types of data streams, including any version of the USB data stream, such as USB 1 (e.g., USB 1.x), USB 2.0 (e.g., USB 2.x), USB 3 (e.g., USB 3.x), USB 4 (e.g., USB 4.x), the Low Voltage Differential Signaling (LVDS) standard used by the DisplayPort digital display interface, etc.

[0039] However, terminating the wireless USB 2.0 link at the host device may increase the circuitry, components, and / or complexity at the host device (e.g., in both logic and memory aspects), require additional resources (e.g., memory and processing resources), and occupy valuable space within the host device. Furthermore, to achieve the high data transfer rates available under USB 2.0 (e.g., 480 megabits per second (Mbps)) for high-speed operation, the data transfer rate of conventional radio frequency communication links may need to be increased. This may mean employing higher-order modulation and / or higher frequency bandwidth for data transfer, increasing circuitry, components, and / or complexity at both devices, using additional resources (e.g., memory and processing resources), and occupying valuable space within the device. Additionally, operating the USB 2.0 endpoints in an electronic device may increase resource consumption (e.g., current).

[0040] The embodiments described herein provide various systems, apparatuses, and techniques to increase data throughput (e.g., transmission rate) on communication links (e.g., wired communication links, wireless communication links) between communication devices implementing wired communication standards (e.g., USB 2.0, USB 3, USB 4, etc.) by utilizing known delay times in wired communication standards to transmit and receive additional data (e.g., referred to herein as packet switching or "PEX" data) on the communication link. For example, embodiments of this disclosure can locally stream USB 2.0 data packets on a wireless communication link while simultaneously transmitting and receiving additional packet-switched data across the communication link using known USB 2.0 delay times. Therefore, implementing the USB device and host controller within the transceiver of the communication device can be avoided. Furthermore, the data rate for USB 2.0 data across the communication link can be maintained at no more than 480 Mbps, thereby avoiding the implementation of higher-order modulation and / or higher frequency bandwidths. Additionally, when packet-switched data and USB 2.0 data are aggregated on a communication link, the combined data rate may exceed 480 Mbps (e.g., greater than 520 Mbps, greater than 640 Mbps, greater than 720 Mbps, greater than 1000 Mbps, etc.).

[0041] Specifically, some disclosed embodiments enable a first electronic device (e.g., a host device) to initially establish a wireless communication link with a second electronic device (e.g., a client device), such as an EHF communication link. The host device may subsequently implement a wired communication standard (e.g., the USB 2.0 standard) on the wireless communication link, enabling it to send data from a first data stream (e.g., a USB 2.0 data stream) to and / or receive data from the first data stream from the client device. The host device may generate deterministic packets according to the wired communication standard, and in some cases, these deterministic packets may be removed during transmission on the wireless communication link and replaced by packet-switched data (or “PEX” data) of a second data stream (e.g., including another USB 2.0 data stream, another USB generated data stream, an SWD data stream, a UART data stream, an SPI data stream, an I2C data stream, etc.). A deterministic packet may refer to a packet sent or received between the host device and the client device that has timing, content, fields, etc., known and expected by both devices. Therefore, deterministic packets are pre-defined and anticipated by both devices, enabling removal by the host device and regeneration by the client device, even if the client device can receive alternative packets from the host device to replace the deterministic packets. Packet-switched data can refer to any suitable type of data (e.g., payload data, configuration data, housekeeping data, control data, timing data, etc.) of any suitable standard or protocol (e.g., USB 2.0, another USB standard, UART, SPI, I2C, SWD, audio) to be exchanged between the host and client devices. Upon receiving packet-switched data, the client device can process the packet-switched data and recreate the deterministic packets removed by the host device to conform to wired communication standards. This enables highly flexible wireless transmission (multiple possible data streams) of packet-switched data while conforming to wired communication standards.

[0042] For example, a host device can generate synchronization packets to be sent during a first synchronization frame (e.g., a Start-of-Frame (SOF) packet) according to a wired communication standard by replacing synchronization information (such as synchronization information used for synchronizing isochronous and interrupting data transmission) with configuration information indicating packet-switched data to be sent or received during a second synchronization frame according to the wired communication standard. In the USB 2.0 standard, a host device can transmit eight SOF packets per frame to a client device, thus dividing a one-millisecond frame into eight 125-microsecond microframes. The portion of each microframe dedicated to SOF packets (e.g., between 158.33 nanoseconds (ns) and 200 ns) is collectively referred to herein as a “synchronization frame,” and the SOF packets are collectively referred to herein as “synchronization packets.” Since some synchronization packets can still be used to facilitate or perform synchronization or interruption functions between devices, in some cases, only some of the synchronization packets may be replaced with configuration or packet-switched data. The host device can then send the synchronization packets to the client device via a wireless communication link. After the client device acknowledges receipt of the synchronization packet, the host device can send or receive packet-switched data of the second data stream from the client device via a wireless communication link. In this way, in addition to the first data stream in a regular data packet according to the USB 2.0 standard, the host device can also wirelessly send or receive a second data stream in the synchronization packet. While the synchronization packet serves as an example of a deterministic packet that can be removed and replaced by the host device and recreated by the client device, it should be understood that the disclosed implementation can be applied to any suitable deterministic packet.

[0043] Therefore, the client device can initially establish a wireless communication link with the host device using wireless communication technology, and receive a first synchronization packet from the host device via the wireless communication link during the first synchronization frame according to the wired communication standard. If the client device determines that the first synchronization packet includes configuration information associated with packet-switched data of the second data stream to be sent or received during the second synchronization frame according to the wired communication standard, the client device can generate and process the second synchronization packet according to the wired communication standard. That is, to comply with the USB 2.0 standard, SOF packets should be received at the beginning of each 125-microsecond microframe. Because the host device sends configuration information to the client device instead of SOF packets to comply with the USB 2.0 standard, the client device should still process SOF packets during the first synchronization frame. In this way, the client device can generate and process the second synchronization packet according to the wired communication standard. The client device then sends or receives packet-switched data of the second data stream from the host device during the second synchronization frame. Similar to the configuration information, the client device can generate and process a third synchronization packet according to the wired communication standard, replacing the packet-switched data of the second data stream sent or received during the second synchronization frame. That is, because the client device sends or receives packet-switched data in the second data stream instead of receiving SOF packets from the host device, in order to comply with the USB 2.0 standard, the client device should still process SOF packets during the second synchronization frame. In this way, the client device can generate and process the third synchronization packets according to wired communication standards. In this manner, in addition to the first data stream in the regular data packets according to the USB 2.0 standard, the client device can also wirelessly send or receive a second data stream in synchronization packets.

[0044] Additional or alternative embodiments provide various systems, apparatuses, and techniques to increase data throughput between communication devices on a wireless communication link by enabling the transmitting device to determine a delay (e.g., a time gap) between a first packet and a second packet of a first data stream transmitted and / or received via a wireless communication link according to a wired communication standard. For example, the delay may correspond to a reversal delay between a host device transmitting a packet (e.g., a data packet) to a client device and receiving a response packet (e.g., a handshake packet) from the client device. As another example, the delay may correspond to an inter-packet delay between the host device transmitting a first packet (e.g., a token packet) and a second packet (e.g., a data packet). The host device may then instruct packet-swapping data to be transmitted or received during the delay and transmit the first data packet via the first wireless communication link using a wired communication standard. The host device may transmit or receive packet-swapping data of the second data stream via the wireless communication link during the delay and transmit or receive the second packet of the first data stream using a wired communication standard after the delay. In this way, the host device can wirelessly transmit or receive the second data stream during the delay between transmitting or receiving packets of the first data stream.

[0045] The client device can thus receive a first packet of the first data stream, and an indication that packet-switched data of the second data stream will be received or transmitted during the delay between receiving the first packet and transmitting or receiving the second packet of the first data stream. Thus, the client device can receive or transmit packet-switched data of the second data stream during the delay, and subsequently, after the delay, the client device can receive or transmit the second packet of the first data stream via a second wireless communication link. In this way, the client device can wirelessly receive or transmit the second data stream during the delay between receiving packets of the first data stream.

[0046] In some cases, the host device may determine to extend the delay between packets of the first data stream, thereby increasing the time between transmitted packets and increasing the amount of packet-switched data in the second data stream transmitted or received during the extended delay. For example, the host device may determine to extend the delay because the size of the packet-switched data to be transmitted is greater than a threshold size. In some embodiments, the host device may include a buffer to delay or time-shift packets of the first data stream during the extended delay, which can then be transmitted after the extended delay has elapsed. Thus, in response to determining the extended delay, the host device may indicate an extended delay between the first and second packets of the first data stream and will transmit or receive packet-switched data in the second data stream during the extended delay. The host device may then transmit the first packets of the first data stream via a wireless communication link using a wired communication standard, and transmit or receive packet-switched data via the wireless communication link during the extended delay. The host device may cause the buffer to delay or time-shift the second packets of the first data stream, and transmit the second packets via a wireless communication link using a wired communication standard in response to determining that the extended delay has elapsed. In this way, the client device can wirelessly transmit or receive an increased amount of the second data stream by extending the delay between packets of the first data stream.

[0047] In this way, the client device can receive the first packets of the first data stream via a wireless communication link using a wired communication standard. In response to receiving an indication that the delay between receiving the first and second packets of the first data stream has been extended and that packet-switched data of the second data stream will be received or transmitted during the extended delay, the client device can receive or transmit packet-switched data via the wireless communication link during the extended delay. After the extended delay has elapsed, the client device can receive the second packets of the first data stream via the first wireless communication link using a wired communication standard. In this manner, the client device can wirelessly receive or transmit an increased amount of the second data stream during the extended delay between receiving packets of the first data stream.

[0048] Alternatively or additionally, the currently disclosed embodiments can increase the data throughput between communication devices on a wireless communication link by enabling the transmission or reception of a second data stream between transactions of the first data stream. That is, there may be periods when communication devices do not perform transactions (e.g., idle time). For example, in the USB 2.0 standard, a transaction includes sending or receiving multiple packets, including token packets, data packets, and handshake packets. However, after the first transaction, there may be no data to be transmitted between the communication devices. At a subsequent time, it may be desirable to transmit data, and a second transaction can be performed. Between these two transactions is an idle time that can be used to send packets of the second data stream. In this way, devices can wirelessly send or receive an increased amount of second data stream between transactions of the first data stream.

[0049] In view of the above, Figure 1 This is a block diagram of an electronic device 10 according to an embodiment of the present disclosure. Referring to the foregoing discussion, a host device, a client device, or both may include electronic device 10. Among other things, electronic device 10 may include one or more processors 12 (collectively referred to herein as a single processor, which may be implemented in any suitable form of processing circuitry), memory 14, non-volatile storage device 16, display 18, input structure 22, input / output (I / O) interface 24, network interface 26, and power supply 29. Figure 1 The various functional blocks shown may include hardware elements (including circuitry), software elements (including computer code stored on a computer-readable medium), or a combination of both. Processor 12, memory 14, non-volatile storage device 16, display 18, input structure 22, input / output (I / O) interface 24, network interface 26, and / or power supply 29 may each be directly or indirectly communicatively coupled to each other (e.g., via or through another component, communication bus, network) to transmit and / or receive data between them. It should be noted that... Figure 1 This is merely one example of a specific implementation and is intended to illustrate the types of components that may exist in electronic device 10.

[0050] For example, electronic device 10 can represent a block diagram of any suitable computing device, including a desktop computer or laptop computer (e.g., one available from Apple Inc., Cupertino, California). Pro, MacBook mini or Mac (in the form of) portable electronic devices or handheld electronic devices such as wireless electronic devices or smartphones (e.g., available from Apple Inc. in Cupertino, California). (Model form), tablet computers (for example, those available from Apple in Cupertino, California) (in the form of a model), wearable electronic devices (e.g., Apple products available from Apple Inc. in Cupertino, California) (in the form of) and other similar devices. It should be noted that, Figure 1 The processor 12 and other related items herein may be generally referred to as "data processing circuitry". This data processing circuitry may be implemented wholly or partially as software, hardware, or any combination thereof. Furthermore, the processor 12 and... Figure 1Other related items may be a single, independent processing module, or may be incorporated, wholly or partially, into any of the other elements within the electronic device 10. Processor 12 may be implemented using a combination of a general-purpose microprocessor, microcontroller, digital signal processor (DSP), field-programmable gate array (FPGA), programmable logic device (PLD), controller, state machine, gated logic, discrete hardware components, dedicated hardware finite state machine, or any other suitable entity capable of performing computation or other manipulations of information. Processor 12 may perform the various functions described herein and below.

[0051] exist Figure 1 In the electronic device 10, a processor 12 may be operatively coupled to a memory 14 and a non-volatile storage device 16 to execute various algorithms. Such programs or instructions executed by the processor 12 may be stored in any suitable article of writing comprising one or more tangible computer-readable media. The tangible computer-readable media may include the memory 14 and / or the non-volatile storage device 16, individually or jointly, to store instructions or routines. The memory 14 and the non-volatile storage device 16 may include any suitable article of writing for storing data and executable instructions, such as random access memory, read-only memory, rewritable flash memory, hard disk drive, and optical disk. Furthermore, programs (e.g., operating systems) encoded on such computer program products may also include instructions executable by the processor 12 to enable the electronic device 10 to provide various functions.

[0052] In some embodiments, display 18 may facilitate a user's viewing of images generated on electronic device 10. In some embodiments, display 18 may include a touchscreen that facilitates user interaction with the user interface of electronic device 10. Furthermore, it should be understood that in some embodiments, display 18 may include one or more liquid crystal displays (LCDs), light-emitting diode (LED) displays, organic light-emitting diode (OLED) displays, active-matrix organic light-emitting diode (AMOLED) displays, or some combination of these and / or other display technologies.

[0053] The input structure 22 of electronic device 10 allows a user to interact with electronic device 10 (e.g., press a button to increase or decrease the volume level). Like network interface 26, I / O interface 24 enables electronic device 10 to interact with a variety of other electronic devices. In some embodiments, I / O interface 24 may include I / O ports for hardwired connections for charging and / or content manipulation using standard connectors and protocols such as the Lightning connector supplied by Apple Inc. of Cupertino, California, Universal Serial Bus (USB), or other similar connectors and protocols. Network interface 26 may include, for example, one or more interfaces for Personal Area Network (PAN), such as... Network; Local Area Network (LAN) or Wireless Local Area Network (WLAN), such as a protocol using one of the IEEE 802.11x series protocols (e.g., Networks; and / or wide area networks (WANs), such as any standards related to the 3rd Generation Partnership Project (3GPP), including, for example, third-generation (3G) cellular networks, Universal Mobile Telecommunications System (UMTS), fourth-generation (4G) cellular networks, Long Term Evolution (LTE) networks. Cellular networks, Long Term Evolution License Auxiliary Access (LTE-LAA) cellular networks, fifth-generation (5G) cellular networks and / or New Radio (NR) cellular networks, satellite networks, etc. Specifically, network interface 26 may include, for example, one or more interfaces for using Release-15 cellular communication standards that include millimeter-wave (mmWave) frequency ranges (e.g., 24.25 GHz - 300 GHz). Network interface 26 of electronic device 10 may allow communication via the aforementioned networks (e.g., 5G, Wi-Fi, LTE-LAA, etc.).

[0054] Network interface 26 may also include one or more interfaces for, for example, a broadband fixed wireless access network (e.g., Mobile broadband wireless network (mobile) Asynchronous digital subscriber lines (e.g., ADSL, VDSL) and digital video terrestrial broadcasting Network and its extensions DVB handheld Networks, ultra-wideband (UWB) networks, AC power lines, etc.

[0055] As shown in the figure, network interface 26 may include transceiver 30. In some embodiments, all or part of transceiver 30 may be housed within processor 12. Alternatively, as described herein, processor 12 may refer to the processing circuitry of transceiver 30. Transceiver 30 may support transmission via one or more antennas ( Figure 1(Not shown) Transmits and receives various wireless signals. The power supply 29 of the electronic device 10 may include any suitable power source, such as a rechargeable lithium polymer (Li-poly) battery and / or an alternating current (AC) power converter. In some embodiments, the electronic device 10 may take the form of a computer, a portable electronic device, a wearable electronic device, or other types of electronic devices.

[0056] Figure 2 The feasibility of the implementation scheme according to this disclosure Figure 1 The diagram shows a functional block diagram of the components of the electronic device 10, namely electronic devices 10A and 10B (collectively referred to as electronic device 10). As shown, each of the processors 12A and 12B (collectively referred to as processor 12), memory 14A and 14B (collectively referred to as memory 14), transceivers 30A and 30B (collectively referred to as transceiver 30), transmitters 32A and 32 (collectively referred to as transmitter 32), receivers 34A and 34B (collectively referred to as receiver 34), and / or antennas 36A and 36B (collectively referred to as antenna 36) of the respective electronic devices (10A and 10B) can be directly or indirectly (e.g., via or through another component, communication bus, network) communicatively coupled to each other to send and / or receive data.

[0057] Electronic device 10A may include transmitter 32A and / or receiver 34A, which respectively enable communication via communication link 38 including wired or wireless communication links, via a network or direct connection, and using any suitable communication technology including radio frequency or wireless technology (e.g., non-standard communication technology, millimeter wave (mmWave) technology, mmWave technology operating in the EHF band, mmWave technology operating in the 60 GHz band, near field communication (NFC) standard, etc.). Standards such as Universal Serial Bus (USB) standards enable the transmission and reception of data between the receiver 34A and / or transmitter 32A of electronic device 10A and electronic device 10B.

[0058] For example, an EHF communication link (e.g., provided via an mmWave antenna) can enable communication between electronic devices 10A and 10B over relatively short distances (e.g., within 10 meters, within 5 meters, within 1 meter, within 50 centimeters, within 20 centimeters, within 15 centimeters, within 10 centimeters, within 5 centimeters, within 4 centimeters, etc.). The 60 GHz band may be unlicensed, thus enabling operational flexibility, although it is envisioned that the EHF communication link can be used in other unlicensed or licensed bands, subject to any applicable licensing or regulatory constraints. Furthermore, implementing an EHF communication link using amplitude shift keying (ASK) modulation may be relatively simple and cost-effective, while avoiding the latency issues associated with more complex modulation / demodulation schemes. By utilizing the near-field (e.g., closer range) provided by the EHF communication link and placing the antennas 36A and 36B of electronic devices 10A and 10B within a relatively close range of each other (e.g., within 10 meters, within 1 meter, within 50 centimeters, within 5 centimeters, etc.), a relatively error-free channel can be achieved. This reduces or eliminates the implementation of error detection and correction routines or components, thereby further reducing the complexity of electronic devices 10A and 10B and reducing the communication latency between electronic devices 10A and 10B. In this way, electronic devices 10A and 10B can establish an EHF wireless communication link 38 and then transmit data streams of different communication standards (including wired communication standards such as USB 2.0) on the EHF communication link 38. Such data streams can therefore conform to their respective communication standards.

[0059] In some cases, electronic devices 10A and 10B may have a host / client relationship, such that one of electronic devices 10A and 10B (e.g., a host device) controls the communication link 38 between electronic devices 10A and 10B. For example, if electronic device 10A controls the communication link 38 between electronic devices 10A and 10B, then electronic device 10A is a host device, and electronic device 10B is a client or peripheral device.

[0060] As shown in the figure, each transmitter 32 and receiver 34 can be combined into transceiver 30. Electronic device 10 may also have one or more antennas 36 electrically coupled to transceiver 30. Antennas 36 can be configured omnidirectionally or directionally, in a single-beam, dual-beam, or multi-beam arrangement, etc. Each antenna 36 can be associated with one or more beams and various configurations. In some embodiments, when implemented as a multi-beam antenna, each beam may correspond to a specific transceiver 30. Depending on the applicable communication standards, electronic device 10 may include (not shown) multiple transmitters, multiple receivers, multiple transceivers, and / or multiple antennas.

[0061] Transmitter 32 can wirelessly transmit packets with different packet types or functions. For example, transmitter 32 can transmit different types of packets generated by processor 12. Receiver 34 can wirelessly receive packets with different packet types. In some examples, receiver 34 can detect the type of packet used and process the packet accordingly. In some embodiments, transmitter 32 and receiver 34 can transmit and receive information via other wired or line systems or devices.

[0062] As shown in the figure, various components of electronic device 10 can be coupled together via bus system 40 (e.g., 40A, 40B). Bus system 40 may include, for example, a data bus, as well as power buses, control signal buses, and status signal buses in addition to the data bus. Components of electronic device 10 can be coupled together or use some other mechanism to accept or provide input to each other.

[0063] Figure 3This is a schematic diagram of electronic devices 10A, 10B transmitting and receiving multiple data streams on a wireless communication link (e.g., communication link 38) according to embodiments of the present disclosure. Each electronic device 10A, 10B's transceiver 30A, 30B may include data type controllers 42A, 42B that determine the input data type from the incoming data stream and determine how to transmit or receive the data. As shown, host device 10A may include a USB (e.g., USB 2.0) host controller 44A that generates, transmits, and / or receives USB data (e.g., USB 2.0 data). Client device 10B may include a USB (e.g., USB 2.0) (client) device controller 44B that generates, transmits, and / or receives USB data (e.g., USB 2.0 data). The corresponding transceivers 30A and 30B of the host device 10A and client device 10B may have corresponding USB interfaces 46A and 46B (e.g., USB 2.0 interfaces), which transmit and receive data at high speed (e.g., according to eUSB2 (Embedded USB 2.0)) with the corresponding USB host controller 44A and USB device controller 44B. eUSB2 is a supplement to the USB 2.0 specification, which addresses issues related to the integration of interface controllers with advanced system-on-chip (SoC) process nodes. As shown, the host device 10A and client device 10B may also include UART controllers 48A and 48B for generating, transmitting, and / or receiving UART data, I2C controllers 52A and 52B for generating, transmitting, and / or receiving I2C data, and SWD controllers 54A and 54B for generating, transmitting, and / or receiving SWD data. Furthermore, the host device 10A and the client device 10B may each include general-purpose I / O (GPIO) interfaces 56A and 56B, respectively, which send GPIO data to and / or receive GPIO data from the GPIO pins of the host device 10A and the client device 10B. It should be understood that the host device 10A and the client device 10B may include more or fewer sets of controllers and / or interfaces (such as SPI controllers and / or interfaces, audio controllers and / or interfaces, etc.).

[0064] In an exemplary example, when data is being transferred, the USB 2.0 host controller 44A may send USB 2.0 data (e.g., high-speed data) to the USB interface 46, the UART controller 48A may send UART data to the UART interface 60A, the I2C controller 52A may send I2C data to the I2C interface 53A, the SWD controller 54A may send SWD data to the SWD interface 55A, and / or GPIO pins may provide GPIO data to the GPIO interface 56A. The data type controller 42A may form packets of (e.g., first data stream) USB 2.0 data with (e.g., second data stream) UART data, (e.g., third data stream) I2C data, (e.g., fourth data stream) SWD data, and / or (e.g., fifth data stream) GPIO data, and send the resulting packets to the transmitter 32A for transmission to the client device 10B via the antenna 36A (e.g., mmWave antenna) on the communication link 38 (e.g., EHF wireless communication link). UART data, I2C data, SWD data, and GPIO data (and other suitable data from other protocols or standards) may be referred to as packet-switched (e.g., PEX) data. Communication link 38 may be half-duplex, allowing data to be transmitted in one direction at a time.

[0065] When a packet is received at receiver 34B via antenna 36B (e.g., mmWave antenna) on communication link 38, the data type controller 42B of client device 10B can extract USB 2.0 data and send it to USB interface 46B, which in turn sends the USB 2.0 data to USB device controller 44B. The data type controller 42B can also extract UART data and send it to UART interface 50B, which in turn sends the UART data to UART controller 48B; extract I2C data and send it to I2C interface 53B, which in turn sends the I2C data to I2C controller 52B; and extract SWD data and send it to SWD interface 55B, which in turn sends the SWD data to SWD controller 54B. The data type controller 42B can also extract GPIO data and send it to GPIO interface 56B, which in turn sends the GPIO data to the GPIO pins of client device 10B. It should be understood that the client device 10B may use a similar process (e.g., in reverse order) to send USB 2.0 data, UART data, I2C data, SWD data and / or GPIO data to the host device 10A.

[0066] In this manner, multiple data streams can be transmitted over communication link 38. As detailed below, data type controllers 42A and 42B can locally stream USB 2.0 data over communication link 38 (e.g., without additional encoding or packetization), while simultaneously sending or receiving packet-switched data (e.g., UART data, I2C data, SWD data, and / or GPIO data) across communication link 38 during USB 2.0 idle periods. Advantageously, it avoids implementing USB 2.0 host and device controllers in the transceivers 30A and 30B of host device 10A and client device 10B (e.g., instead, only USB 2.0 interfaces 46A and 46B can be implemented in host device 10A and client device 10B). Furthermore, the data rate for USB 2.0 data across communication link 38 can be maintained at no more than 480 Mbps, thereby avoiding the implementation of higher-order modulation and / or higher frequency bandwidths. However, when packet-switched data and USB 2.0 data are aggregated on communication link 38, the combined data rate may exceed 480 Mbps (e.g., greater than 520 Mbps, greater than 640 Mbps, greater than 720 Mbps, greater than 1000 Mbps, etc.).

[0067] Figure 4 It is based on the implementation scheme of this disclosure. Figure 1 A schematic diagram of a transmitter 60 (e.g., a transmitting circuit) of an electronic device 10 capable of wirelessly transmitting packet-switched data in synchronous packets. Specifically, Figure 2 The transmitter 32 of the electronic device 10 may include a transmitter 60. As shown, the transmitter 60 may receive outgoing data 62 to be sent to another electronic device (e.g., electronic device 10B). In some cases, the outgoing data 62 may be in the form of packets of a first data stream (e.g., a USB 2.0 data stream). Additionally or alternatively, the packets may be synchronization packets that include synchronization information such as for synchronizing isochronous and interrupting data transmission. For example, for the USB 2.0 standard, synchronization packets may include start-of-frame (SOF) packets.

[0068] In any case, the outgoing data 62 may be in the form of a digital signal transmitted via one or more antennas 36. In some embodiments, the transmitter 60 may include a data injector / extractor 64 (e.g., data injection / extraction circuitry and / or software) that can extract synchronization information (e.g., synchronization packets, such as frame start packets in the USB 2.0 standard), inject configuration information 65 (e.g., indicating that packet switching or “PEX” data 66 of a second data stream will be sent or received during a second synchronization frame), and / or inject packet switching data 66 of the second data stream into the outgoing data 62. For example, during a first synchronization frame (e.g., frame start in the USB 2.0 standard), the data injector / extractor 64 may inject configuration information 65 into the outgoing data 62 in place of the synchronization information. Similarly, during a synchronization frame, the data injector / extractor 64 may inject packet switching data 66 into the outgoing data 62 in place of the synchronization information. In some embodiments, the data injector / extractor 64 may include a data aggregation state machine that aggregates the data to be transmitted in the packet switching data 66. In another or alternative implementation, processor 12 may include data injector / extractor 64 (e.g., data injector / extractor circuitry, data injector / extractor software, or both). Packet exchange data 66 may include any suitable data from transmitter 60 to receiver (e.g., receiver 34 of electronic device 10B), such as payload data, user data, control information, housekeeping or maintenance data for electronic device 10A, electronic device 10B, or both (e.g., data indicating the quality of the wireless communication link between electronic device 10A, electronic device 10B), data related to other components and / or protocols used by electronic device 10A, electronic device 10B, or both, control data of any suitable standard or protocol (e.g., USB 2.0, another USB standard, UART, SPI, I2C, SWD, audio) to be exchanged between electronic device 10A, electronic device 10B, timing data, etc. Therefore, the second data stream of packet-switched data 66 may include data streams of any suitable communication standard, such as another USB 2.0 data stream, another USB generated data stream, UART data stream, SPI data stream, I2C data stream, SWD data stream, audio data stream, video data stream, etc.

[0069] The encoder 68 of transmitter 60 can encode digital signals into analog signals, perform any encoding scheme, group data in the digital signals, etc. Modulator 70 can combine the encoded analog signal with a carrier signal to generate radio waves. Power amplifier (PA) 72 receives a signal from modulator 70, i.e., a modulated signal. Power amplifier 72 amplifies the modulated signal to a suitable level to drive transmission of the signal via one or more antennas 36. Filter 74 of transmitter 60 (e.g., filter circuitry and / or software) can subsequently remove unwanted noise from the amplified signal for transmission via one or more antennas 36. Filter 74 may include one or more suitable filters, such as bandpass filters, bandstop filters, low-pass filters, high-pass filters, and / or decimation filters, to remove unwanted noise from the amplified signal.

[0070] Additionally, transmitter 60 may include any suitable additional components not shown, or may exclude some of the illustrated components, such that transmitter 60 can transmit data 62 via one or more antennas 36. For example, transmitter 60 may include a mixer and / or a digital up-conversion converter. Also, if power amplifier 72 outputs an amplified signal at or approximately within a desired frequency range (making filtering of the amplified signal potentially unnecessary), transmitter 60 may not include filter 74. In this way, transmitter 60 can wirelessly transmit packet-switched data in synchronous packets, and thus transmit multiple data streams using wireless communication link 38.

[0071] Figure 5 It is based on the implementation scheme of this disclosure. Figure 1 A schematic diagram of a receiver 80 (e.g., a receiving circuit) of an electronic device 10 capable of wirelessly receiving packet-switched data in synchronous packets. Specifically, Figure 2The receiver 34 of the electronic device 10 may include a receiver 80. As shown, the receiver 80 may receive received data 82 from one or more antennas 36 in the form of an analog signal. A low-noise amplifier (LNA) 84 may amplify the received analog signal to a suitable level for processing by the receiver 80. A filter 86 (e.g., filter circuitry and / or software) may remove unwanted noise, such as cross-channel interference, from the received signal. The filter 86 may also remove additional signals received by one or more antennas 36 at frequencies different from the desired signal. The filter 86 may include one or more of any suitable filters, such as bandpass filters, bandstop filters, low-pass filters, high-pass filters, and / or decimation filters, for removing unwanted noise or signals from the received signal. A demodulator 88 may remove the radio frequency envelope from the filtered signal and / or extract the demodulated signal from the filtered signal for processing. A decoder 90 may receive the demodulated analog signal and decode it into a digital signal, perform any decoding scheme, and / or degroup the data in the demodulated analog signal into multiple different data streams so that it can be further processed by the electronic device 10.

[0072] Data extractor / injector 92 (e.g., data extraction circuitry / software and / or data injection circuitry / software) can receive decoded digital signals, extract configuration information 65 (e.g., packet-switched data 66 indicating that a second data stream will be transmitted or received during a second synchronization frame), extract packet-switched data 66, and / or inject synchronization information. Specifically, Figure 4 The data injector / injector 64 of the transmitter 60 may have extracted synchronization information (e.g., synchronization packets, such as the start-of-frame packets of the USB 2.0 standard) and injected configuration information 65 and / or packet exchange data 66 of the second data stream into the received data 82 to replace the synchronization information. Thus, the receiver 80 can receive the received data 82 during a synchronization frame (e.g., the start-of-frame packet of the USB 2.0 standard), and the data extractor / injector 92 can extract the configuration information 65 and / or packet exchange data 66 of the second data stream from the digital signal. Furthermore, the data extractor / injector 92 can inject synchronization information (e.g., synchronization packets, such as the start-of-frame packets of the USB 2.0 standard) to replace the extracted packet exchange data 66 to conform to an applicable standard (e.g., the USB 2.0 standard), thereby generating incoming packet data 96.

[0073] Therefore, in some cases, the incoming data 96 may be in the form of synchronous packets, such as the frame start packets of the USB 2.0 standard. In some embodiments, the incoming data 96 may be in the form of packets of a first data stream. In other or alternative embodiments, the processor 12 may include a data extractor / injector 92 (e.g., data extractor / injector circuitry, data extractor / injector software, or both). Additionally, the receiver 80 may include any suitable additional components not shown, or may exclude some of the illustrated components, such that the receiver 80 can receive the received data 82 via one or more antennas 36. For example, the receiver 80 may include a mixer and / or a digital downconverter. In this way, the receiver 80 wirelessly receives packet-switched data in synchronous packets and thus receives multiple data streams using the wireless communication link 38.

[0074] Turn now Figure 6 A timing diagram 110 is illustrated, showing an embodiment of the present disclosure where configuration information 65 (as indicated by control (“CTRL”) data 114) and / or packet exchange data 66 (as indicated by house (“HK”) data 116, transmit (“TX”) data 118, or receive (“RX”) data 120) in a first data stream (e.g., a USB 2.0 data stream) replaces synchronization information (e.g., in the form of a frame start packet 112). While this disclosure illustrates the application of an embodiment to implement a USB 2.0 data stream on an EHF wireless communication link 38, it should be understood that the embodiment can also be applied to other communication standards or technologies (e.g., wired or wireless). For example, the wireless communication link 38 may be... The link and / or may contain one or more different types of data streams, including any version of the USB data stream, such as USB 1 (e.g., USB 1.x), USB 2.0 (e.g., USB 2.x), USB 3 (e.g., USB 3.x), USB 4 (e.g., USB 4.x), the Low Voltage Differential Signaling (LVDS) standard used by the DisplayPort digital display interface, etc.

[0075] In the USB 2.0 standard, a frame 122 may have a duration of one millisecond, and each frame may transmit eight SOF packets 112, thereby dividing the one-millisecond frame 122 into eight 125-microsecond microframes 124. SOF packets 112 may indicate the start of a new frame 122 (and thus be transmitted or received every one millisecond), or, in the case of USB 2.0 (e.g., at least in High Speed ​​(HS) mode), indicate the start of a new microframe 124 (and thus be transmitted or received every 125 milliseconds). The portion of each microframe 124 dedicated to SOF packets 112 may be collectively referred to herein as a “synchronization frame,” and SOF packets 112 may be collectively referred to herein as a “synchronization packet.” The USB 2.0 standard includes several modes (e.g., Low Speed ​​(LS) mode, Full Speed ​​(FS) mode, and HS mode), and at least some of these modes (e.g., FS mode, HS mode) include the use of SOF packets 112. According to the USB 2.0 standard, each SOF packet 112 may have a minimum length of 76 bits and a maximum length of 96 bits, and the portion of each microframe 124 dedicated to the SOF packet 112 is a minimum of 158.33 nanoseconds (ns) and a maximum of 200 ns. Thus, the time range of 158.33 ns to 200 ns can be used to send and / or receive configuration information 65 (e.g., instructions for packet exchange data 66) or packet exchange data 66 for the second data stream, as one SOF packet 112 of the first USB 2.0 data stream is replaced. It should be understood that at least some of the SOF packets 112 may not be replaced by configuration information 65 or packet exchange data 66, because the remaining SOF packets 112 can be used to facilitate or perform synchronization or interruption functions between electronic devices 10A, 10B. Therefore, this disclosure contemplates replacing up to half (e.g., four) of the SOF packets 112 in each frame 122 with configuration information 65 and / or packet exchange data 66, such that synchronization information can still be provided by the remaining half of the SOF packets 112. However, it should be understood that any suitable number of SOF packets (e.g., 1 to 8) in frame 122 may be replaced by configuration information 65 and / or packet exchange data 66.

[0076] Specifically, after establishing the wireless communication link 38 and / or after establishing the USB 2.0 link on the wireless communication link 38, the host device (e.g., electronic device 10A) and the client device (e.g., electronic device 10B) may wait for a predetermined or minimum number of frames 122 to ensure that the data injector / extractor 64 is ready to aggregate and / or inject packet-switched data 66. This may include counting the number of SOFs and / or identifying the sequence / pattern of SOF packets 112, since there may be no alignment between the transceivers 30 of the host device and the client device. Once the predetermined or minimum number of frames 122 have passed and / or the data injector / extractor 64 is ready, the host device's data injector / extractor 64 may replace the last SOF in frame 122 (e.g., in microframe 7) with configuration information 65 indicating the SOF configuration of the next frame 122. That is, the last SOF packet 112 of frame 122 may indicate the SOF of the next frame 122 that can store packet-switched data 66, and / or inform the client device how to operate the next frame 122.

[0077] For example, as illustrated, the data injector / extractor 64 has replaced the last SOF packet 112 of the last SOF 126 (e.g., SOF7) of the first frame 128 with configuration information 65 (CTRL 114). Configuration information 65 (CTRL 114) indicates that the next frame 130 will have housekeeping data (HK 116) in SOF1, transmit data (TX 118) in SOF3, and receive data (RX 120) in SOF5. Each of the housekeeping data (HK 116), transmit data (TX 118), and receive data (RX 120) may have a different data stream than the data stream transmitted using the USB 2.0 standard (e.g., including data packets transmitted using the USB 2.0 standard). As mentioned herein, housekeeping or maintenance data packets include data for maintaining host devices and / or client devices, data indicating the quality of the wireless communication link between host devices and / or client devices, data relating to other components and / or standards used by host devices and / or client devices, etc. Transmitted data is data sent from the host device to the client device, while received data is data received by the host device from the client device. Thus, replacing SOF packets 112 with packet-switched data 66 enables the exchange of multiple bidirectional data streams (e.g., from the host device to the client device, and from the client device to the host device).

[0078] The host device transmits configuration information 65 (CTRL 114) in the last SOF 126 (e.g., SOF 7) of the first frame 128 and waits for acknowledgment from the client device within the same SOF 126 (e.g., SOF 7). If acknowledgment is received from the client device, on the next frame 130, the host device transmits SOF packet 112 according to the USB 2.0 standard (e.g., during SOF 0), and the host device's data injector / extractor 64 replaces the second SOF packet 112 with housekeeping data (HK 116) from SOF 1. The host device also transmits SOF packet 112 according to the USB 2.0 standard (e.g., during SOF 2), and the data injector / extractor 64 replaces the fourth SOF packet 112 with transmit data (TX 118) such as user data, control information, etc., from SOF 3. The host device also transmits SOF packet 112 according to the USB 2.0 standard (e.g., during SOF4), and the data injector / extractor 64 can remove the fourth SOF packet 112 and receive received data (RX 120) such as user data, control information, etc. from the client device in SOF5. The host device also transmits SOF packet 112 according to the USB 2.0 standard (e.g., during SOF6). The data injector / extractor 64 can then replace the last SOF packet 132 (SOF7) of frame 130 with configuration information 65 (CTRL) indicating the SOF configuration of the next frame 134.

[0079] The wireless communication link 38 can continue to operate in this manner, and the host device can dynamically adjust the usage and capacity of the wireless communication link 38 to achieve various configurations of SOF. Alternatively, the host device and / or client device can revert to the USB 2.0 standard for SOF operation, where SOF packets 112 are sent at each SOF as needed (e.g., by sending instructions in the last SOF (SOF7)). Therefore, if up to four SOF packets 112 in each frame 122 can be replaced by configuration information 65 and / or packet-switched data 66, and the last SOF packet 112 (SOF7) of frame 122 is replaced by configuration information 65, then the total time range of up to three SOFs in frame 122 (or 474.99 to 600 nanoseconds) can be replaced by packet-switched data 66 of one or more data streams with a total size of 228 to 288 bits. In this way, by utilizing the SOF packets 112 of the USB 2.0 standard to send and / or receive multiple data streams bidirectionally (e.g., housekeeping data of the second data stream in SOF1 (HK116), transmit data of the third data stream in SOF3 (TX 118), and receive data of the fourth data stream in SOF5 (RX120)), communication using the USB 2.0 standard on the wireless communication link 38 can continue without interruption or error, while increasing the total data throughput.

[0080] Figure 7 This is a flowchart of a method 140 for an electronic device 10A (e.g., a host device) to wirelessly transmit and / or receive a second data stream in SOF packet 112, according to embodiments of the present disclosure. Method 140 can be executed by any suitable device (e.g., a controller) that controls components of the electronic device 10A, such as processor 12A (e.g., processing circuitry as transceiver 30). In some embodiments, method 140 can be implemented by using processor 12A to execute instructions stored in a tangible, non-transitory computer-readable medium such as memory 14A or storage device 16A. For example, method 140 can be executed at least in part by one or more software components (e.g., an operating system of the electronic device 10A, one or more software applications of the electronic device 10A, etc.). Although method 140 is described using steps in a specific order, it should be understood that the present disclosure contemplates that the described steps may be performed in a different order than shown, and that some described steps may be skipped or not performed at all.

[0081] In process block 142, the host device's processor 12A establishes a wireless communication link 38 with the electronic device 10B (e.g., a client device). For example, the wireless communication link 38 may implement mmWave technology (implemented in the EHF band, e.g., the 60GHz band), the NFC standard, etc. Standards, any suitable wireless peer-to-peer communication technology or standard, any suitable wireless network communication technology or standard, etc. In some embodiments, the processor 12A may subsequently establish additional communication links (e.g., wired or wireless) on the wireless communication link 38, including any version of the USB data stream, such as the Low Voltage Differential Signaling (LVDS) standard used by USB 1, USB 2.0, USB 3, USB 4, or DisplayPort digital display interfaces. That is, the wireless communication link 38 may replicate or virtualize the USB 2.0 communication link. In some embodiments, the wireless communication link 38 is an EHF link that replicates or virtualizes the wired USB 2.0 communication link.

[0082] In process block 144, processor 12A sends data of the first data stream to the client device via wireless communication link 38 using wired communication standards. For example, processor 12A may cause transmitter 60 of the host device to send token packets, data packets (e.g., with payload data), etc. of the USB 2.0 data stream to the client device via an EHF link using the USB 2.0 standard. Specifically, processor 12A may send a predetermined or minimum number of packets to ensure that data injector / extractor 64 is ready to aggregate and / or inject packets to exchange data 66.

[0083] In process block 146, processor 12A generates packets (e.g., synchronization packets) to be sent during the first synchronization frame period according to a wired communication standard by replacing synchronization information with configuration information 65, which indicates packet exchange data 66 to be sent or received during the second synchronization frame according to a wired communication standard. Specifically, processor 12A enables data injector / extractor 64 to generate SOF packets 112 to be sent during the SOF (such as the last SOF (SOF7)) according to a USB 2.0 standard by replacing the SOF synchronization information with configuration information 65, which indicates packet exchange data 66 to be sent or received during the second SOF according to USB 2.0 (e.g., including another USB 2.0 data stream, another USB generated data stream, UART data stream, SPI data stream, I2C data stream, SWD data stream, etc.). Figure 6As an example of timing diagram 110, the data injector / extractor 64 can generate SOF packet 112, which will be sent in the last SOF 126 (e.g., SOF7) of the first frame 128, by replacing the synchronization information of SOF packet 112 with configuration information 65 (CTRL 114). Configuration information 65 (CTRL 114) indicates that the next frame 130 will have house data (HK 116) in SOF1 (e.g., the second data stream), transmit data (TX 118) in SOF3 (e.g., the third data stream), and receive data (RX 120) in SOF5 (e.g., the fourth data stream).

[0084] In process block 148, processor 12A transmits data to the client device via wireless communication link 38. That is, processor 12A enables transmitter 60 to transmit SOF packet 112 containing configuration information 65 to the client device via EHF link.

[0085] In decision block 150, processor 12A determines whether acknowledgment of configuration information 65 has been received from the client device via wireless communication link 38. Specifically, in process block 148, processor 12A causes transmitter 60 to send SOF packet 112 in SOF and wait for acknowledgment from the client device. If not, processor 12A repeats process block 146, attempting to set up sending or receiving packet exchange data 66. In some embodiments, processor 12A may wait for acknowledgment from client devices within the same SOF. Figure 6 As an example of timing diagram 110, processor 12A enables transmitter 60 to send SOF packet 112 in the last SOF 126 (e.g., SOF 7) of the first frame 128 and wait for acknowledgment from a client device within the same SOF 126. Acknowledgment may instruct the client device to have received configuration information 65 and be ready to operate based on configuration information 65 (e.g., to receive packet-switched data 66 injected into SOF packet 112 by the host device in the next frame, to inject packet-switched data 66 into SOF packet 112 in the next frame, and to send SOF packet 112 to the host device, or both).

[0086] If an acknowledgment is received from the client device (e.g., via receiver 80), in process block 152, processor 12A may send or receive packet-switched data 66 of the second data stream to or from the client device during the second synchronization frame via wireless communication link 38. In some embodiments, if an acknowledgment is received from the client device during the same SOF (e.g., 126), processor 12A may send or receive packet-switched data 66 of the second data stream to or from the client device. Specifically, processor 12A may cause data injector / extractor 64 to replace subsequent SOF packets 112 in subsequent frames with packet-switched data 66. Packet-switched data 66 may include any suitable data that the host device may send to and / or receive from the client device, such as user data, control information, housekeeping or maintenance data for the host device and / or client device (e.g., data indicating the quality of the wireless communication link between the host device and the client device), data relating to other components and / or standards used by the host device and / or client device, etc. Figure 6 In the example of timing diagram 110, processor 12A can cause data injector / extractor 64 to replace the second SOF packet 112 in SOF1 of frame 130 with housekeeping data (HK 116) and cause transmitter 60 to transmit housekeeping data in SOF1, cause data injector / extractor 64 to replace the fourth SOF packet 112 in SOF3 of frame 130 with transmit data (TX 118) and cause transmitter 60 to transmit transmit data in SOF3, and cause data injector / extractor 64 to remove the sixth SOF packet 112 in SOF5 of frame 130 and cause receiver 80 to receive the received data (RX 120) in SOF5.

[0087] In this manner, in addition to the first data stream in the regular data packets according to the USB 2.0 standard, method 140 enables the host device to wirelessly send and / or receive a second data stream in SOF packets 112. Specifically, by bidirectionally sending and / or receiving multiple data streams using SOF packets 112 of the USB 2.0 standard, communication using the USB 2.0 standard on the wireless communication link 38 can continue without interruption or error, while increasing the overall data throughput.

[0088] Figure 8This is a flowchart of a method 160 for an electronic device 10B (e.g., a client device) to wirelessly receive and / or transmit a second data stream in SOF packet 112, according to embodiments of the present disclosure. Method 160 can be executed by any suitable device (e.g., a controller) that controls components of the electronic device 10B, such as processor 12B (e.g., processing circuitry as transceiver 30). In some embodiments, method 160 can be implemented by using processor 12B to execute instructions stored in a tangible, non-transitory computer-readable medium such as memory 14B or storage device 16B. For example, method 160 can be executed at least in part by one or more software components such as the operating system of the electronic device 10B, one or more software applications of the electronic device 10B, etc. Although method 160 is described using a specific order of steps, it should be understood that the described steps are contemplated to be performed in a different order than shown, and that some described steps may be skipped or not performed at all.

[0089] In process block 162, the processor 12B of the client device establishes a wireless communication link 38. The establishment of the wireless communication link 38 and the details of the wireless communication link 38 are similar to those described in process block 142 of method 140. In process block 164, the processor 12B receives data from the host device via the wireless communication link 38 using a wired communication standard. For example, the processor 12B may cause the receiver 80 of the client device to receive data packets of a USB 2.0 data stream from the host device via an EHF link using the USB 2.0 standard.

[0090] In process block 166, processor 12B receives a first packet from host device via wireless communication link 38 during the first synchronization frame according to a wired communication standard. Specifically, processor 12B enables receiver 80 to receive SOF packet 112 during the SOF frame. In decision block 168, processor 12B determines, according to the wired communication standard, whether the first packet includes configuration information 65 associated with packet-switched data 66 of a second data stream to be sent or received during the second synchronization frame. That is, processor 12B determines, according to the USB 2.0 standard, whether SOF packet 112 includes configuration information 65 associated with packet-switched data 66 of a second data stream to be sent or received during the second SOF. Specifically, SOF packet 112 can be received during the SOF of the first frame of the USB 2.0 standard, and the configuration information 65 of SOF packet 112 can indicate receiving the second SOF in the next frame.

[0091] If processor 12B determines that the first packet does not include configuration information 65, then in process block 170, processor 12B receives the second packet from the host device via wireless communication link 38 during the second synchronization frame. Specifically, processor 12B may cause receiver 80 to receive the second SOF packet 112 from the host device via wireless communication link 38 during the second SOF. In process block 172, processor 12B processes the second packet according to wired communication standards. For example, processor 12B may execute synchronization and / or interrupt routines based on the synchronization information of the second SOF packet 112.

[0092] If processor 12B determines that the first packet includes configuration information 65, then in process block 174, processor 12B sends an acknowledgment of configuration information 65 to the host device via wireless communication link 38. The acknowledgment may instruct the client device to have received configuration information 65 and to be ready to operate based on configuration information 65 (e.g., to receive packet-switched data 66 injected into SOF packet 112 by the host device in the next frame, to inject packet-switched data 66 into SOF packet 112 in the next frame, and to send SOF packet 112 to the host device, or both).

[0093] In process block 176, processor 12B generates and processes a second packet according to the wired communication standard. That is, processor 12B enables data extractor / injector 92 to generate synchronization information (e.g., SOF packet 112 or the content of SOF packet 112), and processor 12B processes the synchronization information instead of the first packet containing configuration information 65. This makes it appear as if the host device and client device conform to the USB 2.0 standard. Otherwise, if the first SOF packet 112 containing configuration information 65 were processed according to the USB 2.0 standard, an error would occur because the first SOF packet 112 would lose the synchronization information removed by the host device's data injector / extractor 64 to make room for configuration information 65, which could cause the wireless communication link 38, or at least the covered USB 2.0 communication link, to be interrupted or disconnected.

[0094] In process block 178, processor 12B receives or transmits packet-switched data 66 of the second data stream during the second synchronization frame. Figure 6 As an example of timing diagram 110, processor 12B enables receiver 80 to receive housekeeping data in SOF1, enables receiver 80 to receive transmit data (TX 118) in SOF3, and enables transmitter 60 of client device to transmit the received data (RX 120) in SOF5.

[0095] In process block 180, processor 12B generates and processes a third packet according to wired communication standards. Specifically, processor 12B enables data extractor / injector 92 to generate synchronization information, and processor 12B processes the synchronization information instead of the second packet with packet exchange data 66 to comply with the USB 2.0 standard. Otherwise, if the first SOF packet 112 with packet exchange data 66 were processed according to the USB 2.0 standard, an error would occur because the first SOF packet 112 would lose the synchronization information removed by the host device's data injector / extractor 64 to make room for packet exchange data 66, which could cause the wireless communication link 38 or at least the covered USB 2.0 communication link to be interrupted or disconnected.

[0096] In this manner, in addition to the first data stream in the regular data packets according to the USB 2.0 standard, method 160 enables the client device to wirelessly receive and / or transmit a second data stream in SOF packets 112. Specifically, by utilizing the SOF packets 112 of the USB 2.0 standard to receive and / or transmit multiple data streams bidirectionally, communication using the USB 2.0 standard on the wireless communication link 38 can continue without interruption or error, while increasing the overall data throughput.

[0097] In another or alternative implementation, the host device may determine the delay (e.g., time gap) between the first and second packets of the first data stream transmitted via the wireless communication link 38 according to wired communication standards, and transmit and / or receive packet-switched data 66 of the second data stream during the delay to increase data throughput. It should be understood that the delay and injection of packet-switched data 66 may comply with the USB 2.0 standard (e.g., without violating timing requirements, data or packet standards, etc.). Figure 9 It is based on the implementation scheme of this disclosure. Figure 1 A schematic diagram of a transmitter 190 (e.g., a transmitting circuit) of an electronic device 10 capable of wirelessly transmitting packet-switching data 66 of a second data stream during a delay between transmitting or receiving packets of a first data stream. Specifically, Figure 2 The transmitter 32 of the electronic device 10 may include a transmitter 190. As shown, the transmitter 190 may receive outgoing data 62 to be sent to another electronic device (e.g., electronic device 10B). The outgoing data 62 may be similar to... Figure 4 The data is transmitted via transmitter 60. Transmitter 60 may include a packet-switched injector 192 (e.g., packet-switched injection circuitry and / or software) that can inject packet-switched data 66 of a second data stream into the transmitted data 76. Packet-switched injector 192 may be... Figure 3 This is a part of the data type controller 42 shown.

[0098] Packet switching injector 192 determines the delay between a first packet and a second packet in the transmission of the first data stream via wireless communication link 38 according to the USB 2.0 standard, and injects packet switching data 66 into the outgoing data 62 to be transmitted during the delay. The delay may correspond to the commutation delay between the host device sending a packet (e.g., a USB 2.0 data packet) to the client device and receiving a response packet (e.g., a USB 2.0 handshake packet) from the client device. The packet switching data 66 and the remaining components of transmitter 190 may be similar to those described above. Figure 4 The transmitter 60 is one of those described. In some embodiments, the processor 12A may extend the delay between the first packet and the second packet of the first data stream and send additional packet-switched data 66 during the extended delay. In such embodiments, the transmitter 190 may include a buffer 194 that delays or time-shifts outgoing data 62 during the extended delay, and selection circuitry 196 (e.g., multiplexing circuitry and / or software). Specifically, the buffer 194 may delay or time-shift outgoing data 62 by approximately 20 to 30 USB 2.0 high-speed bit times. As shown, the selection circuitry 196 may be controlled by a packet-switched injector 192, which enables the transmission of outgoing data 62 (e.g., which may be delayed or time-shifted by the buffer 194) or packet-switched data 66 (e.g., injected by the packet-switched injector 192) within the transmitted data 76. Specifically, during the extended delay, the packet-switched injector 192 may cause the selection circuitry 196 to select packet-switched data 66 for transmission, and the buffer 194 may delay or time-shift the second packet and / or other outgoing data 2 of the first data stream. Once the extended delay has elapsed, the packet-switched injector 192 enables the selection circuit 196 to select the outgoing data 62, which has been delayed or time-shifted by the buffer 194, for transmission. In this way, the transmitter 190 can wirelessly transmit packet-switched data 66 of a second data stream during the delay between transmitting and / or receiving packets of the first data stream, and / or extend the delay to transmit even more packet-switched data 66.

[0099] Figure 10 It is based on the implementation scheme of this disclosure. Figure 1 A schematic diagram of a receiver 200 (e.g., a receiving circuit) of an electronic device 10 that can wirelessly receive packet-switched data 66 of a second data stream during a delay between receiving or transmitting packets of a first data stream. Specifically, Figure 2 The receiver 34 of the electronic device 10 may include a receiver 200. As shown, the receiver 200 may receive received data 82 from one or more antennas 36. The received data 82 may be similar to... Figure 4The data is received by receiver 80. Receiver 200 may include a packet-switched extractor 202 (e.g., packet-switched extraction circuitry and / or software) capable of extracting packet-switched data 66 of the second data stream from the received data 82. Specifically, if received data 82 is received during a delay between receiving or sending packets of the first data stream (e.g., a USB 2.0 data stream), the received data 82 may include packet-switched data 66 of the second data stream, and packet-switched extractor 202 may extract packet-switched data 66 of the second data stream from the received data 82. Packet-switched extractor 202 may be... Figure 3 This is part of the data type controller 42 shown. In this way, the receiver 200 can wirelessly receive packet-switched data 66 of the second data stream during the delay between sending and / or receiving packets of the first data stream, and / or receive even more packet-switched data 66 during a delay extended by the host device.

[0100] In the USB standard, data is exchanged between a host device and a client device using transfers, and these transfers consist of transactions. Each transaction includes sending or receiving multiple packets, including token packets, data packets, and handshake packets. Between each packet, the host device and / or client device may wait for a minimum delay to allow the packet to propagate between devices and / or through multiple levels of the standard. These delays include inter-packet delays (e.g., the delay between two consecutive packets sent from the host device) and reversal delays (e.g., the delay between a packet sent from the host device and the next packet sent from the client device, or the delay between a packet sent from the client device and the next packet sent from the host device). The disclosed embodiments enable the transmission and / or reception of packet-swapping data 66 of a second data stream over these delays on the wireless communication link 38 without modifying the USB 2.0 traffic of the first data stream, thereby maintaining a USB 2.0 link operating on the wireless communication link 38. These embodiments are applicable to all modes of the USB 2.0 standard (e.g., Low Speed ​​(LS) mode, Full Speed ​​(FS) mode, and High Speed ​​(HS) mode), as well as any other suitable version of the USB standard.

[0101] Figure 11This is a timing diagram 210 illustrating packet-switched data 66 of a host device sending and / or receiving a second data stream during a delay period when the host device is sending a first data stream using USB 2.0 bulk, interrupt, or control outgoing or write transfer types, according to an embodiment of this disclosure. Specifically, the USB 2.0 bulk transfer type can be used to transmit large amounts of data and guarantees delivery, but does not guarantee bandwidth or latency. The USB 2.0 interrupt transfer type can be used to poll devices to check if they have any interrupted data to transmit and guarantees reduced latency (e.g., to achieve fast response). The USB 2.0 control transfer type can be used for bidirectional data transmission to query, configure, and / or issue commands to client devices.

[0102] The first row 212 of timing diagram 210 shows the packets of the first data stream (e.g., a USB 2.0 data stream) transmitted between the host device and the client device, as well as the delays between packets when using USB 2.0 bulk, interrupt, or control outgoing transfer types. Specifically, when using USB 2.0 bulk, interrupt, or control outgoing transfer types, the host device may send a token packet 214 to the client device. The token packet 214 indicates to the client device the type of transaction to follow. After the host device sends the token packet 214, the host device may wait for an inter-packet delay 216 before sending the data packet 218. The inter-packet delay 216 refers to the time a device (e.g., the host device) waits between sending two consecutive packets (e.g., the token packet 214 and the data packet 218). According to the USB 2.0 standard, the minimum inter-packet delay 216 is 88 bits, and the maximum inter-packet delay 216 is 192 bits. Bit time corresponds to the time it takes to eject a bit from the network interface controller, which operates at the theoretical maximum data rate of 480 megabits per second (Mbps) in USB 2.0.

[0103] After the host device sends data packet 218, it may wait for a commutation delay 220 until it receives handshake packet 222 from the client device. Commutation delay 220 refers to the time between a device (e.g., the host device) sending a packet (e.g., data packet 218) to a second device (e.g., the client device) and receiving a response packet (e.g., handshake packet 222) from the second device. According to the USB 2.0 standard, the fastest commutation delay 220 is 38 bits. Handshake packet 222 acknowledges the reception of data packet 218 or reports an error. After the host device receives handshake packet 222 from the client device, it may wait for another commutation delay 220.

[0104] The second row 224 of timing diagram 210 illustrates packet-switched data 66 transmitted between the host and client devices during delays 216 and 220 between packets when using USB 2.0 bulk, interrupt, or control outgoing or write transfer types. That is, packet-switched injector 192 can inject packet-switched data 66 (e.g., of a second data stream, or of multiple other data streams) into transmitted data 76 that will be transmitted between the host and client devices via transmitter 190 during delays 216 and 220.

[0105] Figure 12 This is a timing diagram 230 illustrating packet-switched data 66 of a second data stream during the delay of sending and / or receiving a first data stream when the host device uses an outgoing or writing transfer type such as USB 2.0, according to an embodiment of this disclosure. Specifically, the USB 2.0 outgoing transfer type guarantees a certain bandwidth and / or latency, but may include potential data loss. The first row 232 of timing diagram 230 shows the packets of the first data stream (e.g., a USB 2.0 data stream) transmitted between the host device and the client device, and the delay between packets when using an outgoing transfer type such as USB 2.0. Specifically, when using an outgoing transfer type such as USB 2.0, the host device may send a token packet 214 to the client device. After the host device sends the token packet 214, the host device may wait for an inter-packet delay 216 before sending a data packet 218. After the host device sends the data packet 218, the host device may wait for another inter-packet delay 216.

[0106] The second row 234 of timing diagram 210 shows packet-switched data 66 transmitted between the host device and the client device during the inter-packet delay 216 when using outgoing or write transfer types such as USB 2.0. That is, packet-switched injector 192 can inject packet-switched data 66 (e.g., of a second data stream, or of multiple other data streams) into the transmitted data 76 that will be transmitted between the host device and the client device via transmitter 190 during the inter-packet delay 216.

[0107] Figure 13This is a timing diagram 240 illustrating packet-switched data 66 of a second data stream during a delay in the transmission of a first data stream by a host device using a USB 2.0 Bulk, Interrupt, or Control Inbound or Read transfer type, according to an embodiment of this disclosure. The first row 242 of timing diagram 240 shows packets of the first data stream (e.g., a USB 2.0 data stream) transmitted between the host device and the client device, and the delays between packets when using the USB 2.0 Bulk, Interrupt, or Control Inbound transfer type. Specifically, when using the USB 2.0 Bulk, Interrupt, or Control Inbound transfer type, the host device may send a token packet 214 to the client device. After the host device sends the token packet 214, the host device may wait for a commutation delay 220 before receiving a data packet 218 from the client device. After the client device sends the data packet 218, the client device may wait for another commutation delay 220 before receiving a handshake packet 222 from the host device. After sending the handshake packet 222, the host device may wait for another commutation delay 220.

[0108] The second row 244 of timing diagram 210 shows packet-switched data 66 transmitted between the host device and the client device during the commutation delay 220 between packets when using USB 2.0 bulk, interrupt, or control incoming or read transfer types. That is, packet-switched injector 192 can inject packet-switched data 66 (e.g., of a second data stream, or of multiple other data streams) into transmitted data 76 that will be transmitted between the host device and the client device via transmitter 190 during the commutation delay 220.

[0109] Figure 14 This is a timing diagram 250 illustrating packet-switched data 66 of a second data stream during a delay in sending and / or receiving the first data stream when the host device uses an incoming or read transfer type such as USB 2.0, according to an embodiment of this disclosure. The first row 252 of timing diagram 250 shows the packets of the first data stream (e.g., a USB 2.0 data stream) transmitted between the host device and the client device, and the delay between packets when using an incoming transfer type such as USB 2.0. Specifically, when using an incoming transfer type such as USB 2.0, the host device may send a token packet 214 to the client device. After the host device sends the token packet 214, the host device may wait for a commutation delay 220 before receiving a data packet 218 from the client device. After the client device sends the data packet 218, the client device may wait for another commutation delay 220.

[0110] The second row 244 of timing diagram 210 shows packet-switched data 66 transmitted between the host device and the client device during the commutation delay 220 between packets when using an incoming or outgoing transfer type such as USB 2.0. That is, packet-switched injector 192 can inject packet-switched data 66 (e.g., of a second data stream, or of multiple other data streams) into the transmitted data 76 that will be transmitted between the host device and the client device via transmitter 190 during the commutation delay 220.

[0111] refer to Figures 11 to 14 Furthermore, in some implementations, the host device and client device may send or receive packet-switched data 66 only during a subset of the delay, such as only during the switching delay 220, only during the inter-packet delay 216, only during a subset of the switching delay 220, only during a subset of the inter-packet delay 216, only during a subset of both the switching delay 220 and the inter-packet delay 216, etc. In this way, the host device may wirelessly send or receive one or more additional data streams during the delay between packets of the first data stream being sent or received.

[0112] To understand the throughput achievable by sending or receiving one or more additional data streams during the delay between sending or receiving packets of the first data stream, such as Figures 11 to 14 As shown, it can be assumed that the transmitters 190 of the host and client devices are allocated a propagation delay equal to that of the two hubs and their respective cables (e.g., 228 nanoseconds) for transmitting and processing packet-switched data 66 (e.g., including packetized packet-switched data 66, encrypted packet-switched data 66, etc.). Furthermore, it can be assumed that the wireless communication link 38 can operate at a rate of 1 GHz (e.g., according to mmWave technology operating in the EHF band), and therefore 4% of the wireless communication link 38 can be used to transmit packet-switched data 66. Additionally, if the transmitter 190 attempts to transmit packet-switched data 66 every 183 to 200 nanoseconds during the inter-packet delay 216 and / or commutation delay 220, 23% to 25% of the USB 2 capacity can be used to transmit up to 40 megabits per second (Mbps).

[0113] It also provides Figure 15 Table 260 indicates the bus allocation for each microframe according to the USB 2.0 standard. Specifically, for each of the high-speed control, high-speed bulk, high-speed interrupt, and high-speed isochronous USB 2.0 transfer types, Table 260 indicates the maximum number of transfers per microframe, the maximum number of transactions per microframe, and the resulting percentage of bus utilization per microframe according to the USB 2.0 standard.

[0114] Figure 16Table 270 indicates the maximum number of delays available according to the USB 2.0 standard. Specifically, for each of the USB 2.0 transfer types—High-Speed ​​Control Write, High-Speed ​​Control Read, High-Speed ​​Bulk Out, High-Speed ​​Bulk In, High-Speed ​​Interrupt Out, High-Speed ​​Interrupt In, High-Speed ​​Isochronous Out, and High-Speed ​​Isochronous In—Table 270 indicates the maximum packet length, the potential number of time slots, the maximum number of inter-packet delays, and the maximum number of commutation delays according to the USB 2.0 standard.

[0115] Alternatively or concurrently, the currently disclosed embodiments may increase the data throughput between communication devices 10A and 10B on the wireless communication link 38 by enabling the transmission or reception of a second data stream between transactions of the first data stream. That is, there may be periods when electronic devices 10A and 10B do not perform transactions (e.g., idle time). For example, during the first transaction (e.g., as... Figure 13 Following the timing diagram 240 (as depicted in the timing diagram), a second transaction can be executed (e.g., as also by...). Figure 13 (As depicted in timing diagram 240), both are based on the USB 2.0 standard. Because no USB 2.0 data is transmitted between the first and second transactions (e.g., during idle time), the packet-switching injector 192 (e.g., either of electronic devices 10A or 10B) can inject packet-switched data 66 during this time. In this way, electronic devices 10A and 10B can wirelessly send or receive an increased amount of the second data stream (e.g., packet-switched data 66) between transactions of the first data stream (e.g., USB 2.0 data).

[0116] Considering the foregoing, Figure 17Table 280 shows the throughput of maximum packet-switched data 66 during commutation delays 220 and / or idle times for scenarios that maximize the use of the wireless communication link 38 for USB 2.0 data (i.e., the so-called worst-case scenarios), according to the embodiments of this disclosure. Specifically, the worst-case scenarios provided below include artificially high occupancy USB 2.0 conditions following USB 2.0 guidelines, as real-world conditions rarely (if any) completely occupy the wireless communication link 38 like these scenarios. Specifically, the first row 282 of Table 280 indicates the worst-case scenario for six isochronous outgoing and one bulk outgoing USB 2.0 transfer types. In this case, the total transmission time for a 125-microsecond microframe under the USB 2.0 standard is 115.65 microseconds, which is 92.52% of the microframe, and includes two commutation delays 220. Eight bytes of packet-switched data 66 can be sent or received during the commutation delays 220, which is equivalent to 512,000 bits per second. For the remaining time of the microframe (e.g., idle time), 184 bytes of packet-switched data 66 can be sent or received, which equals 11,776,000 bits. Therefore, the total packet-switched data 66 that can be sent or received during the commutation delay 220 and the idle time is 12,288,000 bits. The second row 284 of Table 280 indicates the worst-case scenario for the USB 2.0 transfer type with six isochronous outgoing and four control writes. In this case, the total transfer time for a 125-microsecond microframe under the USB 2.0 standard is 122 microseconds, which is 97.6% of the microframe and includes 24 commutation delays 220. 96 bytes of packet-switched data 66 can be sent or received during the commutation delay 220, which equals 6,144,000 bits per second. For the remaining time of the microframe (e.g., idle time), 60 bytes of packet-switched data 66 can be sent or received, which equals 3,840,000 bits. Therefore, the total packet-switched data 66 that can be sent or received during the commutation delay 220 and idle time is 9,984,000 bits.

[0117] Figure 18Table 290 shows the inter-packet delay 216 and commutation delay 220, as well as the throughput of the maximum packet-switched data 66 during idle time, for a scenario (i.e., the so-called worst-case scenario) where the use of the wireless communication link 38 for maximizing USB 2.0 data (i.e., the so-called worst-case scenario), according to the embodiments of this disclosure. Specifically, the first row 292 of Table 290 indicates the worst-case scenario for six isochronous outgoing and one bulk outgoing USB 2.0 transfer types. In this case, the total transmission time for a 125-microsecond microframe under the USB 2.0 standard is 115.65 microseconds, which is 92.52% of the microframe, and includes nine inter-packet delays 216 and commutation delays 220. 36 bytes of packet-switched data 66 can be sent or received during the inter-packet delay 216 and commutation delay 220, which is equivalent to 2,304,000 bits per second. For the remaining time of the microframe (e.g., idle time), 184 bytes of packet-switched data 66 can be sent or received, which is equivalent to 11,776,000 bits per second. Therefore, the total packet-switched data 66 that can be sent or received during the inter-packet delay 216, commutation delay 220, and idle time is 14,080,000 bits. The second row 294 of Table 290 indicates the worst-case scenario for six isochronous outgoing and four control-written USB 2.0 transfer types. In this scenario, the total transfer time for a 125-microsecond microframe under the USB 2.0 standard is 122 microseconds, which is 97.6% of the microframe and includes 48 inter-packet delays 216 and commutation delays 220. 192 bytes of packet-switched data 66 can be sent or received during the inter-packet delay 216 and commutation delay 220, which equals 12,288,000 bits per second. For the remaining time of the microframe (e.g., idle time), 60 bytes of packet-switched data 66 can be sent or received, which equals 3,840,000 bits. Therefore, the total packet-switched data 66 that can be sent or received during the inter-packet delay 216, the reversal delay 220, and the idle time is 16,128,000 bits.

[0118] Considering the foregoing, Figure 19A and Figure 19BThis is a flowchart of a method 300 for an electronic device 10A (e.g., a host device) to wirelessly transmit and / or receive a second data stream during a delay between packets of a first data stream, according to embodiments of this disclosure. Method 300 can be executed by any suitable device (e.g., a controller) that controls components of the electronic device 10A, such as processor 12A (e.g., processing circuitry as transceiver 30). In some embodiments, method 300 can be implemented by using processor 12A to execute instructions stored in a tangible, non-transitory computer-readable medium such as memory 14A or storage device 16A. For example, method 300 can be executed at least in part by one or more software components (e.g., an operating system of the electronic device 10A, one or more software applications of the electronic device 10A, etc.). Although method 300 is described using a specific order of steps, it should be understood that this disclosure contemplates that the described steps may be performed in a different order than shown, and that some described steps may be skipped or not performed at all.

[0119] In process block 302, the host device's processor 12A establishes a wireless communication link 38 with the electronic device 10B (e.g., a client device). For example, the wireless communication link 38 may include implementations of mmWave technology (implemented in the EHF band, e.g., the 60 GHz band), NFC standards, etc. Standards, any suitable wireless peer-to-peer communication technology or standard, any suitable wireless network communication technology or standard, etc. In some embodiments, the processor 12A may subsequently establish additional communication links (e.g., wired or wireless) on the wireless communication link 38, including any version of the USB data stream, such as LVDS used by USB 1, USB 2.0, USB 3, USB 4, or DisplayPort. That is, the wireless communication link 38 may replicate or virtualize the USB 2.0 communication link. In some embodiments, the wireless communication link 38 is an EHF link that replicates or virtualizes the wired USB 2.0 communication link.

[0120] In process block 304, processor 12A sends data of a first data stream to a client device via wireless communication link 38 using a wired communication standard. For example, processor 12A may cause transmitter 190 of the host device to send token packets 214, data packets 218 (e.g., with payload data), handshake packets 222, etc. of a USB 2.0 data stream to the client device via an EHF link using the USB 2.0 standard.

[0121] In decision block 306, processor 12A determines whether there is packet exchange data 66 for a second data stream to be sent or received between a first packet that transmits a first data stream via wireless communication link 38 using a wired communication standard and a second packet that transmits or receives the first data stream. Specifically, packet exchange injector 192 can determine whether there is packet exchange data 66 for a second data stream to be sent or received between a first packet that transmits a first data stream via wireless communication link 38 using a USB 2.0 standard and a second packet that transmits or receives the first data stream.

[0122] If not, then in process block 308, processor 12A transmits a first packet of the first data stream via wireless communication link 38 using a wired communication standard. That is, processor 12A enables transmitter 190 to transmit the first packet to the client device via an EHF link using the USB 2.0 standard. In process block 310, processor 12A transmits or receives a second packet of the first data stream via wireless communication link 38 using a wired communication standard. That is, processor 12A can use the USB 2.0 standard via an EHF link to enable transmitter 190 to transmit the second packet to the client device or enable receiver 200 to receive the second packet from the client device.

[0123] If processor 12A determines that there is packet-switched data 66 for a second data stream to be sent or received, then in process block 312, processor 12A determines the delay between the first packet and the second packet for sending the first data stream. For example, the delay may include an inter-packet delay 216 between two consecutive packets (e.g., token packet 214 and data packet 218) sent by a device (e.g., a host device), or a reversal delay 220 between a device (e.g., a host device) sending a packet (e.g., data packet 218) to another device (e.g., a client device) and receiving a response packet (e.g., handshake packet 222) from the other device.

[0124] In process block 314, processor 12A indicates that packet-switched data 66 of the second data stream will be sent or received during the delay period. Specifically, processor 12A may send the indication to the client device via transmitter 190. In some cases, processor 12A may receive the indication to receive packet-switched data 66 during the delay period from the client device via receiver 200 of the client device. The indication may be sent or received during a previous delay period, in a first packet of the first data stream, or in a previous packet transmitted between the host device and the client device.

[0125] In process block 316, processor 12A uses a wired communication standard to send a first packet of a first data stream via wireless communication link 38, similar to process block 308. Figure 11As an example, timing diagram 210 shows that processor 12A can cause transmitter 190 to send data packets 218 to client devices.

[0126] In process block 318, processor 12A transmits or receives packet-switched data 66 of a second data stream via wireless communication link 38 using a wired communication standard during the delay period. That is, processor 12A can cause transmitter 190 to transmit packet-switched or “PEX” data 66 to a client device via an EHF link or cause receiver 200 to receive packet-switched data 66 from a client device during the delay period. Figure 11 As an example, timing diagram 210 shows that processor 12A can cause transmitter 190 to send packet-switched data 66 to client device during commutation delay 220 or cause receiver 200 to receive packet-switched data 66 from client device.

[0127] In process block 320, processor 12A uses wired communication standards to send or receive second packets of the first data stream via wireless communication link 38, similar to process block 310. Figure 11 Using timing diagram 210 as an example, processor 12A enables receiver 200 to receive handshake packet 222 from client device (e.g., as an acknowledgment that client device has received data packet 218). In this way, method 300 enables host device to wirelessly transmit or receive a second data stream during the delay between transmitting or receiving packets of the first data stream.

[0128] Figure 20 This is a flowchart of a method 330 for an electronic device 10B (e.g., a client device) to wirelessly receive and / or transmit a second data stream during a delay between receiving or transmitting packets of a first data stream, according to embodiments of this disclosure. Method 330 can be executed by any suitable device (e.g., a controller) that controls components of the electronic device 10B, such as processor 12B (e.g., processing circuitry as transceiver 30). In some embodiments, method 330 can be implemented by using processor 12B to execute instructions stored in a tangible, non-transitory computer-readable medium such as memory 14B or storage device 16B. For example, method 330 can be executed at least in part by one or more software components such as the operating system of the electronic device 10B, one or more software applications of the electronic device 10B, etc. Although method 330 is described using a specific order of steps, it should be understood that this disclosure contemplates that the described steps may be performed in a different order than shown, and that some described steps may be skipped or not performed at all.

[0129] In process block 332, the processor 12B of the client device establishes a wireless communication link 38 with the electronic device 10A (e.g., the host device). The establishment of the wireless communication link 38 and the details of the wireless communication link 38 are similar to those described in process block 302 of method 300.

[0130] In process block 334, processor 12B receives a first packet of a first data stream from a host device via wireless communication link 38 using a wired communication standard. For example, processor 12B may cause receiver 200 of a client device to receive token packets 214, data packets 218 (e.g., with payload data), handshake packets 222, etc., of a USB 2.0 data stream from the host device via an EHF link using the USB 2.0 standard. Figure 11 As an example, timing diagram 210 shows that processor 12B enables receiver 200 of client device to receive data packets 218.

[0131] In decision block 336, processor 12B determines whether an indication has been received that packet-switched data 66 of the second data stream will be received or transmitted during a delay between the transmission of a first packet of the first data stream and the transmission or reception of a second packet of the first data stream. Specifically, processor 12B may receive the indication from the host device via receiver 200. In some cases, processor 12B may transmit an indication to the host device via transmitter 190 of the client device to transmit packet-switched data 66 during the delay. The indication may be received or transmitted during a previous delay, in a first packet of the first data stream, or in a previous packet transmitted between the host device and the client device.

[0132] If the processor 12B determines that no instruction has been received, then in process block 338, the processor 12B uses a wired communication standard to receive or transmit a second packet of the second data stream via wireless communication link 38. That is, the processor 12A can cause the receiver 200 to receive the second packet from the host device via an EHF link using the USB 2.0 standard or cause the transmitter 190 to transmit the second packet to the host device.

[0133] If the processor 12B determines that an instruction has been received, then in process block 340, the processor 12B receives or transmits packet-switched data 66 of the second data stream via wireless communication link 38 during the delay period. That is, the processor 12B can cause the receiver 200 to receive packet-switched data 66 from the host device via the EHF link during the delay period or cause the transmitter 190 to transmit packet-switched data 66 to the host device. Figure 11 As an example, timing diagram 210 shows that processor 12B can cause receiver 200 to receive packet-switched data 66 from host device during commutation delay 220 or cause transmitter 190 to send packet-switched data 66 to host device.

[0134] Then, in process block 338, processor 12B uses wired communication standards to receive or transmit second packets of the second data stream via wireless communication link 38. Figure 11 Using timing diagram 210 as an example, processor 12B can cause transmitter 190 to send handshake packet 222 to host device (e.g., as an acknowledgment that client device has received data packet 218). In this way, method 330 enables client device to wirelessly receive or transmit a second data stream during the delay between receiving or transmitting packets of the first data stream.

[0135] In some cases, the host device may determine to extend the delay between packets of the first data stream, thereby increasing the time between transmitted packets and increasing the amount of packet-switched data 66 of the second data stream transmitted or received during the extended delay. Figure 21A and Figure 21B This is a flowchart of a method 350 for an electronic device 10A (e.g., a host device) to extend the delay between packets transmitting a first data stream, thereby enabling the transmission or reception of additional packets of a second data stream during the extended delay, according to embodiments of the present disclosure. Method 350 can be executed by any suitable device (e.g., a controller) that controls components of the electronic device 10A, such as processor 12A (e.g., processing circuitry as transceiver 30). In some embodiments, method 350 can be implemented by using processor 12A to execute instructions stored in a tangible, non-transitory computer-readable medium such as memory 14A or storage device 16A. For example, method 350 can be executed at least in part by one or more software components (e.g., an operating system of the electronic device 10A, one or more software applications of the electronic device 10A, etc.). Although method 350 is described using steps in a specific order, it should be understood that the present disclosure contemplates that the steps may be performed in a different order than shown, and that some steps may be skipped or not performed at all.

[0136] Method 350 can continue from process block 312 of method 300, and thus in process block 352, the host device's processor 12A determines the delay between the first and second packets of the first data stream transmitted via the wireless communication link according to wired communication standards. In decision block 354, the processor 12A determines whether to receive or determine an indication to extend the delay. For example, the host device may determine to extend the delay because the size of the packet exchange data 66 to be transmitted is greater than a threshold size. Alternatively, the host device may determine to periodically extend the delay. Or, for example, when the size of the USB 2.0 data stream is below a threshold level, the host device may determine to extend the delay. In some embodiments, at certain times, the host device may prioritize the USB 2.0 data stream (e.g., when the size of the USB 2.0 data stream exceeds a threshold level, by default, as requested by the user) and may not extend the delay during those times to ensure faster USB 2.0 data delivery. At other times, the host device may prioritize the data stream of packet-switched data 66 (e.g., when the size of the data stream of packet-switched data 66 exceeds a threshold level, by default, as requested by the user), and may extend the delay during those times to ensure faster delivery of packet-switched data 66.

[0137] If processor 12A determines that it has not yet received or has determined an indication to extend the delay, then in process block 356, processor 12A indicates that it will send or receive packet-switched data 66 of the second data stream during the delay period in the first packet of the first data stream, similar to process block 314 of method 300. In process block 358, processor 12A then sends the first packet of the first data stream via wireless communication link 38 using a wired communication standard, similar to process block 316 of method 300. In process block 360, processor 12A sends or receives packet-switched data 66 of the second data stream via wireless communication link 38 during the delay period, similar to process block 318 of method 300. And in process block 362, processor 12A sends the second packet of the first data stream via wireless communication link 38 using a wired communication standard, similar to process block 320 of method 300.

[0138] If processor 12A determines that an indication of extended delay has been received or determined, then in process block 364, an extended delay is indicated between the transmission of the first packet and the second packet of the first data stream, and packet-switched data 66 of the second data stream will be transmitted or received during the extended delay. Specifically, processor 12A may send the indication to the client device via transmitter 190. The indication may be sent or received during the previous delay, in the first packet of the first data stream, or in previous packets transmitted between the host device and the client device. Figure 11As an example, timing diagram 210 shows that processor 12B can send an indication to the client device that the inter-packet delay 216 between token packet 214 and data packet 218 will be extended.

[0139] In process block 366, processor 12A transmits a first packet of a first data stream via a wireless communication link using a wired communication standard, similar to process block 316 of method 300. Figure 11 Using timing diagram 210 as an example, processor 12B can send token packets 214 via an EHF link using the USB 2.0 standard. In process block 368, processor 12A sends or receives packet-switched data 66 of a second data stream via wireless communication link 38 during an extended delay between sending the first and second packets. That is, processor 12A can cause the packet-switched injector 192 of transmitter 190 to operate selection circuitry 196 to select packet-switched data 66 for transmission to a client device, and cause transmitter 190 to send packet-switched data 66 to the client device. Alternatively, processor 12A can cause receiver 200 to receive packet-switched data 66 from a client device. Figure 11 As an example, timing diagram 210 allows processor 12A to cause packet switching injector 192 to select packet switching data 66 for transmission to client device and to cause transmitter 190 to send packet switching data 66 to client device, or to cause receiver 200 of host device to receive packet switching data 66 from client device during extended inter-packet delay 216.

[0140] In process block 370, processor 12A buffers a second packet of the first data stream transmitted via wireless communication link 38 using a wired communication standard during the extended delay. Specifically, when packet switching injector 192 operates selection circuit 196 to select packet-switched data 66 for transmission to the client device during the extended delay, outgoing data 62, including the second packet (and possibly more packets) of the first data stream, is delayed or time-shifted in buffer 194. Figure 11 As an example, timing diagram 210 shows that processor 12A can cause buffer 194 to delay or time-shift data packets 218 during extended inter-packet delay 216, while transmitter 190 sends packet-switched data 66 to client device.

[0141] In process block 372, processor 12A determines whether the extended delay has elapsed. If not, processor 12A continues to transmit or receive packet-switched data 66 of the second data stream via wireless communication link 38, as described in process block 368, and continues to buffer the second packets of the first data stream, as well as any other packets of the first data stream received by transmitter 190 during the extended delay. Figure 11As an example, timing diagram 210 shows that processor 12A can cause buffer 194 to continue delaying or time-shifting data packets 218 during extended inter-packet delay 216, while transmitter 190 continues to send packet-switched data 66 to client device.

[0142] If processor 12A determines that the extended delay has elapsed, then in process block 374, processor 12A transmits a second packet of the first data stream via wireless communication link 38 using a wired communication standard. Specifically, processor 12A may cause packet switching injector 192 to operate selection circuitry 196 to select outgoing data 62 (e.g., including the second packet of the first data stream and any other buffered packets) delayed or time-shifted by buffer 194 for transmission via EHF link 38 using the USB 2.0 standard. Figure 11 Using timing diagram 210 as an example, processor 12A enables packet switching injector 192 to operate selection circuit 196 to select data packets 218 delayed or time-shifted by buffer 194 for transmission to client device. In this way, method 350 enables host device to extend the delay between packets transmitting the first data stream, thereby enabling the transmission or reception of more packet-switched data 66 of the second data stream during the extended delay.

[0143] Figure 22 This is a flowchart of a method 380 for an electronic device 10B (e.g., a client device) to receive or transmit additional packet exchange data 66 of a second data stream during an extended delay between receiving packets of a first data stream, according to embodiments of this disclosure. Method 380 can be executed by any suitable device (e.g., a controller) that controls components of the electronic device 10B, such as processor 12B (e.g., processing circuitry as transceiver 30). In some embodiments, method 380 can be implemented by using processor 12B to execute instructions stored in a tangible, non-transitory computer-readable medium such as memory 14B or storage device 16b. For example, method 380 can be executed at least in part by one or more software components such as the operating system of the electronic device 10B, one or more software applications of the electronic device 10B, etc. Although method 380 is described using a specific order of steps, it should be understood that this disclosure contemplates that the described steps may be performed in a different order than shown, and that some described steps may be skipped or not performed at all.

[0144] Method 380 may continue from decision block 336 of method 300, and thus in process block 382, ​​the processor 12B of the client device receives an indication that packet-switched data 66 will be received or transmitted during the delay between the first packet and the second packet of the first data stream. In decision block 384, the processor 12B determines whether it has received an indication that the delay between the first packet and the second packet is an extended delay. Specifically, the processor 12B may receive the indication from the host device via receiver 200. This indication may be received during a previous delay, in the first packet of the first data stream, in previous packets transmitted between the host device and the client device, etc.

[0145] If the processor 12B determines that it has not yet received an indication that the delay is an extended delay, then in block 386, the processor 12B receives or transmits packet-switched data 66 of the second data stream via wireless communication link 38 during the delay, similar to process block 340 of method 330. In process block 388, the processor 12B subsequently receives a second packet of the first data stream via wireless communication link 38 according to a wired communication standard, similar to process block 338 of method 330.

[0146] If processor 12B determines that it has received an indication that the delay is an extended delay, then in process block 390, processor 12B receives or transmits packet-switched data 66 of the second data stream via wireless communication link 38 during the extended delay. That is, processor 12B can cause receiver 200 to receive packet-switched data 66 from host device via EHF link or cause transmitter 190 to transmit packet-switched data 66 to host device during the extended delay. Figure 11 Using timing diagram 210 as an example, assuming that the inter-packet delay 216 has been extended by the host device, the processor 12B can cause the receiver 200 to receive packet-switched data 66 from the host device during the extended inter-packet delay 216 or cause the transmitter 190 to send packet-switched data 66 to the host device.

[0147] Then, in process block 392, processor 12B receives a second packet of the first data stream via wireless communication link 38 after an extended delay, according to a wired communication standard. That is, processor 12B enables receiver 200 to receive the second packet from the host device via an EHF link using the USB 2.0 standard. Figure 11 Using timing diagram 210 as an example, processor 12B enables receiver 200 to receive data packets 218 from host device. In this way, method 350 enables client device to receive or send additional packets of second data stream exchange data 66 during an extended delay between receiving packets of the first data stream.

[0148] Figure 23 It is based on the implementation scheme of this disclosure. Figure 9A detailed schematic diagram of transmitter 190 is provided. As shown, outgoing data 62 can be received at line receiver 400 and traverses sampler 402 (e.g., sampling circuitry or software), synchronization detector and packet identifier (PID) decoder 404 (e.g., synchronization detection circuitry / software that detects the synchronization or "synchronization" field of packets of outgoing data 62, and PID decoding circuitry / software that decodes the packet identifier of packets of outgoing data 62), and resilient buffer (e.g., buffer 194) that buffers outgoing data 62 (e.g., packets of the first data stream) when processor 12 extends the delay between packets of the first data stream. Specifically, buffer 194 can delay or time-shift outgoing data 62 by approximately 20 to 30 USB 2.0 high-speed bit times. As shown, packet-switched data 66 may include housekeeping data, debug and / or serial line debug (SWD) data, UART data (e.g., UART1, UART2), and / or audio data. In some implementations, packet-switched data 66 may be combined with a transmission encoder, a packet-switched (PEX) state machine, and eUSB2 (embedded USB 2.0) logic (e.g., which may be collectively included in...). Figure 9 Packet exchange injector 192 and / or Figure 3 The buffer 406 in the data type controller 42 delays or time-shifts the packet-switched data 66 until the processor 12 is ready to send the packet-switched data 66. That is, the packet-switched injector 192 may include transmission encoding circuitry and / or software, a packet-switching state machine (e.g., a state machine that determines how to process the outgoing packet-switched data 66), and / or logic for implementing and / or operating the embedded USB 2.0 (e.g., for processing the outgoing USB 2.0 data 62). eUSB2 is a complement to the USB 2.0 specification, addressing issues related to the integration of the interface controller with advanced system-on-chip (SoC) process nodes. Like buffer 194, buffer 406 may delay or time-shift the packet-switched data 66 by approximately 20 to 30 USB 2.0 high-speed bit times. It should be understood that the term "logic" may include software (e.g., machine-executable instructions stored in memory such as memory 14), hardware (e.g., circuitry), or both. The packet switching injector 192 can receive a high-speed, high-accuracy clock 407 (e.g., operating at a frequency of 1 GHz ± 500 parts per million (ppm) or better) for operation.

[0149] The packet-switched injector 192 operates a selection circuit 196 to select either outgoing data 62 or packet-switched data 66. Its output can traverse a pulse-shaping filter 408 and a mixer 410 to be mixed with a voltage-controlled oscillator 412. The output can be amplified by a power amplifier 72 and then transmitted as transmitted data 76 by an mmWave patch antenna (e.g., antenna 36).

[0150] Figure 24 It is based on the implementation scheme of this disclosure. Figure 10 A detailed schematic diagram of receiver 200 is provided. As shown, the received signal 82 is received at an mmWave patch antenna (e.g., antenna 36) and passes through a low-noise amplifier 84, a demodulator 88, an analog baseband filter 86A and a pulse shaping filter 86B (e.g., one or more filters 86), a sampler 420 (e.g., sampling circuitry and / or software), and a combined synchronization detector, an SOF counter, a PID decoder, a receive decoder, and a packet switching state machine (e.g., which may collectively include...). Figure 10 Packet exchange extractor 202 and / or Figure 3 The data type controller 42 and eUSB2 logic are used to transmit. That is, the packet exchange extractor 202 may include synchronization detection circuitry and / or software, SOF counting circuitry and / or software, PID decoding circuitry and / or software, receive decoding circuitry and / or software, packet exchange state machine (e.g., for processing incoming packet exchange data 66) and / or logic for implementing and / or operating the embedded USB 2.0 (e.g., for processing incoming USB 2.0 data 96). The packet exchange extractor 202 may extract packet exchange data 66 from the received data 82 and delay or time-shift packet exchange data 66 in buffer 422 until it is ready for processing. Buffer 422 may delay or time-shift packet exchange data 66 by approximately 20 to 30 USB 2.0 high-speed bit times. As shown, packet exchange data 66 may include housekeeping data, debug and / or serial line debug (SWD) data, UART data (e.g., UART1, UART2), audio data, etc. The packet switching extractor 202 can send the incoming data 62 to the line driver 424 for processing.

[0151] The specific embodiments described above have been illustrated by way of example, and it should be understood that various modifications and alternatives are permissible. It should also be understood that the claims are not intended to limit us to the specific forms disclosed, but rather to cover all modifications, equivalents, and alternatives falling within the substance and scope of this disclosure.

[0152] The techniques described herein and protected by the claims are referenced and applied to specific examples of physical and practical nature, which significantly improve the technical field and are therefore not abstract, intangible, or purely theoretical. Furthermore, if any claim appended to the end of this specification contains one or more elements designated as "means for [performing] [function]..." or "steps for [performing] [function]...", those elements shall be interpreted in accordance with 35U.SC112(f). However, for any claim containing elements designated in any other manner, those elements shall not be interpreted in accordance with 35U.SC112(f).

Claims

1. A method comprising: A wireless communication link with an electronic device is established via at least one processor; The first data stream is transmitted to the electronic device via the wireless communication link using the at least one processor, employing wired communication standards. The at least one processor generates packets to be transmitted during a first synchronization frame of the wired communication standard by replacing synchronization information with configuration information, the configuration information indicating packet exchange data to be transmitted or received during a second synchronization frame of the wired communication standard. The packet is transmitted to the electronic device via the at least one processor and via the wireless communication link; Receive confirmation from the electronic device via the at least one processor and via the wireless communication link; as well as The packet-switched data of the second data stream is transmitted to the electronic device or received from the electronic device via the wireless communication link via the at least one processor.

2. The method according to claim 1, wherein the wired communication standard includes one of the Universal Serial Bus (USB) 1 standard, USB 2.0 standard, USB 3 standard, USB 4 standard, Low Voltage Differential Signaling (LDS) standard used by DisplayPort digital display interface, or Universal Asynchronous Receiver-Transmitter (UAST) standard.

3. The method of claim 1, wherein the configuration information identifies the second synchronization frame to be sent or received during its transmission of the packet-switched data.

4. The method according to claim 1, wherein the second data stream includes a universal serial bus data stream, a universal asynchronous receiver / transmitter data stream, a serial peripheral interface data stream, or an inter-integrated circuit data stream.

5. The method of claim 1, wherein receiving the acknowledgment from the electronic device via the wireless communication link via the at least one processor occurs during the first synchronization frame.

6. An electronic device, comprising: One or more antennas; A transmitting circuit configured to transmit signals via the one or more antennas; A receiving circuit configured to receive signals from the one or more antennas; as well as At least one processor, coupled to the transmitting circuit and the receiving circuit, and configured to: Establish wireless communication links with other electronic devices; The receiving circuit uses a wired communication standard to receive data from the other electronic device via the wireless communication link; This enables the receiving circuit to receive a first packet from the other electronic device via the wireless communication link during the first synchronization frame of the wired communication standard; as well as In response to determining that the first packet includes configuration information associated with packet exchange data of a second data stream to be transmitted or received during a second synchronization frame of the wired communication standard: Generate and process a second packet according to the wired communication standard; and During the second synchronization frame of the wired communication standard, the receiving circuit is caused to receive the packet-switched data of the second data stream, or the transmitting circuit is caused to transmit the packet-switched data of the second data stream to the other electronic device.

7. The electronic device of claim 6, wherein the second group is configured to facilitate synchronization or interruption functions between the electronic device and the other electronic device.

8. The electronic device of claim 6, wherein the second packet includes a frame start packet according to the wired communication standard.

9. The electronic device of claim 6, wherein the first synchronization frame and the second synchronization frame each comprise 158.33 nanoseconds to 200 nanoseconds.

10. The electronic device of claim 6, wherein the first group and the second group each comprise 76 bits to 96 bits.

11. The electronic device of claim 6, wherein the first frame of the wired communication standard includes a first plurality of synchronization frames, wherein the first plurality of synchronization frames includes the first synchronization frame, wherein the second frame includes a second plurality of synchronization frames, and wherein the second plurality of synchronization frames includes the second synchronization frame.

12. The electronic device of claim 11, wherein the first frame and the second frame each comprise one millisecond.

13. The electronic device of claim 6, wherein the at least one processor is configured to associate the configuration information with packet-switched data of a third data stream to be transmitted or received during a third synchronization frame of the wired communication standard and packet-switched data of a fourth data stream to be transmitted or received during a fourth synchronization frame of the wired communication standard: During the third synchronization frame of the wired communication standard, the receiving circuit is caused to receive the packet-switched data of the third data stream, or the transmitting circuit is caused to transmit the packet-switched data of the third data stream to the other electronic device; and During the fourth synchronization frame of the wired communication standard, the receiving circuit is caused to receive the packet-switched data of the fourth data stream, or the transmitting circuit is caused to transmit the packet-switched data of the fourth data stream to the other electronic device.

14. The electronic device of claim 13, wherein the frame of the wired communication standard includes the second synchronization frame, the third synchronization frame, and the fourth synchronization frame, and wherein the total time of the second synchronization frame, the third synchronization frame, and the fourth synchronization frame includes 474.99 nanoseconds to 600 nanoseconds.

15. The electronic device of claim 13, wherein the frame of the wired communication standard includes the second synchronization frame, the third synchronization frame, and the fourth synchronization frame, and wherein the total size of the packet-switched data of the second synchronization frame, the packet-switched data of the third synchronization frame, and the packet-switched data of the fourth synchronization frame includes 228 bits to 288 bits.

16. The electronic device of claim 6, wherein the at least one processor is configured to generate and process a third packet according to the wired communication standard to replace the packet-switched data of the second data stream received or transmitted during the second synchronization frame of the wired communication standard.

17. The electronic device of claim 6, wherein the configuration information indicates the data type of the packet-switched data.

18. The electronic device of claim 17, wherein the data type of the packet-switched data includes user data, control information, maintenance data, or any combination thereof.

19. An electronic device comprising: One or more antennas; A transmitting circuit configured to transmit signals via the one or more antennas; A receiving circuit configured to receive signals from the one or more antennas; as well as At least one processor, coupled to the transmitting circuit and the receiving circuit, and configured to: Determine the delay between a first packet of a first data stream transmitted via a wireless communication link according to a wired communication standard and a second packet of the first data stream transmitted or received. Indicates that a second data stream will be sent during the delay period; This enables the transmitting circuit to transmit the first packet of the first data stream via the wireless communication link using the wired communication standard; This causes the transmitting circuit to transmit the packet-switched data of the second data stream via the wireless communication link during the delay period; as well as This causes the transmitting circuit to transmit the second packet of the first data stream via the wireless communication link using the wired communication standard, or causes the receiving circuit to receive the second packet of the first data stream.

20. The electronic device of claim 19, wherein the delay includes commutation delay or inter-packet delay.

21. The electronic device of claim 19, wherein the at least one processor is configured to cause the transmitting circuit to transmit the packet-switched data of the first data stream via the wireless communication link in an extremely high frequency band during the delay.

22. The electronic device of claim 19, wherein the one or more antennas comprise millimeter-wave antennas, and wherein the at least one processor is configured to cause the transmitting circuit to transmit the packet-switched data of the first data stream over the wireless communication link via the millimeter-wave antenna in a 60 GHz band during the delay.

23. The electronic device of claim 19, wherein the at least one processor is configured to send an indication to transmit packet-switched data of the second data stream during the delay in the first packet of the first data stream.

24. The electronic device of claim 19, comprising a buffer configured to delay outgoing data packets, wherein the at least one processor is configured to: Determine whether to extend the delay; In response to determining to extend the delay: The packet exchange data indicates an extended delay between the first packet and the second packet that transmit the first data stream, and the second data stream will be transmitted during the extended delay. This enables the transmitting circuit to transmit the first packet of the first data stream via the wireless communication link using the wired communication standard; This enables the transmitting circuit to transmit the packet-switched data of the second data stream via the wireless communication link during the extended delay period; This causes the buffer to delay the second packet of the first data stream during the extended delay; as well as In response to determining that the extended delay has passed, the transmitting circuit transmits the second packet of the first data stream via the wireless communication link using the wired communication standard.

25. The electronic device of claim 19, wherein the at least one processor is configured to cause the transmitting circuit to transmit additional packets of the second data stream during an idle period between transmitting the first packet of the first data stream and transmitting or receiving the second packet of the first data stream.

26. One or more tangible, non-transitory computer-readable media, including instructions that, when executed by one or more processors, cause the one or more processors to: Establish wireless communication links with electronic devices; The first packet of the first data stream is received from the electronic device via the wireless communication link using a wired communication standard; Based on receiving an instruction to receive or transmit the packet-switched data during a delay between receiving the first packet and receiving or transmitting the second packet of the first data stream, packet-switched data of the second data stream is received or transmitted via the wireless communication link; as well as The second packet of the first data stream is received or transmitted via the wireless communication link using the wired communication standard.

27. One or more tangible non-transitory computer-readable media of claim 26, comprising instructions that, when executed by the one or more processors, cause the one or more processors to receive or transmit the packet-switched data via the wireless communication link during the delay.

28. One or more tangible non-transitory computer-readable media according to claim 26, wherein the wired communication standard includes one of the Universal Serial Bus (USB) 1 standard, USB 2.0 standard, USB 3 standard, USB 4 standard, Low Voltage Differential Signaling standard used by DisplayPort digital display interface, or Universal Asynchronous Receiver-Transmitter standard.

29. One or more tangible non-transitory computer-readable media according to claim 26, wherein the second data stream includes a universal serial bus data stream, a universal asynchronous receiver / transmitter data stream, a serial peripheral interface data stream, or an inter-integrated circuit data stream.

30. One or more tangible non-transitory computer-readable media of claim 26, comprising instructions that, when executed by the one or more processors, cause the one or more processors to receive or transmit the packet-switched data during one or more commutation delays, one or more idle times, or both of a microframe.

31. One or more tangible non-transitory computer-readable media according to claim 30, wherein the microframe comprises 125 microseconds and the packet-switched data comprises at least 9,984,000 bits.

32. One or more tangible non-transitory computer-readable media of claim 26, comprising instructions that, when executed by the one or more processors, cause the one or more processors to receive or transmit the packet-switched data during one or more inter-packet delays, one or more commutation delays, one or more idle times, or any combination thereof in a microframe.

33. One or more tangible non-transitory computer-readable media according to claim 32, wherein the microframe comprises 125 microseconds and the packet-switched data comprises at least 14,080,000 bits.

34. A method comprising: The delay between the first packet and the second packet of the first data stream transmitted via a wireless communication link according to the wired communication standard is determined by the processing circuitry of the electronic device. An instruction to extend the delay is received via the receiver of the electronic device; A second indication of an extended delay in transmitting the first packet and the second packet is transmitted via the transmitter of the electronic device; The first packet is transmitted via the transmitter via the wireless communication link according to the wired communication standard; During the extended delay, packet-switched data is transmitted via the transmitter through the wireless communication link or received via the receiver; The second packet is buffered via the processing circuit during the extended delay; and The second packet is transmitted via the transmitter via the wireless communication link according to the wired communication standard.

35. The method of claim 34, further comprising transmitting via the transmitter a third indication of transmitting or receiving the packet-switched data during the extended delay.

36. The method of claim 34, further comprising determining, via the processing circuitry, that the extended delay has elapsed.

37. The method of claim 36, wherein the second packet is transmitted via the transmitter based on the extended delay having elapsed.

38. The method of claim 34, wherein the packet-switched data includes user data, control information, maintenance data, or any combination thereof.

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