Micro-led array with adaptive pwm phase shift

Abstract

A method for controlling turn-on and turn-off of pixels within an LED array is described. Turn-on delay of a pixel within the LED array is based on a duty cycle of the pixel. Pixels are grouped based on corresponding duty cycles. Turn-on delay of each pixel is based on a group that includes the pixel and a position of the pixel within the group. The LED array is driven by circuitry in a CMOS backplane.

Description

[0001] priority This application claims priority to U.S. Provisional Patent Application No. 62 / 951199, filed December 20, 2019, which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates generally to light-emitting diodes, and more specifically to power supplies for miniature light-emitting diodes. Background Technology

[0003] Miniature light-emitting diode (μLED) arrays are an emerging technology in the lighting and display industries. A μLED array typically comprises thousands to millions of tiny light-emitting diode (LED) pixels that can emit light and can be individually controlled. Compared to other lighting and display technologies, μLED arrays can provide higher brightness and better energy efficiency, making them desirable for a wide range of applications—among others—such as televisions, automotive headlights, and mobile phones. Attached Figure Description

[0004] To provide a more complete understanding of this disclosure and its features and advantages, reference is made to the following description in conjunction with the accompanying drawings, wherein similar reference numerals denote similar parts, in which: Figure 1 An example lighting system according to some embodiments of the present disclosure is illustrated.

[0005] Figure 2 An example table illustrating the duty cycle of pixels within a μLED array according to some embodiments of the present disclosure is shown.

[0006] Figure 3 An example pixel numbering method according to some embodiments of the present disclosure is illustrated.

[0007] Figure 4 The illustration shows an example grouping of pixels within a μLED array according to some embodiments of the present disclosure.

[0008] Figure 5 An example timing diagram of pixel turn-on in a μLED array according to some embodiments of the present disclosure is illustrated.

[0009] Figure 6 An example current diagram of the power supply output current according to some embodiments of the present disclosure is illustrated.

[0010] Figure 7 Another example timing diagram of pixel turn-on in a μLED array according to some embodiments of the present disclosure is illustrated.

[0011] Figure 8 An example current diagram of the power supply output current according to some embodiments of the present disclosure is illustrated.

[0012] Figure 9 The illustration shows an example process for implementing pulse width modulation dimming according to some embodiments of the present disclosure.

[0013] Figure 10 An example pixel batching method according to some embodiments of the present disclosure is illustrated.

[0014] Figure 11 An example system according to some embodiments of the present disclosure is illustrated.

[0015] Figure 12 An example lighting system according to some embodiments of the present disclosure is illustrated.

[0016] Figure 13 The figures illustrate some embodiments of the present disclosure for implementation. Figure 11 Example hardware layout of the system.

[0017] Figure 14 The illustration shows an example hardware arrangement for implementing the system according to some embodiments of the present disclosure.

[0018] Figure 15 An example system according to some embodiments of the present disclosure is illustrated. Detailed Implementation

[0019] The systems, methods, and apparatus of this disclosure may include one or more innovative aspects, wherein the innovative aspects may contribute individually or in combination to the desired properties disclosed herein. Details of one or more implementations of the subject matter described herein are set forth in the following description and figures.

[0020] For the purpose of illustrating the process of providing appropriate current levels to μLED pixels to achieve the image as described herein, it may be useful to understand the phenomena that may function in a headlight. The following basic information can be considered as the basis for the proper interpretation of this disclosure. Such information is provided for illustrative purposes only and therefore should not be construed in any way as limiting the broad scope of this disclosure and its potential applications.

[0021] For μLED arrays, image data can be provided to define the image displayed by the μLED array. To display and realize the image, the current level of the pixels within the μLED array can be adjusted based on the image and / or light profile to be generated. One method for adjusting the current level is to utilize pulse width modulation (PWM) dimming. Specifically, for PWM dimming, the pixels within the μLED array can be turned on and off at a specific frequency, and the ratio between the on-time and period or cycle time can be adjusted to produce the pixel's duty cycle. For PWM dimming, the average DC current through the pixels of the μLED array can be the product of the current amplitude supplied to the pixel and the pixel's duty cycle.

[0022] PWM dimming used to adjust the pixel current level in a μLED array can produce a square-wave shaped pixel current with rich harmonic components. The sum of the currents of all pixels in the μLED array can also include harmonic components, which can cause high root-mean-square (RMS) current and resistive losses. Furthermore, electromagnetic interference (EMI) and harmonic noise levels can be high due to the harmonic components. Conventional methods attempting to address rich harmonics involve setting the pixel turn-on delay based on the total number of pixels in the μLED array and the pixel positions within the μLED array. Specifically, the cycle period of the PWM dimming method can be divided by the total number of pixels in the μLED array to determine the amount of delay time between the turn-on of each pixel in the μLED array. Each pixel in the μLED array is then turned on in the order defined by its position within the μLED array, where each subsequent turn-on of a pixel in that order is the delay time following the turn-on of the previous pixel in that order. However, this conventional method may still have abundant harmonic components with high RMS current, resistive losses, EMI, and / or harmonic noise levels, especially when pixels with the same or similar duty cycles are positioned adjacently in the turn-on sequence of the μLED array. Furthermore, the increased number of pixels in a μLED array compared to the number of pixels in a non-μLED array is likely to only exacerbate these problems.

[0023] Embodiments of this disclosure provide a method for controlling the on (activation) and off (deactivation) of pixels within a μLED array. The systems and processes disclosed herein can define the on-time of pixels within a μLED array based on the pixel's duty cycle. Pixels can be grouped based on corresponding duty cycles, and the on-time of pixels can be determined based on the groups comprising each pixel.

[0024] As those skilled in the art will appreciate, aspects of this disclosure—particularly the aspects of pixel turn-on control of the μLED array described herein—can be embodied in various ways, such as as a method, system, computer program product, or computer-readable storage medium. Therefore, aspects of this disclosure can take the form of a completely hardware embodiment, a completely software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining software and hardware aspects, which are generally referred to herein as “circuit,” “module,” or “system.” The functionality described in this disclosure can be implemented as an algorithm executed by one or more hardware processing units (e.g., one or more microprocessors) of one or more computers. Although processors are mentioned herein, any logic capable of performing the indicated functions can be used. In various embodiments, different steps and step portions of each method described herein can be executed by different processing units. Furthermore, aspects of this disclosure can take the form of a computer program product embodied in one or more computer-readable media, preferably non-transitory, on which computer-readable program code is embodied (e.g., stored). In various embodiments, such computer programs may be downloaded (updated) to existing devices and systems (e.g., existing lighting systems, etc.) or stored during the manufacture of these devices and systems.

[0025] In the following detailed description, various aspects of the illustrative implementation may be described using terminology commonly used by those skilled in the art to communicate the substance of their work to others skilled in the art. For example, the term “connection” means a direct electrical or magnetic connection between things connected without any intermediate devices, while the term “coupling” means a direct electrical or magnetic connection between things connected, or an indirect connection via one or more passive or active intermediate devices. The term “circuit” means one or more passive and / or active components arranged to cooperate with each other to provide the desired function.

[0026] For the purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term "between" when used to refer to a measurement range includes both ends of the measurement range.

[0027] This specification uses the phrases "in one embodiment" or "in an embodiment," each of which can refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," etc., used with respect to embodiments of this disclosure are synonymous. This disclosure may use perspective-based descriptions such as "above," "below," "top," "bottom," and "side"; such descriptions are used to facilitate discussion and are not intended to limit the application of the disclosed embodiments. Unless otherwise specified, the use of ordinal adjectives such as "first," "second," and "third" to describe common objects merely indicates that different instances of the same object are referenced and is not intended to imply that the objects so described must be in a given order in time, space, sequence, or any other manner.

[0028] In the following detailed description, reference is made to the accompanying drawings, which form a part of this detailed description, illustrating some embodiments that may be practiced. In the drawings, the same reference numerals refer to the same or similar elements / materials; therefore, unless otherwise stated, the interpretation of an element / material with a given reference numeral in the context of one drawing applies to other drawings in which elements / materials with the same reference numerals may be illustrated. The drawings are not necessarily drawn to scale. Furthermore, it will be understood that some embodiments may include more elements than illustrated in the drawings, some embodiments may include a subset of the elements illustrated in the drawings, and some embodiments may incorporate any suitable combination of features from two or more drawings.

[0029] Various operations can be described sequentially as multiple discrete actions or operations in a manner most conducive to understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations must be sequentially related. In particular, these operations may not be performed in the order presented. The described operations may be performed in a different order than the described embodiments. In additional embodiments, various additional operations may be performed, and / or the described operations may be omitted.

[0030] In some of the examples provided herein, interactions may be described based on two, three, four, or more electrical components. However, this is merely for clarity and illustrative purposes. It should be understood that the devices and systems described herein can be combined in any suitable manner. Along similar design alternatives, any components, modules, and elements illustrated in the figures can be combined in a variety of possible configurations, all of which are clearly within the broad scope of this disclosure. In some cases, it may be easier to describe one or more functionalities of a given set of processes by referring to only a limited number of electrical components.

[0031] As used herein, the states of a switch can be referred to as “open” and “closed.” In some embodiments, a switch may include a physical throw, wherein the term “open” may refer to a throw that opens the circuitry implementing the switch to prevent current flow, and the term “closed” may refer to a throw that closes the circuitry implementing the switch to allow current flow. In some embodiments, a switch may include a transistor, wherein the term “open” may refer to a transistor exhibiting high resistance that allows a minimum amount of current flow, and the term “closed” may refer to a transistor exhibiting a large amount of current flow. Furthermore, when referring to a switch that includes a transistor that allows or prevents current flow, it should be understood that the current flow when the switch allows current flow may be the amount of current flowing through the transistor when it is “closed,” and the current flow when the switch prevents current flow may be the amount of current flowing through the transistor when it is “open” (which may be non-zero in some instances). It should be understood that the amount of current allowed to flow through the transistor when it is “open” and “closed” may depend on the characteristics of the transistor, and the terms “open” and “closed” should be interpreted as terms that a person skilled in the art would understand when referring to a transistor used as a switch.

[0032] As used herein, pixels of light-emitting diodes (LEDs), micro-light-emitting diodes (μLEDs), and μLED arrays may be referred to as “on” and “off.” The term “on” may refer to a state in which current is allowed to flow through the LED, μLED, and / or μLED array pixel, or a transition to that state. The term “off” may refer to a state in which current is blocked from flowing through the LED, μLED, and / or μLED array pixel, or a transition to that state. In some embodiments, a μLED array may include thousands or millions of light-emitting LEDs positioned together on a substrate of centimeter-scale or smaller area. Each pixel may include a μLED as described herein. μLED arrays can support high-density pixels with a lateral dimension of less than approximately 100 μm by 100 μm. As used herein, LED refers to an independently controllable LED. Alternatively or additionally, μLED refers to an LED having a lateral dimension of approximately 1 μm to approximately 100 μm. For example, a μLED array may have a lateral dimension of approximately 50 μm in diameter or width.

[0033] The following detailed description presents various descriptions of certain specific embodiments. However, it should be understood that other embodiments may be utilized, and structural or logical changes may be made without departing from the scope of this disclosure. In general, the innovations described herein may be embodied in a variety of different ways, for example, as defined and covered by the claims and / or selected examples, and the following detailed description should not be construed as limiting.

[0034] Figure 1An example lighting system 100 according to some embodiments of the present disclosure is illustrated. For example, in some embodiments, the lighting system 100 may include a system used in the lighting and / or display industries. The lighting system 100 may be implemented as part of a larger system, wherein the lighting system 100 may provide illumination and / or display for the larger system. In some embodiments, the lighting system 100 may be implemented as part of a television, automotive headlights, or mobile phone.

[0035] The lighting system 100 may include a μLED array 102. The μLED array 102 may include a plurality of pixels, wherein, as illustrated, in some embodiments, the plurality of pixels may be arranged in a matrix. In some embodiments, the plurality of pixels may be arranged in one or more rows and one or more columns to form a rectangle. In other embodiments, the plurality of pixels may be arranged to form other shapes. The μLED array 102 may include thousands or millions of pixels. For example, the μLED array 102 may include approximately 20,000 pixels or more—such as millions of pixels—within 5,000 pixels. Each pixel may include a μLED as described herein. The μLED array 102 may support high-density pixels with a lateral dimension of less than 150 μm by 150 μm. In some embodiments, the μLED array 102 may have a size of approximately 50 μm in diameter or width.

[0036] Each of the plurality of pixels may include a pixel unit. For simplicity, a single pixel unit 104 is illustrated and described. It should be understood that each of the plurality of pixels may include a pixel unit, wherein the pixel unit may include features of pixel unit 104. Pixel unit 104 may include a light-emitting diode (LED) 106, a PWM switch 108, and a current source 110. LED 106 may have a size in the micrometer range (i.e., between 1 micrometer (μm) and 100 μm). For example, in some embodiments, the pixel size of LED 106 may have an approximate (within 10 μm by 10 μm) 40 μm by 40 μm dimension. In some embodiments, the pixel size may have a lateral dimension of less than 100 μm.

[0037] LED 106 may include μLEDs. When current is applied through LED 106, LED 106 can emit light. The intensity of the light emitted by LED 106 can depend on the amount of current applied through LED 106. For example, the smaller the current applied through LED 106, the smaller the intensity of the light emitted by LED 106. Conversely, the larger the current applied through LED 106, the greater the intensity of the light emitted by LED 106.

[0038] PWM switch 108 and current source 110 can control the amount of current applied through LED 106. PWM switch 108 and current source 110 can operate in combination with power supply 112 coupled to μLED array 102 to control the amount of current applied through LED 106. Power supply 112, current source 110, and PWM switch 108 can be coupled in series with LED 106 and can provide current through LED 106. Specifically, power supply 112 can apply a voltage Vin to μLED array 102. Current source 110 can be coupled to power supply 112 and can control the amount of current flowing supplied by power supply 112. In some embodiments, current source 110 may include a transistor, wherein the transistor can control the amount of current based on the state of the transistor. PWM switch 108 can control whether current is allowed to flow through LED 106. Specifically, when the PWM switch 108 is open, the circuit (including the power supply 112, current source 110, PWM switch 108, and LED 106) can be disconnected, thereby preventing current from flowing through LED 106. When the PWM switch 108 is closed, the circuit can be complete, thereby allowing current to flow through LED 106.

[0039] The lighting system 100 may further include a control 114 coupled to the μLED array 102. The control 114 may include circuitry performing the processes described herein. The control 114 may control the operation of the μLED array 102. For example, the control 114 may control the state of a PWM switch (such as PWM switch 108) of a pixel unit (such as pixel unit 104). For example, the control 114 may cause the PWM switch 108 to open to prevent current from flowing through LED 106, and may cause the PWM switch 108 to close to allow current to flow through LED 106.

[0040] Control 114 may include image processor 116 and such as I 2 Digital interface 118 of C. Digital interface 118 can facilitate communication with control 114. For example, digital interface 118 can facilitate communication between control 114 and μLED array 102. Furthermore, digital interface 118 can facilitate communication with the rest of the lighting system 100. For example, digital interface 118 can facilitate receiving one or more queries, such as query 120, from a system in which the lighting system 100 is implemented by control 114. The query or its translation can be transmitted to the pixel matrix via digital interface 118. In response to the query, μLED array 102 can provide feedback, such as feedback 122, to control 114 via digital interface 118. Digital interface 118 can facilitate the transmission of feedback 122 or its translation to the system in which the lighting system 100 is implemented.

[0041] Image processor 116 can process data received by control 114. For example, control 114 can receive image data 124, wherein image data 124 indicates an image to be displayed by μLED array 102. The image indicated by image data 124 may indicate one or more illumination patterns to be displayed by μLED array 102, a user interface to be displayed by μLED array 102, the intensity of light to be displayed by μLED array 102, one or more directions of light to be displayed by μLED array 102, the color to be displayed by μLED array 102, a portion of μLED array 102 emitting light, or some combination thereof. Image processor 116 can process image data 124 and determine characteristics of each pixel within μLED array 102 such that the image is displayed. For example, characteristics may include PWM duty cycle (which may be referred to herein as "PWM duty cycle" or "duty cycle") and / or the amplitude of each pixel within μLED array 102 to produce the image indicated by image data 124. Image processor 116 may provide one or more indications, such as indication 126, to μLED array 102 of the PWM duty cycle and / or amplitude of pixels within μLED array 102. The indication may include one or more signals that may cause a pixel's PWM switch to turn on and off according to the pixel's PWM duty cycle, and / or cause a pixel's current source to generate current according to the pixel's amplitude.

[0042] In response to receiving an indication of the PWM duty cycle and / or amplitude, pixels within the μLED array 102 can operate according to the PWM duty cycle and / or amplitude. Specifically, a pixel's PWM switch (such as PWM switch 108) can be turned on and off according to the pixel's PWM duty cycle. Furthermore, a current source (such as current source 110) can generate a current corresponding to the pixel's amplitude. For example, pixel unit 104 can receive a signal that causes current source 110 to apply a current corresponding to the amplitude of pixel unit 104. Additionally, pixel unit 104 can receive a signal that causes PWM switch 108 to be turned on and off according to the PWM duty cycle. For example, the PWM duty cycle can include a percentage of the period during which PWM switch 108 will be on, wherein the signal causes PWM switch 108 to be on for that percentage of the PWM duty cycle and off for the remainder of the period. When PWM switch 108 is on, the current generated by the current source can cause current to flow through LED 106, thereby causing LED 106 to emit light. When the PWM switch 108 is turned off, it can prevent current from flowing through the LED 106.

[0043] In some embodiments, image processor 116 can perform image processing calculations by directly generating modulated images. Alternatively, standard image files can be processed or otherwise converted to provide modulation that matches the image. Image data comprising primarily PWM duty cycle values ​​can be processed in image processor 116 for all pixels within μLED array 102. In embodiments where the amplitude is a fixed value or a value that changes very little, amplitude-related commands can be given separately through a simpler digital interface. Control 114 can interpret digital data that can be used by a PWM generator to generate PWM signals for the pixels and can be used by a digital-to-analog converter (DAC) to generate control signals for obtaining the desired current source amplitude.

[0044] Figure 2 An example table 200 is illustrated according to some embodiments of the present disclosure for indicating the duty cycle 202 of pixels within a μLED array. For example, table 200 may indicate a μLED array (such as μLED array 102). Figure 1 The duty cycle 202. The duty cycle 202 can be determined by the image processor (such as image processor 116). Figure 1 Based on image data (such as image data 124 ( Figure 1 To determine.

[0045] Table 200 may indicate the arrangement or representation of pixels within a μLED array. For example, Table 200 indicates that the μLED array in the illustrated embodiment may be arranged in five columns and five rows, or may be represented by five columns and five rows. In particular, in the illustrated embodiment, the μLED array may include 25 pixels, wherein the pixels may be arranged in five columns and five rows. While μLED arrays may include thousands or millions of pixels in most instances and may be arranged in different ways, in this embodiment, the 25 pixels are illustrated as rectangles to provide an understanding of the subject matter described herein.

[0046] Table 200 can indicate the duty cycle 202 of pixels based on their position within the μLED array. For example, a first duty cycle 202a of "10%" can indicate that pixels located in the first column and first row of the μLED array should have a 10% duty cycle. A second duty cycle 202b of "11%" can indicate that pixels located in the second column and first row of the μLED array should have an 11% duty cycle. A duty cycle can be provided for each pixel within the μLED array in Table 200.

[0047] Figure 3 An example pixel numbering method 300 according to some embodiments of the present disclosure is illustrated. Specifically, pixel numbering method 300 shows... Figure 2The pixel numbers of the pixels in the μLED array illustrated in Table 200. The pixel numbers in the pixel numbering method can be determined by an image processor (such as image processor 116). Figure 1 The image processor can assign pixel numbers to pixels based on pixel positions within the μLED array.

[0048] Pixel numbering method 300 provides an indication of column number 302 and row number 304 for each pixel. Pixel numbering method 300 further provides an indication of pixels 306 sorted based on the indications of column number 302 and row number 304, wherein in the illustrated embodiment, each pixel is indicated by a corresponding duty cycle. For example, corresponding to the indications of the first column and first row in pixel numbering method 300, pixels with a first duty cycle 202a having "10%" located in the first column and first row of table 200 are shown. Furthermore, corresponding to the indications of the second column and first row in pixel numbering method 300, pixels with a second duty cycle 202b having "11%" located in the second column and second row of table 200 are shown.

[0049] Pixel numbering method 300 further provides a pixel number 308 corresponding to the pixel. Pixel number 308 can be a pixel number sequentially from "1" to within the μLED array. For example, in the illustrated embodiment, pixel number 308 is from "1" to "25". In the illustrated embodiment, pixel number 308 is assigned in column-first order. Specifically, in the illustrated embodiment, pixel number "1" is assigned to pixels in the first column and first row, as illustrated in the illustrated pixel numbering method 300 by pixel number "1" located above the indication of column number "1" and row number "1". Pixel numbers can be assigned in column-first order, wherein the next pixel number of pixel number 308 is assigned to pixels in the next column and the same row until no pixels remain in the same row. When no pixels remain in the same row, the next pixel number of pixel number 308 can be assigned to the first column in the next row. For example, in the illustrated pixel numbering method 300, pixel number "2" is assigned to a pixel in the second column and the first row, as illustrated by the pixel number "2" located above the indication of column number "2" and row number "1". Numbering can continue for pixels in the first row until the pixel located at column number "5" and row number "1" is numbered with pixel number "5". Since there is no pixel number "1" remaining in the illustrated embodiment, the next pixel number "6" can be assigned to the pixel in the next row with column number "1", which in the illustrated embodiment has column number "2". Therefore, in the illustrated embodiment, the pixel with column number "1" and row number "2" can be assigned pixel number "6". Pixel numbering can proceed in column-first order until all pixels in the μLED array have been assigned pixel numbers.

[0050] Although the illustrated pixel numbering method 300 is shown in a list-first manner, it should be understood that in other embodiments, pixel numbering may be performed in a different order. For example, pixel numbering may be a row-first method or any other order conceivable in other embodiments. Furthermore, it should be understood that pixel numbering method 300 is shown to provide an understanding of the numbering of pixels within the μLED array, which can be used to determine the sequence number for turning on pixels within the μLED array, as further described throughout this disclosure. Additionally, although numbers are used to indicate pixels in the illustrated embodiment, it should be understood that in other embodiments, other indicators (such as alphanumeric characters) may be used to indicate pixels.

[0051] Figure 4 The illustration shows an example grouping 400 of pixels within a μLED array according to some embodiments of the present disclosure. The pixel grouping 400 can be performed by an image processor, such as image processor 116. Figure 1 The grouping 400 shown in the diagram can be derived from table 200 (). Figure 2 The illustration shows the grouping of pixels in the μLED array. Furthermore, grouping 400 employs pixel numbering method 300 (…). Figure 3 Pixel number 308 assigned to pixel in ) Figure 3 () is used to refer to the pixels of the μLED array.

[0052] Pixel grouping 400 can be performed based on the duty cycle of a pixel. For example, an image processor can group pixels based on their duty cycle to produce grouping 400. The image processor can produce multiple groups, each of which can correspond to a duty cycle range. Pixels can be assigned to groups based on a duty cycle range determined for a pixel. For example, a pixel with a specific duty cycle can be assigned to a group having a corresponding duty cycle range that includes that specific duty cycle.

[0053] The illustrated grouping 400 comprises five groups, as indicated by group number 402. As can be seen, in the illustrated embodiment, each group is labeled with a consecutive number; however, it should be understood that in other embodiments, each group may be labeled with other indicators. In some embodiments, the group number may be defined by the group's duty cycle range and / or the pixel's duty cycle. In other embodiments, multiple groups may be defined, and the duty cycle range may be defined based on the group number and / or the pixel's duty cycle. Furthermore, the group number may be predetermined, may be based on an indication from the system in which the μLED array is implemented, or may be determined by the image processor based on the duty cycle determined from image data received from the image processor. It should be understood that in the embodiments, two or more groups may be generated for grouping 400.

[0054] Group 400 includes a duty cycle range 404 for each group. The duty cycle range 404 can indicate which pixels, based on their pixel-level duty cycle, should be included in each group. Specifically, the duty cycle range 404 can indicate which pixels having a duty cycle within the range should be assigned to the corresponding group of the duty cycle range 404. For example, the first group 406 (indicated by group number "1") in the illustrated embodiment can have a corresponding first duty cycle range 408 from 10% to less than 20%. Based on the first duty cycle range 408, the first group 406 should include pixels having a duty cycle within the first duty cycle range 408 from 10% to less than 20%. Furthermore, the second group 410 (indicated by group number "2") in the illustrated embodiment can have a corresponding second duty cycle range 412 from 20% to less than 30%. Based on the second duty cycle range 412, the second group 410 should include pixels having a duty cycle within the second duty cycle range 412, ranging from 20% to less than 30%. The duty cycle ranges 404 can be separate, such that the duty cycle ranges 404 do not overlap, and pixels are not assigned to two groups.

[0055] It should be understood that the duty cycle range 404 shown in the illustration is for illustrative purposes only, and in other embodiments, the duty cycle range 404 may be different. In embodiments, the duty cycle range 404 may have the same size or different sizes. For example, each group in the illustrated embodiment has a size of 10%. Furthermore, in embodiments, the duty cycle range 404 may include all possible duty cycles or a subset of all possible duty cycles. For example, in the illustrated embodiment, the duty cycle range 404 includes duty cycles ranging from 10% to less than 60%, which is a subset of all possible duty cycles for a pixel. The size of the duty cycle range 404 and / or the duty cycles included in the duty cycle range 404 may be predetermined, may be based on instructions from the system in which the μLED array is implemented, may be determined by the image processor based on duty cycles determined from image data received from the image processor, or some combination thereof.

[0056] Grouping 400 further indicates the pixels included in each group. Specifically, grouping 400 indicates pixel number 414 of the pixels included in each group. Pixel number 414 may refer to pixel number 308 assigned to the pixel by pixel numbering method 300. Pixels may be assigned to groups based on a duty cycle range 404 corresponding to each group. For example, a first group 406 having a first duty cycle range 408 of 10% to less than 20% may include pixels that have been determined to have a duty cycle in the range of 10% to less than 20%. In the illustrated embodiment, the first group 406 may include pixels corresponding to pixel numbers “1”, “2”, “3”, “18”, and “19”, said pixels being based on pixels having a duty cycle in the range of 10% to less than 20%, as can be obtained from... Figure 3This can be seen in pixel numbering method 300. For example, it can be seen that the pixel with column number "1" and row number "1" has a first duty cycle of 10% 202a. Figure 2 ), and was assigned pixel number "1". Based on a first duty cycle of 10% 202a, in the range of 10% to less than 20%, the pixel assigned pixel number "1" can be assigned to the first group 406.

[0057] Image processors (such as Image Processor 116) Figure 1 The image processor can generate groups as shown by grouping 400, and can group pixels within a group. For example, the image processor can define groups and associate duty cycle ranges 404 with groups. The image processor can assign pixels to different groups based on the pixel's duty cycle and the duty cycle range 404 corresponding to each group. Furthermore, the image processor may have already determined the pixel's duty cycle based on image data processed by the image processor.

[0058] Figure 5 An example timing diagram 500 for pixel activation within a μLED array according to some embodiments of the present disclosure is illustrated. In particular, timing diagram 500 may illustrate table 200 according to some embodiments of the present disclosure. Figure 2 The timing diagram 500 indicates the turn-on time of the pixel. According to some embodiments of this disclosure, the example illustrated in timing diagram 500 may be an implementation of a PWM dimming method to provide current to pixels within a μLED array. The leading edge of a step in timing diagram 500 can indicate the turn-on time of the corresponding pixel. Pixels can remain on for a period of time indicated by the duty cycle corresponding to the pixel.

[0059] Timing diagram 500 can indicate cycle 502 of the PWM dimming method. In the illustrated embodiment, cycle 502 extends over a period from a first time 504 to a second time 506. According to the embodiments described herein, cycle 502 can be used to determine when each pixel of the μLED array is turned on to generate image data (such as image data 124 ( Figure 1 The image is indicated by the following parameters. For example, the duty cycle of a pixel can indicate the percentage of cycle 502 during which each pixel will be turned on. Furthermore, the turn-on delay that can be determined for each pixel can indicate the amount of time after the first time 504 of cycle 502 during which each pixel will be turned on.

[0060] Timing diagram 500 shows the sequence according to group 400 ( Figure 1The timing diagram 500 shows the on-time of pixels within five groups. Specifically, the timing diagram 500 shows five distinct rows, each corresponding to a specific group. The first group 508 is illustrated by the first row, the second group 510 by the second row, the third group 512 by the third row, the fourth group 514 by the fourth row, and the fifth group 516 by the fifth row. Each group corresponds to the group indicated by grouping 400. Specifically, the first group 508 corresponds to the first group 406 (… Figure 4 The second group 510 corresponds to the second group 410 ( Figure 4 (e.g., ...). It should be understood that, for clarity, different groups are shown in different rows, and the time axis of timing diagram 500 applies to each row. For example, first time 504 and second time 506 can be applied to the same position on the time axis, as indicated by the corresponding dashed lines in the timing diagram.

[0061] Each pixel within the μLED array can have an associated turn-on delay, which defines the amount of time after the start of a cycle in which the pixel will be turned on. For example, in the illustrated embodiment, the turn-on delay can define the amount of time after a first time 504 of cycle 502 in which the pixel will be turned on. The turn-on delay of each pixel within the μLED array can be determined based on the group to which the pixel is assigned, the number of pixels assigned to the group that includes the pixel, the sequence number of the pixels within the group that includes the pixel, the period of cycle 502, or some combination thereof. For example, the first group 508 can include five pixels as indicated by the first group 406 of group 400. In particular, the first group 508 can include a pixel labeled with pixel number "1", a pixel labeled with pixel number "2", a pixel labeled with pixel number "3", a pixel labeled with pixel number "18", and a pixel labeled with pixel number "19". As described throughout this disclosure, pixels can be included in a group based on their duty cycle. The period of loop 502 can be divided by the number of pixels in the group to determine the delay increment for that group, where the delay increment can be used to determine the turn-on delay for each pixel in the group. For example, the period of loop 502 can be divided by five to determine the delay increment for the first group 508. This process can be repeated for each group to determine the delay increment for each group. For example, the delay increment for each group can be determined by the equation td = Tpwm / Npxtot, where td is the delay increment for that group, Tpwm is the period of loop 502, and Npxtot is the number of pixels in that group.

[0062] The sequence number of pixels within a group can be determined based on the positions of pixels within the group and pixels within the μLED array. Specifically, the sequence number of pixels within a group can be determined based on the position of a pixel within the μLED array relative to the positions of other pixels within the group. Furthermore, the sequence number can be based on a pixel numbering method (such as pixel numbering method 300). Figure 3The pixel number assigned to a pixel in the pixel numbering method indicates the pixel's position within the μLED array. Determining the sequence number of pixels within a group can include sorting the pixels in ascending order according to their corresponding pixel numbers. For example, pixels in the first group of 406 can be sorted in ascending order to produce a pixel labeled "1", a pixel labeled "2", a pixel labeled "3", a pixel labeled "18", and a pixel labeled "19". For pixels sorted in ascending order, sequence numbers can be assigned to the pixels, starting with the sequence number "0" assigned to the first pixel in the ordered group and incrementing by the sequence number of the next pixel in the ordered group. For example, in the illustrated embodiment, for the first group 508, the pixel with pixel number "1" can be assigned sequence number "0", the pixel with pixel number "2" can be assigned sequence number "1", the pixel with pixel number "3" can be assigned sequence number "2", the pixel with pixel number "18" can be assigned sequence number "3", and the pixel with pixel number "19" can be assigned sequence number "4". This process can be repeated for each group to assign sequence numbers to the pixels in each group.

[0063] The turn-on delay of each pixel can be determined based on the delay increment of a group of pixels and the sequence number assigned to the pixel. Specifically, the turn-on delay of a pixel can be determined by multiplying the delay increment by the sequence number assigned to that pixel. For example, the turn-on delay of the pixel labeled "1" can be determined by multiplying the delay increment of the first group by 0, the turn-on delay of the pixel labeled "2" can be determined by multiplying the delay increment of the first group by 1, the turn-on delay of the pixel labeled "3" can be determined by multiplying the delay increment of the first group by 2, the turn-on delay of the pixel labeled "18" can be determined by multiplying the delay increment of the first group by 3, and the turn-on delay of the pixel labeled "19" can be determined by multiplying the delay increment of the first group by 4. For example, the turn-on delay of each pixel can be determined by the equation tod = td * (Npx - 1), where tod is the turn-on delay of the pixel, td is the delay increment of the group including the pixel, Npx is the position of the pixel in the ordered pixels of the group including the pixel, and (Npx - 1) is the sequence number. This process can be repeated for each pixel to determine the turn-on delay of each pixel.

[0064] According to some embodiments, timing diagram 500 illustrates pixel turn-on based on a determined pixel turn-on delay. Specifically, the leading edge of a step shown in the timing diagram illustrates the turn-on time of a pixel, and the number within the step indicates the pixel number of the pixel being turned on. For example, a first group 508 includes a first step 518 showing the turn-on time of a pixel with pixel number "1", a second step 520 showing the turn-on time of a pixel with pixel number "2", a third step 322 showing the turn-on time of a pixel with pixel number "3", a fourth step 324 showing the turn-on time of a pixel with pixel number "18", and a fifth step 326 showing the turn-on time of a pixel with pixel number "19". The position of the step can be determined based on the turn-on delay determined for the pixel. For example, a pixel with pixel number "1" can be determined to have zero turn-on delay and therefore can be turned on at a first time 504. The pixel with pixel number "2" can be determined to have a first turn-on delay of 528, and therefore can be turned on after the first turn-on delay of 528 following the first time of 504. Furthermore, the pixel with pixel number "3" can be determined to have a second turn-on delay of 530, and therefore can be turned on after the first time of 504 following the second turn-on delay of 530.

[0065] As can be seen from timing diagram 500, the turn-on time of pixels in different groups may differ due to different delay increments. Since different groups include different pixel numbers, the delay increments may also differ. For example, as illustrated in step 534, the turn-on time of the pixel with pixel number "20" can be defined by the turn-on delay 532, where the pixel with pixel number "20" is the second pixel to be turned on within the second group 510. The turn-on delay 532 of the pixel with pixel number "20" is longer than the first turn-on delay 528 of the pixel with pixel number "2", where the pixel with pixel number "2" is the second pixel to be turned on within the first group 508.

[0066] The on-time of pixels within a group can be uniformly distributed within cycle 50. Specifically, for all pixels within a group, the difference between the on-time of a pixel within the group and the subsequent on-time of the next pixel to be on within that group can be equal. For example, the difference 536 between the on-time of pixel "2" and pixel "3" can be equal to the difference 538 between the on-time of pixel "3" and pixel "18". The difference between on-times can be defined based on a delay increment.

[0067] Although timing diagram 500 illustrates the on-time of pixels, it should be understood that the duration for which pixels remain on is determined by… Figure 3The pixel duty cycle definition is shown in pixel numbering method 300. For example, a pixel with pixel number "1" can have a first duty cycle 202a of 10%. Figure 2 After being switched on as shown in step 518, the pixel with pixel number "1" can remain switched on for 10% of cycle 502. Once the pixel with pixel number "1" has been switched on for 10% of cycle 502, the pixel can be switched off and remain switched off until the next cycle.

[0068] The method including an on-time delay shown in timing diagram 500 allows pixels with similar duty cycles to have a delay between their on-time and off-time, wherein pixels with similar duty cycles can be defined as pixels included in the same group. The delay between the on-time and off-time may cause delays during operation due to power supplies (such as power supply 112). Figure 1 The difference in total current supplied to the μLED array is less than the difference in total current in conventional PWM dimming methods used to produce the same image. Compared to conventional PWM dimming methods, for the method shown in timing diagram 500, the reduced difference can result in lower RMS current, lower resistive losses, lower EMI, and / or lower harmonic noise levels. For example, uniformly distributing the on-time for each group of cycle 502 (as achieved by this method) can cause the additive harmonic currents to be canceled out, which can result in less peaking and more DC-like current supplied by the power supply compared to conventional PWM dimming methods.

[0069] Figure 6 An example current diagram 600 for power supply output current is illustrated according to some embodiments of the present disclosure. Specifically, current diagram 600 may be illustrated with respect to timing diagram 500 (…). Figure 5 In the case of the method described, the power supply (such as power supply 112) Figure 1 In PWM loops (such as loop 502) Figure 5 The current output from the )) is sent to the μLED array.

[0070] As can be seen from current diagram 600, the current supplied by the power source to the μLED array may vary during cycling. This variance may be due to the pixels being turned on and off during cycling due to differences in the pixel's on and off times. In the illustrated embodiment, the current can reach a maximum current of 100 mA, such as in the first position 602. Furthermore, the current can reach a minimum current of 60 mA, such as in the second position 604. When producing the same image as that produced by the μLED array in current diagram 600, the difference between the maximum and minimum currents in the illustrated embodiment can be smaller than the difference between the maximum and minimum currents that would be produced by conventional PWM dimming applied to the μLED array.

[0071] Figure 7 Another example timing diagram 700 for pixel turn-on in a μLED array according to some embodiments of the present disclosure is illustrated. In particular, timing diagram 700 may illustrate the pixel turn-on timing of another PWM dimming method disclosed in this application. Specifically, timing diagram 700 may illustrate Table 200 according to some embodiments of the present disclosure (…). Figure 2 The timing diagram 700 indicates the turn-on time of the pixel. According to some embodiments of this disclosure, the example illustrated in timing diagram 700 can be implemented by providing current to the pixels in the μLED array using a PWM dimming method. The leading edge of a step in timing diagram 700 can indicate the turn-on time of the corresponding pixel. Pixels can remain on for the time indicated by the duty cycle corresponding to the pixel.

[0072] Timing diagram 700 can indicate cycle 702 of the PWM dimming method. In the illustrated embodiment, cycle 702 extends over a period from a first time 704 to a second time 706. According to the embodiments described herein, cycle 702 can be used to determine when each pixel of the μLED array is turned on to generate image data (such as image data 124 ( Figure 1 The image is indicated by the following parameters. For example, the duty cycle of a pixel can indicate the percentage of cycle 702 during which each pixel will be turned on. Furthermore, the turn-on delay that can be determined for each pixel can indicate the amount of time after the first time 704 of cycle 702 during which each pixel will be turned on.

[0073] The method shown in timing diagram 700 may include the method in timing diagram 500 ( Figure 5 The same process described above generates pixel turn-on delays. The method shown in timing diagram 700 may further include applying a shift to pixels in some groups to shift the turn-on time of the pixels. In particular, the shift of each group may be added to the turn-on time determined as described with respect to timing diagram 500 to produce the turn-on time of the method that generates timing diagram 700.

[0074] The shift for each group can be determined based on the delay increments of each group. For example, in some embodiments, the shift can be determined based on the minimum delay increment of the group. In other embodiments, the shift can be determined based on the average delay increment, the maximum delay increment of the group, or, in other embodiments, based on another metric of delay. In some embodiments, the shift can be predetermined. In the illustrated embodiment, the shift can be determined based on the minimum delay increment of the group.

[0075] The minimum delay increment can be determined by comparing the delay increments of different groups. As can be seen from timing diagram 700, in the illustrated embodiment, the delay increment 708 of the fifth group 718 (which can be determined based on the difference between adjacent on-times of pixels within the group) is the minimum delay increment. Therefore, delay increment 708 can be used to determine the shift for each group.

[0076] Each group can have a unique shift. The shift of a group can be determined based on the delay increment 708 and the group number. For example, the first group 710 can have group number "1", the second group 712 can have group number "2", the third group 714 can have group number "3", the fourth group 716 can have group number "4", and the fifth group 718 can have group number "5". The shift of each group can be determined by multiplying the delay increment 708 by a factor one smaller than the group number. For example, the shift of the first group 710 can be determined by multiplying the delay increment 708 by 0, so that no shift is applied to the pixels in the first group. The shift of the second group 712 can be determined by multiplying the delay increment 708 by 1, and so on for the remaining groups. Therefore, the shift of a group can be defined by the equation s = td'*(Gx-1), where s is the shift of the group, td' is the delay increment used for the shift (i.e., the delay increment 708 in the illustrated embodiment), and Gx is the group number. This process can be repeated for each group to determine the shift of each group.

[0077] The update turn-on delay for each pixel can be determined by adding a shift to the turn-on delay as defined with respect to timing diagram 500. For the illustrated embodiment, since the shift of the first group 710 is 0, pixels within the first group 710 can have the same characteristics as the first group 508 (…). Figure 5 The pixels in the second group 712 have the same turn-on delay as the pixels in the second group 510. Pixels in the second group 712 can be added to the second group 510 by shifting the second group 712 by 720. Figure 5 The on-time delay of pixels in the third group 714 is adjusted to produce an updated on-time delay for pixels in the second group 712, where shift 720 equals delay increment 708. Pixels in the third group 714 can have their shift 722 added to the third group 512 ( Figure 5 The on-hook delay of the pixels within the third group 714 is used to generate the updated on-hook delay of the pixels within the third group 714, where the shift 722 is equal to twice the delay increment 708. The updated on-hook delay of the pixel can be determined by the equation tod' = tod + s, where tod' is the updated on-hook delay of the pixel, tod is the on-hook delay of the pixel as determined with respect to timing diagram 500, and s is the shift of the group including the pixel.

[0078] In instances where the turn-on delay of some pixels within a group exceeds the period of cycle 702 due to a corresponding shift, the turn-on time of the pixel may occur in subsequent adjacent cycles. For example, a pixel with pixel number "22" may have a turn-on delay defined by tod' = (td * 3) + s, based on the pixel with pixel number "22" being assigned sequence number "3", where tod' is the updated turn-on delay of the pixel, tod is the delay increment of the third group 714, and s is the shift of the third group 714. Based on the position of the pixels in the third group 714 within the μLED array, pixel number "22" may have already been assigned sequence number "3". For the pixel with pixel number "22", the turn-on delay defined by tod' may be greater than the period of cycle 702. Based on the turn-on delay greater than the period of the cycle, the turn-on time of the pixel with pixel number "22" may occur in subsequent adjacent cycles. For example, the turn-on time of the pixel with pixel number "22" may be represented by step 724. Furthermore, step 726, which shows the turn-on time of the pixel with pixel number "22", can come from the previous set of turn-on times of the third group 714.

[0079] Applying the shift according to the method can further induce a power source (such as power source 112). Figure 1 The difference in total current supplied to the μLED array during operation is reduced. Compared to conventional PWM dimming methods, the reduced difference can result in lower RMS current, lower resistive losses, lower EMI, and / or lower harmonic noise levels for the method shown in timing diagram 700. For example, this method can cause the additive harmonic currents to cancel each other out, which can result in less peaking and more DC-like current supplied by the power supply compared to conventional PWM dimming methods.

[0080] Figure 8 An example current diagram 800 for power supply output current is illustrated according to some embodiments of the present disclosure. Specifically, current diagram 800 may be illustrated with respect to timing diagram 700 (…). Figure 7 In the case of the method described, the power supply (such as power supply 112) Figure 1 In PWM loops (such as loop 702) Figure 7 The current output to the μLED array.

[0081] As can be seen from current diagram 600, the current supplied by the power source to the μLED array may vary during cycling. This variance may be due to the difference in pixel turn-on and turn-off times during cycling. In the illustrated embodiment, the current can reach a maximum current of 90 mA, such as at the first position 802. Furthermore, the current can reach a minimum current of 70 mA, such as at the second position 804. When generating the same image as that produced by the μLED array when generating current diagram 800, the difference between the maximum and minimum currents in the illustrated embodiment can be smaller than the difference between the maximum and minimum currents that would be generated by conventional PWM dimming applied to the μLED array. In particular, process 900 can be implemented with respect to timing diagram 500 ( Figure 5 ) or timing diagram 700 ( Figure 7 The method described is as follows. Process 900 can be controlled by controls (such as control 114). Figure 1 )) to perform on μLED arrays (such as μLED array 102 ( Figure 1 )) performs PWM dimming. For example, the control's image processor (such as image processor 116) Figure 1 The process 900 can be executed, and the digital interface of the control (such as digital interface 118) can be used. Figure 1 This can facilitate communication between the control and other components, such as μLED arrays.

[0082] In stage 902, the control can determine the duty cycle of the pixels within the μLED array. Specifically, the control can determine the pixel duty cycle based on an image to be generated by the μLED array, wherein the image can be based on image data received by the control (such as image data 124 (…)). Figure 1 To determine.

[0083] In stage 904, controls can assign pixel numbers to pixels. For example, controls can assign pixel numbers according to pixel numbering method 300 ( Figure 3 Each pixel is assigned a pixel number.

[0084] In stage 906, the control can generate groups for pixels. Specifically, the control can generate two or more groups and determine the duty cycle range for each group. The control can assign pixels to groups based on the pixel's duty cycle and the corresponding duty cycle range for each group. For example, the control can assign pixels to groups based on group 400 (…). Figure 4 The group is generated by describing the group.

[0085] In stage 908, the control can determine the delay increment for each group. Specifically, the control can determine the period of the loop used for PWM dimming. Furthermore, the control can determine the number of pixels in each group. The control can divide the loop period by the number of pixels in each group. For example, as with timing diagram 500 ( Figure 5 The control can generate a delay increment for a group, as described by the delay increment.

[0086] In stage 910, the control can determine the turn-on delay for each pixel. Specifically, the control can determine the turn-on delay for each pixel based on the delay increment of the pixel's group and sequence number. The control can multiply the delay increment by the pixel's sequence number to determine the turn-on delay for each pixel. For example, as with timing diagram 500 ( Figure 5 The control can determine the turn-on delay for each pixel, as described by the turn-on delay description.

[0087] In stage 912, the control can apply a shift to the turn-on delay to produce an updated turn-on delay. Specifically, the control can determine the shift for each group of pixels. In some embodiments, the shift can be determined based on the delay increment of the group. The control can add the shift of each group to the turn-on delay to produce an updated turn-on delay for the pixel. For example, the control can adjust the shift based on timing diagram 700 (…). Figure 7 The shift application described in the diagram is used to apply the shift. In some embodiments, such as in an embodiment implementing a method without shifting, stage 912 may be omitted.

[0088] In stage 914, the control can turn on the pixel according to the turn-on delay determined in stage 910 or stage 912. Specifically, the control can provide the μLED array with one or more indications of the PWM duty cycle and / or amplitude (such as indication 126). Figure 1 This instruction can enable the PWM switch corresponding to each pixel (such as PWM switch 108). Figure 1 The switch is turned on according to the turn-on delay determined in stage 910 or stage 912. This indication can further cause the PWM switch corresponding to each pixel to turn off according to the pixel's duty cycle.

[0089] Figure 10 An example pixel batching method 1000 according to some embodiments of the present disclosure is illustrated. For example, the pixel batching method 1000 may include batching pixels in a μLED array into multiple batches based on pixel positions within the μLED array. The batches generated by the pixel batching method 1000 can be processed in process 900 (…). Figure 9 In this context, pixels are used instead of individual pixels to determine the turn-on time of a batch. Specifically, batches can be grouped based on their duty cycle, and batches can be turned on based on a turn-on delay determined for each batch, wherein each pixel within a batch is turned on and off according to the batch's turn-on delay and duty cycle.

[0090] Table 1002 may indicate a μLED array (such as μLED array 102 ( Figure 1 The duty cycle is 1004. A duty cycle of 1004 can be achieved by an image processor (such as image processor 116). Figure 1 Based on image data (such as image data 124 ( Figure 1 The arrangement of pixels within the μLED array is determined by the table. Table 1002 may indicate or represent the arrangement of pixels within the μLED array. For example, Table 1002 indicates that the μLED array of the illustrated embodiment may be arranged in six columns and eight rows, or may be represented by six columns and eight rows. In particular, in the illustrated embodiment, the μLED array may include 48 pixels, wherein the pixels may be arranged in six columns and eight rows. While μLED arrays may include thousands or millions of pixels in most instances and may be arranged in different ways, 48 ​​pixels are illustrated in the illustrated embodiment to provide an understanding of the subject matter described herein.

[0091] Table 1002 can indicate the duty cycle 1004 of pixels based on their position within the μLED array. For example, a first duty cycle 1004a of "10%" could indicate that pixels located in the first column and first row of the μLED array should have a 10% duty cycle. A second duty cycle 1004b of "12%" could indicate that pixels located in the second column and first row of the μLED array should have a 12% duty cycle. A duty cycle can be provided for each pixel within the μLED array in Table 200.

[0092] The pixels indicated by Table 1002 can be batched based on pixel positions within the μLED array. For example, the pixels indicated by Table 1002 can be batched into multiple batches based on pixel positions, with each batch comprising multiple pixels. In some embodiments, pixels to be included in a batch can be defined by multiple columns and multiple rows to be included in that batch. For example, in the illustrated embodiment, a batch can be defined to include two columns and two rows, with pixels within the defined area being included in the batch. In the illustrated embodiment, the first batch 1006 can be defined to include pixels within the defined areas of the first two columns and the first two rows. Therefore, the first batch 1006 (indicated by the dashed box) can include pixels corresponding to a first duty cycle 1004a, pixels corresponding to a second duty cycle 1004b, pixels corresponding to a third duty cycle 1004c (located in the first column and second row of Table 1002), and pixels corresponding to a fourth duty cycle 1004d (located in the second column and second row of Table 1002). In the illustrated embodiment, the second batch 1008 can be defined to include pixels within the defined areas of the second two columns and the first two rows. Therefore, the second batch 1008 (indicated by the dashed box) may include pixels corresponding to the fifth duty cycle 1004e (located in the third column and first row of Table 1002), pixels corresponding to the sixth duty cycle 1004f (located in the fourth column and first row of Table 1002), pixels corresponding to the seventh duty cycle 1004g (located in the third column and second row of Table 1002), and pixels corresponding to the eighth duty cycle 1004h (located in the fourth column and second row of Table 1002). The remaining pixels within the μLED array as indicated in Table 1002 may be batched accordingly in the illustrated embodiment, such that each batch may include an area defined by two corresponding columns and two corresponding rows. Although the batch in the illustrated embodiment is shown as including pixels within an area defined by two columns and two rows, it should be understood that in other embodiments, the defined area of ​​a batch may be defined by different column and / or row numbers, or in other embodiments it may be defined by other arrangement relationships. Furthermore, the device performing the process 900 (such as image processor 116) may be used as a basis for further processing. Figure 1 The computational power and / or pixel number within the μLED array are used to determine the region defined for each batch.

[0093] Table 1010 may show the duty cycle corresponding to each batch generated by the pixel batching method 1000. Each batch may have a duty cycle based on the duty cycles of the pixels included in that batch. The duty cycle of a batch can be determined by averaging the duty cycles of the pixels included in that batch. For example, the first batch duty cycle 1012 of the first batch 1006 can be generated by determining the average of the first duty cycle 1004a, the second duty cycle 1004b, the third duty cycle 1004c, and the fourth duty cycle 1004d corresponding to the pixels in the first batch 1006. In particular, the average of the first duty cycle 1004a of "10%", the second duty cycle 1004b of "12%", the third duty cycle 1004c of "11%", and the fourth duty cycle 1004d of "11%" can constitute the first batch duty cycle 1012 of the first batch 1006 of "11%". Furthermore, the second batch duty cycle 1014 of the second batch 1008 can be generated by determining the average of the fifth duty cycle 1004e, the sixth duty cycle 1004f, the seventh duty cycle 1004g, and the eighth duty cycle 1004h. Specifically, the average of the fifth duty cycle 1004e ("22%), the sixth duty cycle 1004f ("24%), the seventh duty cycle 1004g ("21%), and the eighth duty cycle 1004h ("23%) can constitute the second batch duty cycle 1014 of "22.5%". Therefore, the batch duty cycle determination can be performed on the remaining batches generated by the pixel batching method 1000. Although the batch duty cycle is shown in the illustrated embodiment as including a decimal point, it should be understood that in other embodiments, the batch duty cycle may be rounded to an integer.

[0094] Process 900 can be used to determine the on-time of each batch, where the batch can replace pixels in process 900. For example, multiple batches can be grouped together based on the batch's duty cycle. Batches within each group can receive an order number indicating the order of the batches within that group. Furthermore, the delay increment for each group can be determined based on the number of batches within that group. The on-time of each batch can be determined based on the delay increment of the corresponding order number of that batch. In some embodiments, a shift can be applied to the on-time based on the batch number to produce updated on-time and on-delay.

[0095] Each pixel can be turned on based on the turn-on delay of the corresponding batch to which it belongs. For example, pixels in the first batch 1006 corresponding to the first duty cycle 1004a, the second duty cycle 1004b, the third duty cycle 1004c, and the fourth duty cycle 1004d can be turned on based on the turn-on delay determined for the first batch 1006 based on process 900. Each pixel can remain on within the corresponding batch duty cycle or the corresponding duty cycle of the pixel.

[0096] Figure 11An example system 1100 according to some embodiments of the present disclosure is illustrated. In some embodiments, system 1100 may include a portion of a vehicle headlight system. For example, in some embodiments, system 1100 may include an active headlight system in which the intensity and / or image of the light output by system 1100 can be varied. System 1100 or a portion thereof may reside in a vehicle, in a vehicle's headlights, or some combination thereof. System 1100 may implement pixelated configurations that may be made by the LED array.

[0097] System 1100 may be coupled to vehicle bus 1102 and power supply 1104. Power supply 1104 may provide power to system 1100. Bus 1102 may be coupled to one or more components that can provide data and / or utilize data provided to system 1100. The data provided on bus 1102 may relate to environmental conditions around the vehicle (such as time of day, whether it is raining, whether there is fog, ambient light level, and other environmental data), vehicle conditions (such as whether the vehicle is parked, whether the vehicle is moving, the vehicle's current speed, and the vehicle's current direction of travel), and / or the presence / location of other vehicles or pedestrians around the vehicle. System 1100 may provide feedback (such as information about system operation) to components.

[0098] System 1100 may further include sensor module 1106. In some embodiments, sensor module 1106 may include one or more sensors capable of sensing the environment surrounding the vehicle. For example, one or more sensors may sense the surrounding environment that can affect the image generated by light emitted by system 1100. In some embodiments, the sensors may sense environmental conditions around the vehicle, and / or the presence / location of other vehicles or pedestrians around the vehicle. Sensor module 1106 may operate in combination with data provided on bus 1102, or may operate in lieu of a portion of the data provided on bus 1102 (such as environmental conditions and / or the presence / location of other vehicles or pedestrians). Sensor module 1106 may output data indicating what the sensors have sensed.

[0099] System 1100 may further include transceiver 1108. In some embodiments, transceiver 1108 may have a Universal Asynchronous Receiver-Transmitter (UART) interface or a Serial Peripheral Interface (SPI). Transceiver 1108 may be coupled to bus 1102 and sensor module 1106, and may receive data from bus 1102 and sensor module 1106. In some embodiments, transceiver 1108 may multiplex data received from bus 1102 and sensor module 1106, and may direct feedback to bus 1102 or sensor module 1106.

[0100] System 1100 may further include processor 1110. Processor 1110 may be coupled to transceiver 1108 and exchange data with transceiver 1108. For example, processor 1110 may receive data from transceiver 1108 provided by bus 1102 and / or sensor module 1106. Processor 1110 may generate image data indicating an image to be produced by light emitted from system 1100. Image data may include image data 124 (…). Figure 1 One or more features of the system. The processor 1110 may further generate one or more queries that request information from one or more components of the system. The queries may include query 120 ( Figure 1 One or more features of the transceiver. The processor 1110 may further provide feedback to the transceiver 1108 to be directed to the bus 1102 or the sensor module 1106.

[0101] System 1100 may further include a headlight 1112 for the vehicle. In some embodiments, the headlight 1112 may include an active headlight, wherein the active headlight can produce multiple different light outputs. The headlight 1112 may include a lighting system 1114. The lighting system 1114 may include the lighting system 100 ( Figure 1 One or more features of the headlight 1112. The headlight 1112 may be coupled to the processor 1110 and may exchange data with the processor 1110. In particular, the lighting system 1114 may be coupled to the processor 1110 and may exchange data with the processor 1110. The lighting system 1114 may receive image data and queries from the processor 1110 and may provide feedback to the processor 1110.

[0102] System 1100 may further include power protection 1116. Power protection 1116 may be coupled to power supply 1104 and may receive power from power supply. Power protection 1116 may include one or more filters that may reduce conducted emissions and provide power immunity. In some embodiments, power protection 1116 may provide electrostatic discharge (ESD) protection, load dump protection, alternator field attenuation protection, reverse polarity protection, or some combination thereof.

[0103] System 1100 may further include a processor power supply 1118. The processor power supply 1118 may be coupled to power protection 1116 and may receive power from power supply 1104. The processor power supply 1118 may include a low-dropout (LDO) regulator that can generate power from the power supplied by power supply 1116 to power processor 1110. The processor power supply 1118 may be further coupled to processor 1110 and may supply power to processor 1110.

[0104] System 1100 may further include a power supply 1120. Power supply 1120 may be coupled to power protection 1116 and may receive power from power supply 1104. In some embodiments, power supply 1120 may include a converter that converts power from power supply 1104 into power for headlight 1112. For example, power supply 1120 may include a DC-DC converter that converts power from power supply 1120 from a first voltage to a second voltage for lighting system 1114 of headlight 1112.

[0105] Figure 12 An example lighting system 1200 according to some embodiments of the present disclosure is illustrated. For example, lighting system 1100 ( Figure 11 The lighting system 1200 may include one or more features of the lighting system 1200. The lighting system 1200 may include features such as headlight 1112 (…). Figure 11 This is achieved in the headlights.

[0106] The lighting system 1200 may include a control module 1202. The control module 1202 may include controls 114. Figure 1 One or more features of ). The control module 1202 may be coupled to the system's processor (such as processor 1110 ( Figure 11 The control module 1202 can receive image data and queries from the processor. The control module 1202 can further provide feedback to the processor.

[0107] The control module 1202 may include a digital interface 1204. The digital interface 1204 facilitates communication with a processor and other components within the lighting system 1200. For example, in some embodiments, the digital interface 1204 may include an SPI interface, which facilitates communication.

[0108] Control module 1202 may further include image processor 1206. Image processor 1206 may include image processor 116 ( Figure 1 One or more features of the image processor 1206. The image processor 1206 can receive image data via digital interface 1204 and can process the image data to generate an indication of PWM duty cycle and / or light intensity, for causing the light system 1200 to generate an image indicated by the image data. The image processor 1206 can further determine the on-time according to the method described herein and provide an indication of the on-time. For example, the image processor 1206 can perform a process 900 for determining the on-time ( Figure 9 ), and accordingly generate an indication of the connection time.

[0109] The control module 1202 may further include a frame buffer 1208 and a backup image storage device 1210. The frame buffer 1208 may receive instructions generated by the image processor 1206 and store instructions for implementation. The backup image storage device 1210 may further store instructions for PWM duty cycle, light intensity, and / or on-time. Instructions stored in the backup image storage device 1210 can be implemented without instructions stored in the frame buffer 1208. For example, when the frame buffer 1208 is empty, the frame buffer 1208 can retrieve instructions from the backup image storage device 1210.

[0110] The control module 1202 may further include a PWM generator 1212. The PWM generator 1212 may receive an instruction from the frame buffer 1208 and generate a PWM signal according to the instruction. The PWM generator 1212 may further determine the intensity of the light based on the instruction and generate a signal to induce the intensity of the light to be generated.

[0111] The lighting system 1200 may include a μLED array 1214. The μLED array 1214 may include a plurality of pixels, wherein each pixel includes a pixel unit 1216. The μLED array 1214 may include a μLED array 102 (… Figure 1 ) one or more features. Furthermore, pixel unit 1216 may include pixel unit 104 ( Figure 1 One or more features of ). In particular, pixel unit 1216 may include LED 1218, PWM switch 1220, and current source 1222. LED 1218, PWM switch 1220, and current source 1222 may each include LED 106 ( Figure 1 ), PWM switch 108 ( Figure 1 ) and current source 110 ( Figure 1 One or more features of the LED 1218. Pixel unit 1216 can receive signals from PWM generator 1212. The PWM signal from PWM generator 1212 can cause PWM switch 1220 to open and close according to the value of the PWM signal. The signal corresponding to the light intensity can cause current source 1222 to generate current, thereby causing LED 1218 to generate the corresponding light intensity.

[0112] The lighting system 1200 may further include an LED power supply 1224. The LED power supply 1224 may be coupled to the power supply 1120. Figure 11 It can receive power from power supply 1120. LED power supply 1224 can generate power for the LEDs of μLED array 1214. LED power supply 1224 can be coupled to μLED array 1214 and can provide power to μLED array 1214 for the LEDs.

[0113] Figure 13 The illustrations depict some embodiments of the present disclosure for implementation Figure 11 The system 1100 is illustrated in the example hardware layout 1300. In particular, the hardware layout 1300 may illustrate the hardware components that can implement the system 1100.

[0114] Hardware arrangement 1300 may include an integrated LED 1308. The integrated LED 1308 may include an LED die 1302 and a complementary metal-oxide-semiconductor (CMOS) backplane 1304. The LED die 1302 may be coupled to the CMOS backplane 1304 via one or more interconnects 1310, wherein the interconnects 1310 provide signal transmission between the LED die 1302 and the CMOS backplane 1304. The interconnects 1310 may include one or more solder bump connectors, one or more copper pillar bump connectors, or some combination thereof.

[0115] LED chip 1302 may include a μLED array 1214 ( Figure 12 The LED die 1302 may include multiple pixels of the μLED array 1214. The LED die 1302 may include a shared active layer and a shared substrate for the μLED array 1214, thereby making the μLED array 1214 a monolithic μLED array. Each pixel of the μLED array 1214 may include an individual segmented active layer and / or substrate. Therefore, the LED die 1302 may be a monolithic die with a segmented surface, wherein a corresponding pixel of the μLED array 1214 occupies each segment of that surface. In some embodiments, the LED die 1302 may further include a PWM switch and a current source for the μLED array 1214. In other embodiments, the PWM switch and current source may be included in the CMOS backplane 1304.

[0116] CMOS backplane 1304 may include a local control module 1202 ( Figure 12 ) and LED power supply 1224 ( Figure 12 The CMOS backplane 1304 can provide PWM and intensity signals to the μLED array 1214 via interconnects 1310, causing the μLED array 1214 to generate light according to the PWM signals and intensities. Because of the relatively large number and density of connections driving the μLED array compared to a standard μLED array, different embodiments can be used to electrically connect the CMOS backplane 1304 and the LED die 1302. The bonding pad pitch of the CMOS backplane 1304 can be the same as the bonding pad pitch in the μLED array, or the bonding pad pitch of the CMOS backplane 1304 can be larger than the bonding pad pitch in the μLED array 1214.

[0117] The hardware layout 1300 may further include a board 1306. Board 1306 may include a power protection 1116 (…). Figure 11 ), power supply 1120 ( Figure 11 ), processor power supply 1118 ( Figure 11 ), Sensor module 1106 ( Figure 11 ), transceiver 1108 ( Figure 11 ), processor 1110 ( Figure 11 ( ), or a portion thereof, of the circuitry. Board 1306 may be coupled to CMOS backplane 1304. For example, in the illustrated embodiment, board 1306 may be coupled to CMOS backplane 1304 via one or more lead connections 1312. Board 1306 and CMOS backplane 1304 may exchange—among other things—image data, power, and / or feedback via coupling.

[0118] Figure 14 The illustration shows an example hardware arrangement for implementing the system according to some embodiments of the present disclosure. Figure 14 As shown in the example about Figure 1 and Figure 12 The example layout is described. Specifically, Figure 14 Further details of the control 1410 and pixel matrix 1420 of system 1400, as described in more detail above, are shown. Note that not all components, such as those used to provide... Figure 14 The various modules shown illustrate the functionality of the processor and memory. In some embodiments, Figure 14 The circuit shown can be mounted on a CMOS backplane.

[0119] Data can be supplied to control 1410 to control LED 1442. Specifically, control 1410 includes an input frame buffer 1412 with inputs to which serial image data to be provided for display can be received via a digital interface. The serial image data may include instructions generated by an image processor (not shown). As described above, when input frame buffer 1412 is empty, it can be accessed from a backup image storage device (…). Figure 12 The input frame buffer 1412 can provide serial image data to the processor's Cyclic Redundancy Check (CRC) image analysis module 1414, which can determine whether the buffered serial image data is valid. If so, valid data can be supplied to the display frame buffer 1416.

[0120] Data from the CRC image analysis module 1414 and the display frame buffer 1416 can be supplied to the pixel driver 1420 to drive the LED 1442. Specifically, data from the CRC image analysis module 1414 can be supplied to the rising edge phase shift module 1424 of the pixel driver 1420, while data from the display frame buffer 1416 can be supplied to the pulse duration module 1422 of the pixel driver 1420. The rising edge phase shift module 1424 can also receive a PWM signal of a predetermined frequency from the PWM generator 1418. Therefore, the rising edge phase shift module 1424 can use the data from the CRC image analysis module 1414 to determine how much to shift the rising edge of the PWM signal, while the data from the display frame buffer 1416 can be used to adjust the duration of the resulting PWM signal.

[0121] The resulting PWM signal, with adjusted phase shift and duration, can be supplied to the control terminal of the input transconductance device 1432. As shown, the input transconductance device 1432 can be a p-channel enhancement-mode MOSFET, although other types of FETs can also be used. Therefore, the modified PWM signal can be supplied to the gate of MOSFET 1432. The source of MOSFET 1432 can be connected to the power supply Vcc. The drain of MOSFET 1432 can be connected to the output of comparator 1438 and to the control terminal of another MOSFET 1436. The input of comparator 1438 can be a predetermined bias voltage and a voltage dependent on the modified PWM signal. The source of MOSFET 1432 (and therefore the PWM signal) is coupled to one end of resistor 1434, and the other end of resistor 1434 can be coupled to another input of comparator 1438 and the source of another MOSFET 1436. The drain of the other MOSFET 1436 can be coupled to amplifier 1440 before being supplied to LED 1442. The drain of another MOSFET 1436 can also be coupled to switch 1444 to provide a feedback voltage to control 1410, as well as... Figure 1 As indicated in the document.

[0122] Applications supported by μLED arrays include augmented reality (AR) and virtual reality (VR). Various types of devices can be used to deliver AR / VR to users, including headsets, glasses, and projectors. Figure 15 Example systems according to some embodiments of the present disclosure are illustrated. In particular, Figure 15An AR / VR system 1500 with components similar to those described above is illustrated. The AR / VR system 1500 includes a μLED array 1510, an AR or VR display 1520, a μLED array controller 1530, a sensor 1540, and a system controller 1550. The components of the AR / VR system 1500 can be housed in a single structure, or one or more of the components shown can be mounted individually. For example, the first set of components, the μLED array 1510, the AR or VR display 1520, and the sensor 1540 can be mounted on a single device, such as those described above, while the second set of components, the μLED array controller 1530, and / or the system controller 1550 can be separately mounted from the first set of components and connected wirelessly. Although some components are shown, other components may exist for functionality but are not described for convenience. Similarly, Figure 15 One or more of the components shown can be combined or completely eliminated.

[0123] Power and user data are supplied to system controller 1550. User data input may include information provided by audio commands, haptic feedback, eye or pupil positioning, or a connected keyboard, mouse, or game controller. System controller 1550 controls μLED array controller 1530 based on signals from sensor 1540. Sensor 1540 may include a camera, depth sensor, audio sensor, accelerometer, two-axis or three-axis gyroscope, and other types of motion and / or environmental / wearer sensors. Sensor 1540 is configured to receive control input. Other sensors may include, but are not limited to, barometric pressure, stress, temperature, or any other suitable sensors required for local or remote environmental monitoring. In some embodiments, control input may include detected touch or tap, gesture input, or control based on the position of the headset or display. As another example, an estimated position of AR / VR system 1500 relative to an initial position can be determined based on one or more measurement signals from one or more gyroscopes or position sensors that measure translational or rotational movement.

[0124] As described above, the μLED array 1510 can support a micro-LED pixel array in which hundreds, thousands, or even millions of emitting LEDs are positioned together on a substrate with an area of ​​centimeters or smaller. The μLED array 1510 can be monochromatic, RGB, or other desired chromaticity. The pixels of the μLED array 1510 can be square, rectangular, hexagonal, or have curved edges. For example, pixels can have the same size, different sizes, or similar sizes and be grouped to present a larger effective pixel size, and controlled via a CMOS backplane. In some embodiments, separate μLED arrays can be used to provide a display image, wherein AR features are provided by different and separate μLED arrays.

[0125] In some embodiments, the μLED array controller 1530 may control one group of pixels for displaying content (AR / VR and / or non-AR / VR) to the user, while controlling another group of pixels as tracking pixels to provide tracking light used in eye tracking to adjust the content. The content display pixels are designed to emit light in the visible wavelength range (approximately 400 nm to 780 nm). The tracking pixels may be designed to emit light in the visible and / or IR wavelength range (approximately 780 nm to 2200 nm). In some embodiments, the tracking pixels and content pixels may be activated simultaneously. In some embodiments, the tracking pixels may be controlled to emit tracking light during periods when the content pixels are deactivated and therefore not displaying content to the user.

[0126] In some embodiments, the μLED pixels and the circuitry supporting the μLED array 1510 may be packaged and include a base or printed circuit board for powering and controlling the light generation of the μLEDs. The printed circuit board supporting the μLED array 1510 may include vias, heat sinks, ground planes, traces, and flip-chip or other mounting systems. The base or printed circuit board may be formed from any suitable material such as ceramic, silicon, aluminum, etc. If the base material is conductive, an insulating layer may be formed on the substrate material, and a pattern of metal electrodes may be formed on the insulating layer for contact with the μLED array 1510. The base may act as a mechanical support, provide an electrical interface between the electrodes and power supply on the μLED array 1510, and also provide heat sink functionality.

[0127] The AR / VR system 1500 may incorporate optics in the μLED array 1510 and / or the AR / VR display 1520, for example, coupling light emitted from the μLED array 1510 to the AR / VR display 1520. In some embodiments, the optical elements may be, for example, plano-concave lenses, convex lenses, Fresnel lenses, or any other suitable optical elements that affect the directionality of light from the μLED array 1510. Each optical element may have at least one coating, such as a UV-blocking or anti-reflective coating. In some embodiments, the optical elements may be designed to polarize the transmitted light. In addition to or instead of the lenses described above, optical elements in other embodiments include an aperture and / or a filter. The optical elements may be used to magnify and / or correct images, such as correcting or minimizing various two-dimensional or three-dimensional optical errors.

[0128] In one embodiment, the μLED array controller 1530 can provide power and real-time control to the light-emitting array 1510. For example, the μLED array controller 1530 can implement individual pixel-level or group pixel-level control of amplitude and duty cycle. The μLED array controller 1530 may include a frame buffer for storing images that can be supplied to the μLED array 1510 for generation or processing. The μLED array controller 1530 and / or system controller 1550 may include digital control interfaces such as an internal integrated circuit serial bus, a serial peripheral interface (SPI), USB-C, HDMI, a display port, or other suitable image or control modules configured to transmit image data, control data, or instructions.

[0129] In operation, pixels in an image can be used to define the response of the μLED array 1510, where the intensity and spatial modulation of the LED pixels are based on the image. To mitigate data rate issues, groups of pixels (e.g., square blocks of YxY pixels) can be controlled as individual blocks. In some embodiments, high-speed and high-data-rate operation is supported, where pixel values ​​from successive images can be loaded as consecutive frames in an image sequence at rates between 30 Hz and 100 Hz, with 60 Hz being typical, but 27 Hz being essentially the minimum. Pulse width modulation can be used to control each pixel to emit light at an intensity that depends at least in part on a pattern and intensity of the image.

[0130] In some embodiments, the system controller 1550 may use data from the sensor 1540 to integrate a measurement signal received from an accelerometer over time to estimate a velocity vector, and integrate the velocity vector over time to determine the estimated position of a reference point for the AR / VR system 1500. In other embodiments, the reference point used to describe the position of the AR / VR system 1500 may be based on a depth sensor, a camera positioning view, or a light field flow. Based on changes in the position, orientation, or movement of the AR / VR system 1500, the system controller 1550 may send images or commands to the luminescent array controller 1530. Changes or modifications to images or commands may also be made through user data input or automated data input.

[0131] Selected Example Example 1 is a complementary metal-oxide-semiconductor (CMOS) die for controlling pixels of a light-emitting diode (LED) array. The CMOS die includes: a digital interface providing control signals to the LED array; and logic coupled to the digital interface. The logic is configured to: determine the duty cycle of each pixel based on image data to use the pixels to display an image; divide the pixels into at least a first group of first pixels and a second group of second pixels based on the pixel duty cycles, the duty cycles of the first pixels being different from those of the second pixels; and determine a first on-delay of the first pixels based on a first number of first pixels, and a second on-delay of the second pixels based on a second number of second pixels, so as to activate the first and second pixels respectively according to the first and second on-delays to use the control signals to display the image.

[0132] In Example 2, the subject of Example 1 includes the following: the duty cycle of the first pixel is within a first duty cycle range, the duty cycle of the second pixel is within a second duty cycle range, and the first duty cycle range is separate from the second duty cycle range.

[0133] In Example 3, the subject matter of Examples 1-2 includes, wherein: each first pixel has a unique first sequence number, each second pixel has a unique second sequence number, and the logic is further configured to: divide the period of the loop by a first quantity to generate a first delay increment, and multiply the first delay increment by the unique first sequence number of each first pixel to generate a first turn-on delay for each first pixel; and divide the period of the loop by a second quantity to generate a second delay increment, and multiply the second delay increment by the unique second sequence number of each second pixel to generate at least a portion of a second turn-on delay.

[0134] In Example 4, the subject of Example 3 includes the logic being further configured to: determine each first sequence number based on the position of the associated first pixel within the LED array; and determine each second sequence number based on the position of the associated second pixel within the LED array.

[0135] In Example 5, the subject of Examples 3-4 includes the logic being further configured to: determine a shift of a second group, the shift of the second group being equal to the smaller of the first delay increment and the second delay increment; and add the shift to the turn-on delay generated by the multiplication to produce a second turn-on delay.

[0136] In Example 6, the subject matter of Examples 1-5 includes the LEDs of the LED array being independently controllable and having a lateral dimension of less than approximately 100 μm.

[0137] Example 7 is a light-emitting diode (LED) structure, including: a complementary metal-oxide-semiconductor (CMOS) die configured to provide control signals based on image data of an image; and an LED array including pixels, which are divided into at least a first group of first pixels and a second group of second pixels based on the duty cycle of the pixels, a first turn-on delay of the first pixels based on a first number of first pixels, a second turn-on delay of the second pixels based on a second number of second pixels, the first pixels and the second pixels being configured to be activated according to the first turn-on delay and the second turn-on delay, respectively, using control signals to display an image.

[0138] In Example 8, the subject of Example 7 includes the following: each pixel in the first group of pixels has a unique first sequence number, each pixel in the second group of pixels has a unique second sequence number, and the turn-on delay of the pixels in the first group of pixels is the period of the cycle divided by the pixel number in the first group of pixels to produce a first delay increment, and the first delay increment is multiplied by the unique first sequence number to produce a pixel turn-on delay, and the turn-on delay of the pixels in the second group of pixels is the period of the cycle divided by the number of pixels in the second group of pixels to produce a second delay increment, and the second delay increment is multiplied by the unique second sequence number to produce at least a portion of the pixel turn-on delay.

[0139] In Example 9, the subject of Example 8 includes the following: a unique first-order number for each pixel in the first group of pixels is determined based on the position of the pixel in the LED array relative to the other pixels in the first group of pixels; and a unique second-order number for each pixel in the second group of pixels is determined based on the position of the pixel in the LED array relative to the other pixels in the second group of pixels.

[0140] In Example 10, the subject of Examples 8-9 includes a first pixel within a first group of pixels and a first pixel within a second group of pixels configured to be active simultaneously.

[0141] In Example 11, the subject of Examples 8-10 includes: applying a shift to the turn-on delay of pixels within the second group of pixels to determine the turn-on delay of pixels within the second group of pixels, and the shift of the second group is equal to the smaller of the first delay increment and the second delay increment.

[0142] In Example 12, the subject of Examples 7-11 includes a pulse width modulation (PWM) generator for generating a PWM signal based on the determined turn-on delay and duty cycle of a plurality of pixels, which causes PWM switches corresponding to the plurality of pixels to be activated and deactivated.

[0143] In Example 13, the subject of Examples 7-12 includes LED dies containing an LED array.

[0144] In Example 14, the subject of Examples 7-13 includes the fact that each of the plurality of pixels has a lateral dimension of less than 100 μm.

[0145] In Example 15, the subject of Examples 7-14 includes an LED array where the LEDs are independently controllable.

[0146] Example 16 is a vehicle headlight system, comprising: a printed circuit board including micrologic configured to generate data for light to be produced by the vehicle headlight system; an LED die having an array of light-emitting diodes (LEDs) comprising a plurality of pixels; and a complementary metal-oxide-semiconductor (CMOS) backplane coupled to the printed circuit board and the LED die. The CMOS backplane is configured to: determine a duty cycle of the plurality of pixels based on the data; determine a pixel on-time of the plurality of pixels in a first group having a duty cycle within a first range, based on a first number of pixels in a first group; and determine a pixel on-time of a second group having a duty cycle within a second range, based on a second number of pixels in a second group.

[0147] In Example 17, the subject matter of Example 16 includes the following: each pixel in the first group has a unique first sequence number, each pixel in the second group has a unique second sequence number, and the CMOS backplane is further configured to: divide the cycle period by a first number to generate a first delay increment, and for each pixel in the first group, multiply the first delay increment by the unique first sequence number to generate the pixel's on-time; and divide by a second number of cycles to generate a second delay increment, and for each pixel in the second group, multiply the second delay increment by the unique second sequence number to at least partially generate the pixel's on-time.

[0148] In Example 18, the subject of Example 17 includes a CMOS backplane further configured to: determine each first sequence number based on the position of associated pixels within a first group; and determine each second sequence number based on the position of associated pixels within a second group.

[0149] In Example 19, the subject matter of Examples 17-18 includes, in order to determine the on-time of pixels in the second group, the CMOS backplane is further configured to: determine a shift of the second group, the shift of the second group being equal to the smaller of a first delay increment and a second delay increment; and add the shift to the on-time generated by multiplying the second delay increment by a unique second sequence number to produce a second on-time.

[0150] In Example 20, the subject matter of Examples 16-19 includes, wherein: a CMOS backplane includes: a PWM generator for generating pulse width modulation (PWM) signals; and a plurality of PWM switches corresponding to the plurality of pixels, the plurality of PWM switches being configured to control the current flowing through the plurality of pixels. The CMOS backplane is further configured to activate the plurality of pixels according to an on-time by generating a plurality of PWM signals by the PWM generator according to an on-time, and the plurality of PWM signals being configured to activate and deactivate the plurality of PWM switches according to the on-time.

[0151] Example 21 is at least one machine-readable medium comprising instructions that, when executed by processing circuitry, cause the processing circuitry to perform an operation to implement any one of Examples 1-20.

[0152] Example 22 is an apparatus that includes an apparatus that implements any one of Examples 1-20.

[0153] Example 23 is a system that implements any one of Examples 1-20.

[0154] Example 24 is a method to implement any one of Examples 1-20.

[0155] Other implementation notes, changes, and applications It should be understood that not all objectives or advantages may be achieved according to any particular embodiment described herein. Therefore, for example, those skilled in the art will recognize that certain embodiments may be configured to operate in a manner that achieves or optimizes one or more advantages as taught herein, without necessarily achieving other objectives or advantages as taught or suggested herein.

[0156] It should be understood that the circuits in the accompanying drawings and their teachings are easily scalable and can accommodate a large number of components, as well as more complex / precise arrangements and configurations. Therefore, the examples provided should not limit the scope or inhibit the extensive teachings, such as those potentially applicable to countless other architectures.

[0157] In some embodiments, any number of circuits in the figures can be implemented on a board of the associated electronic device. This board can be a general-purpose circuit board that can house various components of the internal electronic system of the electronic device and further provide connectors for other peripheral devices. More specifically, the board can provide electrical connections through which other components of the system can communicate electrically. Any suitable processor (including digital signal processors, microprocessors, supporting chipsets, etc.), computer-readable non-transitory memory elements, etc., can be appropriately coupled to the board based on specific configuration requirements, processing requirements, computer design, etc. Other components such as external storage devices, additional sensors, controllers for audio / video displays, and peripheral devices can be attached to the board via cables as insert cards or integrated into the board itself. In various embodiments, the functionality described herein can be implemented in emulation form as software or firmware running within one or more configurable (e.g., programmable) elements arranged in a structure supporting these functions. The emulated software or firmware can be provided on a non-transitory computer-readable storage medium including instructions that allow the processor to perform those functionalities.

[0158] In some embodiments, the circuitry of the figures may be implemented as a standalone module (e.g., a device with associated components and circuitry configured to perform a particular application or function) or as a plug-in module in the application-specific hardware of an electronic device. Note that some embodiments of this disclosure may be readily included, in whole or in part, in a system-on-a-chip (SOC) package. SOC stands for integrated circuit (IC) that integrates components of a computer or other electronic system onto a single chip. It may include digital, analog, mixed-signal, and generally radio frequency functions: all of which can be provided on a single chip substrate. Other embodiments may include a multi-chip module (MCM) in which multiple individual ICs reside within a single electronic package and are configured to interact closely with each other via the electronic package. In various other embodiments, the components and / or processes described herein (such as control 114 ( Figure 1 It can be implemented in one or more silicon cores of application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and other semiconductor chips.

[0159] It is also important to note the functions associated with the components and / or programs described herein (such as control 114). Figure 1 ) and / or program 900 ( Figure 9The diagram may illustrate some possible functions that can be performed by or within the system described herein. Where appropriate, some of these operations may be removed or deleted, or these operations may be significantly modified or altered without departing from the scope of this disclosure. Furthermore, the timing of these operations may vary considerably. The preceding operational flow has been provided for illustrative and discussion purposes. The embodiments described herein offer considerable flexibility, as any suitable arrangement, timing, configuration, and periodic mechanism can be provided without departing from the teachings of this disclosure.

[0160] Those skilled in the art will recognize a variety of other changes, substitutions, variations, alterations, and modifications, and this disclosure is intended to cover all such changes, substitutions, variations, alterations, and modifications as they fall within the scope of the appended claims. Note that all optional features of any device and system described herein may also be implemented relative to the methods or processes described herein, and details in the examples may be used anywhere in one or more embodiments.

Claims

1. A complementary metal-oxide-semiconductor die for controlling pixels in a light-emitting diode array, the complementary metal-oxide-semiconductor die comprising: A digital interface that provides control signals to the LED array; and The logic coupled to the digital interface is configured as follows: The duty cycle of each pixel is determined based on image data in order to use the pixels to display the image. The pixels are divided into at least a first group of first pixels and a second group of second pixels based on the pixel's duty cycle, wherein the duty cycle of the first pixel differs from that of the second pixel. A first turn-on delay of the first pixel is determined based on a first number of first pixels, and a second turn-on delay of the second pixel is determined based on a second number of second pixels, so that the first pixel and the second pixel are activated according to the first turn-on delay and the second turn-on delay respectively, so as to display an image using control signals; The light-emitting diodes in the aforementioned light-emitting diode array are independently controllable and have a lateral dimension of less than 100 μm.

2. The complementary metal-oxide-semiconductor die according to claim 1, wherein: The duty cycle of the first pixel is within the first duty cycle range. The duty cycle of the second pixel is within the second duty cycle range, and The first duty cycle range is separate from the second duty cycle range.

3. The complementary metal-oxide-semiconductor die according to claim 1, wherein: Each of the first pixels has a unique first sequence number. Each second pixel has a unique second sequence number, and The logic is further configured as follows: Divide the cycle period by a first quantity to generate a first delay increment, and multiply the first delay increment by the unique first sequence number of each first pixel to generate a first on delay for each first pixel. Divide the cycle period by a second quantity to generate a second delay increment, and multiply the second delay increment by a unique second sequence number of each second pixel to generate at least a portion of the second turn-on delay.

4. The complementary metal-oxide-semiconductor die of claim 3, wherein the logic is further configured as follows: Each first sequence number is determined based on the position of the associated first pixel within the LED array; and Each second sequence number is determined based on the position of the associated second pixel within the LED array.

5. The complementary metal-oxide-semiconductor die of claim 3, wherein the logic is further configured as follows: Determine the shift of the second group, whereby the shift of the second group is equal to the smaller of the first delay increment and the second delay increment; and The shift is added to the turn-on delay generated by the multiplication to produce a second turn-on delay.

6. A light-emitting diode structure, comprising: Complementary metal-oxide-semiconductor dies are configured to provide control signals based on image data. and The array of light-emitting diodes includes pixels, which are divided into at least a first group of first pixels and a second group of second pixels based on the pixel's duty cycle. A first turn-on delay of the first pixel is based on a first number of first pixels, and a second turn-on delay of the second pixel is based on a second number of second pixels. The first and second pixels are configured to be activated according to the first and second turn-on delays, respectively, and an image is displayed using a control signal. Each of the plurality of pixels has a lateral dimension of less than 100 μm.

7. The light-emitting diode structure according to claim 6, wherein: Each pixel within the first group has a unique first sequence number. Each pixel within the second group has a unique second sequence number, and The on-time delay of pixels within the first group is calculated by dividing the cycle period by the number of pixels in the first group to generate a first delay increment, and this first delay increment is multiplied by a unique first sequence number to generate the pixel's on-time delay. The turn-on delay of pixels within the second group is the cycle period divided by the number of pixels within the second group to produce a second delay increment, and the second delay increment is multiplied by a unique second sequence number to produce at least a portion of the pixel's turn-on delay.

8. The light-emitting diode structure according to claim 7, wherein: The unique first-order number of each pixel in the first group of pixels is determined based on the position of the pixel in the LED array relative to the other pixels in the first group of pixels; as well as The unique second sequence number of each pixel in the second group of pixels is determined based on the position of the pixels in the LED array relative to the other pixels in the second group of pixels.

9. The light-emitting diode structure according to claim 7, wherein, The first pixel in the first group of pixels and the first pixel in the second group of pixels are configured to be active simultaneously.

10. The light-emitting diode structure according to claim 7, wherein: A shift is applied to the turn-on delay of the pixels within the second group of pixels to determine the turn-on delay of the pixels within the second group of pixels, and The shift of the second group is equal to the smaller of the first delay increment and the second delay increment.

11. The light-emitting diode structure according to claim 6, further comprising a pulse width modulation generator for generating a pulse width modulation signal based on the determined turn-on delay and duty cycle of a plurality of pixels, the pulse width modulation signal causing pulse width modulation switches corresponding to the plurality of pixels to be activated and deactivated.

12. The light-emitting diode structure according to claim 6, further comprising a light-emitting diode die including a light-emitting diode array.

13. The light-emitting diode structure according to claim 6, wherein the light-emitting diodes of the light-emitting diode array are independently controllable.

14. A vehicle headlight system, comprising: A printed circuit board, the printed circuit board including micrologic configured to generate data for light to be produced by a vehicle headlight system; A light-emitting diode die having a light-emitting diode array, the light-emitting diode array comprising multiple pixels; and A complementary metal-oxide-semiconductor (CMOS) backplane coupled to a printed circuit board and a light-emitting diode (LED) die, wherein the CMOS backplane is configured as follows: The duty cycle of multiple pixels is determined based on the data. Based on a first number of pixels within a first group, the on-time of the pixels within the first group is determined, the first group having a duty cycle within a first range, and Based on a second number of pixels within the second group, the on-time of the pixels within the second group is determined, the second group including pixels with a duty cycle within a second range; Each of the plurality of pixels has a lateral dimension of less than 100 μm.

15. The vehicle headlight system according to claim 14, wherein: Each pixel in the first group has a unique first sequence number. Each pixel in the second group has a unique second sequence number, and The complementary metal-oxide-semiconductor backplane is further configured as follows: Divide the cycle period by a first quantity to generate a first delay increment, and for each pixel in the first group, multiply the first delay increment by a unique first sequence number to generate the pixel's on-time. Divide by a second number of periods to generate a second delay increment, and for each pixel in the second group, multiply the second delay increment by a unique second sequence number to generate at least partially the on-time of the pixel.

16. The vehicle headlight system of claim 15, wherein the complementary metal-oxide-semiconductor backplane is further configured as follows: Each first sequence number is determined based on the position of the associated pixels within the first group; and Each second sequence number is determined based on the position of the associated pixels within the second group.

17. The vehicle headlight system according to claim 15, wherein, To determine the on-time of the pixels in the second group, the complementary metal-oxide-semiconductor backplane is further configured as follows: Determine the shift of the second group, whereby the shift of the second group is equal to the smaller of the first delay increment and the second delay increment; and The shift is added to the turn-on time generated by multiplying the second delay increment by the unique second sequence number to produce the second turn-on time.

18. The vehicle headlight system according to claim 14, wherein: The complementary metal-oxide-semiconductor backplane includes: A pulse width modulation generator that generates pulse width modulation signals, and A plurality of pulse width modulation switches corresponding to the plurality of pixels, the plurality of pulse width modulation switches being configured to control the current flowing through the plurality of pixels; The complementary metal-oxide-semiconductor backplane is further configured to activate the plurality of pixels according to the on-time by generating a plurality of pulse width modulation signals by a pulse width modulation generator according to the on-time, and The plurality of pulse width modulation signals are configured to activate and deactivate the plurality of pulse width modulation switches according to the on-time.

Images