SoC array server automated testing method and SoC array server

Abstract

The embodiment of the present invention discloses an automated testing method for a SoC array server, which is applied to a BMC mainboard in the SoC array server. The SoC array server also includes a backplane, a blade board, and a switch board. The backplane includes a backplane controller and a fan controller, and the fan controller is connected to a plurality of fans; the blade board includes a blade board controller, a SoC board, and a serial port controller. The method specifically comprises: making the backplane controller, the fan, the blade board controller, the SoC board, the serial port controller, and the switch board work normally, and setting a preset duration and a preset range to verify them respectively, finally obtaining a verification result, and generating a corresponding test report. The present invention verifies each part of the automated testing system of the SoC array server using different verification methods, obtains accurate test results, generates a complete test report based on the test results, and realizes comprehensive, accurate, and efficient testing of the SoC array server.

Description

Technical Field

[0001] The present invention relates to the technical field of equipment testing, and in particular to an automated testing method for a SoC array server and the SoC array server. Background Art

[0002] With the continuous advancement of science and technology and the advent of the information age, the demand for data processing and computing continues to grow. As a high-performance server that integrates multiple functions such as processors, memory, and I / O interfaces, SoC (System on Chip) array servers can meet the growing demand for data processing with their high density and high computing power. They are of great significance to large-scale data centers, cloud computing, artificial intelligence, and other fields, and have been widely used in these fields. Furthermore, testing of SoC array servers has also begun to attract widespread attention. Due to the complexity and large scale of SoC array servers, traditional manual testing and detection methods face many challenges, including time-consuming and labor-intensive, prone to human errors, and increased system deployment and maintenance costs.

[0003] Therefore, there is an urgent need for a reliable and automated SoC array server testing solution that can perform comprehensive and efficient testing on various components inside the server. Summary of the invention

[0004] Based on this, it is necessary to propose an automated testing method for a SoC array server and a SoC array server to address the above problems, which can achieve comprehensive and efficient testing of various internal components of the SoC array server.

[0005] In a first aspect, the present invention provides an automated testing method for a SoC array server, the method being applied to a BMC mainboard of the SoC array server, the SoC array server further comprising a backplane, a blade board, and a switch board, the backplane comprising a backplane controller and a fan controller, the fan controller being connected to a plurality of fans; the blade board comprising a blade board controller, a SoC board, and a serial port controller; the method comprising:

[0006] Sending a first serial port command to the backplane controller, and generating a first test result according to whether a successful command returned by the backplane controller is received within a first preset time period;

[0007] adjusting the fan speed based on the fan controller within a first preset range, and generating a second test result according to whether the actual speed of the fan after adjustment meets the speed threshold;

[0008] Receiving the startup duration of the switch board, and generating a third test result according to whether the startup duration meets a preset duration range;

[0009] Sending a second serial port command to the blade board controller, and generating a fourth test result according to whether a successful command returned by the blade board controller is received within the first preset time period;

[0010] Monitoring the continuous output of serial port data of the serial port controller, and generating a fifth test result according to whether the serial port data output by the serial port controller is received within the first preset time period;

[0011] Obtain at least one of the startup time, network speed, USB test result, deep recovery mode test result, and serial port test result of the SoC array server, and generate a sixth test result according to whether the startup time, network speed, USB test result, deep recovery mode test result, and serial port test result all meet preset standards;

[0012] Performing an aging test of a preset aging time for each component of the SoC board, and generating a seventh test result according to the operation of the system during the aging test;

[0013] Restarting the system multiple times, obtaining the restart duration of the system each time, and generating an eighth test result according to the multiple restart durations;

[0014] A test report is generated and output based on the first test result, the second test result, the third test result, the fourth test result, the fifth test result, the sixth test result, the seventh test result, and the eighth test result.

[0015] Optionally, the sending of the first serial port command to the backplane controller and generating a first test result according to whether a successful command returned by the backplane controller is received within a first preset time period include:

[0016] Sending a serial port command to the backplane controller and waiting for a first preset time, if a success command sent back by the backplane controller is received within the first preset time, the first test result is normal;

[0017] If the success command is not received within the first preset time length, repeat the step of sending the serial port command to the backplane controller and the subsequent steps n times. If the success command is not received n times, the first test result is an error and the test is terminated.

[0018] Optionally, adjusting the fan speed based on the fan controller within the first preset range, and generating a second test result according to whether the actual speed of the fan after adjustment meets the speed threshold, includes:

[0019] The fan speed is adjusted based on the fan controller within a first preset range, each value within the first preset range corresponds to a speed threshold, and if a certain value is selected within the first preset range to adjust the fan speed, and the actual speed of the fan after adjustment meets the speed threshold, then the second test result is normal;

[0020] If the actual speed of the fan after adjustment does not meet the speed threshold, repeat the step of selecting a value within the first preset range to adjust the fan speed and the subsequent steps n times. If the actual fan speed obtained n times does not meet the speed threshold, the second test result is an error and the test is terminated.

[0021] Optionally, the receiving the startup duration of the switch board and generating a third test result according to whether the startup duration meets a preset duration range includes:

[0022] Restarting the switch board, receiving the startup duration of the switch board, and if the startup duration is within a preset duration range, the third test result is normal;

[0023] If the startup duration does not meet the preset duration range, repeat the step of restarting the switch board and the subsequent steps n times. If the startup durations obtained n times do not meet the preset duration range, the third test result is an error, and the test is terminated at this time.

[0024] Optionally, the sending of the second serial port command to the blade board controller and generating a fourth test result according to whether a success command returned by the blade board controller is received within the first preset time period include:

[0025] Sending a serial port command to the blade board controller and waiting for a first preset time, if a success command sent back by the blade board controller is received within the first preset time, the fourth test result is normal;

[0026] If the success instruction is not received within the first preset time length, repeat the step of sending the serial port instruction to the blade board controller and the subsequent steps n times. If the success instruction is not received n times, the fourth test result is an error and the test is terminated at this time.

[0027] Optionally, the monitoring of the continuous output of the serial port data of the serial port controller and generating a fifth test result according to whether the serial port data output by the serial port controller is received within the first preset time period include:

[0028] Monitor the continuous output of the serial port data of the serial port controller. If the serial port data output by the serial port controller is not received within the first preset time, wait for the second preset time. If the serial port data is not received within the second preset time, the fifth test result is an error, and the test is terminated at this time.

[0029] Optionally, obtaining at least one of the startup time, network speed, USB test result, deep recovery mode test result, and serial port test result of the SoC array server, and generating a sixth test result according to whether the startup time, network speed, USB test result, deep recovery mode test result, and serial port test result all meet preset standards, includes:

[0030] Restart the SoC array server to obtain the startup time; obtain at least one of the network speed, USB test result, deep recovery mode test result, and serial port test result. If the startup time, network speed, USB test result, deep recovery mode test result, and serial port test result all meet the preset standards, the sixth test result is normal;

[0031] If at least one of the startup duration, network speed, USB detection result, deep recovery mode detection result, and serial port detection result does not meet the preset standard, the step of restarting the SoC array server and the subsequent steps are repeated n times. If at least one of the n detection results does not meet the preset standard, the sixth test result is an error, and the test is terminated at this time.

[0032] Optionally, performing an aging test of a preset aging time on each component of the SoC board, and generating a seventh test result according to the operation of the system during the aging test, includes:

[0033] An aging test is performed on each component of the SoC board, and the aging test has a preset aging duration. If the system restarts and / or crashes during the aging test, the seventh test result is an error, and the test is terminated at this time.

[0034] Optionally, the restarting the system multiple times, obtaining the restart duration of the system each time, and generating an eighth test result according to the multiple restart durations, includes:

[0035] Simulating a user usage scenario, restarting the system multiple times, and obtaining the restart duration of the system each time. If the restart duration of the system each time meets the preset restart duration standard, the eighth test result is normal;

[0036] If the restart duration of the system at least once does not meet the preset restart duration standard, the eighth test result is an error, and the test is terminated at this time.

[0037] In a second aspect, the present invention provides a SoC array server, the SoC array server comprising a BMC mainboard, a backplane, a blade board, and a switch board connected to each other, the backplane comprising a backplane controller and a fan controller, the fan controller being connected to a plurality of fans; the blade board comprising a blade board controller, a SoC board, and a serial port controller;

[0038] The BMC motherboard is used to manage and monitor the operating status of the entire SoC array server; the BMC motherboard is also used to monitor the health status of the SoC array server in real time and perform remote management and maintenance;

[0039] The backplane controller is connected to the BMC mainboard, and is used to connect and coordinate various hardware components on the backplane, ensure that the various hardware components can operate and communicate normally, and manage and control various sub-modules on the entire backplane;

[0040] The blade board controller is connected to the backplane controller, and the blade board controller is used to communicate with each component in the blade board and manage and monitor the operating status of each component in the blade board;

[0041] The serial port controller is connected to the BMC mainboard, the blade board controller, the SoC board, and the switch board, and is used to configure and control the serial port devices in the SoC array server, support each serial port communication, and provide the status monitoring function of the SoC array server;

[0042] The switch board is used to establish a high-speed and stable data channel between various components inside the SoC array server; the switch board is also used to support fast data exchange between various components inside the SoC array server and support flexible network configuration to meet the needs of different business scenarios;

[0043] The fan controller is used to control the fan speed and monitor the fan status;

[0044] The SoC board includes a SoC chip, and the SoC board is used to perform various computing tasks and data processing operations on the SoC array server;

[0045] The BMC mainboard is used to execute the automated testing method for the SoC array server as described in any one of the first aspects.

[0046] The embodiments of the present invention have the following beneficial effects:

[0047] The present invention provides an automated testing method for a SoC array server, the method being applied to a BMC motherboard of a SoC array server, the SoC array server further comprising a backplane, a blade board, and a switch board, the backplane comprising a backplane controller and a fan controller, the fan controller being connected to a plurality of fans; the blade board comprising a blade board controller, a SoC board, and a serial port controller; the method specifically comprises: making the backplane controller, the fan, the blade board controller, the SoC board, the serial port controller, and the switch board work normally respectively, and setting a preset duration and a preset range to verify them respectively, finally obtaining a verification result, and generating a test report. The present invention verifies each part of the automated testing system of the SoC array server using different verification methods, obtains accurate test results, generates a complete test report based on the test results, and realizes comprehensive and efficient testing of the SoC array server. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0049] in:

[0050] Figure 1 A schematic diagram of a flow chart of an automated testing method for a SoC array server provided in an embodiment of the present application;

[0051] Figure 2 A schematic diagram showing an example of an automated testing method for a SoC array server provided in an embodiment of the present application;

[0052] Figure 3 A schematic diagram of the structure of a SoC array server provided in an embodiment of the present application. DETAILED DESCRIPTION

[0053] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0054] The embodiment of the present application proposes an automated testing method for a SoC array server, which uses an intelligent automated testing system to perform comprehensive and efficient automated testing on various components of the SoC array server, such as the backplane MCU, blade MCU, serial port MCU, switch board, and SoC board, thereby improving the reliability and performance of the server and reducing the cost of system deployment and maintenance. The method can accurately detect whether the components are working properly and generate corresponding test reports, and then can timely discover potential problems based on the test reports, further realizing important technical support for the deployment and maintenance of large-scale SoC array servers.

[0055] See also Figure 1 , is a flow chart of an automated testing method for a SoC array server provided in an embodiment of the present application, the method is applied to a BMC mainboard of a SoC array server, the SoC array server further includes a backplane, a blade board, and a switch board; the backplane includes a backplane controller and a fan controller; the fan controller is connected to a plurality of fans; the blade board includes a blade board controller, a SoC board, and a serial port controller; the method specifically includes:

[0056] Step 101: Send a first serial port command to a backplane controller, and generate a first test result according to whether a successful command sent back by the backplane controller is received within a first preset time period.

[0057] In an embodiment of the present application, the BMC mainboard sends a serial port instruction to the backplane controller and waits for a first preset time. If a successful instruction is received from the backplane controller within the first preset time, the first test result is normal. If no successful instruction is received within the first preset time, the step of sending the serial port instruction to the backplane controller and the subsequent steps are repeated n times. If no successful instruction is received n times, the first test result is an error, and the test is terminated at this time.

[0058] The first preset duration may be preferably 3s, and n may be preferably 3 times. It should be noted that the first preset duration and the value of n here are only a preferred example, and other values ​​that meet the standards can be applied to the embodiments of the present application, and are not too limited here.

[0059] An example is given for step 101: the BMC motherboard sends a serial port command to the backplane controller and waits for 3 seconds. If a success command is received from the backplane controller within 3 seconds, it indicates that the backplane controller is normal, and the first test result returned is normal. If no success command is received from the backplane controller within 3 seconds, it indicates that the backplane controller may be abnormal. In this case, the above steps are retried three times. If the success command is not received for the three times or other abnormal signals unrelated to the success command are received, it is confirmed that the backplane controller is abnormal. In this case, the first test result returned is an error, the user is reminded that the backplane controller has an abnormality, and the test process is terminated.

[0060] Step 102: Adjust the fan speed based on the fan controller within a first preset range, and generate a second test result according to whether the actual fan speed after adjustment meets the speed threshold.

[0061] In a feasible implementation, the fan speed is adjusted based on the fan controller within a first preset range, and each value within the first preset range corresponds to a speed threshold. If a value is selected within the first preset range to adjust the fan speed, and the actual speed of the fan after adjustment meets the speed threshold, the second test result is normal; if the actual speed of the fan after adjustment does not meet the speed threshold, the step of selecting a value within the first preset range to adjust the fan speed and the subsequent steps are repeated n times. If the actual fan speeds obtained n times do not meet the speed threshold, the second test result is an error, and the test is terminated at this time.

[0062] Among them, the full load speed of the fan is 15000 rpm, so the preset first preset range is 10% to 100%. At this time, the number of revolutions corresponding to 10% of the full load speed of the fan is 1500 rpm, so the speed threshold corresponding to 10% is set to 1500±10% (where 1500 is 15000*10%); and so on, the speed threshold corresponding to each value in the first preset range of 10% to 100% is obtained. As mentioned above, the first preset duration can be preferably 3s, and n can be preferably 3 times. It should be noted that the first preset duration and the value of n here are only a preferred example, and the other values ​​that meet the standards can be applied to the embodiments of the present application, and no excessive restrictions are made here.

[0063] An example is given for step 102: the BMC mainboard selects a value from 10% to 100% to adjust the fan speed. Assuming 25% is selected, the corresponding speed threshold is 3750±25% (where 3750 is 15000*25%). If the actual speed after adjustment does not exceed the speed threshold of 3750±25%, it means that the fan is normal, and the second test result returned is normal; if the actual speed after adjustment exceeds the speed threshold of 3750±25%, it means that the fan may be abnormal. At this time, the aforementioned adjustment steps are retried 3 times. If the results of the 3 times all show that the fan is abnormal, that is, the actual speed of the fan exceeds the speed threshold of 3750±25% in the 3 times, it is determined that the fan is abnormal. At this time, the second test result is returned as an error to remind the user that the fan is abnormal, and the test process is terminated.

[0064] It should be noted that, in addition to selecting any value within the first preset range to adjust the speed of the fan in step 102 , the speed of the fan may also be adjusted gradually from 10% to 100%.

[0065] Step 103: Receive the startup duration of the switch board, and generate a third test result according to whether the startup duration meets a preset duration range.

[0066] In an embodiment of the present application, the switch board is restarted and the startup time of the switch board is received. If the startup time is within the preset time range, the third test result is normal; if the startup time is not within the preset time range, the step of restarting the switch board and the subsequent steps are repeated n times. If the startup time obtained n times does not meet the preset time range, the third test result is an error, and the test is terminated at this time.

[0067] It can be understood that step 103 is mainly for the power-on and power-off test of the switch board, which is used to test whether the switch board restart circuit is normal and whether the network path is normal. Among them, the switch board startup time is generally 30s, and the longest does not exceed 40s, so the preset time range is preferably 30s to 40s, and n is preferably 3 times.

[0068] An example is given for step 103: restart the switch board and receive the startup time of the switch board. If the startup time is between 30s and 40s, it means that the switch board is normal, and the third test result returned is normal; if the startup time exceeds 40s, or the network access is abnormal, it means that the switch board may have an abnormality. Repeat the above steps three times. If the startup time obtained in the three times exceeds 40s, the third test result is returned as an error to remind the user that the switch board has an abnormality and terminate the test process.

[0069] Step 104: Send a second serial port command to the blade board controller, and generate a fourth test result according to whether a success command sent back by the blade board controller is received within a first preset time period.

[0070] In an embodiment of the present application, a serial port command is sent to the blade board controller and a first preset time period is waited. If a success command is received from the blade board controller within the first preset time period, the fourth test result is normal. If no success command is received within the first preset time period, the step of sending the serial port command to the blade board controller and the subsequent steps are repeated n times. If no success command is received n times, the fourth test result is an error and the test is terminated at this time.

[0071] As mentioned above, the first preset time duration is preferably 3 seconds, and n is preferably 3 times.

[0072] An example is given for step 104: the BMC mainboard sends a serial port instruction to the blade board controller and waits for 3 seconds. If a successful instruction returned by the blade board controller is received within 3 seconds, it means that the blade board controller is normal, and the fourth test result returned is normal. If the BMC mainboard fails to receive the successful instruction returned by the blade board controller or receives other abnormal signals within 3 seconds, it means that the blade board controller may have an abnormality. At this time, the above steps are retried 3 times. If no successful instruction is received from the blade board controller in 3 times, it is confirmed that the blade board controller is abnormal. At this time, the fourth test result returned is an error, reminding the user that an abnormality has occurred in the blade board controller and terminating the test process.

[0073] Step 105 , monitoring the continuous output of serial port data from the serial port controller, and generating a fifth test result according to whether the serial port data output by the serial port controller is received within the first preset time period.

[0074] In an embodiment of the present application, the continuous output of serial port data of the serial port controller is monitored. If the serial port data output by the serial port controller is not received within the first preset time period, the second preset time period is waited for. If the serial port data is not received within the second preset time period, the fifth test result is an error, and the test is terminated at this time.

[0075] It is understandable that the serial port MCU is the real-time serial port output party, and the BMC motherboard only needs to monitor whether the serial port data is continuously output to obtain the operation status of the serial port controller. Among them, the first preset time length is preferably 3s as mentioned above, and the second preset time length is preferably 30s.

[0076] An example is given for step 105: the BMC mainboard monitors whether the serial port data of the serial port controller is continuously output. If the serial port data output by the serial port controller is not received within 3 seconds, it means that the serial port controller may be abnormal. At this time, wait for 30 seconds. If no serial port data is received during the 30 seconds of waiting, it is confirmed that the serial port controller is abnormal. At this time, the fifth test result is returned as an error, reminding the user that the serial port controller has an abnormality and terminating the test process. If the serial port data transmitted by the serial port controller is received within 3 seconds, it means that the serial port controller is normal, and the fifth test result is returned as normal.

[0077] Step 106: Obtain at least one of the startup time, network speed, USB test result, deep recovery mode test result, and serial port test result of the SoC array server, and generate a sixth test result based on whether the startup time, network speed, USB test result, deep recovery mode test result, and serial port test result all meet preset standards.

[0078] In an embodiment of the present application, the SoC array server is restarted to obtain the startup time; at least one of the network speed, USB test result, deep recovery mode test result, and serial port test result is obtained; if the startup time, network speed, USB test result, deep recovery mode test result, and serial port test result all meet the preset standard, the sixth test result is normal; if at least one of the startup time, network speed, USB test result, deep recovery mode test result, and serial port test result does not meet the preset standard, the step of restarting the SoC array server and the subsequent steps are repeated n times; if at least one of the n test results does not meet the preset standard, the sixth test result is an error, and the test is terminated at this time.

[0079] It is understandable that step 106 is to test and verify the SoC function in the SoC array server. Among them, the preset standard for the startup time of restarting the SoC array server is to complete the startup within 2 minutes; the preset standard for the network speed is 2500W speed; the preset standard for the USB test result is whether the ADB (Android Debug Bridge, Android Debug Bridge is a versatile command line tool that allows devices to communicate with each other) is connected normally; the preset standard for the deep recovery mode test result is whether the deep flashing mode is started normally; the preset standard for the serial port test result is whether the serial port transmits data normally.

[0080] An example is given for step 106: restart the SoC array server to obtain the startup time; obtain at least one of the network speed, USB test result, deep recovery mode test result, and serial port test result. If the startup time is within 2 minutes, the network speed is 2500M, the USB test result shows that ADB is connected normally, the deep recovery mode test result shows that the deep flashing mode is started normally, and the serial port test result shows that the serial port data transmission is normal, then the SoC function is confirmed to be normal, and the sixth test result is returned as normal; if any one of the startup time, network speed, USB test result, deep recovery mode test result, and serial port test result does not meet the aforementioned preset standards, it means that the SoC function may be abnormal. At this time, repeat the aforementioned steps 3 times. If at least one of the 3 test results does not meet the preset standards, it is confirmed that the SoC function is abnormal. At this time, it is necessary to return the sixth test result as an error to remind the user that the SoC function has an abnormality and terminate the test process.

[0081] Step 107 : Perform an aging test with a preset aging time on each component of the SoC board, and generate a seventh test result according to the operation status of the system during the aging test.

[0082] In an embodiment of the present application, an aging test is performed on each component of the SoC board, and the aging test has a preset aging duration. If the system restarts and / or crashes during the aging test, the seventh test result is an error, and the test is terminated at this time.

[0083] The preset aging time is 3*24 hours. The aging test is mainly aimed at various components of the SoC board, such as CPU, GPU, network card, etc.

[0084] An example is given for step 107: an aging test is performed on each component of the SoC board for 3*24 hours. If the system restarts and / or crashes during the aging test, the system aging test is confirmed to be unsuccessful. At this time, the seventh test result is returned as an error, the user is reminded that an abnormal situation occurred in the aging test, and the test process is terminated; if during the aging test, the system has been running normally without restarting and / or crashing, the system aging test is successful, and the seventh test result is returned as normal.

[0085] Step 108: Restart the system multiple times, obtain the restart duration of each system, and generate an eighth test result based on the multiple restart durations.

[0086] In an embodiment of the present application, the system is restarted multiple times to simulate user usage scenarios, and the restart duration of each system is obtained. If the restart duration of each system meets the preset restart duration standard, the eighth test result is normal; if the restart duration of the system at least once does not meet the preset restart duration standard, the eighth test result is an error, and the test is terminated at this time.

[0087] It is understandable that the purpose of step 108 is to simulate the frequent restart verification operation in user use and test whether the frequent restart will cause damage to the SoC array server. The preset restart time standard is 2 minutes.

[0088] An example is given for step 108: imitating the user usage scenario, the system is restarted multiple times frequently, assuming it is restarted 100 times, and the restart duration of each system is obtained. If the system completes the restart within 2 minutes each time, the eighth test result is normal; if the restart duration of the system is not within 2 minutes at least once, it means that the system's resistance to frequent restarts is not good enough. At this time, the eighth test result is returned as an error, reminding the user that an abnormality occurred in the restart operation test, and terminating the test process.

[0089] Step 109: Generate and output a test report based on the first test result, the second test result, the third test result, the fourth test result, the fifth test result, the sixth test result, the seventh test result, and the eighth test result.

[0090] Understandably, see Figure 2 , is an example schematic diagram of an automated testing method for a SoC array server provided in an embodiment of the present application. After all test verifications are completed, a complete test report is generated for the first test result, the second test result, the third test result, the fourth test result, the fifth test result, the sixth test result, the seventh test result, and the eighth test result, and is automatically output and displayed to the user end.

[0091] In the embodiment of the present application, by verifying each part of the automated test system of the SoC array server using different verification methods, accurate test results are obtained, and a complete test report is generated based on the test results, thereby achieving comprehensive and efficient testing of the SoC array server.

[0092] See also Figure 3 , is a schematic diagram of a SoC array server structure provided in an embodiment of the present application. The SoC array server includes a BMC mainboard 310, a backplane 320, a blade board 330, and a switch board 340 connected to each other. The backplane 320 includes a backplane controller 321 and a fan controller 322. The fan controller 322 is connected to multiple fans. The blade board 330 includes a blade board controller 331, a SoC board 332, and a serial port controller 333. Specifically:

[0093] The BMC (Baseboard Management Controller) mainboard 310 can be connected to the switch board 340 through at least one of Ethernet, UART (Universal Asynchronous Receiver-Transmitter) serial port, and Console console. The BMC mainboard 310 is also connected to the backplane controller 321 and the serial port controller 333 through the UART serial port; the backplane controller 321 is connected to the switch board 340 and the blade board controller 331 through the I / O control method, the backplane controller 321 is connected to the fan controller 322 through the PM BUS (Power Management Bus), and the backplane controller 321 can also be connected to the blade board controller 331 through the UART serial port; the blade board controller 331 is connected to the serial port controller 333 and the SoC board 332 through the I / O control method; the SoC board 332 is connected to the serial port controller 333 through the UART serial port, and the SoC board 332 is connected to the switch board 340 through Ethernet; the serial port controller 333 can also be connected to the switch board 340 through Ethernet.

[0094] The BMC motherboard 310 is the core control board of the SoC array server, responsible for managing and monitoring the operating status of the entire server. It integrates a series of management functions, such as remote monitoring, fault diagnosis, power control, fan control, etc. Through the BMC motherboard 310, administrators can monitor the health status of the server in real time and perform remote management and maintenance.

[0095] The backplane 320 integrates a backplane controller 321 and a fan controller 322 .

[0096] The backplane controller 321 is a control module on the SoC array server backplane 320, which is used to manage and control the various sub-modules on the entire backplane 320. It is responsible for connecting and coordinating the various hardware components on the backplane 320 to ensure that they can operate normally and communicate. There is data exchange between the backplane controller 321 and the BMC motherboard 310. Through this communication, the BMC motherboard 310 can monitor and manage all sub-modules on the backplane 320.

[0097] The fan controller 322 is responsible for controlling the speed of the above-mentioned multiple fans and monitoring the fan status. Figure 2 The preferred number of fans is 4, but this does not mean that only 4 fans can be connected to the SoC array server. This is just an example of a preferred embodiment and does not impose too many restrictions.

[0098] The blade board 330 integrates a blade board controller 331, a SoC board 332, and a serial port controller 333. There are preferably 4 blade boards 330, 10 SoC boards 332, and 2 serial port controllers 333. It should be noted that this is only a preferred case and does not impose too many restrictions on the number.

[0099] The blade board controller 331 is a control module on the SoC array server blade board 330, which is used to manage and monitor the operating status of the blade board 330. It is responsible for communicating with various components in the blade board 330. There is data exchange between the blade board controller 331 and the backplane controller 321. Through this communication, the backplane controller 321 can uniformly manage and monitor the blade board 330.

[0100] SoC board 332 is the core computing unit of SoC array server. Each SoC board integrates a SoC chip, including processor, memory, I / O interface, etc. SoC board 332 is the computing and data processing core of SoC array server. They are responsible for executing various computing tasks and data processing operations on SoC array server. In SoC array server, multiple SoC boards 332 form an array, which are connected and work together through switch board 340 and backplane controller 321 to achieve high-performance data processing and computing capabilities.

[0101] The serial port controller 333 is connected to the BMC mainboard 310, the blade board controller 331, the SoC board 332, and the switch board 340. It is a control module in the SoC array server and is responsible for managing and controlling each serial port in the SoC array server. It can configure and control each serial port device in the SoC array server, support serial port communication, and provide the status monitoring function of the SoC device in the SoC array server.

[0102] The switch board 340 is an important component in the SoC array server, responsible for processing the network communication inside the SoC array server. It integrates a high-performance switch chip to establish a high-speed and stable data channel between the various components inside the SoC array server. The switch board 340 allows fast data exchange between various components and supports flexible network configuration to meet the needs of different business scenarios. Among them, the switch board can be preferably a 25G switch board. Similarly, this is only a preferred case and is not too restrictive.

[0103] It is understandable that the above Figure 1 The automated testing method for a SoC array server described in the specification is performed in the BMC mainboard 310 in the SoC array server.

[0104] In the embodiment of the present application, the BMC mainboard 310 performs the following steps: Figure 1 Any of the automated testing methods for SoC array servers described in Figure 1 The contents of the illustrated embodiments are not described in detail here.

[0105] In an embodiment of the present application, a computer-readable storage medium is provided, which stores a computer program. When the computer program is executed by a processor, the processor executes a method of any one of the above method embodiments.

[0106] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the program can be stored in a non-volatile computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0107] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0108] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. An automated testing method for a SoC array server, It is characterized in that The method is applied to a BMC mainboard of a SoC array server, wherein the SoC array server further comprises a backplane, a blade board, and a switch board, wherein the backplane comprises a backplane controller and a fan controller, and the fan controller is connected to a plurality of fans; The blade board includes a blade board controller, a SoC board, and a serial port controller; the method includes: Sending a first serial port command to the backplane controller, and generating a first test result according to whether a successful command returned by the backplane controller is received within a first preset time period; adjusting the fan speed based on the fan controller within a first preset range, and generating a second test result according to whether the actual speed of the fan after adjustment meets the speed threshold; Receiving the startup duration of the switch board, and generating a third test result according to whether the startup duration meets a preset duration range; Sending a second serial port command to the blade board controller, and generating a fourth test result according to whether a successful command returned by the blade board controller is received within the first preset time period; Monitoring the continuous output of serial port data of the serial port controller, and generating a fifth test result according to whether the serial port data output by the serial port controller is received within the first preset time period; Obtain at least one of the startup time, network speed, USB test result, deep recovery mode test result, and serial port test result of the SoC array server, and generate a sixth test result according to whether the startup time, network speed, USB test result, deep recovery mode test result, and serial port test result all meet preset standards; Performing an aging test of a preset aging time for each component of the SoC board, and generating a seventh test result according to the operation status of the system during the aging test; Restarting the system multiple times, obtaining the restart duration of the system each time, and generating an eighth test result according to the multiple restart durations; A test report is generated and output based on the first test result, the second test result, the third test result, the fourth test result, the fifth test result, the sixth test result, the seventh test result, and the eighth test result.

2. The method according to claim 1, It is characterized in that The sending of the first serial port command to the backplane controller and generating a first test result according to whether a successful command returned by the backplane controller is received within a first preset time period include: Sending a serial port command to the backplane controller and waiting for a first preset time, if a success command sent back by the backplane controller is received within the first preset time, the first test result is normal; If the success command is not received within the first preset time length, repeat the step of sending the serial port command to the backplane controller and the subsequent steps n times. If the success command is not received n times, the first test result is an error and the test is terminated.

3. The method according to claim 1, It is characterized in that The fan speed is adjusted based on the fan controller within the first preset range, and a second test result is generated according to whether the actual speed of the fan after adjustment meets the speed threshold, including: The fan speed is adjusted based on the fan controller within a first preset range, each value within the first preset range corresponds to a speed threshold, and if a certain value is selected within the first preset range to adjust the fan speed, and the actual speed of the fan after adjustment meets the speed threshold, then the second test result is normal; If the actual speed of the fan after adjustment does not meet the speed threshold, repeat the step of selecting a value within the first preset range to adjust the fan speed and the subsequent steps n times. If the actual fan speed obtained n times does not meet the speed threshold, the second test result is an error and the test is terminated.

4. The method according to claim 1, It is characterized in that The receiving the startup duration of the switch board and generating a third test result according to whether the startup duration meets a preset duration range includes: Restarting the switch board, receiving the startup duration of the switch board, and if the startup duration is within a preset duration range, the third test result is normal; If the startup duration does not meet the preset duration range, repeat the step of restarting the switch board and the subsequent steps n times. If the startup durations obtained n times do not meet the preset duration range, the third test result is an error, and the test is terminated at this time.

5. The method according to claim 1, It is characterized in that The sending of the second serial port command to the blade board controller and generating a fourth test result according to whether a successful command returned by the blade board controller is received within the first preset time period include: Sending a serial port command to the blade board controller and waiting for a first preset time, if a success command sent back by the blade board controller is received within the first preset time, the fourth test result is normal; If the success instruction is not received within the first preset time length, repeat the step of sending the serial port instruction to the blade board controller and the subsequent steps n times. If the success instruction is not received n times, the fourth test result is an error and the test is terminated at this time.

6. The method according to claim 1, It is characterized in that The monitoring of the continuous output of the serial port data of the serial port controller and generating a fifth test result according to whether the serial port data output by the serial port controller is received within the first preset time period include: Monitor the continuous output of the serial port data of the serial port controller. If the serial port data output by the serial port controller is not received within the first preset time, wait for the second preset time. If the serial port data is not received within the second preset time, the fifth test result is an error, and the test is terminated at this time.

7. The method according to claim 1, It is characterized in that Obtaining at least one of the startup duration, network speed, USB test result, deep recovery mode test result, and serial port test result of the SoC array server, and generating a sixth test result according to whether the startup duration, network speed, USB test result, deep recovery mode test result, and serial port test result all meet preset standards, including: Restart the SoC array server to obtain the startup time; obtain at least one of the network speed, USB test result, deep recovery mode test result, and serial port test result. If the startup time, network speed, USB test result, deep recovery mode test result, and serial port test result all meet the preset standards, the sixth test result is normal; If at least one of the startup duration, network speed, USB detection result, deep recovery mode detection result, and serial port detection result does not meet the preset standard, the step of restarting the SoC array server and the subsequent steps are repeated n times. If at least one of the n detection results does not meet the preset standard, the sixth test result is an error, and the test is terminated at this time.

8. The method according to claim 1, It is characterized in that The aging test of the preset aging time is performed on each component of the SoC board, and a seventh test result is generated according to the operation status of the system during the aging test, including: An aging test is performed on each component of the SoC board, and the aging test has a preset aging duration. If the system restarts and / or crashes during the aging test, the seventh test result is an error, and the test is terminated at this time.

9. The method according to claim 1, It is characterized in that The multiple restarts of the system, obtaining the restart duration of each system, and generating an eighth test result according to the multiple restart durations, including: Simulating a user usage scenario, restarting the system multiple times, and obtaining the restart duration of the system each time. If the restart duration of the system each time meets the preset restart duration standard, the eighth test result is normal; If the restart duration of the system at least once does not meet the preset restart duration standard, the eighth test result is an error, and the test is terminated at this time.

10. A SoC array server, It is characterized in that The SoC array server includes a BMC mainboard, a backplane, a blade board, and a switch board that are connected to each other. The backplane includes a backplane controller and a fan controller, and the fan controller is connected to a plurality of fans. The blade board includes a blade board controller, a SoC board, and a serial port controller. The BMC motherboard is used to manage and monitor the operating status of the entire SoC array server; the BMC motherboard is also used to monitor the health status of the SoC array server in real time and perform remote management and maintenance; The backplane controller is connected to the BMC mainboard, and is used to connect and coordinate various hardware components on the backplane, ensure that the various hardware components can operate and communicate normally, and manage and control various sub-modules on the entire backplane; The blade board controller is connected to the backplane controller, and the blade board controller is used to communicate with each component in the blade board and manage and monitor the operating status of each component in the blade board; The serial port controller is connected to the BMC mainboard, the blade board controller, the SoC board, and the switch board, and is used to configure and control the serial port devices in the SoC array server, support each serial port communication, and provide the status monitoring function of the SoC array server; The switch board is used to establish a high-speed and stable data channel between various components inside the SoC array server; the switch board is also used to support fast data exchange between various components inside the SoC array server and support flexible network configuration to meet the needs of different business scenarios; The fan controller is used to control the fan speed and monitor the fan status; The SoC board includes a SoC chip, and the SoC board is used to perform various computing tasks and data processing operations on the SoC array server; Wherein, the BMC mainboard is used to execute the automated testing method of the SoC array server as described in any one of claims 1 to 9.

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