A method for calculating loss and junction temperature of DC / AC converter based on current path analysis

Abstract

The application provides a DC / AC converter loss and junction temperature calculation method based on current path analysis. Specifically, the working mode of the DC / AC converter topology is analyzed, the power device and capacitor element information of each current path is obtained, which is summarized and recorded as a current path matrix; based on the current path matrix, the voltage and current calculation expression of each power device in the DC / AC converter topology is derived, and the voltage and current waveform of the power device is calculated by substituting the power device driving signal and the DC / AC converter output voltage and current waveform; the steady-state average loss and junction temperature of the power device in the DC / AC converter are calculated by combining the power device loss model and the system thermal circuit model and using the iterative algorithm. The application is suitable for loss and junction temperature calculation of any DC / AC converter topology, and the calculation process only needs linear operation, without solving complex differential equations, which greatly reduces the time cost of loss and temperature rise evaluation calculation process of different parameter combination schemes in the design stage of the DC / AC converter.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of power electronics, and relates to a DC / AC converter loss and junction temperature calculation method, in particular to a DC / AC converter loss and junction temperature calculation method based on current path analysis. BACKGROUND

[0002] With the deepening of the degree of electrification of modern energy systems, the power handling scale of power electronic converters is rapidly growing due to their high efficiency of electric energy conversion, and the application scenarios are also continuously expanding. Under the strong driving of industrial development, the demand for high-performance power electronic converters is increasing, the requirement for power density is becoming increasingly stringent, and the single-machine power handling capacity coverage range is also continuously expanding to meet the needs of diversified application scenarios. In high-power and high-density application scenarios, increasing the DC bus voltage level and using a multi-level topology scheme will exhibit great advantages in cost, efficiency, power density, waveform quality and other aspects compared with the traditional two-level topology scheme. In some traditional application scenarios, the two-level topology scheme is still the preferred scheme due to its simple and reliable topology, low cost and other advantages. Designing a converter has a high degree of freedom, including but not limited to the selection of circuit topology, the selection of modulation strategy, the determination of switching frequency, and the selection and combination of power devices and passive devices. However, how to calculate the loss and temperature of each scheme in limited computing resources and time cost to seek the optimal scheme in a specific application scenario is still a big challenge for designers.

[0003] Currently, the methods for evaluating the steady-state performance of different inverter schemes can be divided into three categories: First, simulation analysis based on power electronic simulation software platform. The corresponding circuit model is built in the simulation software, and the corresponding script file is written. The global optimal scheme is obtained by realizing the automatic parameter scanning and performance comparison through the official interface provided by the software. The simulation analysis method is essentially a numerical solution algorithm for the differential equations of the circuit model based on the binary resistance model of power devices. The simulation results are the most accurate, but this also leads to a very tedious and time-consuming scheme evaluation process. Second, numerical calculation method based on circuit steady-state behavior model. When the modulation carrier ratio is greater than 21, the steady-state output current of the DC / AC converter can be simplified as a sinusoidal waveform. Based on the sinusoidal output current and the specific modulation strategy, the current waveform of each power device is obtained, and then the instantaneous loss and periodic average loss are obtained by combining the loss model of the power device. The literature "J. Ebersberger, M. Hagedorn, M. Lorenz and A. Mertens, "Potentials and Comparison of Inverter Topologies for Future All-Electric Aircraft Propulsion," in IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 10, no. 5, pp. 5264-5279, Oct. 2022" summarizes the general power device conduction loss and switching loss calculation method, and specifically derives the power device loss expression corresponding to several common inverter topologies. However, for complex multi-level topologies and variable modulation strategies, the derivation process of the loss expression will also become very tedious, making it difficult to be practically applied. Third, qualitative comparative analysis method based on engineering experience. Relying on the personal experience of engineers or rough empirical formulas, different inverter schemes are quickly compared and evaluated in terms of key indicators. However, this method has the defects of strong subjectivity in the analysis process and lack of objective evaluation criteria. It is usually used for preliminary screening of technical routes, and the final scheme still needs to be determined through quantitative comparison and optimization design. SUMMARY

[0004] In order to improve the shortcomings of the above methods, the present application proposes a DC / AC converter loss and junction temperature calculation method based on current path analysis.

[0005] The technical scheme of the present application is as follows:

[0006] A DC / AC converter loss and junction temperature calculation method based on current path analysis, comprising the following steps:

[0007] (1) analyzing all working modes of the DC / AC converter topology, collecting power device and capacitor element information of each current path corresponding to each working mode to obtain a current path matrix CP;

[0008] (2) calculating voltage and current waveforms of each power device in the DC / AC converter topology according to the current path matrix CP;

[0009] (3) calculating steady-state average loss and power device chip junction temperature of the DC / AC converter topology according to the calculated power device voltage and current waveforms, combining a power device loss model and a system thermal circuit model.

[0010] Further, the specific steps of obtaining the current path matrix include:

[0011] converting the DC / AC converter topology into a directed graph according to a conversion relationship between the power device and the capacitor element and the directed graph;

[0012] searching all node paths between a reference ground node and an output node in the directed graph by means of a graph theory path search algorithm;

[0013] obtaining power device and capacitor element information of each current path according to the node paths to obtain the current path matrix CP.

[0014] Further, the conversion relationship between the power device and the capacitor element and the directed graph is:

[0015] for a device with bidirectional current conduction, including IGBT, MOSFET and bus capacitor, etc., the device is converted into a directed graph defined by a node set V={1, 2} and a directed edge set E={(1, 2), (2, 1)}, wherein 1 and 2 represent the numbers of nodes at both ends of the device, and (1, 2) represents a directed edge from node 1 to node 2; for a device with unidirectional current conduction, including a diode, the device is converted into a directed graph defined by a node set V={1, 2} and a directed edge set E={(1, 2)}, wherein the direction of the directed edge is the same as the direction of the conduction current of the device.

[0016] Further, the graph theory path search algorithm is:

[0017] starting from a starting node, accessing each possible path in a depth-first strategy, and using a stack to avoid repeated access to nodes, when the terminating node is accessed, the node path from the starting node to the terminating node is recorded, and the entire directed graph is traversed.

[0018] Further, the matrix format of the current path matrix CP is shown in formula 1:

[0019] CP r×(t+2) =[PDr×t SV r×1 CD r×1 ]#(1)

[0020] The current path matrix CP is composed of three sub-matrices of PD, SV and CD, wherein the PD sub-matrix represents the information of power devices through which each current path passes, the SV sub-matrix represents the output voltage value corresponding to each current path, and the CD sub-matrix represents the conductive direction of each current path, and r in the matrix subscript is the number of current paths between the reference ground node and the output node of the topology, and t is the number of power devices of the topology.

[0021] Further, the specific steps of calculating the voltage and current waveforms of each power device in the DC / AC converter topology are as follows:

[0022] According to the current path matrix CP, the output voltage of the DC / AC converter is calculated;

[0023] The DC / AC converter is equivalent to a voltage source, and the response current waveform of the load under this voltage excitation, i.e. the output current of the DC / AC converter, is solved by using circuit analysis calculation method;

[0024] According to the current path matrix CP, the voltage and current calculation expressions of the power device are derived, and the specific voltage and current waveforms of the power device are obtained by substituting the power device driving waveform and the output voltage and output current of the DC / AC converter.

[0025] Further, the calculation formula of the output voltage U xo of the DC / AC converter is shown in formula 2:

[0026]

[0027] Wherein, s is the total number of voltage nodes in the DC / AC converter topology, V k is the voltage value of the kth voltage node, w k is the connection flag of the kth voltage node and the output node, and the calculation expression is shown in formula 3:

[0028]

[0029] Wherein CD(i) is the ith element of the CD sub-matrix, representing the conductive direction of the ith current path; CD(j) is the jth element of the CD sub-matrix, representing the conductive direction of the jth current path; M k is the set of row numbers of the current path in which the output voltage is equal to V k ; SV(x) is the xth element of the SV sub-matrix, representing the voltage value of the output node when the xth current path is turned on; e ie is the switch state flag bit of the full-controlled device in the i-th current path j e is the switch state flag bit of the full-controlled device in the i-th current path

[0030]

[0031] PD(i,j) is the i-th row and j-th column element of the PD sub-matrix, which represents the information that the i-th current path passes through the j-th power device, g xj is the driving signal of the j-th power device;

[0032] The specific steps of the circuit analysis and calculation method include:

[0033] The DC / AC converter output voltage U xo is transformed into a frequency domain signal U xo，fd (nω0) by an FFT algorithm;

[0034] The frequency domain signal I xo，fd (nω0) of the DC / AC converter output current is calculated according to the expression as shown in expression 5 load (nω0), wherein Z xo，fd (nω0) is the complex frequency domain impedance of the load, and ω0 is the fundamental angular frequency of the converter;

[0035]

[0036] The frequency domain signal I xo (nω0) of the DC / AC converter output current is transformed into a response current waveform I Qxj of the load by an iFFT algorithm.

[0037] Further, the current calculation expression of the power device is as shown in expression 6:

[0038]

[0039] I(k,j) is the current waveform of the power device, sgn(PD(k,j)) is a sign function, PD(k,j) is the k-th row and j-th column element of the PD sub-matrix, which represents the information that the k-th current path passes through the j-th power device, I k (k) is the current of the k-th current path, h k (k) is the direction flag bit of the k-th current path, and its expression is as shown in expression 7, h j (j) is the direction flag bit of the j-th current path, e k (k) is the turn-on flag bit of the full-controlled device in the k-th current path;

[0040]

[0041] wherein CD(k) is the kth element of the CD sub-matrix, representing the conductive direction of the kth current path;

[0042] The voltage waveform of the power device is obtained by subtracting the voltage waveform of its two end nodes. For the ni node in the topology, the calculation expression of its voltage is shown in Equation 8:

[0043]

[0044] wherein U ni (i) is the voltage value of the node ni at the ith time point iT s (i-1) is the voltage value of the node ni at the (i-1)th time point (i-1)T ni (i-1) s (i) is the voltage value of the node ni at the ith time point iT xo (i-1) is the voltage value of the node ni at the (i-1)th time point (i-1)T s (i) is the output voltage value of the DC / AC converter at the ith time point iT L is the current path matrix between the node n ref i and ni (in the present application, the matrix is denoted by subscript L), CP R is the current path matrix between the node n out i and ni (in the present application, the matrix is denoted by subscript R), s L and s R are respectively the conductive state of the power device in the current path CP L and CP R , V k，L and V k，R are respectively the number of voltage nodes in the current path CP k，L and CP k，R , p i and p i are respectively the connection flag of the kth voltage node in the current path CP L and CP L to the node ni, and the expression is shown in Equation 9:

[0045]

[0046] wherein e ref is the switch state flag of the power device in the ith current path; d R is the conductive flag of the diode in the ith current path; PD R (i,j) is the i-row j-column element of the current path matrix CP out , representing the information that the ith current path between the node n DxjLet be the current of the j-th power device.

[0047] Furthermore, the specific steps for calculating the steady-state average loss and junction temperature of each power device in the DC / AC converter topology include:

[0048] Using the power device loss model and the system thermal circuit model, the average loss and junction temperature of each power device in the DC / AC converter topology are calculated based on the initial junction temperature parameters. The junction temperature result of this round is used as the junction temperature input for the next round of calculation. The average loss and junction temperature are calculated iteratively until the difference between the junction temperatures of two consecutive calculations is less than a set threshold. At this point, the loss and heat in the DC / AC converter have reached a steady state. The average loss and junction temperature obtained from the last calculation are the steady-state average loss and junction temperature.

[0049] Furthermore, the power device loss model varies depending on the device type; the loss model P for IGBT devices... tot，IGBT As shown in Equation 10, the diode loss model P tot，Diode As shown in Equation 11:

[0050]

[0051] P tot，Diode =P cond(D) +P rr #(11)

[0052] Among them, P tot(T) The total loss of the IGBT chip, including conduction loss P. cond(T) Turn-on loss P on and turn-off loss P off The specific calculation expression is shown in Equation 12, P tot(D) The total loss of the freewheeling diode in a diode or IGBT device, including conduction loss P. cond(D) and reverse recovery loss P rr The specific calculation expression is shown in Equation 13:

[0053]

[0054]

[0055] Where T is the fundamental period, T s To calculate the step size, m is the array length of the waveform sequence, satisfying m = T / T s T j(T) V represents the average junction temperature of the device chip. ce (I, T) j(T) ) represents the forward conduction IV model of IGBT, E on (I, U, T) j(T) ) and E off(I, U, T j(T) ) are turn-on and turn-off loss models of IGBT, respectively; T j(D) is the average junction temperature of the freewheeling diode chip, V f (I, T j(D) ) is the on-state I-V model of the freewheeling diode, E rr (I, U, T j(D) ) is the turn-off loss model of the freewheeling diode; I(i) is the current flowing through the IGBT at the iT s moment, I(i-1) is the current flowing through the IGBT at the (i-1)T s moment, U(i) is the voltage of the IGBT at the iT s moment, U(i-1) is the voltage of the IGBT at the (i-1)T s moment.

[0056] The system thermal circuit model is composed of heat sources and thermal resistances, the total number of the heat sources is the same as the total number of the power device chips in the DC / AC converter topology, and the thermal resistances are composed of the thermal resistance R th(s-a) from the heat sink to the environment, the thermal resistance R th(c-s) from the power device shell to the heat sink, and the thermal resistance R th(j-c) from the power device chip junction to the shell; according to the system thermal circuit model, the junction temperature calculation expression of the IGBT chip and its freewheeling diode chip is shown in formula 14, and the junction temperature expression of the diode device chip is shown in formula 15:

[0057]

[0058] T j，Dxk = P tot，Diode，xk · R th(j-c) + P tot，xk · R th(c-s) + ΔT s-a + T a #(15)

[0059] Wherein, T j(T)，IGBT，xk is the junction temperature of the x-phase k-number IGBT chip, P tot(T)，xk is the loss of the x-phase k-number IGBT chip, T j(D)，IGBT，xk is the junction temperature of the freewheeling diode chip of the x-phase k-number IGBT, P tot(T)，xk is the loss of the freewheeling diode chip of the x-phase k-number IGBT, T j，Dxk is the junction temperature of the x-phase k-number diode chip, P tot，Diode，xk is the loss of the x-phase k-number diode chip; T a is the ambient temperature, ΔT c-s，xk is the temperature difference value of the thermal resistance R th(c-s) from the x-phase k-number power device shell to the heat sink, and ΔTs-a The thermal resistance R from the heatsink to the environment th(s-a) The temperature difference is calculated using the formula shown in Equation 16:

[0060]

[0061] Among them, P tot，IGBT，xk P represents the total loss of the k-th IGBT device in phase x. tot，Diode，xk Let t be the total loss of the k-th diode in phase x. For a three-phase system, x represents one of the three phases {a, b, c}, and t is the total number of power devices in any phase topology of the three-phase system.

[0062] The beneficial effects of this invention are as follows:

[0063] This invention is applicable to loss and junction temperature calculations for any DC / AC converter topology. Moreover, the calculation process only requires linear operations and does not require solving complex differential equations, which greatly reduces the time spent on loss and temperature rise evaluation calculations for different parameter combinations during the DC / AC converter design phase. Attached Figure Description

[0064] Figure 1 This is a schematic diagram illustrating the transformation relationship between power devices and capacitors and directed edges in a DC / AC converter according to an example of the present invention.

[0065] Figure 2 This is a flowchart of the depth-first path search algorithm for directed graphs in an example of the present invention.

[0066] Figure 3 This is a flowchart illustrating the calculation of the voltage waveform of the power device in an example of the present invention.

[0067] Figure 4 This is a flowchart illustrating the calculation of steady-state average loss and junction temperature of the power device in an example of the present invention.

[0068] Figure 5 This is a schematic diagram of the thermal path model of the converter system in an example of the present invention.

[0069] Figure 6 This is a schematic diagram of a three-level NPC topology and its corresponding directed graph.

[0070] Figure 7 This is a schematic diagram of the linear circuit equivalent to the DC / AC converter topology in the example of the present invention using a voltage source model. Detailed Implementation

[0071] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and specific examples.

[0072] The flow of the calculation method is as follows: first, the converter topology is converted into a directed graph, and all node paths between the reference ground node and the output node in the DC / AC converter topology are found by means of a path search algorithm of graph theory, so as to realize the analysis of the working mode of the DC / AC converter topology. Subsequently, the power device and capacitor element information of each current path is obtained according to the node path, and is summarized and recorded as a current path matrix. Secondly, based on the current path matrix, the voltage and current calculation expressions of each power device in the DC / AC converter topology are derived, and are substituted into the power device driving signal and the DC / AC converter output voltage and current waveform, so as to calculate the voltage and current waveform of the power device. Finally, the steady-state average loss and junction temperature of the power device in the DC / AC converter are calculated by using an iterative algorithm in combination with the power device loss model and the system thermal circuit model.

[0073] The first step is to analyze all working modes of the converter topology, and to summarize the power device and capacitor element information of the current path of each working mode, so as to obtain a current path matrix. The specific process is as follows:

[0074] Firstly, the converter topology is converted into a directed graph. The specific conversion relationship is shown in FIG. 1, that is, full-controlled devices such as IGBT and MOSFET and capacitor devices are converted into two opposite directed edges between their two end nodes, and a diode is converted into a directed edge between its two end nodes, and the direction of the directed edge is the same as the reference direction of the diode. Figure 1

[0075] Secondly, all node paths between the reference ground node n ref and the output node n out in the directed graph are searched, so as to realize the analysis of the working mode. The positive node path is obtained by taking n out as a starting node and n ref as a terminating node, and calling a path search algorithm of graph theory; the reverse node path is obtained by taking n ref as a starting node and n out as a terminating node, and calling a path search algorithm of graph theory. In the present method, a depth-first path search algorithm is adopted, and the flow chart thereof is shown in FIG. 2. Figure 2

[0076] Finally, the directed edge set through by each current path is obtained according to the positive and reverse node paths, and the device information represented by these directed edges is summarized as a current path matrix, denoted as CP, and the general form thereof is as follows:

[0077] CP r×(t+2) = [PD r×t SV r×1 CD r×1 ]#(1) ​​

[0078] The current path matrix is composed of three sub-matrices: the first is an r x t sub-matrix PD representing the information of each current path passing through the power device. Wherein, r is the number of reference nodes of the topology ref The number of current paths between the output node n out The i x j element of the PD matrix is denoted as PD(i, j). If the value is zero, it represents that the i-th current path does not pass through the j-th power device; if the value is not zero, it represents that the i-th current path passes through the j-th power device. Further, for the non-zero elements in the PD matrix, the absolute value represents the type of the power device, and the absolute value of 1 represents full-controlled devices such as IGBT and MOSFET, and the absolute value of 2 represents uncontrolled devices such as diode; the sign of the non-zero element represents the relative relationship between the output current direction and the reference direction of the power device, and the positive sign represents the same direction, and the negative sign represents the opposite direction. The second is a column matrix SV representing the corresponding output level value of each current path, wherein the i-th element is denoted as SV(i), representing the voltage value of the output node when the i-th current path is turned on. The third is a column matrix CD representing the conductive direction of each current path, wherein the i-th element is denoted as CD(i). If the value is 1, it represents that the current path can only be turned on when the output current is positive; if the value is 2, it represents that the current path can only be turned on when the output current is negative; if the value is 3, it represents that the current path can be turned on under any output current polarity.

[0079] In the second step, the voltage and current calculation expressions of each power device in the DC / AC converter topology are derived based on the current path matrix obtained in the first step, and the power device driving signals and the output voltage and current waveforms of the DC / AC converter are substituted to calculate the voltage and current waveforms of the power device. The specific process is as follows:

[0080] Firstly, the output voltage waveform of the DC / AC converter topology is calculated, and the output current waveform is calculated according to the load impedance characteristics.

[0081] The calculation expression of the output voltage of the DC / AC converter topology is as follows:

[0082]

[0083] Wherein, s is the total number of voltage nodes in the converter topology, V k is the voltage value corresponding to the k-th voltage node, w k is the connection flag of the k-th voltage node and the output node, and only one of all connection flags is 1. The calculation expression of the connection flag w k is as follows:

[0084]

[0085] Among them, M k The output voltage is equal to V k The set of current path numbers, e i Let f be the switching status flag bit of the fully controlled device in the i-th current path. The calculation expressions for these two parameters are:

[0086]

[0087] Among them, g xj For the drive signal of the Qxj device, if the drive signal of Qxj is high, then g xj =1, if the drive of Qxj is low, then g xj =0.

[0088] The output voltage U is obtained xo Then, the time-domain waveform is transformed into a frequency-domain signal U using the FFT algorithm. xo，fd This is used as the voltage source excitation, and the output current I is calculated using the complex frequency domain analysis method of the circuit. xo Therefore, the expression for calculating the output current of the DC / AC converter topology is:

[0089]

[0090] Among them, Z load For the impedance spectrum of a linear load, I xo，fd The frequency domain signal of the output current is given, and then the time domain waveform I of the output current can be obtained by iFFT algorithm transformation. xo .

[0091] Secondly, the calculation expressions for the current waveforms of each power device in the topology are as follows:

[0092]

[0093] Where sgn(x) is the sign function, I k Let I be the current in the k-th current path, and its value is related to the output current I. xo Directly related, its calculation expression is as follows:

[0094]

[0095] Among them, h k The direction flag for the k-th current path is calculated as follows:

[0096]

[0097] Finally, the flowchart for calculating the voltage waveforms of each power device in the topology is as follows: Figure 3The voltage waveform of the diode is shown, which is obtained by subtracting the voltage of its two nodes. For the voltage calculation of any node ni, first find all the node paths passing through ni from the previously obtained forward and reverse node paths; then replace the node ni in the forward and reverse node paths with the current path matrix CP ref The forward and reverse node paths between ni and ni+1 are converted into a current path matrix, denoted as CP L The forward and reverse node paths between ni and ni+1 are converted into a current path matrix, denoted as CP out The forward and reverse node paths between ni and ni+1 are converted into a current path matrix, denoted as CP R ; finally, the voltage waveform of ni is calculated according to the current path matrix CP L and CP R , and the specific calculation expression is:

[0098]

[0099] where U ni (i) is the voltage value of node ni at iT s , U ni (i-1) is the voltage value of node ni at (i-1)T s , U xo (i) is the output voltage value at iT s , s L and s R are the number of voltage nodes in CP L and CP R respectively, V k，L and V k，R are the voltage values corresponding to the kth voltage node in the respective current path model, and p k，L and p k，R are the connection flag bits of the kth voltage node and node ni in the respective current path model. The specific calculation expression is:

[0100]

[0101] where d i is the flag bit of the conduction of the i-th current path diode, and the calculation expression is as follows:

[0102]

[0103] Thirdly, the steady-state average loss and junction temperature of the power devices in the DC / AC converter topology are calculated by using the iterative algorithm combined with the power device loss model and the system thermal circuit model. For example, Figure 4The calculation flow chart for calculating the steady-state average loss and junction temperature of the power device is shown. First, an initial junction temperature T0 is set, and then the average loss and junction temperature of each power device in the DC / AC converter topology are calculated according to the initial junction temperature T0. The junction temperature result of this round is taken as the junction temperature input for the next round of calculation. The average loss and junction temperature are iteratively calculated until the difference between the junction temperatures calculated in the first and second times is less than a set threshold. At this time, the loss and heat in the DC / AC converter reach a steady state, and the average loss and junction temperature obtained by the last calculation are the steady-state average loss and junction temperature.

[0104] As Figure 4 shown in the calculation flow chart, the loss calculation process of the power device chip is as follows: The loss of the IGBT device in the converter topology includes the loss of the IGBT chip and the loss of the antiparallel diode chip. Therefore, the total loss can be represented as:

[0105] P tot，IGBT = P tot(T) + P tot(D) #(12)

[0106] Where P tot(T) is the total loss of the IGBT chip, and P tot(D) is the total loss of the freewheeling diode chip. The total loss of the IGBT chip can be represented as:

[0107] P tot(T) = P cond(T) + P on + P off #(13)

[0108] Where P cond(T) is the forward conduction loss of the IGBT chip, P on and P off are the turn-on loss and turn-off loss of the IGBT chip, respectively. The specific expressions of these losses are as follows:

[0109]

[0110] Where T is the fundamental period, T s is the calculation step, and m = T / T s , T j(T) is the average junction temperature of the device chip, V ce (I, T) is the forward conduction I-V model of the IGBT, E on (I, U, T) and E off (I, U, T) are the turn-on loss and turn-off loss models, respectively.

[0111] The loss of the freewheeling diode chip of the IGBT device includes the conduction loss and the turn-off loss, and the total loss can be represented as:

[0112] P tot(D) =P cond(D) +P rr #(15)

[0113] Among them, P cond(D) For the conduction loss of the freewheeling diode chip, P rr The turn-off loss of the freewheeling diode chip is caused by the reverse recovery process on the freewheeling diode when the IGBT device is turned off. The specific expressions for these losses are as follows:

[0114]

[0115] Among them, T j(D) V represents the average junction temperature of the freewheeling diode chip. f (I, T) is the conduction IV model of the freewheeling diode, E rr (I, U, T) is the turn-off loss model for the freewheeling diode.

[0116] Similarly, the total loss of the diode devices in the converter topology can be expressed as:

[0117] P tot，Diode =P cond(D) +P rr #(17)

[0118] like Figure 4 The calculation process for the junction temperature of the power device chip in the calculation flow shown is as follows: Figure 5 The diagram shows a schematic of the thermal path model of the converter system, where R th(s-a) R is the average thermal resistance from the heat sink to the environment. th(c-s) R is the thermal resistance from the power device case to the heat sink. th(j-c) Let be the thermal resistance from the chip junction to the casing. Then, the junction temperature of the IGBT chip and its freewheeling diode chip in the converter topology can be expressed as:

[0119]

[0120] Among them, T a For ambient temperature, ΔT c-s，xk The thermal resistance R from the housing of the x-phase Qxk device to the heat sink. th(c-s) The temperature difference value, ΔT s-a The thermal resistance R from the heatsink to the environment th(s-a) The temperature difference value is expressed as follows:

[0121]

[0122] Similarly, the junction temperature of the diode chip in the converter topology can be expressed as:

[0123] T j，xk =P tot，Diode，xk ·R th(j-c) +P tot，xk ·R th(c-s) +ΔT s-a +T a #(20)

[0124] The implementation process of the algorithm proposed in this invention will be illustrated using a three-level NPC topology as an example:

[0125] First, the DC / AC converter topology is converted into a directed graph that is easy for the program to process. All current paths in the directed graph are analyzed and stored as a current path matrix. The three-level NPC topology and its corresponding directed graph are shown below. Figure 6 As shown, using Figure 2 The depth-first path search algorithm shown searches for the path between reference node 0 and output node 3 in the directed graph, obtaining the forward and reverse node paths of the three-level NPC topology, as shown in the following set:

[0126]

[0127] Based on the set of node paths, the set of directed edges traversed by each current path is obtained. The device parameter information and direction information corresponding to these directed edges are summarized into a current path matrix. Current paths that pass through the same device but have opposite directions are merged. Finally, the current path matrix of the three-level NPC topology is as follows:

[0128]

[0129] This current path matrix has four rows, representing four different current paths in a three-level NPC topology. Taking the first and second rows as examples, let's illustrate the meaning of the parameters in the matrix: the current path corresponding to the first row is a bidirectional conductive current path passing through devices Qx1 and Qx2, and its output voltage when conducting is V(C). d1 Furthermore, Qx1 and Qx2 are fully controllable devices, and their device reference direction is opposite to the output current reference direction. This means that when the first current path is active, the current polarity of Qx1 and Qx2 is opposite to the output current polarity. The current path corresponding to the second row is a reverse-conducting current path passing through Qx2 and Dx5, and its corresponding output voltage is 0 when it is active. Additionally, Qx2 is a fully controllable device, and Dx5 is a diode; both of these devices have reference directions opposite to the output current reference direction.

[0130] Next, the steady-state output voltage waveform of the topology is calculated based on the extracted current path matrix and the driving waveform under steady-state conditions, and the steady-state output current waveform is calculated based on the load impedance characteristics. According to equations (2), (3), and (4), the output voltage calculation expression for the three-level NPC topology can be obtained as follows:

[0131]

[0132] Substituting the steady-state DC voltage of the capacitors and the fundamental periodic drive waveform of the power devices into the above equation, the steady-state output voltage waveform of the three-level NPC topology can be obtained. Next, taking an RLC load as an example, the calculation process of the output current is explained. The three-level NPC topology is equivalent to a voltage source, resulting in the following... Figure 7 The linear circuit shown. Then, the frequency domain signal of the steady-state output current can be expressed as:

[0133]

[0134] Among them, U 3L-NPC，fd (nω0) is the amplitude at the angular frequency nω0 in the output voltage spectrum of the three-level NPC topology, which can be obtained by transforming the time-domain output voltage waveform of the three-level NPC topology using the FFT algorithm according to equation (23). 3L-NPC，fd (nω0) is the amplitude of the output current in the frequency domain at the angular frequency nω0 of the three-level NPC topology. The steady-state output current time-domain waveform I can then be calculated using the iFFT algorithm. 3L-NPC .

[0135] Then, the voltage and current waveforms on each power device in the topology are calculated based on the calculated steady-state output current waveform. The calculation expressions for the current waveforms on each power device can be obtained from equations (6), (7), and (8), where the calculation expressions for the current waveforms of Qx1, Qx2, and Dx5 are as follows:

[0136]

[0137] The expressions for the current waveforms of the other three power devices are similar, and will not be repeated here.

[0138] The voltage waveform of a power device is obtained by subtracting the voltage waveforms at its two endpoints. The calculation expressions for the voltage waveforms of Qx1, Qx2, and Dx5 are as follows:

[0139]

[0140] Among them, U n1 The voltage waveform at node 1, U n2 This is the voltage waveform at node 2. (U...) n2Taking the calculation of node voltage waveform as an example, the calculation process is as follows: According to the set of forward and reverse node paths shown in (21), find all the node paths that pass through node 2. The set is as follows:

[0141]

[0142] Based on (26), the set of directed edges traversed by the current path between node 2 and the reference ground node, and the set of directed edges traversed by the current path between node 2 and the output node are extracted respectively. The corresponding current path matrices are as follows:

[0143]

[0144] Based on (9) and (27), the calculation expression for the voltage waveform at node 2 can be obtained as follows:

[0145]

[0146] Similarly, the calculation expression for the voltage waveform at node 1 can be obtained as follows:

[0147] U n1 =V(C d1 )#(29)

[0148] Finally, combining the loss model of the power devices and the system thermal circuit model, the average loss and junction temperature of the power devices under steady-state conditions are calculated. The loss expression of the IGBT device in the converter topology can be obtained from the above equations (12)-(16), and the calculation formula of its chip junction temperature can be obtained from the above equations (18) and (19). The loss expression of the diode is shown in the above equation (17), and the calculation formula of its chip junction temperature is shown in the above equation (20). Figure 5 The flowchart shown is for calculating the loss and junction temperature under steady-state conditions. The final steady-state loss and junction temperature are obtained through iteration. During the calculation process, the loss and junction temperature parameters are continuously calculated and updated based on the loss model of the power device and the thermal circuit model of the system until the difference between two iterations is less than the set threshold. At this point, the system can be considered to have reached steady state. The loss and junction temperature obtained in the last iteration are the steady-state solutions obtained by substitution.

[0149] The above description is merely one embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope disclosed in the present invention, based on the technical solution and concept of the present invention, shall fall within the scope of protection of the present invention.

Claims

1. A method for calculating loss and junction temperature of a DC / AC converter based on current path analysis, characterized by, Comprising the following steps: (1) analyzing all working modes of the DC / AC converter topology, collecting power device and capacitor element information of each working mode, and obtaining a current path matrix CP; The specific steps include: According to the conversion relationship between the power device and the capacitor element and the directed graph, the DC / AC converter topology is converted into a directed graph; With the aid of a graph theory path search algorithm, all node paths between the reference ground node and the output node in the directed graph are searched; According to the node path, the power device and capacitor element information of each current path is obtained, and the current path matrix CP is obtained by summarizing; the matrix format of the current path matrix CP is shown in formula (1): ， Current path matrix By , and three sub-matrices, wherein, the sub-matrix represents the power device information through which each current path passes, the sub-matrix represents the output level value corresponding to each current path, the sub-matrix represents the conductive direction of each current path, and r in the matrix subscript is the number of current paths between the reference ground node and the output node of the topology, and t is the number of power devices of the topology. (2) According to the current path matrix CP, the voltage and current waveforms of each power device in the DC / AC converter topology are calculated; the specific steps are as follows: According to the current path matrix CP, the output voltage of the DC / AC converter is calculated ; The DC / AC converter is equivalent to a voltage source, and the response current waveform of the load under this voltage excitation is solved by using a circuit analysis calculation method, that is, the output current of the DC / AC converter; According to the current path matrix CP, the voltage and current calculation expressions of the power device are derived, and the specific voltage and current waveforms of the power device are obtained by substituting the power device driving signal and the output voltage and output current of the DC / AC converter; (3) According to the calculated power device voltage and current waveforms, combined with the power device loss model and the system thermal circuit model, the steady-state average loss and the power device chip junction temperature of the DC / AC converter topology are calculated; The output voltage of the DC / AC converter The calculation formula is shown as formula (2): ， where s is the total number of voltage nodes in the DC / AC converter topology, V k is the voltage value of the kth voltage node, w k is the communication flag bit of the kth voltage node and the output node, and its calculation expression is shown in equation (3): ， wherein is the i-th element of the CD sub-matrix, indicating the conductive direction of the i-th current path; is the j-th element of the CD sub-matrix, indicating the conductive direction of the j-th current path; M k is the output voltage equal to V k is the set of row numbers of the current paths in which the output voltage is equal to V is the x-th element of the SV sub-matrix, indicating the voltage value of the output node when the x-th current path is turned on; e i is the switching state flag bit of the full-controlled device in the i-th current path, is the switching state flag bit of the full-controlled device in the j-th current path, and the calculation expression is shown in equation (4): ， wherein, is the i-th row j-th column element of the PD sub-matrix, indicating the information of the i-th current path passing through the j-th power device, is the driving signal of the j-th power device; The specific steps of the circuit analysis calculation method include: The DC / AC converter output voltage U xo The FFT algorithm is transformed into a frequency domain signal U xo,fd ; The frequency domain signal I of the DC / AC converter output current is calculated according to an expression as shown in formula (5) xo,fd where Z load is the complex frequency domain impedance of the load, is the fundamental angular frequency of the converter; ， The frequency domain signal I of the DC / AC converter output current xo,fd The response current waveform I of the load obtained by the iFFT algorithm xo .

2. The method of claim 1, wherein, The conversion relationship between the power device and the capacitor element and the directed graph is: For current bidirectional conduction devices, including IGBT, MOSFET and bus capacitor, it is converted into a directed graph defined by node set V={1,2} and directed edge set E={(1,2),(2,1)}, wherein 1 and 2 represent the node numbers of the two ends of the device, and (1,2) represents a directed edge from node 1 to node 2; for current unidirectional conduction devices, including diodes, it is converted into a directed graph defined by node set V={1,2} and directed edge set E={(1,2)}, wherein the direction of the directed edge is the same as the conduction current direction of the device.

3. The method of claim 1, wherein, The graph theory path search algorithm is: Starting from the starting node, each possible path is accessed in a depth-first strategy, and a stack is used to avoid repeated node access, and when the terminating node is accessed, the node path from the starting node to the terminating node is recorded, and the entire directed graph is traversed.

4. The method of claim 1, wherein, The current calculation expression of the power device is shown in formula (6): ， wherein, is the current waveform of the power device, sgn is a sign function, is the kth row and jth column element of the PD sub-matrix, representing the information of the kth current path passing through the jth power device, I k is the current of the kth current path, h k is the direction flag bit of the kth current path, whose expression is shown in equation (7), is the direction flag bit of the jth current path, e k is the turn-on flag bit of the full-controlled device in the kth current path; ， wherein is the kth element of the CD sub-matrix, indicating the conductive direction of the kth current path; The voltage waveform of the power device is obtained by subtracting the voltage waveforms of its two end nodes, and for the ni node in the topology, the calculation expression of its voltage is shown in formula (8): ， wherein, U ni (i) is iT s the voltage value of node n ni (i-1) is (i-1)T s the voltage value of node n xo (i) is iT s the output voltage value of DC / AC converter at time iT, CP L is the current path matrix between node n ref and n R is the current path matrix between node n out and n L and s R are respectively the CP L and CP R the number of voltage nodes in the corresponding current path model, V k,L and V k,R are respectively the voltage value corresponding to the kth voltage node in the respective current path model, p k,L and p k,R are respectively the connection flag bit of the kth voltage node in the respective current path model and node n , whose expression is shown in equation (9): ， wherein e i is the on-off state flag of the full-controlled device in the i-th current path; d i is the on-off state flag of the diode in the i-th current path; is the i-th row and j-th column element of the current path matrix CP L , indicating the information that the i-th current path between node n ref and n is passing through the j-th power device, R is the i-th row and j-th column element of the current path matrix CP out , indicating the information that the i-th current path between node n Dxj and n is passing through the j-th power device; I Dxj is the current of the j-th power device.

5. The method of claim 1, wherein, The specific steps of calculating the steady-state average loss and junction temperature of each power device in the DC / AC converter topology include: Using the power device loss model and the system thermal circuit model, the average loss and the junction temperature of each power device in the DC / AC converter topology are calculated according to the initial junction temperature parameters, and the junction temperature result of this round is taken as the junction temperature input of the next round of calculation. The average loss and the junction temperature are iteratively calculated until the difference between the junction temperatures calculated in the first and the second time is less than the set threshold. At this time, the loss and the heat in the DC / AC converter reach the steady state, and the average loss and the junction temperature obtained by the last calculation are the steady state average loss and the steady state junction temperature.

6. The method of claim 5, wherein, The power device loss model varies depending on the device type, and the loss model of an IGBT device As shown in equation (10), the loss model of a diode As shown in equation (11): ， ， wherein, Etotal is the total loss of the IGBT chip, including turn-on loss Eon, turn-off loss Eoff, and turn-off loss Eoff, the specific calculation expression is shown in equation (12), Etotal is the total loss of the diode or the freewheeling diode of the IGBT device, including turn-on loss Eon, and reverse recovery loss Eoff, the specific calculation expression is shown in equation (13): ， ， where T is the fundamental period, T s is the calculation step, is the array length of the waveform sequence, satisfying , is the average junction temperature of the device chip, is the forward conduction I-V model of the IGBT, and are the turn-on loss and turn-off loss models of the IGBT, respectively; is the average junction temperature of the freewheeling diode chip, is the conduction I-V model of the freewheeling diode, is the turn-off loss model of the freewheeling diode; is the current flowing through the IGBT at time t, is the current flowing through the IGBT at time t, is the voltage of the IGBT at time t, is the voltage of the IGBT at time t; The system thermal circuit model is composed of heat sources and thermal resistances, the total number of the heat sources is the same as the total number of power device chips in the DC / AC converter topology, the thermal resistances are composed of thermal resistances from the heat sink to the environment , thermal resistances from the power device housing to the heat sink , and thermal resistances from the power device chip junction to the housing ; according to the system thermal circuit model, the junction temperature calculation expression of the IGBT chip and its freewheeling diode chip is shown as formula (14), and the junction temperature calculation expression of the diode device chip is shown as formula (15): ， ， wherein, Tjk is the junction temperature of the kth IGBT chip in phase x, Pjk is the loss of the kth IGBT chip in phase x, Tjrk is the junction temperature of the kth freewheeling diode chip of the IGBT in phase x, Pjrk is the loss of the kth freewheeling diode chip of the IGBT in phase x, Tjk is the junction temperature of the kth diode chip in phase x, Pjk is the loss of the kth diode chip in phase x; Tamb is the ambient temperature, Tjk is the junction temperature of the kth IGBT chip in phase x, Tjk is the junction temperature of the kth IGBT chip in phase x, Tjk is the junction temperature of the kth IGBT chip in phase x, Tjk is the junction temperature of the kth IGBT chip in phase x, ， wherein, Ptotal k is the total loss of the kth IGBT device in phase x, Ptotal k is the total loss of the kth diode in phase x, for a three-phase system, Ptotal k represents the total power dissipation of one phase of the three phases, t is the total number of power devices in the topology of any one phase of the three-phase system.

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