A signal processing circuit and method

Abstract

The present disclosure provides a signal processing circuit and method, which can be applied to the field of microelectronic device technology. The method comprises: a first transistor, a source of the first transistor being used for connecting a first signal input end, a gate of the first transistor being used for connecting a second signal input end; a second transistor, a drain of the second transistor being used for connecting a drain of the first transistor and a signal output end, a gate of the second transistor being used for connecting the second signal input end; a third transistor, a drain of the third transistor being used for connecting a source of the second transistor, a source of the third transistor being used for grounding; and a fourth transistor, a source of the fourth transistor being used for connecting a gate of the third transistor, a drain of the fourth transistor being used for connecting a third signal input end.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of microelectronic devices, and in particular, to a signal processing circuit and method. BACKGROUND

[0002] In the related art, deep neural networks (DNN) have shown development potential in various fields. However, the DNN algorithm is always accompanied by a large number of multiply-accumulate (MAC) and memory access operations. Based on this, there is a problem of high energy consumption of the circuit deploying the DNN algorithm. SUMMARY

[0003] In view of the above problems, the present disclosure provides a signal processing circuit and method.

[0004] According to a first aspect of the present disclosure, a signal processing device is provided, comprising: a first transistor, a source of the first transistor being configured to be connected to a first signal input end, a gate of the first transistor being configured to be connected to a second signal input end; a second transistor, a drain of the second transistor being configured to be connected to a drain of the first transistor and a signal output end, a gate of the second transistor being configured to be connected to the second signal input end; a third transistor, a drain of the third transistor being configured to be connected to a source of the second transistor, a source of the third transistor being configured to be grounded; a fourth transistor, a source of the fourth transistor being configured to be connected to a gate of the third transistor, a drain of the fourth transistor being configured to be connected to a third signal input end; wherein the first signal input end is configured to receive a power supply signal, the second signal input end is configured to receive a transmission signal, the third signal input end is configured to receive a voltage reduction duration signal, the voltage reduction duration signal is configured to determine a duration of voltage reduction of the signal output end, and the signal output end is configured to output a new transmission signal corresponding to the power supply signal, the transmission signal and the voltage reduction duration signal.

[0005] According to an embodiment of the present disclosure, a gate of the fourth transistor is configured to be connected to a fourth signal input end; wherein the third signal input end is configured to transmit the voltage reduction duration signal to the fourth transistor, the fourth signal input end is configured to receive a transistor control signal, the transistor control signal is configured to control a conduction state of the fourth transistor, and the fourth transistor is configured to transmit the voltage reduction duration signal to the third transistor in the conduction state.

[0006] According to an embodiment of the present disclosure, the fourth transistor is further configured to cache a level holding signal for a cache duration, so that, in a case where the fourth transistor is in an off state, the signal output end outputs the new transmission signal within the cache duration by the third transistor through the cached voltage reduction duration signal.

[0007] According to an embodiment of the present disclosure, the third transistor and the fourth transistor are both made of indium gallium zinc oxide.

[0008] According to an embodiment of the present disclosure, the signal processing circuit is N in number, a signal output end of an n-1th signal processing circuit in the N signal processing circuits is connected to a second signal input end of an nth signal processing circuit, n is a positive integer less than or equal to N and greater than 1, and N is a positive integer.

[0009] According to an embodiment of the present disclosure, the first transistor is a P-type doped field effect transistor, and the second transistor is an N-type doped field effect transistor.

[0010] The second aspect of the present disclosure provides a signal processing method using the above signal processing circuit, comprising: in the case that the transmission signal is at a low level, turning on the first transistor and turning off the second transistor to transmit a power signal to the signal output end through the first transistor; in the case that the transmission signal is converted from the low level to a high level, turning off the first transistor and turning on the second transistor to make the third transistor receive a voltage from the signal output end through the second transistor; using the third transistor to continuously reduce the voltage of the signal output end for a voltage reduction duration corresponding to the voltage reduction duration signal, so that the signal output end outputs a new transmission signal.

[0011] According to an embodiment of the present disclosure, the signal processing method further comprises: using the fourth transistor to buffer the voltage reduction duration signal from the third signal input end and transmit the buffered voltage reduction duration signal to the gate of the third transistor.

[0012] According to an embodiment of the present disclosure, the signal processing method further comprises: in the case that the transistor control signal is at a high level, turning on the fourth transistor to transmit the voltage reduction duration signal to the third transistor through the fourth transistor.

[0013] According to an embodiment of the present disclosure, the signal processing method further comprises: in the case that the transistor control signal is at a low level, turning off the fourth transistor to stop receiving the voltage reduction duration signal from the third signal input end.

[0014] According to the information processing device and method provided by the present disclosure, the duration of the voltage reduction of the signal output end is controlled by only using the third transistor and the fourth transistor, so that the transmission signal can be delayed by a small number of devices. Based on this, the signal processing circuit of the present disclosure is used for multiplication and accumulation, which can reduce the power consumption and circuit area of the circuit. BRIEF DESCRIPTION OF DRAWINGS

[0015] The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments of the present disclosure taken in conjunction with the accompanying drawings, in which:

[0016] Figure 1 A schematic diagram of a signal processing circuit according to an embodiment of the present disclosure is shown schematically;

[0017] Figure 2 A schematic diagram of a signal processing circuit according to another embodiment of the present disclosure is shown schematically;

[0018] Figure 3 A timing diagram of a transmission signal, a voltage reduction duration signal, and a transistor control signal according to an embodiment of the present disclosure is shown schematically;

[0019] Figure 4 A simulation result diagram of a signal processing circuit according to an embodiment of the present disclosure is shown schematically;

[0020] Figure 5 A schematic diagram of a cascaded signal processing circuit according to an embodiment of the present disclosure is shown schematically;

[0021] Figure 6a A top view of a cascaded signal processing circuit according to an embodiment of the present disclosure is shown schematically;

[0022] Figure 6b A side view of a cascaded signal processing circuit according to an embodiment of the present disclosure is shown schematically;

[0023] Figure 7 A flowchart of a signal processing method according to an embodiment of the present disclosure is shown schematically. DETAILED DESCRIPTION

[0024] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It is to be understood, however, that the description is merely exemplary and is intended to provide a thorough understanding of the embodiments of the present disclosure. The following detailed description and specific examples are presented to provide a thorough understanding of the embodiments of the present disclosure. It will be apparent, however, that the embodiments of the present disclosure can be practiced without these specific details. In addition, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present disclosure.

[0025] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the present disclosure. As used herein, the term "includes" and "comprises" and the like means the inclusion or presence of the stated features, steps, operations, and / or components, but not the exclusion or absence of one or more other features, steps, operations, or components.

[0026] All terms used herein, including technical and scientific terms, have the meanings commonly understood by one of ordinary skill in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning that is consistent with the context of the specification, and should not be interpreted in an idealized or overly formal manner.

[0027] In the case of using expressions such as "at least one of A, B, and C, etc.", it is generally intended to mean any of the following: "A", "B", "C", "at least one of A and B", "at least one of A and C", "at least one of B and C", "at least one of A, B, and C", "at least one of A, B, and C, etc.", and "A, B, and C, etc.".

[0028] In the technical solutions of the present application, the user information (including but not limited to user personal information, user image information, user equipment information, such as location information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved are all information and data authorized by the user or authorized by all parties, and the collection, storage, use, processing, transmission, provision, disclosure and application of related data comply with relevant laws, regulations and standards of relevant countries and regions, necessary security measures are taken, public order and good customs are not violated, and corresponding operation entrances are provided for users to choose authorization or refusal.

[0029] In the related art, the combination of analog computation and in-memory computation is considered an effective way to reduce the energy consumption of MAC and memory access operations. Among them, TD (Time Domain) computation is compatible with digital circuits, and due to its analog nature, it has low power consumption advantage in low precision computation.

[0030] In TD computation, the multiplication result is usually converted into an analog delay value at each stage, which is controlled by input activation and local weight. Although the delay value varies due to transistor mismatch, TD computation has the advantages of low signal-to-noise ratio, high efficiency, and more energy saving than digital circuits because it uses a more flexible way to handle transistors. On the other hand, voltage or current domain computation requires the design of an ADC (Analog to Digital Converter) to convert the analog MAC output back to the digital domain. Standard digital library units such as DFF (Data Flip Flop) can be used to convert the MAC output from the time domain to the digital domain, which will shorten the design time.

[0031] In the related art, only SRAM (Static Random Access Memory) is used to implement time-domain delay computation. However, additional current starvation circuits or variable capacitance blocks are needed in TD-SRAM units to implement MAC multiplication, so the area is large and the energy consumption is high.

[0032] In view of this, the embodiment of the present disclosure provides a signal processing circuit which can delay the time domain of a signal, comprising: a first transistor, a source of the first transistor is connected to a first signal input end, and a gate of the first transistor is connected to a second signal input end. A second transistor, a drain of the second transistor is connected to a drain of the first transistor and a signal output end, and a gate of the second transistor is connected to the second signal input end. A third transistor, a drain of the third transistor is connected to a source of the second transistor, and a source of the third transistor is grounded. A fourth transistor, a source of the fourth transistor is connected to a gate of the third transistor, and a drain of the fourth transistor is connected to a third signal input end. Wherein, the first signal input end is used to receive a power signal, the second signal input end is used to receive a transmission signal, and the third signal input end is used to receive a voltage reduction duration signal, the voltage reduction duration signal is used to determine the duration of the voltage reduction of the signal output end, and the signal output end is used to output a new transmission signal corresponding to the power signal, the transmission signal and the voltage reduction duration signal.

[0033] Figure 1 A schematic diagram of a signal processing circuit according to an embodiment of the present disclosure is shown schematically.

[0034] As Figure 1 shown, the signal processing circuit of the embodiment comprises: a first transistor 101, a source of the first transistor 101 is connected to a first signal input end 102, and a gate of the first transistor 101 is connected to a second signal input end 103. A second transistor 104, a drain of the second transistor 104 is connected to a drain of the first transistor 101 and a signal output end 105, and a gate of the second transistor 104 is connected to the second signal input end 103. A third transistor 106, a drain of the third transistor 106 is connected to a source of the second transistor 104, and a source of the third transistor 106 is grounded 108. A fourth transistor 109, a source of the fourth transistor 109 is connected to a gate of the third transistor 106, and a drain of the fourth transistor is connected to a third signal input end 107. Wherein, the first signal input end 102 is used to receive a power signal, the second signal input end 103 is used to receive a transmission signal, and the third signal input end 107 is used to receive a voltage reduction duration signal, the voltage reduction duration signal is used to determine the duration of the voltage reduction of the signal output end 105, and the signal output end 105 is used to output a new transmission signal corresponding to the power signal, the transmission signal and the voltage reduction duration signal.

[0035] According to an embodiment of the present disclosure, the first transistor 101 is a P-type doped field effect transistor. The second transistor 104 is an N-type doped field effect transistor, and the third transistor 106 and the fourth transistor 109 can each be an IGZO TFT (Indium Gallium Zinc Oxide Thin Film Transistor).

[0036] According to an embodiment of the present disclosure, the first transistor 101 and the second transistor 104 can constitute an inverter circuit. The inverter circuit can be used to output a new transmission signal opposite to a transmission signal level. For example, in a case where the transmission signal is a high level, the first transistor 101 can be in an off state, and the second transistor 104 can be in an on state. Thus, the power signal of the first signal input end 102 is difficult to be transmitted to the signal output end 105, and the signal output end 105 outputs a low level transmission signal.

[0037] In a case where the transmission signal is a low level, the first transistor 101 can be in an on state, and the second transistor 104 can be in an off state. Thus, the power signal of the first signal input end 102 is transmitted to the signal output end 105, and the signal output end 105 outputs a high level transmission signal.

[0038] According to an embodiment of the present disclosure, the power signal can be a high level signal.

[0039] According to an embodiment of the present disclosure, the transmission signal can be a signal for transmitting information by high and low levels. For example, in a case where the transmission signal is a high level, the information transmitted by the transmission signal can be “1”; in a case where the transmission signal is a low level, the information transmitted by the transmission signal can be “0”.

[0040] According to an embodiment of the present disclosure, the third transistor 106 is used to control the speed of voltage drop of the signal output end 105 according to the voltage drop duration corresponding to the voltage drop duration signal. For example, the third transistor 106 can be used to delay the time when the voltage of the signal output end 105 is converted from a high level to a low level according to the voltage drop duration corresponding to the voltage drop duration signal.

[0041] For example, in a case where the voltage drop duration signal lasts for 10 seconds, the channel conductance of the third transistor 106 is adjusted by the voltage duration drop signal 107, so that the third transistor 106 provides different sizes of pull-down driving for the inverter composed of the first transistor 101 and the second transistor 104. Further, the time when the voltage of the signal output end 105 is converted from a high level to a low level can be delayed for 10 seconds.

[0042] Based on this, in the case that the transmission signal is converted from high level to low level, the new transmission signal output by the signal output terminal 105 will be delayed to convert from low level to high level due to the influence of the third transistor 106.

[0043] According to the embodiments of the present disclosure, by using only the third transistor 106 and the fourth transistor 109 to control the duration of voltage reduction of the signal output terminal 105, the transmission signal can be delayed by a small number of devices. Based on this, the signal processing circuit of the present disclosure is used for multiplication and accumulation, which can reduce the power consumption and circuit area of the circuit.

[0044] According to the embodiments of the present disclosure, the voltage value of the voltage reduction duration signal can be negatively related to the voltage reduction duration. For example, the greater the voltage value of the voltage reduction duration signal, the stronger the conduction ability of the third transistor, and the shorter the voltage reduction duration; the smaller the voltage value of the voltage reduction duration signal, the weaker the conduction ability of the third transistor, and the longer the voltage reduction duration.

[0045] According to the embodiments of the present disclosure, the gate of the fourth transistor 109 is used to connect the fourth signal input terminal 110. Among them, the third signal input terminal 107 is used to transmit the voltage reduction duration signal to the fourth transistor 109, the fourth signal input terminal 110 is used to receive the transistor control signal, the transistor control signal is used to control the conduction state of the fourth transistor 109, and the fourth transistor 109 is used to transmit the voltage reduction duration signal to the third transistor 106 in the conduction state.

[0046] According to the embodiments of the present disclosure, by using the transistor control signal to control the conduction state of the fourth transistor 109, the duration of outputting the voltage reduction duration signal to the third transistor 106 can be flexibly controlled by controlling the conduction state of the fourth transistor 109, thereby improving the flexibility of signal delay.

[0047] According to the embodiments of the present disclosure, the fourth transistor is also used to cache the level maintaining signal within the cache duration, so that in the case that the fourth transistor is in the off state, the signal output terminal outputs the new transmission signal within the cache duration by the third transistor through the cached voltage reduction duration signal.

[0048] According to the embodiments of the present disclosure, the materials of the third transistor and the fourth transistor both include indium gallium zinc oxide.

[0049] According to the embodiments of the present disclosure, since the fourth transistor is an IGZO transistor with low leakage characteristics in the off state, the fourth transistor can cache the voltage at the gate of the third transistor.

[0050] According to an embodiment of the present disclosure, the cache duration can be a duration for which the fourth transistor caches the voltage reduction duration signal. The cache duration can be determined by the property of the fourth transistor itself.

[0051] According to an embodiment of the present disclosure, the voltage reduction duration can be determined by the cache duration, the on duration of the fourth transistor, and the size of the voltage reduction duration signal.

[0052] According to an embodiment of the present disclosure, by caching the voltage reduction duration signal by the fourth transistor, even if the fourth transistor is turned off, the level of the signal output end can be maintained by the third transistor, so that the signal output end outputs the new transmission signal. Therefore, the consumption of the electrical energy used to maintain the fourth transistor on can be reduced, and the power consumption of the signal processing circuit can be further reduced.

[0053] Figure 2 An exemplary schematic diagram of a signal processing circuit according to another embodiment of the present disclosure is shown.

[0054] Figure 3 An exemplary timing diagram of a transmission signal, a voltage reduction duration signal, and a transistor control signal according to an embodiment of the present disclosure is shown.

[0055] Figure 4 An exemplary simulation result diagram of a signal processing circuit according to an embodiment of the present disclosure is shown.

[0056] As shown in FIG. 1, Figures 2 to 4 Figure 2 In FIG. 1, P1 can represent the first transistor, N1 can represent the second transistor, T1 can represent the fourth transistor, and T2 can represent the third transistor.

[0057] The gate of T1 can be used to connect a word line (WL), and the other end of the word line can be connected to the fourth signal input end. The drain of T1 is connected to a bit line (BL), and the other end of the bit line can be connected to the third signal input end. The source of T1 is connected to the gate of T2, and the connection point is a storage node (SN), which can correspond to the gate of the third transistor.

[0058] By applying a transistor control signal (VWL), the on and off of T1 can be controlled. For example, when VWL=‘1’, T1 is turned on, the bit line signal is transmitted to the storage node SN, and after the transmission of the bit line signal is completed, VWL=‘0’ is set, and T1 is turned off. The bit line data can include the voltage reduction duration signal. In the case where the size of the voltage (VBL) of the bit line signal is different, the potential of the SN node is different, and the channel conductance of T2 is regulated by the potential of the SN node, so that T2 provides different voltage sizes of pull-down driving for the inverter circuit composed of P1 and N1, that is, the inverter circuit presents different output flip-flop delays under different VBL.​

[0059] Based on this, since the IGZO transistor has the low leakage current in the off state, even if T1 is turned off, the drain of T1 can maintain the output of the voltage drop signal of the cached time length. Further, a delay unit can be formed by T1 and T2. Based on this, by connecting the drain of T1 to the gate of T2, the gate capacitance provides a capacitive load for T1, so that the SN node behaves as a voltage that can maintain the cached time length. Based on this, since this voltage is input as the gate of T2, the channel conductance of T2 can be regulated. Further, in the case of regulating the channel conductance of T2 by the size of the SN node voltage, the SN node voltage only needs to be in a small voltage range, which can include 0-0.8V, to regulate the conductance of the T2 transistor.

[0060] Figure 4 In this way, as the VBL voltage changes, the conductance value of the T2 transistor can be changed, so that the T2 transistor provides different sizes of pull-down drive for the inverter circuit, and different sizes of delay are presented. In addition, since the IGZO transistor has the low leakage current in the off state, the voltage drop signal of the SN end can be cached for a time length, which can include 10s-1000s. In the case where the time length of the cached voltage drop signal is greater than the cache time length, the SN end voltage will be reduced. Therefore, to maintain high-precision time-domain delay, dynamic refreshing is required. The operation of this dynamic refreshing can include repeatedly controlling the turn-on and turn-off of the fourth transistor.

[0061] According to an embodiment of the present disclosure, the signal processing circuit is N, and the signal output end of the n-1th signal processing circuit in the N signal processing circuits is used to connect the second signal input end of the nth signal processing circuit, n is a positive integer less than or equal to N and greater than 1, and N is a positive integer.

[0062] According to an embodiment of the present disclosure, the signal processing circuit is formed by using only a small number of transistors, and the signal processing circuits are cascaded through the second signal input end and the signal output end, so that the transmission signal can be delayed step by step.

[0063] Figure 5 The schematic diagram of the cascaded signal processing circuit according to an embodiment of the present disclosure is schematically shown.

[0064] As Figure 5As shown, by cascading N IGZO-based signal processing circuits, MAC (Multiply Accumulate) can be achieved. The first signal processing circuit 501, the second signal processing circuit 502, the third signal processing circuit 503, and the fourth signal processing circuit 504 can be included. In can represent the transmission signal input to the first signal processing circuit 501. out1 can represent the transmission signal transmitted by the first signal processing circuit 501 to the second signal processing circuit 502. out2 can represent the transmission signal transmitted by the second signal processing circuit 502 to the third signal processing circuit 503. out3 can represent the transmission signal transmitted by the third signal processing circuit 503 to the fourth signal processing circuit 504. out4 can represent the transmission signal output by the fourth signal processing circuit 504.

[0065] Taking the cascade of four signal processing circuits as an example, MAC = t1x1 + t2x2 + t3x3 + t4x4, where t1 can represent the voltage reduction duration of the first signal processing circuit, t2 can represent the voltage reduction duration of the second signal processing circuit, t3 can represent the voltage reduction duration of the third signal processing circuit, and t4 can represent the voltage reduction duration of the fourth signal processing circuit. t1, t2, t3, and t4 can correspond to the weights described above. x1 can represent the voltage value of the voltage reduction duration signal of the first signal processing circuit. x2 can represent the voltage value of the voltage reduction duration signal of the second signal processing circuit. x3 can represent the voltage value of the voltage reduction duration signal of the third signal processing circuit. x4 can represent the voltage value of the voltage reduction duration signal of the fourth signal processing circuit. Therefore, the delay unit composed of IGZO can achieve MAC operation, while having the characteristics of low power consumption and small area.

[0066] Figure 6a A top view of a cascaded signal processing circuit according to an embodiment of the present disclosure is schematically shown.

[0067] Figure 6b A side view of a cascaded signal processing circuit according to an embodiment of the present disclosure is schematically shown.

[0068] As Figure 6a and Figure 6bAs shown, the three signal processing circuits can be stacked in three dimensions or arranged in two dimensions. Since each signal processing circuit only uses the third transistor and the fourth transistor for time delay, the stacked N signal processing circuits or the arranged N signal processing circuits have the advantages of low power consumption and small area. GND can represent ground. D can represent a signal output end. SN0, SN1 and SN2 can represent the storage nodes of the three signal processing circuits, i.e., the gates of the third transistors of the signal processing circuits, respectively. Layer0, Layer1 and Layer2 can represent the three signal processing circuits, respectively. IGZO can represent the third transistors and the fourth transistors of the three signal processing circuits, respectively. VWL1, VWL2 and VWL3 can represent the word lines of the three signal processing circuits, respectively. VBL1, VBL2 and VBL3 can represent the bit lines of the three signal processing circuits, respectively.

[0069] According to embodiments of the present disclosure, unlike silicon processes, IGZO transistors belong to a back-end low-temperature preparation process, so that the IGZO material transistors can be prepared at a relatively low temperature. Based on this, BEOL process compatibility can be achieved, making it possible to stack signal processing circuits, thereby reducing the area and improving the integration of stacked circuits.

[0070] According to embodiments of the present disclosure, compared with the MAC operation based on non-volatile voltage domain analog such as SRAM, the signal processing circuit based on IGZO transistors can overcome the dependence on high-voltage power signals in the voltage domain and reduce power consumption.

[0071] According to embodiments of the present disclosure, the delay unit implemented based on SRAM requires an additional variable capacitance module, and when implementing MAC operation, there are problems of large area and high power consumption. The signal processing circuit based on IGZO transistors is composed of only the first transistor, the second transistor, the third transistor and the fourth transistor, reducing the area overhead.

[0072] According to embodiments of the present disclosure, using the off-state low leakage characteristic of the IGZO transistor, two IGZO transistors (2T) and an inverter circuit are connected in series to form the signal processing circuit of the present disclosure, and the conductance of the IGZO transistor is modulated by the voltage change of the storage node, so that the inverter circuit realizes time-domain delay of different sizes. Using the gradual conductance characteristic varying with time, the multi-stage inverter cascade can realize MAC operation.

[0073] Figure 7 A flowchart of a signal processing method according to embodiments of the present disclosure is schematically shown.

[0074] In operation S710, in a case where the transmission signal is at a low level, the first transistor is turned on and the second transistor is turned off, so as to transmit the power signal to the signal output terminal by using the first transistor.

[0075] In operation S720, in a case where the transmission signal is converted from a low level to a high level, the first transistor is turned off and the second transistor is turned on, so as to make the third transistor receive the voltage from the signal output terminal by the second transistor.

[0076] In operation S730, the voltage of the signal output terminal is continuously reduced for a voltage reduction duration corresponding to the voltage reduction duration signal by using the third transistor, so as to make the signal output terminal output a new transmission signal.

[0077] According to an embodiment of the present disclosure, by using only the third transistor and the fourth transistor to control the duration of the voltage reduction of the signal output terminal, the transmission signal can be delayed by a small number of devices. Based on this, the signal processing circuit of the present disclosure is used for multiplication and accumulation, which can reduce the power consumption and circuit area of the circuit.

[0078] According to an embodiment of the present disclosure, the above-mentioned signal processing method further comprises: using the fourth transistor to buffer the voltage reduction duration signal from the third signal input terminal and transmit the buffered voltage reduction duration signal to the gate of the third transistor.

[0079] According to an embodiment of the present disclosure, the voltage reduction duration signal can be transmitted to the gate of the third transistor flexibly by controlling the turn-on and turn-off of the fourth transistor, which improves the flexibility of transmitting the voltage reduction duration signal. Moreover, by buffering the voltage reduction duration signal by the fourth transistor, the buffered voltage reduction duration signal can be transmitted to the gate of the third transistor in a case where the fourth transistor is turned off, which can reduce power consumption.

[0080] According to an embodiment of the present disclosure, the above-mentioned signal processing method further comprises: in a case where the transistor control signal is at a high level, turning on the fourth transistor to transmit the voltage reduction duration signal to the third transistor by using the fourth transistor.

[0081] According to an embodiment of the present disclosure, the voltage reduction duration signal can be transmitted to the third transistor by turning on the fourth transistor, which can realize the delay processing of the transmission signal.

[0082] According to an embodiment of the present disclosure, the above-mentioned signal processing method further comprises: in a case where the transistor control signal is at a low level, turning off the fourth transistor to stop receiving the voltage reduction duration signal from the third signal input terminal.

[0083] According to the embodiment of the present disclosure, since the fourth transistor can buffer the voltage drop duration signal, by turning off the fourth transistor when the transistor control signal is low, the circuit power consumption can be reduced without affecting the output of the new transmission signal at the signal output terminal.

[0084] Thus far, the embodiments of the present disclosure have been described in detail with reference to the accompanying drawings. It should be noted that the implementation not shown or described in the drawings or the main text is in the form known to those skilled in the art, and is not described in detail. In addition, the definitions of the elements and methods described above are not limited to the various specific structures, shapes or manners mentioned in the embodiments, and can be simply changed or replaced by those skilled in the art.

[0085] It should also be noted that the directional terms mentioned in the embodiments, such as "up", "down", "front", "back", "left", "right", etc., are only with reference to the direction of the drawings, and are not intended to limit the scope of the present disclosure. Throughout the drawings, the same elements are represented by the same or similar reference numerals. When the conventional structure or configuration may cause confusion in understanding the present disclosure, it will be omitted.

[0086] In addition, the shape and size of each component in the drawings do not reflect the actual size and ratio, but only illustrate the content of the embodiments of the present disclosure. In addition, in the claims, any reference symbol located between parentheses should not be construed as a limitation on the claims.

[0087] Unless otherwise known as the opposite meaning, the numerical parameters in the specification and the appended claims are approximate values, which can be changed according to the desired characteristics obtained by the content of the present disclosure. Specifically, all numbers used in the specification and claims to express the content of the composition, reaction conditions, etc. should be understood as being modified by the term "about" in all cases. Generally, it means that it includes a change of ±10% in some embodiments, ±5% in some embodiments, ±1% in some embodiments, ±0.5% in some embodiments from the specified amount.

[0088] Furthermore, the word "comprise" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of more than one such element.

[0089] The ordinal numbers used in the specification and claims, such as "first", "second", "third", etc., are used to modify the corresponding elements and do not mean that the elements have any ordinal number, nor represent the order or sequence of the elements or the order of the manufacturing method. The ordinal numbers are used only to clearly distinguish a element having a certain name from another element having the same name.

[0090] Further, unless specifically stated or otherwise will be apparent to one skilled in the art, the described features or steps of described operations can be performed in any order and are not limited to the described or the order they are described.

[0091] It should be noted that the operations of the flowcharts disclosed in the embodiments of the present disclosure are not necessarily in the order as shown, and the operations of the flowcharts can be executed in different orders, or can be executed simultaneously.

[0092] The algorithms and displays presented herein are not inherently related to any particular computer, virtual system, or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct more specialized apparatus to perform the required method steps. The required structure for a variety of these systems will be apparent from the description above. In addition, the present disclosure is not necessarily limited to any particular programming language, and various languages can be used to implement the teachings of the disclosure. It will be appreciated that a variety of programming aspects could be employed to implement the disclosure in this manner.

[0093] The present disclosure can be implemented with the aid of hardware including a number of different elements, and with the aid of suitably programmed computers. The various components of the present disclosure can be implemented in hardware, or as software modules running in one or more processors, or combinations thereof. Those skilled in the art will appreciate that a microprocessor or digital signal processor (DSP) can be used in practice to implement some or all of the functions of some or all of the components in the relevant devices according to the embodiments of the present disclosure. The present disclosure can also be implemented as a device or apparatus program (for example, a computer program and a computer program product) for performing part or all of the methods described herein. Such a program implementing the present disclosure can be stored on a computer readable medium, or can be in the form of one or more signals. Such signals can be downloaded from an Internet website, or provided on a carrier signal, or in any other form.

[0094] All the modules of the embodiments of the present disclosure can be hardware structures, and the physical implementation of the hardware structures includes but is not limited to physical devices, and the physical devices include but are not limited to transistors, memristors.

[0095] Those skilled in the art will appreciate that the modules in the apparatuses in the embodiments can be adapted and placed in one or more apparatuses other than the embodiments. The modules or units or components in the embodiments can be combined into one module or unit or component, and further can be divided into multiple sub-modules or sub-units or sub-components. Except that at least some of such features and / or processes or units are mutually exclusive, all combinations of all features disclosed in this specification (including accompanying claims, abstract and drawings) and all processes or units of any methods or apparatuses so disclosed can be adopted in any combination. Unless explicitly stated otherwise, each feature disclosed in this specification (including accompanying claims, abstract and drawings) can be replaced by alternative features providing the same, equivalent, or similar functionality. And in unitary claim recitations of a plurality of apparatuses, several of the apparatuses can be embodied by one and the same hardware item with non-coinciding functions.

[0096] Similarly, it is to be understood that the embodiments of the present disclosure described above and illustrated in the drawings are by way of example only, and are not intended to limit the various aspects of the disclosure in their full scope. In order to facilitate an understanding of one or more aspects of the disclosure, various features of the disclosure are sometimes grouped together in a single embodiment, a figure, or described in a description of one or more embodiments. However, the disclosure should not be construed as reflecting a necessity to

[0097] The specific embodiments described above are further intended to be illustrative of the broader aspects of the present disclosure, and the foregoing description of the broad aspects of the present disclosure is intended to be taken as a summary of the nature and substance of those aspects. It should be appreciated that the foregoing description is intended as a description of the various aspects of the disclosure and as such is not intended to limit the scope of the disclosure.

Claims

1. A signal processing circuit comprising: a first transistor, a source of the first transistor being configured to be connected to a first signal input, a gate of the first transistor being configured to be connected to a second signal input; a second transistor, a drain of the second transistor being configured to be connected to a drain of the first transistor and a signal output, a gate of the second transistor being configured to be connected to the second signal input; a third transistor, a drain of the third transistor being configured to be connected to a source of the second transistor, a source of the third transistor being configured to be connected to ground; a fourth transistor, a source of the fourth transistor being configured to be connected to a gate of the third transistor, a drain of the fourth transistor being configured to be connected to a third signal input; wherein the first signal input is configured to receive a power signal, the second signal input is configured to receive a transmission signal, the third signal input is configured to receive a voltage reduction duration signal, the voltage reduction duration signal is configured to determine a duration of voltage reduction of the signal output, and the signal output is configured to output a new transmission signal corresponding to the power signal, the transmission signal and the voltage reduction duration signal; wherein a gate of the fourth transistor is configured to be connected to a fourth signal input; wherein the third signal input is configured to transmit the voltage reduction duration signal to the fourth transistor, the fourth signal input is configured to receive a transistor control signal, the transistor control signal is configured to control a conduction state of the fourth transistor, and the fourth transistor is configured to transmit the voltage reduction duration signal to the third transistor in the conduction state.

2. The circuit of claim 1, wherein, The fourth transistor is further configured to cache the voltage reduction duration signal for a cache duration, so that the signal output outputs the new transmission signal for the cache duration by the cached voltage reduction duration signal through the third transistor in a case that the fourth transistor is in an off state.

3. The circuit of claim 1, wherein, Materials of the third transistor and the fourth transistor both comprise indium gallium zinc oxide.

4. The circuit of any one of claims 1-3, wherein, The signal processing circuit is N, a signal output of an n-1th signal processing circuit of the N signal processing circuits is configured to be connected to a second signal input of an nth signal processing circuit, n is a positive integer less than or equal to N and greater than 1, and N is a positive integer.

5. The circuit of any one of claims 1-3, wherein, The first transistor is a P-type doped field effect transistor, and the second transistor is an N-type doped field effect transistor.

6. A signal processing method using the signal processing circuit of claim 1, comprising: in a case that the transmission signal is a low level, turning on the first transistor and turning off the second transistor to transmit the power signal to the signal output through the first transistor; in a case that the transmission signal is converted from a low level to a high level, turning off the first transistor and turning on the second transistor to make the third transistor receive a voltage from the signal output through the second transistor. The third transistor is used to continuously reduce the voltage of the signal output end according to the voltage reduction duration corresponding to the voltage reduction duration signal, so that the signal output end outputs the new transmission signal.

7. The signal processing method of claim 6, further comprising: The fourth transistor is used to buffer the voltage reduction duration signal from the third signal input end and transmit the buffered voltage reduction duration signal to the gate of the third transistor.

8. The signal processing method of claim 7, further comprising: When the transistor control signal is high, the fourth transistor is turned on to transmit the voltage reduction duration signal to the third transistor by using the fourth transistor.

9. The signal processing method of claim 7, further comprising: When the transistor control signal is low, the fourth transistor is turned off to stop receiving the voltage reduction duration signal from the third signal input end.

Images