Adjustable delay device and memory
By introducing an adjustable delay device into the memory and utilizing a delay adjustment module combining PMOS and NMOS transistors, the problem of non-adjustable delay in the prior art is solved, and high-precision delay control is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SEMITRONIX
- Filing Date
- 2023-09-11
- Publication Date
- 2026-05-22
AI Technical Summary
Existing technologies cannot meet the requirements for high-precision memory latency, nor can they accurately adjust the latency according to the rapidly changing input signal requirements.
An adjustable delay device is provided, including a delay main module and a delay adjustment module. By combining PMOS and NMOS transistors and using signal input to control the access of the adjustment circuit, the delay time can be precisely adjusted.
It enables precise adjustment of the delay time, improves the accuracy of the delay timing, and meets the requirements for high-precision delay.
Smart Images
Figure CN117238331B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electronic power technology, and in particular to an adjustable delay device and a memory. Background Technology
[0002] With the development of electronic technology, the types of memory in chips are increasing, and the storage method and speed of memory affect the evaluation of chip performance. Read / write latency is a common function of memory, and most memory on the market can implement read / write latency based on input signals.
[0003] However, with the rapidly changing storage delay requirements of input signals, the delay required by the memory is not a fixed time. In the existing technology, the delay time can be adjusted by changing the number of delay devices in the memory. However, for some chips, the existing technology cannot meet the requirements of high-precision delay time. Summary of the Invention
[0004] Therefore, it is necessary to provide an adjustable delay device and memory that can adjust the delay according to the needs and improve the accuracy of the delay time in order to address the above-mentioned technical problems.
[0005] In a first aspect, this application provides an adjustable delay device, characterized in that the device comprises:
[0006] The delay module is used to delay the input first signal for a first time and then output the second signal.
[0007] The delay adjustment module connected to the output of the delay main module is used to receive the corresponding delay signal according to the delay requirement, delay the second signal for a second time, and then output the third signal.
[0008] In one embodiment, the delay adjustment module includes a delay unit and an adjustment unit;
[0009] The delay unit includes a first delay circuit and a second delay circuit; the adjustment unit includes at least one adjustment circuit connected in parallel with the second delay circuit, and the adjustment circuit is provided with a signal input terminal for inputting a delay signal to control the connection of the corresponding adjustment circuit.
[0010] In one embodiment, the first delay circuit includes a first PMOS transistor and a second PMOS transistor;
[0011] The drain of the first PMOS transistor is connected to the drain of the second PMOS transistor; the gate of the first PMOS transistor and the gate of the second PMOS transistor are connected to the output terminal of the delay main module; the source of the first PMOS transistor and the source of the second PMOS transistor are connected to the output terminal of the delay adjustment module.
[0012] In one embodiment, the second delay circuit includes a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor.
[0013] The drain of the first NMOS transistor is connected to the output terminal of the delay adjustment module, the gate is connected to the output terminal of the delay main module, and the source is connected to the drain of the second NMOS transistor; the gate of the second NMOS transistor is connected to the output terminal of the delay main module, and the source is connected to the drain of the third NMOS transistor; the gate of the third NMOS transistor is connected to the output terminal of the delay main module, and the source is connected to the common ground.
[0014] In one embodiment, the adjustment circuit includes at least one first adjustment circuit for correspondingly providing at least one delayed signal input; the first adjustment circuit includes a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor.
[0015] The gate of the fourth NMOS transistor is connected to the input terminal of the delay signal, the drain is connected to the output terminal of the delay adjustment module, and the source is connected to the drain of the fifth NMOS transistor; the gate of the fifth NMOS transistor is connected to the input terminal of the delay signal, and the source is connected to the drain of the sixth NMOS transistor; the gate of the sixth NMOS transistor is connected to the output terminal of the delay main module, and the source is connected to the common ground.
[0016] In one embodiment, the adjustment circuit includes at least one second adjustment circuit for correspondingly providing at least one delay signal input; the second adjustment circuit includes a seventh NMOS transistor and an eighth NMOS transistor;
[0017] The gate of the seventh NMOS transistor is connected to the input terminal of the delay signal, the drain is connected to the output terminal of the delay adjustment module, and the source is connected to the drain of the eighth NMOS transistor; the gate of the eighth NMOS transistor is connected to the output terminal of the delay main module, and the source is connected to the common ground.
[0018] In one embodiment, the adjustment circuit includes at least one third adjustment circuit for correspondingly providing at least one delayed signal input; the third adjustment circuit includes a ninth NMOS transistor, a tenth NMOS transistor, and an eleventh NMOS transistor;
[0019] The gate of the ninth NMOS transistor is connected to the gate of the tenth NMOS transistor and is connected to the input terminal of the delay signal; the drain of the ninth NMOS transistor is connected to the drain of the tenth NMOS transistor and is connected to the output terminal of the delay adjustment module; the source of the ninth NMOS transistor is connected to the source of the tenth NMOS transistor and is connected to the drain of the eleventh NMOS transistor; the gate of the eleventh NMOS transistor is connected to the output terminal of the delay main module, and the source is connected to the common ground.
[0020] In one embodiment, the delay main module includes a plurality of delay units connected in sequence, wherein the delay unit is a MOS capacitor.
[0021] In one embodiment, the device includes a preamplifier circuit module connected to the input of the delay main module for correcting level jumps generated during the transmission of the first signal.
[0022] Secondly, this application also provides a memory, which includes a storage array and peripheral circuitry. The peripheral circuitry includes a control circuit, a row and column decoder, and a read / write circuit connected in sequence. The read / write circuitry includes an adjustable delay device as described in the first aspect above.
[0023] The control circuit is used to control the storage structure of the storage array based on the first signal, and to perform read and write operations on the first signal using a row and column decoder.
[0024] The read / write circuit is used to adjust the delay of the first signal during read / write operations.
[0025] The aforementioned adjustable delay device and memory, through the delay main module for delaying the input first signal for a first time and then outputting a second signal, and the delay adjustment module connected to the output end of the delay main module for receiving the corresponding delay signal according to the delay requirements, delaying the second signal for a second time, and then outputting a third signal, realize the adjustable delay of the read and write process and improve the accuracy of the delay time. Attached Figure Description
[0026] Figure 1 This is a structural block diagram of an adjustable delay device in one embodiment;
[0027] Figure 2 This is a structural block diagram of the delay adjustment module 102 in one embodiment;
[0028] Figure 3 Here is a block diagram of the first delay circuit 211 in one embodiment;
[0029] Figure 4 This is a block diagram of the second delay circuit 212 in one embodiment;
[0030] Figure 5 Here is a block diagram of the adjustment circuit 221 in one embodiment;
[0031] Figure 6 Here is a block diagram of the adjustment circuit 221 in another embodiment;
[0032] Figure 7 Here is a block diagram of the adjustment circuit 221 in another embodiment;
[0033] Figure 8 Here is a block diagram of the regulating circuit in an example embodiment;
[0034] Figure 9 This is a structural block diagram of the delay main module 101 in one embodiment;
[0035] Figure 10 This is a structural block diagram of an adjustable delay device in another embodiment;
[0036] Figure 11 This is a structural block diagram of an adjustable delay device in an example embodiment. Detailed Implementation
[0037] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0038] Obviously, the accompanying drawings described below are merely some examples or embodiments of this application. Those skilled in the art can apply this application to other similar scenarios based on these drawings without any inventive effort. Furthermore, it is understood that although the efforts made in this development process may be complex and lengthy, for those skilled in the art related to the content disclosed in this application, any changes to design, manufacturing, or production based on the technical content disclosed in this application are merely conventional technical means and should not be construed as insufficient disclosure of the content of this application.
[0039] In this application, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment that is mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this application may be combined with other embodiments without conflict.
[0040] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "a," "an," "a kind," "the," and similar words used in this application do not indicate quantity limitation and may indicate singular or plural. The terms "comprising," "including," "having," and any variations thereof used in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units not listed, or may include other steps or units inherent to these processes, methods, products, or devices. The terms "connected," "linked," and similar words used in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "A plurality" used in this application refers to two or more. The terms "first," "second," "third," etc., used in this application are merely to distinguish similar objects and do not represent a specific ordering of objects.
[0041] In one embodiment, such as Figure 1 As shown, an adjustable delay device is provided, including a delay main module 101 and a delay adjustment module 102. The delay main module 101 is used to delay the input first signal for a first time and then output a second signal; the delay adjustment module 102, connected to the output terminal of the delay main module 101, is used to receive the corresponding delay signal according to the delay requirement, delay the second signal for a second time, and then output a third signal.
[0042] Specifically, the first time is the longest delay time, and the second time is the length of time after adjusting the longest delay time. After the first signal flows into the delay main module 101, the delay main module 101 performs the longest delay on the first signal to obtain the second signal, which is then input to the delay adjustment module 102. The delay adjustment module 102 receives the corresponding delay signal according to the delay requirements and adjusts the longest delay time of the second signal to obtain the third signal.
[0043] In this embodiment, the maximum signal delay time is determined by the delay main module, and the maximum signal delay time is adjusted by the delay adjustment module to select a suitable signal delay time. This solves the problem of the non-adjustable delay time in the prior art and improves the accuracy of the delay time.
[0044] In one embodiment, such as Figure 2As shown, the delay adjustment module 102 includes a delay unit 21 and an adjustment unit 22. The delay unit 21 includes a first delay circuit 211 and a second delay circuit 212. The adjustment unit 22 includes at least one adjustment circuit 221 connected in parallel with the second delay circuit 212. The adjustment circuit is provided with a signal input terminal for inputting a delay signal DS to control the connection of the corresponding adjustment circuit 221.
[0045] Among them, such as Figure 3 As shown, the first delay circuit 211 includes a first PMOS transistor PQ1 and a second PMOS transistor PQ2.
[0046] The first PMOS transistor PQ1 and the second PMOS transistor PQ2 are connected in parallel, with the drain of the first PMOS transistor PQ1 connected to the drain of the second PMOS transistor PQ2; the gate of the first PMOS transistor PQ1 and the gate of the second PMOS transistor PQ2 are connected to the output terminal of the delay main module 101; and the source of the first PMOS transistor PQ1 and the source of the second PMOS transistor PQ2 are connected to the output terminal of the delay adjustment module 102.
[0047] Among them, such as Figure 4 As shown, the second delay circuit 212 includes a first NMOS transistor NQ1, a second NMOS transistor NQ2, and a third NMOS transistor NQ3.
[0048] The first NMOS transistor NQ1, the second NMOS transistor NQ2, and the third NMOS transistor NQ3 are connected in series. The drain of the first NMOS transistor NQ1 is connected to the output terminal of the delay adjustment module 102, the gate is connected to the output terminal of the delay main module 101, and the source is connected to the drain of the second NMOS transistor NQ2. The gate of the second NMOS transistor NQ2 is connected to the output terminal of the delay main module 101, and the source is connected to the drain of the third NMOS transistor NQ3. The gate of the third NMOS transistor NQ3 is connected to the output terminal of the delay main module 101, and the source is connected to a common ground.
[0049] In one embodiment, such as Figure 5 As shown, the adjustment circuit 221 includes at least one first adjustment circuit for providing at least one delay signal input. The first adjustment circuit includes a fourth NMOS transistor NQ4, a fifth NMOS transistor NQ5, and a sixth NMOS transistor NQ6.
[0050] The fourth NMOS transistor NQ4, the fifth NMOS transistor NQ5, and the sixth NMOS transistor NQ6 are connected in series. The gate of the fourth NMOS transistor NQ4 is connected to the input terminal of the delay signal DS, the drain is connected to the output terminal of the delay adjustment module 102, and the source is connected to the drain of the fifth NMOS transistor NQ5. The gate of the fifth NMOS transistor NQ5 is connected to the input terminal of the delay signal DS, and the source is connected to the drain of the sixth NMOS transistor NQ6. The gate of the sixth NMOS transistor NQ6 is connected to the output terminal of the delay main module 101, and the source is connected to the common ground.
[0051] In another embodiment, such as Figure 6 As shown, the adjustment circuit 221 includes at least one second adjustment circuit for providing at least one delay signal input. The second adjustment circuit includes a seventh NMOS transistor NQ7 and an eighth NMOS transistor NQ8.
[0052] The seventh NMOS transistor NQ7 and the eighth NMOS transistor NQ8 are connected in series. The gate of the seventh NMOS transistor NQ7 is connected to the input terminal of the delay signal DS, the drain is connected to the output terminal of the delay adjustment module 102, and the source is connected to the drain of the eighth NMOS transistor NQ8. The gate of the eighth NMOS transistor NQ8 is connected to the output terminal of the delay main module 101, and the source is connected to the common ground.
[0053] In yet another embodiment, such as Figure 7 As shown, the adjustment circuit 221 includes at least one third adjustment circuit for providing at least one delay signal input. The third adjustment circuit includes a ninth NMOS transistor NQ9, a tenth NMOS transistor NQ10, and an eleventh NMOS transistor NQ11.
[0054] The ninth NMOS transistor NQ9 and the tenth NMOS transistor NQ10 are connected in parallel, and then connected in series with the eleventh NMOS transistor NQ11. The gate of the ninth NMOS transistor NQ9 and the gate of the tenth NMOS transistor NQ10 are connected and connected to the input terminal of the delay signal DS. The drain of the ninth NMOS transistor NQ9 and the drain of the tenth NMOS transistor NQ10 are connected and connected to the output terminal of the delay adjustment module 102. The source of the ninth NMOS transistor NQ9 and the source of the tenth NMOS transistor NQ10 are connected and connected to the drain of the eleventh NMOS transistor NQ11. The gate of the eleventh NMOS transistor is connected to the output terminal of the delay main module 101, and the source is connected to the common ground.
[0055] For example, such as Figure 8As shown, an adjustment circuit controlled by delay signals DS0, DS1, and DS2 is provided. DS0 controls adjustment circuit one, which includes the fourth NMOS transistor NQ4, the fifth NMOS transistor NQ5, and the sixth NMOS transistor NQ6; DS1 controls adjustment circuit two, which includes the seventh NMOS transistor NQ7 and the eighth NMOS transistor NQ8; and DS2 controls adjustment circuit three, which includes the ninth NMOS transistor NQ9, the tenth NMOS transistor NQ10, and the eleventh NMOS transistor NQ11. The delay signals DS0, DS1, and DS2 are external input signals with an input range of 000-111. 0 represents a low signal (e.g., VSS), and 1 represents a high signal (e.g., VDD). The three delay signals control the NMOS transistors; when connected to 0, the NMOS transistors are off, and when connected to 1, they are on. By controlling the change in the NMOS transistor array connected to the circuit, the width-to-length ratio of the PMOS / NMOS transistors is altered, thereby adjusting the delay time.
[0056] In various embodiments of the delay adjustment module 102 described above, by setting PMOS and NMOS transistors in the circuit, and utilizing the width-to-length ratio of the PMOS and NMOS transistors connected to the circuit, the delay of the second signal is adjusted to obtain the third signal, thereby improving the accuracy of the delay time.
[0057] In one embodiment, such as Figure 9 As shown, the delay main module 101 includes a plurality of delay units connected in sequence, wherein the delay unit is a MOS capacitor Q.
[0058] Specifically, a number of MOS capacitors Q connected in series constitute the delay main module 101. After being turned on, the number of MOS capacitors Q connected in series are MOS gate oxide capacitors. The total capacitance of the MOS gate oxide capacitors is C = C1 + C2 + C3 + ... + Cn. The size of the total capacitance is related to the number of MOS capacitors Q. The more MOS capacitors Q connected in series, the larger the total capacitance and the longer the first delay time.
[0059] In other embodiments, the delay main module 101 can be implemented using other delay units, such as inverters or multi-stage series inverters as delay units. This application does not impose specific limitations on the delay main module 101.
[0060] In one embodiment, such as Figure 10 As shown, the adjustable delay device also includes a pre-amplifier circuit module 103 connected to the input terminal of the delay main module 101, which is used to correct the level jump generated during the transmission of the first signal.
[0061] The preamplifier circuit module 103 includes a NAND gate and multiple NOT gates. The multiple NOT gates are connected in sequence to one pin of the NAND gate, and both input pins of the NAND gate are connected to the first signal input terminal.
[0062] Alternatively, the NAND gate can be replaced with a NOR gate.
[0063] In this embodiment, by adding a pre-circuit module before the delay main module, the short-time delay generated by NOT gates and NAND gates, or NOT gates and OR gates, is used to eliminate the problem of the first signal level jumping due to signal glitches during the transmission of the first signal.
[0064] In one example embodiment, such as Figure 11 As shown, an adjustable delay device is provided, comprising a preamplifier circuit 103, a delay main module 101, and a delay adjustment module 102 connected in sequence, wherein:
[0065] The preamplifier circuit 103 includes four NOT gates connected in series and one NAND gate.
[0066] The delay main module 101 includes a MOS gate oxide capacitor consisting of at least three MOS caps connected in series, wherein the gate of the MOS gate oxide capacitor is connected to the first signal input terminal.
[0067] The delay adjustment module 102 includes a delay unit 21 and an adjustment unit 22. The delay unit 21 includes a first delay circuit 211 and a second delay circuit 212. The adjustment unit 22 includes three adjustment circuits connected in parallel with the second delay circuit 212. Delay signals DS0, DS1, and DS2 control the corresponding three adjustment circuits. The delay signal DS0 controls the first adjustment circuit including the fourth NMOS transistor NQ4, the fifth NMOS transistor NQ5, and the sixth NMOS transistor NQ6. The delay signal DS1 controls the second adjustment circuit including the seventh NMOS transistor NQ7 and the eighth NMOS transistor NQ8. The delay signal DS2 controls the third adjustment circuit including the ninth NMOS transistor NQ9, the tenth NMOS transistor NQ10, and the eleventh NMOS transistor NQ11.
[0068] The delay signals DS2, DS1, and DS0 correspond to eight input levels from 000 to 111. 0 represents a low signal (e.g., VSS), and 1 represents a high signal (e.g., VDD). The three delay signals control the NMOS transistor; the NMOS transistor is off when connected to 0 and on when connected to 1.
[0069] If the NMOS transistors are of uniform size, and assuming the width-to-length ratio of the PMOS transistors is x, when the delay signals DS2, DS1, and DS0 are 000, the first, second, and third adjustment circuits are not connected to the circuit. At this time, the width-to-length ratio of the PMOS / NMOS transistors is... The delay duration of the output third signal is the longest delay time generated by the delay main module. When the delay signals DS2, DS1, and DS0 are 001, the first adjustment circuit is connected to the circuit, while the second and third adjustment circuits are not connected. At this time, the width-to-length ratio of the PMOS / NMOS transistor is... The delay duration of the output third signal is Divide by The delay duration is equal to half of the longest delay time generated by the main delay module. Similarly, when delay signals DS2, DS1, and DS0 are 010, the delay duration of the output third signal is 2 / 5 of the longest delay time generated by the main delay module. When delay signals DS2, DS1, and DS0 are 011, the delay duration of the output third signal is 2 / 7 of the longest delay time generated by the main delay module. When delay signals DS2, DS1, and DS0 are 100, the delay duration of the output third signal is 1 / 3 of the longest delay time generated by the main delay module. When delay signals DS2, DS1, and DS0 are 101, the delay duration of the output third signal is 1 / 4 of the longest delay time generated by the main delay module. When delay signals DS2, DS1, and DS0 are 110, the delay duration of the output third signal is 2 / 9 of the longest delay time generated by the main delay module. When the delay signals DS2, DS1, and DS0 are 111, the delay duration of the output third signal is 2 / 11 of the longest delay time generated by the delay main module.
[0070] It should be noted that the number of control levels of the adjustment circuit can be increased according to the specific application scenario, thereby increasing the number of delay signal inputs. Furthermore, depending on the specific needs, the design of the first, second, or third adjustment circuit, or even other adjustment circuit designs, can be selected to provide controllable signal inputs with different delays.
[0071] In addition, the size of the NMOS transistors can be adjusted according to actual needs, and the width-to-length ratio of the PMOS / NMOS transistors can be changed to precisely adjust the delay time. For example, the sizes of the ninth NMOS transistor NQ9, the tenth NMOS transistor NQ10, and the eleventh NMOS transistor NQ11 on the third adjustment circuit controlling the DS2 delay signal can be adjusted so that the delay durations corresponding to 000-111 are 1 / 2, 2 / 5, 2 / 7, 1 / 4, 1 / 5, 2 / 11, and 2 / 13 of the longest delay time generated by the main delay module, respectively. See Table 1 below.
[0072] Table 1
[0073]
[0074]
[0075] In this table, the theoretical score is the ratio of the theoretical delay time when DS2, DS1, and DS0 are the corresponding delay signals in that row to the theoretical delay time when the delay signals of DS2, DS1, and DS0 are 000. The theoretical decimal value is the numerical value corresponding to this ratio. t_transfer represents the simulated delay time from Vdd / 2 at the rising edge of the input signal to Vdd / 2 at the falling edge of the output signal. t_fall represents the simulated delay time from 0.9*Vdd to 0.1*Vdd at the falling edge of the output signal. The t_transfer delay ratio and t_fall delay ratio are the ratios of the simulated delay time when DS2, DS1, and DS0 are the corresponding delay signals in that row to the simulated delay time when the delay signals of DS2, DS1, and DS0 are 000. The data in the table shows that the simulated delay time and the theoretical delay time are basically consistent.
[0076] In one embodiment, a memory is provided, the memory including a storage array and peripheral circuitry, the peripheral circuitry including a control circuit, a row and column decoder, and a read / write circuitry connected in sequence, the read / write circuitry including an adjustable delay device as described in the above example embodiment.
[0077] The control circuit is used to control the storage structure of the storage array based on a first signal, and to perform read and write operations on the first signal using a row and column decoder. The read / write circuit is used to adjust the delay of the first signal during read and write operations.
[0078] For example, the memory array is an SRAM array structure. When the memory performs a delayed read operation, at the rising edge of the externally input clock signal clk, the precharge circuit in the control circuit and the circuit in the adjustable delay device in the read / write circuit are enabled to delay the clock rising edge. When the delay ends, the precharge circuit is deactivated. At the falling edge of the externally input clock signal clk, the isolation circuit in the control circuit and the circuit in the adjustable delay device in the read / write circuit, as well as the sensitive amplifier, are enabled to delay the clock falling edge. When the delay ends, the sensitive amplifier and the isolation circuit are deactivated.
[0079] When the memory performs a delayed write operation, at the rising edge of the externally input clock signal clk, the precharge circuit in the control circuit and the circuit in the adjustable delay device in the read / write circuit are enabled to delay the clock rising edge. After the delay ends, the precharge circuit is deactivated. At the falling edge of the externally input clock signal clk, the circuit in the adjustable delay device in the read / write circuit and the write driver circuit are enabled to delay the clock falling edge. After the delay ends, the write driver circuit is deactivated.
[0080] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0081] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.
Claims
1. An adjustable delay device, characterized in that, The device includes: The delay module is used to delay the input first signal for a first time and then output the second signal. The delay adjustment module connected to the output of the delay main module is used to receive the corresponding delay signal according to the delay requirement, delay the second signal for a second time, and then output the third signal. The delay adjustment module includes a delay unit and an adjustment unit; The delay unit includes a first delay circuit and a second delay circuit; The adjustment unit includes at least one adjustment circuit connected in parallel with the second delay circuit. The adjustment circuit is provided with a signal input terminal for inputting a delay signal to control the state of the NMOS transistor in the corresponding adjustment circuit, changing the width-to-length ratio of the PMOS transistor in the first delay circuit and the NMOS transistor in the adjustment circuit, and adjusting the second signal by delay to obtain the third signal.
2. The adjustable delay device according to claim 1, characterized in that, The first delay circuit includes a first PMOS transistor and a second PMOS transistor; The drain of the first PMOS transistor is connected to the drain of the second PMOS transistor. The gate of the first PMOS transistor and the gate of the second PMOS transistor are connected to the output terminal of the delay main module; The source of the first PMOS transistor and the source of the second PMOS transistor are connected to the output terminal of the delay adjustment module.
3. The adjustable delay device according to claim 1, characterized in that, The second delay circuit includes a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor. The drain of the first NMOS transistor is connected to the output terminal of the delay adjustment module, the gate is connected to the output terminal of the delay main module, and the source is connected to the drain of the second NMOS transistor. The gate of the second NMOS transistor is connected to the output terminal of the delay main module, and the source is connected to the drain of the third NMOS transistor; The gate of the third NMOS transistor is connected to the output terminal of the delay main module, and the source is connected to the common ground.
4. The adjustable delay device according to claim 1, characterized in that, The adjustment circuit includes at least one first adjustment circuit for correspondingly providing at least one delayed signal input; The first adjustment circuit includes a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor; The gate of the fourth NMOS transistor is connected to the input terminal of the delay signal, the drain is connected to the output terminal of the delay adjustment module, and the source is connected to the drain of the fifth NMOS transistor. The gate of the fifth NMOS transistor is connected to the input terminal of the delay signal, and the source is connected to the drain of the sixth NMOS transistor. The gate of the sixth NMOS transistor is connected to the output terminal of the delay main module, and the source is connected to the common ground.
5. The adjustable delay device according to claim 1, characterized in that, The adjustment circuit includes at least one second adjustment circuit for correspondingly providing at least one delayed signal input; The second adjustment circuit includes a seventh NMOS transistor and an eighth NMOS transistor; The gate of the seventh NMOS transistor is connected to the input terminal of the delay signal, the drain is connected to the output terminal of the delay adjustment module, and the source is connected to the drain of the eighth NMOS transistor. The gate of the eighth NMOS transistor is connected to the output terminal of the delay main module, and the source is connected to the common ground.
6. The adjustable delay device according to claim 1, characterized in that, The adjustment circuit includes at least one third adjustment circuit for correspondingly providing at least one delayed signal input; The third adjustment circuit includes a ninth NMOS transistor, a tenth NMOS transistor, and an eleventh NMOS transistor; The gate of the ninth NMOS transistor is connected to the gate of the tenth NMOS transistor and is connected to the input terminal of the delay signal; the drain of the ninth NMOS transistor is connected to the drain of the tenth NMOS transistor and is connected to the output terminal of the delay adjustment module; the source of the ninth NMOS transistor is connected to the source of the tenth NMOS transistor and is connected to the drain of the eleventh NMOS transistor. The gate of the eleventh NMOS transistor is connected to the output terminal of the delay main module, and the source is connected to the common ground.
7. The adjustable delay device according to claim 1, characterized in that, The delay module includes several delay units connected in sequence, wherein the delay unit is a MOS capacitor.
8. The adjustable delay device according to any one of claims 1-7, characterized in that, The device includes a preamplifier circuit module connected to the input of the delay main module, used to correct level jumps generated during the transmission of the first signal.
9. A memory, characterized in that, The memory includes a storage array and peripheral circuitry. The peripheral circuitry includes a control circuit, a row and column decoder, and a read / write circuit connected in sequence. The read / write circuitry includes an adjustable delay device as described in any one of claims 1 to 8. The control circuit is used to control the storage structure of the storage array based on the first signal, and to perform read and write operations on the first signal using a row and column decoder. The read / write circuit is used to adjust the delay of the first signal during read / write operations.