Memory integrated with computing, logic operation method and electronic device

Abstract

Embodiments of the present application provide a storage and calculation integrated memory, a logic operation method and an electronic device, and are applied to the technical field of semiconductor chip storage and operation. The logic operation device includes a half-floating gate transistor as a storage unit; a first voltage signal is output to a first input end of the half-floating gate transistor, a second voltage signal is output to a second input end of the half-floating gate transistor, and a third voltage signal used for indicating a control variable is output to a third input end of the half-floating gate transistor; the third voltage signal is used for adjusting a voltage sensing state of the half-floating gate; the control variable is used for indicating different voltage sensing states of the half-floating gate; the first voltage signal and the second voltage signal are used for adjusting the voltage of the half-floating gate in different voltage sensing states of the half-floating gate; and the voltage of the adjusted half-floating gate is used for indicating an operation result of a logic operation between an input variable corresponding to the first voltage signal and an input variable corresponding to the second voltage signal.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor chip storage and operation, and particularly relates to an in-memory computing memory, a logic operation method and an electronic device. BACKGROUND

[0002] The Von Neumann architecture is an architecture in which a processor and a memory are two independent devices. The processor reads data from the memory through a control unit of the memory, and then stores the processing result back to the memory. However, such an architecture is built on the premise that the processing speed of the processor is close to that of the memory. With the performance improvement of the processor, the processing speed of the processor is far higher than that of the memory, and the difference in processing speed greatly affects the efficiency of data operation of the processor.

[0003] An improved way is to use a part of the structure of the memory as a processing part to obtain an in-memory computing memory, which fundamentally solves the problem of mismatching of the processing speed of the independent processor and the memory, and greatly improves the efficiency of data operation. However, in this improved way, the processing part in the in-memory computing memory no longer performs storage, so that in the case of occupying the storage area of the in-memory computing memory, the storage capacity of the in-memory computing memory is reduced compared with the general memory. In addition, it changes the original memory chip manufacturing process, increases the difficulty of chip manufacturing, and also reduces the data processing rate of the in-memory computing memory due to the incompatibility of the processing part and the storage part in the in-memory computing memory. SUMMARY

[0004] The embodiments of the present application provide an in-memory computing memory, a logic operation method and an electronic device. Based on the data stored in the in-memory computing memory, operation is performed in the storage part of the in-memory computing memory, and the data result after operation is stored in the storage part, so that the in-memory computing is realized without reducing the storage capacity and the data processing rate of the in-memory computing memory.

[0005] To achieve the above object, the embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, an in-memory computing memory is provided, comprising a controller and a memory array, each memory cell of the memory array being a semi-floating gate transistor; the semi-floating gate transistor comprises a first input end, a second input end, a third input end, and a semi-floating gate; the controller is configured to output a first voltage signal to the first input end of the semi-floating gate transistor, output a second voltage signal to the second input end of the semi-floating gate transistor, and output a third voltage signal for indicating a control variable to the third input end of the semi-floating gate transistor; the third voltage signal is used to adjust a voltage induced state of the semi-floating gate; the control variable is used to indicate different voltage induced states of the semi-floating gate; the first voltage signal and the second voltage signal are used to adjust the voltage of the semi-floating gate in different voltage induced states of the semi-floating gate; and the voltage of the adjusted semi-floating gate is used to indicate an operation result of a logical operation between an input variable corresponding to the first voltage signal and an input variable corresponding to the second voltage signal.

[0007] The embodiments of the present application achieve the storage of data based on the semi-floating gate transistor, the logical operation processing of the stored data using the semi-floating gate transistor, and the storage of the operation result of the logical operation processing in the semi-floating gate of the semi-floating gate transistor. The fast and complete logical operation is achieved without reducing the storage capacity of the in-memory computing memory.

[0008] In some possible implementations, the semi-floating gate transistor specifically comprises a drain, a select gate, a control gate, and a semi-floating gate located at the control gate; the select gate is the first input end, and the control gate is the third input end, or the control gate is the first input end, and the select gate is the third input end; and the drain is the second input end. In the embodiments of the present application, any one of the select gate and the control gate is used as the third input end to input the third control voltage, and the other is used as the first input end to input the first control voltage. In the two forms, the implementation effect of the scheme is consistent through the adjustment of the specific voltage values of the first control voltage and the third control voltage.

[0009] In some possible implementation manners, in two adjacent periods: the voltage of the half-floating gate in the latter period is determined by the first voltage signal, the second voltage signal, the third voltage signal, and the voltage of the half-floating gate in the former period; the voltage of the half-floating gate in the former period is used to indicate a storage variable; the voltage of the half-floating gate in the latter period is used to indicate an operation result obtained after the storage variable, an input variable corresponding to the first voltage signal, and an input variable corresponding to the second voltage signal are input into a target formula; and the target formula is determined according to the voltage sensing state of the half-floating gate. In the embodiment of the present application, the third voltage signal is used to adjust the voltage sensing state of the half-floating gate, and the input variable corresponding to the first voltage signal and the input variable corresponding to the second voltage signal and the storage variable of the half-floating gate exhibit different operation logics in different voltage sensing states of the half-floating gate, that is, different target formulas are corresponded. The target formula of the half-floating gate transistor can be determined through the third control voltage, and then a logical operation is performed according to the determined target formula.

[0010] In some possible implementation manners, when the control variable is 1, the target formula is: When the control variable is 0, the target formula is: Wherein, Z' is the storage variable; Z is the operation result; T1 is the input variable corresponding to the first voltage signal; T1' is the value obtained after the input variable corresponding to the first voltage signal is logically negated; and T2 is the input variable corresponding to the second voltage signal. In the embodiment of the present application, different control variables are input to determine the corresponding target formula, so as to perform an operation on the input variable and the storage variable.

[0011] In some possible implementation manners, the controller is configured to: control the first voltage signal to indicate that the corresponding input variable is 1, control the second voltage signal to indicate that the corresponding input variable is 0, and control the third voltage signal to indicate that the control variable is 1, so that the operation result indicated by the voltage of the half-floating gate is 0, to perform first initialization on the half-floating gate. In the embodiment of the present application, the operation of erasing the storage data in the half-floating gate transistor or the operation of writing 0 can be realized through the operation.

[0012] In some possible implementation manners, the controller is configured to: perform first initialization on the half-floating gate in a first period; in a second period, control the first voltage signal to indicate that the corresponding input variable is 0, control the second voltage signal to indicate the first input variable, and control the third voltage signal to indicate that the control variable is 0, so that the operation result indicated by the voltage of the half-floating gate is the first input variable. In the embodiment of the present application, the operation of storing the first input variable in the half-floating gate transistor can be realized through the operation.

[0013] ​In some possible implementation, the controller is configured to: in the first period, perform first initialization on the semi-floating gate; in the second period, control the first voltage signal to indicate the first input variable, control the second voltage signal to indicate the corresponding input variable as 1, and control the third voltage signal to indicate the control variable as 0, so that the operation result of the voltage indication of the semi-floating gate is a logical "NOT" operation on the first input variable. The operation of performing the logical "NOT" operation on the input variable in the two-step operation is realized, and the operation result is stored in the semi-floating gate of the semi-floating gate transistor.

[0014] In some possible implementation, the controller is configured to: in the first period, perform first initialization on the semi-floating gate; in the second period, control the first voltage signal to indicate the corresponding input variable as 0, control the second voltage signal to indicate the first input variable, and control the third voltage signal to indicate the control variable as 0; in the third period, control the first voltage signal to indicate the corresponding input variable as 0, control the second voltage signal to indicate the second input variable, and control the third voltage signal to indicate the control variable as 0, so that the operation result of the voltage indication of the semi-floating gate is a logical "OR" operation on the first input variable and the second input variable. The operation of performing the logical "OR" operation on the two input variables in the three-step operation is realized, and the operation result is stored in the semi-floating gate of the semi-floating gate transistor.

[0015] In some possible implementation, the controller is configured to: in the first period, perform first initialization on the semi-floating gate; in the second period, control the first voltage signal to indicate the first input variable, control the second voltage signal to indicate the second input variable, and control the third voltage signal to indicate the control variable as 0; in the third period, control the first voltage signal to indicate the second input variable, control the second voltage signal to indicate the first input variable, and control the third voltage signal to indicate the control variable as 0, so that the operation result of the voltage indication of the semi-floating gate is a logical "XOR" operation on the first input variable and the second input variable. The operation of performing the logical "XOR" operation on the two input variables in the three-step operation is realized, and the operation result is stored in the semi-floating gate of the semi-floating gate transistor.

[0016] In some possible implementation, the controller is configured to: in the first period, perform first initialization on the semi-floating gate;

[0017] In the second period, the first voltage signal is controlled to indicate the first input variable, the second voltage signal is controlled to indicate the corresponding input variable as 1, and the third voltage signal is controlled to indicate the control variable as 0; in the third period, the first voltage signal is controlled to indicate the second input variable, the second voltage signal is controlled to indicate the corresponding input variable as 0, and the third voltage signal is controlled to indicate the control variable as 1, so that the operation result indicated by the voltage of the semi-floating gate is a logical OR NOT operation on the first input variable and the second input variable. Through the operation, the logical OR NOT operation on the two input variables is realized in three steps, and the operation result is stored in the semi-floating gate of the semi-floating gate transistor.

[0018] In some possible implementation manners, the controller is configured to: in the first period, perform first initialization on the semi-floating gate; in the second period, control the first voltage signal to indicate the corresponding input variable as 0, control the second voltage signal to indicate the first input variable, and control the third voltage signal to indicate the control variable as 0; and in the third period, control the first voltage signal to indicate the corresponding input variable as 1, control the second voltage signal to indicate the second input variable, and control the third voltage signal to indicate the control variable as 1, so that the operation result indicated by the voltage of the semi-floating gate is a logical AND operation on the first input variable and the second input variable. Through the operation, the logical AND operation on the two input variables is realized in three steps, and the operation result is stored in the semi-floating gate of the semi-floating gate transistor.

[0019] In some possible implementation manners, the controller is configured to: in the first period, perform first initialization on the semi-floating gate; in the second period, control the first voltage signal to indicate the first input variable, control the second voltage signal to indicate the corresponding input variable as 1, and control the third voltage signal to indicate the control variable as 0; and in the third period, control the first voltage signal to indicate the second input variable, control the second voltage signal to indicate the corresponding input variable as 1, and control the third voltage signal to indicate the control variable as 0, so that the operation result indicated by the voltage of the semi-floating gate is a logical AND NOT operation on the first input variable and the second input variable. Through the operation, the logical AND NOT operation on the two input variables is realized in three steps, and the operation result is stored in the semi-floating gate of the semi-floating gate transistor.

[0020] In some possible implementation, the controller is configured to: in the first period, perform first initialization on the semi-floating gate; in the second period, control the first voltage signal to indicate the second input variable, control the second voltage signal to indicate the first input variable, and control the third voltage signal to indicate that the control variable is 0, so that the operation result of the voltage indication of the semi-floating gate is the logical "not" operation on the second input variable and the logical "and" operation on the first input variable. The embodiment of the present application realizes the operation of the logical "implication non" operation on the two input variables or the operation of the logical "inverse implication non" in two steps, and stores the operation result in the semi-floating gate of the semi-floating gate transistor.

[0021] In some possible implementation, the controller is configured to: control the first voltage signal to indicate that the corresponding input variable is 0, control the second voltage signal to indicate that the corresponding input variable is 1, and control the third voltage signal to indicate that the control variable is 0, so that the operation result of the voltage indication of the semi-floating gate is 1, to perform second initialization on the semi-floating gate. The embodiment of the present application realizes the operation of writing 1 in the semi-floating gate of the semi-floating gate transistor through the operation.

[0022] In some possible implementation, the controller is configured to: in the first period, perform second initialization on the semi-floating gate; in the second period, control the first voltage signal to indicate the first input variable, control the second voltage signal to indicate the second input variable, and control the third voltage signal to indicate that the control variable is 1; in the third period, control the first voltage signal to indicate the second input variable, control the second voltage signal to indicate the first input variable, and control the third voltage signal to indicate that the control variable is 1, so that the operation result of the voltage indication of the semi-floating gate is the logical "XOR" operation on the first input variable and the second input variable. The embodiment of the present application realizes the operation of the logical "XOR" operation on the two input variables in three steps, and stores the operation result in the semi-floating gate of the semi-floating gate transistor.

[0023] In some possible implementation, the controller is configured to: in the first period, perform second initialization on the semi-floating gate; in the second period, control the first voltage signal to indicate the first input variable, control the second voltage signal to indicate the second input variable, and control the third voltage signal to indicate that the control variable is 1, so that the operation result of the voltage indication of the semi-floating gate is the logical "not" operation on the first input variable and the logical "or" operation on the second input variable. The embodiment of the present application realizes the operation of the logical "implication" operation on the two input variables or the operation of the logical "inverse implication" in two steps, and stores the operation result in the semi-floating gate of the semi-floating gate transistor.

[0024] In some possible implementation manners, the semi-floating gate transistor further includes a source; the source is configured to output a fourth power supply signal; and the fourth power supply signal is configured to indicate an operation result indicated by the voltage of the semi-floating gate. The embodiments of the present application achieve reading of the stored data in the semi-floating gate through the source of the semi-floating gate transistor.

[0025] In a second aspect, the embodiments of the present application further provide a logic operation method applied to a memory-computer integrated memory; the memory-computer integrated memory includes a controller and a memory array, each memory cell of the memory array being a semi-floating gate transistor; the semi-floating gate transistor includes a first input end, a second input end, a third input end, and a semi-floating gate; the method includes: outputting a first voltage signal to the first input end of the semi-floating gate transistor, outputting a second voltage signal to the second input end of the semi-floating gate transistor, and outputting a third voltage signal used for indicating a control variable to the third input end of the semi-floating gate transistor; the third voltage signal is used for adjusting a voltage sensing state of the semi-floating gate; the control variable is used for indicating different voltage sensing states of the semi-floating gate; the first voltage signal and the second voltage signal are used for adjusting the voltage of the semi-floating gate in the different voltage sensing states of the semi-floating gate; and the voltage of the semi-floating gate after the adjustment is used for indicating an operation result of a logic operation between an input variable corresponding to the first voltage signal and an input variable corresponding to the second voltage signal.

[0026] In some possible implementation manners, the semi-floating gate transistor specifically includes: a drain, a select gate, a control gate, and a semi-floating gate located at the control gate; the select gate is the first input end, and the control gate is the third input end, or the control gate is the first input end, and the select gate is the third input end; and the drain is the second input end.

[0027] In some possible implementation manners, the method specifically includes: in two adjacent periods: the voltage of the semi-floating gate in a later period is determined by the first voltage signal, the second voltage signal, the third voltage signal, and the voltage of the semi-floating gate in a previous period; the voltage of the semi-floating gate in the previous period is used for indicating a storage variable; and the voltage of the semi-floating gate in the later period is used for indicating an operation result obtained after the input variable corresponding to the first voltage signal, the input variable corresponding to the second voltage signal, and the storage variable are input into a target formula; and the target formula is determined by the voltage sensing state of the semi-floating gate.

[0028] In some possible implementation manners, when the control variable is 1, the target formula is: When the control variable is 0, the target formula is: wherein Z' is the storage variable; Z is the operation result; T1 is the input variable corresponding to the first voltage signal; T1' is a value obtained after the input variable corresponding to the first voltage signal is subjected to a logic NOT operation; and T2 is the input variable corresponding to the second voltage signal.

[0029] ​In some possible implementation manners, the method further includes: controlling the first voltage signal to indicate that the corresponding input variable is 1, controlling the second voltage signal to indicate that the corresponding input variable is 0, and controlling the third voltage signal to indicate that the control variable is 1, so that the operation result of the voltage indication of the semi-floating gate is 0, to perform first initialization on the semi-floating gate.

[0030] In some possible implementation manners, the method further includes: in a first period, performing first initialization on the semi-floating gate; in a second period, controlling the first voltage signal to indicate that the corresponding input variable is 0, controlling the second voltage signal to indicate the first input variable, and controlling the third voltage signal to indicate that the control variable is 0, so that the operation result of the voltage indication of the semi-floating gate is the first input variable.

[0031] In some possible implementation manners, the method further includes: in a first period, performing first initialization on the semi-floating gate; in a second period, controlling the first voltage signal to indicate the first input variable, controlling the second voltage signal to indicate that the corresponding input variable is 1, and controlling the third voltage signal to indicate that the control variable is 0, so that the operation result of the voltage indication of the semi-floating gate is a logical NOT operation on the first input variable.

[0032] In some possible implementation manners, the method further includes: in a first period, performing first initialization on the semi-floating gate; in a second period, controlling the first voltage signal to indicate that the corresponding input variable is 0, controlling the second voltage signal to indicate the first input variable, and controlling the third voltage signal to indicate that the control variable is 0; in a third period, controlling the first voltage signal to indicate that the corresponding input variable is 0, controlling the second voltage signal to indicate the second input variable, and controlling the third voltage signal to indicate that the control variable is 0, so that the operation result of the voltage indication of the semi-floating gate is a logical OR operation on the first input variable and the second input variable.

[0033] In some possible implementation manners, the method further includes: in a first period, performing first initialization on the semi-floating gate; in a second period, controlling the first voltage signal to indicate the first input variable, controlling the second voltage signal to indicate the second input variable, and controlling the third voltage signal to indicate that the control variable is 0; in a third period, controlling the first voltage signal to indicate the second input variable, controlling the second voltage signal to indicate the first input variable, and controlling the third voltage signal to indicate that the control variable is 0, so that the operation result of the voltage indication of the semi-floating gate is a logical XOR operation on the first input variable and the second input variable.

[0034] In some possible implementation, the method further includes: in the first period, performing first initialization on the semi-floating gate; in the second period, controlling the first voltage signal to indicate the first input variable, controlling the second voltage signal to indicate the corresponding input variable as 1, and controlling the third voltage signal to indicate the control variable as 0; in the third period, controlling the first voltage signal to indicate the second input variable, controlling the second voltage signal to indicate the corresponding input variable as 0, and controlling the third voltage signal to indicate the control variable as 1, so that the operation result indicated by the voltage of the semi-floating gate is a logical OR NOT operation on the first input variable and the second input variable.

[0035] In some possible implementation, the method further includes: in the first period, performing first initialization on the semi-floating gate; in the second period, controlling the first voltage signal to indicate the corresponding input variable as 0, controlling the second voltage signal to indicate the first input variable, and controlling the third voltage signal to indicate the control variable as 0; in the third period, controlling the first voltage signal to indicate the corresponding input variable as 1, controlling the second voltage signal to indicate the second input variable, and controlling the third voltage signal to indicate the control variable as 1, so that the operation result indicated by the voltage of the semi-floating gate is a logical AND operation on the first input variable and the second input variable.

[0036] In some possible implementation, the method further includes: in the first period, performing first initialization on the semi-floating gate; in the second period, controlling the first voltage signal to indicate the first input variable, controlling the second voltage signal to indicate the corresponding input variable as 1, and controlling the third voltage signal to indicate the control variable as 0; in the third period, controlling the first voltage signal to indicate the second input variable, controlling the second voltage signal to indicate the corresponding input variable as 1, and controlling the third voltage signal to indicate the control variable as 0, so that the operation result indicated by the voltage of the semi-floating gate is a logical AND NOT operation on the first input variable and the second input variable.

[0037] In some possible implementation, the method further includes: in the first period, performing first initialization on the semi-floating gate; in the second period, controlling the first voltage signal to indicate the second input variable, controlling the second voltage signal to indicate the first input variable, and controlling the third voltage signal to indicate the control variable as 0, so that the operation result indicated by the voltage of the semi-floating gate is a logical NOT operation on the second input variable and then a logical AND operation with the first input variable.

[0038] In some possible implementation, the method further includes: controlling the first voltage signal to indicate the corresponding input variable as 0, controlling the second voltage signal to indicate the corresponding input variable as 1, and controlling the third voltage signal to indicate the control variable as 0, so that the operation result indicated by the voltage of the semi-floating gate is 1, to perform second initialization on the semi-floating gate.

[0039] In some possible implementation manners, the method further includes: in the first period, performing second initialization on the semi-floating gate; in the second period, controlling the first voltage signal to indicate the first input variable, controlling the second voltage signal to indicate the second input variable, and controlling the third voltage signal to indicate that the control variable is 1; and in the third period, controlling the first voltage signal to indicate the second input variable, controlling the second voltage signal to indicate the first input variable, and controlling the third voltage signal to indicate that the control variable is 1, so that the operation result indicated by the voltage of the semi-floating gate is a logical "exclusive or" operation on the first input variable and the second input variable.

[0040] In some possible implementation manners, the method further includes: in the first period, performing second initialization on the semi-floating gate; in the second period, controlling the first voltage signal to indicate the first input variable, controlling the second voltage signal to indicate the second input variable, and controlling the third voltage signal to indicate that the control variable is 1, so that the operation result indicated by the voltage of the semi-floating gate is a logical "exclusive or" operation on the first input variable and the second input variable.

[0041] In some possible implementation manners, the semi-floating gate transistor further includes a source; and the method further includes: the semi-floating gate transistor outputs a fourth power supply signal through the source; and the fourth power supply signal is used to indicate the operation result indicated by the voltage of the semi-floating gate.

[0042] In a third aspect, an electronic device is further provided, including at least one memory and calculation integrated memory as described in the first aspect; the memory and calculation integrated memory is configured to perform a logical operation using data stored in the memory and calculation integrated memory, and store an operation result in the memory and calculation integrated memory.

[0043] In a fourth aspect, a computer readable storage medium is further provided, including instructions, when the instructions are executed on the electronic device described above, the electronic device performs the method as described in the second aspect.

[0044] In a fifth aspect, a chip system is further provided. The chip system includes at least one processor and at least one interface circuit. The at least one processor and the at least one interface circuit can be interconnected through a circuit. The processor is configured to support the chip system to implement various functions or steps in the method embodiments described above. The at least one interface circuit can be configured to receive signals from other devices (for example, a memory) or send signals to other devices (for example, a communication interface). The chip system can include a chip, and can also include other discrete devices.

[0045] In a sixth aspect, the embodiments of the present application further provide a computer program product comprising instructions which, when executed on the chip system or the electronic device, cause the chip system or the electronic device to perform each function or step in the method embodiments described above, for example, to perform the method shown in the second aspect.

[0046] The technical effects of the second aspect to the sixth aspect are referred to the technical effects of the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0047] Figure 1 A structure schematic diagram of a semi-floating gate transistor provided by the embodiments of the present application;

[0048] Figure 2 A schematic diagram of writing data in a semi-floating gate transistor provided by the embodiments of the present application;

[0049] Figure 3 A schematic diagram of erasing data in a semi-floating gate transistor provided by the embodiments of the present application;

[0050] Figure 4 A structure schematic diagram of an electronic device provided by the embodiments of the present application;

[0051] Figure 5 A structure schematic diagram of another electronic device provided by the embodiments of the present application;

[0052] Figure 6 A structure schematic diagram of a storage operator provided by the embodiments of the present application;

[0053] Figure 7 A structure schematic diagram of an integrated storage and calculation memory provided by the embodiments of the present application;

[0054] Figure 8A A structure schematic diagram of an integrated storage and calculation memory provided by the embodiments of the present application;

[0055] Figure 8B A logic operation schematic diagram of an integrated storage and calculation memory provided by the embodiments of the present application;

[0056] Figure 8C A logic operation schematic diagram of another integrated storage and calculation memory provided by the embodiments of the present application;

[0057] Figure 9 A structure schematic diagram of another integrated storage and calculation memory provided by the embodiments of the present application;

[0058] Figure 10A A port setting schematic diagram of a semi-floating gate transistor provided by the embodiments of the present application;

[0059] Figure 10BA port setting diagram of another half-floating gate transistor provided by an embodiment of the present application is shown in FIG. 6.

[0060] Figure 11 A flow diagram of a logic operation method provided by an embodiment of the present application is shown in FIG. 9.

[0061] Figure 12 A structure diagram of a chip system provided by an embodiment of the present application is shown in FIG. 10. DETAILED DESCRIPTION

[0062] It should be noted that the terms "first", "second" and the like in the embodiments of the present application are only used to distinguish the same type of features, and should not be understood as indicating relative importance, quantity, order and the like.

[0063] The terms "exemplary" or "for example" and the like in the embodiments of the present application are used to represent an example, illustration or description. Any embodiment or design scheme described as "exemplary" or "for example" in the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. Rather, the terms "exemplary" or "for example" are intended to present the relevant concept in a specific manner.

[0064] The terms "coupling", "connection" in the embodiments of the present application should be understood in a broad sense, for example, can refer to a direct connection in a physical sense, or can refer to an indirect connection through electronic devices, for example, a connection through resistors, inductors, capacitors or other electronic devices.

[0065] First, some basic concepts related to the embodiments of the present application are described:

[0066] Semi-Floating-Gate Transistor (SFGT) is a transistor between Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and Floating Gate Transistor (FGT). MOSFET transistor is the most basic device in current integrated circuits. The progress of technology makes the size of MOSFET transistor continuously shrink, and its power and density are always increasing. The flash memory chip such as U disk uses FGT transistor. Flash memory chip is also called non-volatile memory. Non-volatile means that information is still saved and will not be lost without power supply. This device needs current to pass through a layer of about 5 nanometer thick silicon oxide medium when writing and erasing, so it needs high operating voltage (about 20 volts) and long operating time (microsecond level). The erase and write operation of Tunneling Field-Effect Transistor (TFET) is based on the quantum tunneling effect in silicon body, while the erase and write operation of traditional FGT body transistor is to make electrons tunnel through the insulating medium. Scientists combine a TFET transistor and a floating gate device to form a new device with a "semi-floating gate" structure, called Semi-Floating-Gate Transistor (SFGT). The SFGT transistor obtained by combining TFET transistor and floating gate device is easier and faster about data erasing and writing. The TFET structure is used to charge and discharge the floating gate, so as to complete the operation of data erasing and writing. The semi-floating gate realizes the functions of data storage and reading. This structure can make the data erasing and writing of SFGT transistor easier and faster, and the whole process can be completed under low voltage condition, which creates conditions for realizing low power consumption of chip.

[0067] As shown in Figure 1 The embodiment of the present application provides a Semi-Floating-Gate Transistor 520, which comprises a source 521, a drain 522, a control gate 523, a selection gate 524, a semi-floating gate 525 and a gate oxide layer 526. One feature of the Semi-Floating-Gate Transistor is that the semi-floating gate 525 is not completely covered by the gate oxide layer 526. On the gate oxide layer 526, a semi-floating gate window 527 is opened at the N-region channel on the side of the semi-floating gate 525 and the drain 522. The principle of writing operation of the Semi-Floating-Gate Transistor is as shown in Figure 2As shown, by applying a reverse bias to the select gate 524 and the control gate 523 using the TFET structure (i.e. P+ region, N- region and N+ region) on the drain 522 side, the energy band of the N- region is bent downward more, so that the electrons in the valence band of the P+ region tunnel into the conduction band of the N region, while the holes enter the semi-floating gate 525 from the N region to the P region through the semi-floating gate window 527, thereby completing the operation of writing "1" on the semi-floating gate 525. The principle of performing an erase operation on the semi-floating gate transistor is as follows: Figure 3 As shown, by applying a forward bias to the control gate 523 and the drain 522, the electrons flow from the N region to the semi-floating gate 525 through the semi-floating gate window 527, neutralize the holes stored on the semi-floating gate 525, and complete the erase operation. Since the gate oxide layer 526 is not damaged during the erase process of the semi-floating gate transistor, the endurance thereof is theoretically infinite. The principle of performing a read operation on the semi-floating gate transistor is as follows: under the same read bias voltage, according to whether the holes are stored on the semi-floating gate 525, the channel will exist in two states of closing and opening, so that different fourth power signals, i.e. read currents, will be obtained, and the window of the read current exceeds 14uA. Therefore, the semi-floating gate memory has excellent characteristics such as nanosecond-level high operation speed and unlimited number of erase and write times, and is considered as one of the storage technologies expected to replace DRAM.

[0068] As shown in Figure 4 or Figure 5 An electronic device 100 is provided in the embodiments of the present application, which comprises a storage operator 110 and a logic operator 120. The storage operator 110 is configured to perform a logic operation based on data stored in the storage operator 110 and store an operation result in the storage operator 110. As shown in Figure 4 The logic operator 120 is configured to receive the operation result of the storage operator 110 and perform a logic operation on the operation result. Alternatively, as shown in Figure 5 The logic operator 120 is configured to perform a logic operation on data and send an operation result to the storage operator 110 for a logic operation.

[0069] Exemplarily, the logic operator 120 is an adder, a subtractor, a multiplier, a divider, etc.

[0070] As shown in Figure 6As shown in the figure, this application embodiment provides a storage arithmetic unit 110, which is based on the von Neumann architecture and includes a processor 200 and a memory 300. The von Neumann architecture is an architecture that separates the processor 200 and the memory 300 into two independent devices. The processor 200 reads stored data from the memory 300 through the control unit 310 of the memory 300, performs arithmetic processing, and then stores the processed data back into the memory 300. However, as the performance of the processor 200 improves, its processing speed far exceeds that of the memory 300, and this difference in processing speed significantly affects the efficiency of the processor 200's data processing.

[0071] One improvement method is as follows Figure 7 As shown, for Figure 4 , Figure 5 and Figure 6 The storage arithmetic unit 110 shown is improved by using a portion of the memory 300 as a processing unit 410, resulting in an in-memory computing memory 400. This in-memory computing memory 400 enables partial computational tasks to be performed internally, significantly shortening data transport distances, reducing the frequency of external processor 200 accessing data in the in-memory computing memory 400, alleviating bandwidth pressure on data transmission, and improving computational efficiency and energy efficiency. However, in this improved approach, the processing unit 410 in the in-memory computing memory 400 no longer performs storage. Therefore, due to its additional occupation of the storage area of ​​the in-memory computing memory 400, the storage capacity of the in-memory computing memory 400 is reduced compared to a general memory 300. In addition, it changes the original chip manufacturing process of the memory 300, increasing the difficulty of chip manufacturing. Furthermore, due to the incompatibility between the processing unit 410 and the storage unit 420 in the in-memory computing memory 400, the data processing speed of the in-memory computing memory 400 is reduced.

[0072] One improvement method is as follows Figure 8A As shown, this application proposes yet another type of in-memory computing memory, employing DRAM memory cells combined with sense amplifiers (SA). The DRAM memory cells are controlled via the WL control line, and data from the SA is read via the BL control line. Through V... SEL Voltage is controlled by logic operations, via V A Voltage and V B Voltage input is an input variable that requires logical operations. V is measured via SA. BL Voltage and V REF Voltage, compare V BL Voltage and V REF The calculation result can be obtained by determining the magnitude of the voltage. Where V BL The voltage value is V AVoltage, V B Voltage and V SEL The average value of the voltage. When V SEL When the voltage is 0, a logical AND operation is performed. The voltage comparison result and the operation result are as follows: Figure 8B As shown. When V SEL When the voltage is not zero, a logical "OR" operation is performed. The voltage comparison result and the operation result are as follows: Figure 8C As shown. However, this method can only implement a limited number of simple logical operations. If more complex logical operations are required, multiple computing devices need to be connected, which increases the computation time and the number of computing devices. In addition, the calculation results obtained in this way must be stored and organized according to the calculation method of the logical operation, which greatly increases the complexity of data flow control for stored data.

[0073] Therefore, this application provides another in-memory computing memory 500, such as... Figure 9 As shown, the array includes a controller 510 and a memory array; each memory cell in the memory array is a semi-floating gate transistor 520. The controller 510 sends input variables to the semi-floating gate transistors 520, performs logical operations between the input variables and the stored variables in the semi-floating gate transistors 520, and obtains the operation result. The semi-floating gate transistors 520 store the operation result and make it available for retrieval. The structure of the semi-floating gate transistor 520 is as follows. Figure 1 As shown.

[0074] For a single semi-floating gate transistor 520, such as Figure 10A As shown, select gate 524 is used as the first input terminal, drain 522 as the second input terminal, and control gate 523 as the third input terminal; or, as... Figure 10B As shown, the selection gate 524 is used as the first input terminal, the drain 522 as the second input terminal, and the control gate 523 as the third input terminal. The controller 510 outputs a first voltage signal to the semi-floating gate transistor 520 through the first input terminal, a second voltage signal to the semi-floating gate transistor 520 through the second input terminal, and a third voltage signal indicating the control variable to the semi-floating gate transistor 520 through the third input terminal. Figure 1 , Figure 2 , Figure 3As shown, in each cycle, the first voltage signal, the second voltage signal and the third voltage signal received by the half-floating gate transistor 520 will determine the voltage stored in the half-floating gate 525 of the half-floating gate transistor 520 according to the target formula. In each cycle, the determined voltage of the half-floating gate 525 is used to indicate the operation result obtained after the target formula inputs the first voltage signal corresponding input variable, the second voltage signal corresponding input variable and the storage variable; here, the storage variable is the operation result indicated by the voltage of the half-floating gate 525 determined in the last cycle; here, the target formula represents the internal change state of the half-floating gate transistor 520, which is determined by the control variable. For example, Figure 10A and Figure 10B It can be seen that the half-floating gate transistor 520 has a diode structure, when the voltage on the control gate 523 is greater than the voltage on the drain 522, the diode is turned on, the PN junction of the half-floating gate transistor 520 is turned on, and each input voltage can adjust the voltage on the half-floating gate 525 through the PN junction; when the voltage on the control gate 523 is less than the voltage on the drain 522, the PN junction is turned off, and each input voltage can adjust the voltage on the half-floating gate 525 through the TFET structure of the half-floating gate transistor 520. Based on the electrical storage principle of the half-floating gate transistor 520 and the corresponding voltage configuration, the following two target formulas can be obtained:

[0075] When the control variable is 1, the target formula is:

[0076]

[0077] When the control variable is 0, the target formula is:

[0078]

[0079] Wherein, Z' is the storage variable on the half-floating gate 525; Z is the operation result; T1 is the input variable corresponding to the first voltage signal; is the value of the input variable corresponding to the first voltage signal after logical "NOT" operation; T2 is the input variable corresponding to the second voltage signal.

[0080] Exemplarily, in the formula: Figure 10A The control gate 523 is taken as the first input end, the drain 522 is taken as the second input end, and the selection gate 524 is taken as the third input end:

[0081] The third voltage signal corresponding to the selection gate 524 can be set to two voltage states of 1.0V and -1.2V; when the third voltage signal is 1.0V, the control variable is 1; when the third voltage signal is -1.2V, the control variable is 0.

[0082] The first voltage signal corresponding to the control gate can be set to two voltage states of 0.8V and -2.0V; when the first voltage signal is 0.8V, the input variable corresponding to the first voltage signal is 1; when the first voltage signal is -2.0V, the input variable corresponding to the first voltage signal is 0.

[0083] The second voltage signal corresponding to the drain 522 can be set to two voltage states of 1.0V and 0V; when the second voltage signal is 1.0V, the input variable corresponding to the second voltage signal is 1; when the second voltage signal is 0V, the input variable corresponding to the second voltage signal is 0.

[0084] The amount of holes stored on the semi-floating gate 525 is adjusted according to the first voltage signal, the second voltage signal and the third voltage signal; when there is no hole stored on the semi-floating gate 525, the channel of the semi-floating gate transistor 520 is turned off, and the read current obtained represents that the operation result / storage variable of the semi-floating gate 525 is 0; when there is a hole stored on the semi-floating gate 525, the channel of the semi-floating gate transistor 520 is turned on, and the read current obtained represents that the operation result / storage variable of the semi-floating gate 525 is 1.

[0085] When the control variable is 1, the target formula is used to perform logical operation, and the logical operation result is shown in Table 1 as follows:

[0086] Table 1: Logical operation table when the control variable is 1:

[0087]

[0088]

[0089] When the control variable is 0, the target formula is used to perform logical operation, and the logical operation result is shown in Table 2 as follows:

[0090] Table 2: Logical operation table when the control variable is 0:

[0091] [T1] [T2] V CG ]]> V D ]]> Z' Z 0 0 -2.0V 0V 0 0 0 1 -2.0V 1.0V 0 1 1 0 0.8V 0V 0 0 1 1 0.8V 1.0V 0 0 0 0 -2.0V 0V 1 1 0 1 -2.0V 1.0V 1 1 1 0 0.8V 0V 1 1 1 1 0.8V 1.0V 1 1

[0092] In the above Table 1 and Table 2, in one period, T1 is the input variable corresponding to the first voltage signal; T2 is the input variable corresponding to the second voltage signal; V CG is the voltage value of the first voltage signal; V D is the voltage value of the second voltage signal; Z' is the storage variable indicated by the voltage of the semi-floating gate 525 in the last period; Z is the operation result indicated by the semi-floating gate 525 in the current period. By selecting the target formula and the input voltage value, the corresponding logical operation function can be realized.

[0093] Exemplarily, inFigure 10B Taking the implementation mode of selecting the gate 524 as the first input terminal, the drain 522 as the second input terminal, and the control gate 523 as the third input terminal as an example:

[0094] The third voltage signal corresponding to the control gate 523 can be set to two voltage states of 0.8 V and -2.0 V; when the third voltage signal is 0.8 V, the control variable is 1; and when the third voltage signal is -2.0 V, the control variable is 0.

[0095] The first voltage signal corresponding to the select gate 524 can be set to two voltage states of 1 V and -1.2 V; when the first voltage signal is 1 V, the input variable corresponding to the first voltage signal is 1; and when the first voltage signal is -1.2 V, the input variable corresponding to the first voltage signal is 0.

[0096] The second voltage signal corresponding to the drain 522 can be set to two voltage states of 1.0 V and 0 V; when the second voltage signal is 1.0 V, the input variable corresponding to the second voltage signal is 1; and when the second voltage signal is 0 V, the input variable corresponding to the second voltage signal is 0.

[0097] The amount of holes stored on the semi-floating gate 525 is adjusted according to the first voltage signal, the second voltage signal, and the third voltage signal; when there is no hole stored on the semi-floating gate 525, the channel of the semi-floating gate transistor 520 is turned off, and the read current obtained represents that the operation result / stored variable of the semi-floating gate 525 is 0; when there is a hole stored on the semi-floating gate 525, the channel of the semi-floating gate transistor 520 is turned on, and the read current obtained represents that the operation result / stored variable of the semi-floating gate 525 is 1.

[0098] When the control variable is 1, the target formula is used to perform a logical operation, and the existing logical operation result is shown in Table 3.

[0099] Table 3: Logical operation table when the control variable is 1

[0100] [["t1", "t1"]] [T2] V SG ]]> V D ]]> Z' Z 0 0 -1.2V 0V 0 0 0 1 -1.2V 1.0V 0 0 1 0 1V 0V 0 0 1 1 1V 1.0V 0 0 0 0 -1.2V 0V 1 1 0 1 -1.2V 1.0V 1 1 1 0 1V 0V 1 0 1 1 1V 1.0V 1 1

[0101] When the control variable is 0, the target formula is used to perform a logical operation, and the existing logical operation result is shown in Table 4.

[0102] Table 4: Logical operation table when the control variable is 0

[0103] [T1] [T2] V SG ]]> V D ]]> Z' Z 0 0 -1.2V 0V 0 0 0 1 -1.2V 1.0V 0 1 1 0 1V 0V 0 0 1 1 1V 1.0V 0 0 0 0 -1.2V 0V 1 1 0 1 -1.2V 1.0V 1 1 1 0 1V 0V 1 1 1 1 1V 1.0V 1 1

[0104] Exemplarily, the access voltage of each port in the operation of implementing the write 1 operation, the write 0 operation, the storage operation, the read data operation and the erase data operation based on the above-mentioned semi-floating gate transistor 520 is shown in Table 5 as follows:

[0105] Table 5: Example of access voltage of each port

[0106]

[0107] In Table 5, V CG is the voltage input to the control gate 523, V SG is the voltage input to the select gate 524, V D is the voltage input to the drain 522, and V S is the voltage input to the source 521.

[0108] The embodiment of the present application sets the third voltage signal to correspond to the encoding control variable being 0 or 1; encodes the respective input variables with different voltage values of the first voltage signal and different voltage values of the second voltage signal, and encodes the corresponding storage variable with the voltage value of the semi-floating gate 525 determined in the above-mentioned period. The voltage state of the semi-floating gate 525 is changed by the first voltage signal, the second voltage signal and the third voltage signal. According to the voltage state on the semi-floating gate 525, the channel of the semi-floating gate transistor 525 will exist in two states of off and on, thereby obtaining different read currents. The different read currents in the two cases of channel off and on are encoded, and the operation result of the target formula is obtained. Through the above-mentioned setting, the embodiment of the present application realizes the storage of data by the semi-floating gate transistor 520 based on the storage-computing integrated memory 500, and uses the semi-floating gate transistor 520 to perform logical operation processing on the stored data, and then stores the operation result obtained by the logical operation processing in the semi-floating gate 525 of the semi-floating gate transistor 520. On the basis of not reducing the storage capacity of the storage-computing integrated memory 500, fast and complete logical operation is realized.

[0109] The storage-computing integrated memory 500 including the semi-floating gate transistor 520 as shown in Figure 10A and Figure 10B may be used to perform the method as shown in Figure 11 .

[0110] S110, initializing the storage variable of the voltage indication of the semi-floating gate 525.

[0111] S120, outputting the first voltage signal to the first input end, outputting the second voltage signal to the second input end, and outputting the third voltage signal indicating the control variable to the third input end; adjusting the voltage indication operation result of the semi-floating gate 525 through the first voltage signal, the second voltage signal and the third voltage signal.

[0112] S130, outputting the fourth power signal through the source 521 of the semi-floating gate transistor 520; the fourth power signal is the read current, used to indicate the operation result.

[0113] The semi-floating gate transistor 520 shown in the above Figure 10A and Figure 10B The semi-floating gate transistor 520 shown in the above

[0114] Table 6: Sixteen kinds of Boolean logic operation schematic table

[0115]

[0116] In some embodiments, the initialization operation mentioned in the above step S110 includes a first initialization of initializing the operation result indicated by the voltage of the semi-floating gate 525 to 0, and a second initialization of initializing the operation result indicated by the voltage of the semi-floating gate 525 to 1.

[0117] In some embodiments, the operation of the first initialization is to control the first voltage signal to indicate that the corresponding input variable is 1, control the second voltage signal to indicate that the corresponding input variable is 0, and control the third voltage signal to indicate that the control variable is 1, so that the operation result indicated by the voltage of the semi-floating gate is 0.

[0118] Exemplarily, in the implementation manner of Figure 10A selecting the gate 524 as the first input end, the drain 522 as the second input end, and the control gate 523 as the third input end.

[0119] The voltage value of the first voltage signal is 0.8V, and the corresponding input variable is 1; the voltage value of the second voltage signal is 0V, and the corresponding input variable is 0; the voltage value of the third voltage signal is 1.0V, and the corresponding control variable is 1, so the target formula is performed. At this time, the input variable corresponding to the first voltage signal is 1, and after taking the complement, it is 0; the input variable corresponding to the second voltage is 0; the result of the logical "or" operation of the two is 0. At this time, whether the value of the storage variable Z' is 1 or 0, the operation result obtained by performing the logical "and" operation with 0 is 0. In this way, the first initialization operation can be completed, that is, the operation of writing Z=0 as shown in Table 6, and it represents the operation logic as FALSE.

[0120] In some embodiments, the operation of the second initialization is to control the first voltage signal to indicate that the corresponding input variable is 0, control the second voltage signal to indicate that the corresponding input variable is 1, and control the third voltage signal to indicate that the control variable is 0, so that the operation result indicated by the voltage of the semi-floating gate 525 is 1.

[0121] Exemplarily, the first input end is the gate 524, the second input end is the drain 522, and the third input end is the control gate 523. Figure 10A Exemplarily, the first input end is the gate 524, the second input end is the drain 522, and the third input end is the control gate 523.

[0122] The voltage value of the first voltage signal is -2.0V, and the corresponding input variable is 0; the voltage value of the second voltage signal is 1V, and the corresponding input variable is 1; the voltage value of the third voltage signal is -1.2V, and the corresponding control variable is 0. The target formula is The logic operation is performed. At this time, the input variable corresponding to the first voltage signal is 0, and after taking the NOT operation, it is 1; the input variable corresponding to the second voltage signal is 1; and the result of the logic AND operation of the two is 1. At this time, whether the value of the storage variable Z' is 1 or 0, the operation result of the logic OR operation of the two is 1. In this way, the second initialization operation, that is, the operation of writing Z=1 or the operation of erasing data as shown in Table 6, can be completed, and the representative operation logic is TRUE.

[0123] In some embodiments, the operation of storing the first input variable into the semi-floating gate 525 is as follows:

[0124] First, the first initialization is performed.

[0125] Then, the first operation is performed: the first voltage signal is controlled to indicate that the corresponding input variable is 0, the second voltage signal is controlled to indicate the first input variable, and the third voltage signal is controlled to indicate that the control variable is 0, so that the voltage of the semi-floating gate 525 indicates the operation result of the first input variable.

[0126] Exemplarily, as shown in Table 6, after the first initialization, the storage variable corresponding to the semi-floating gate 525 is 0. At this time, based on the storage variable of 0, the third voltage signal corresponding to the input control variable of 0 is input, and the target formula the first operation is performed, the first input variable p is input through the second voltage signal, and the input variable of 0 is input through the first voltage signal. In the target formula, the input variable corresponding to the first voltage signal is taken to be 1, and then the logic AND operation of 1 and the first input variable p is performed to obtain the first input variable p. Finally, the logic OR operation of the first input variable p and the storage variable Z' of 0 is performed, so that the final operation result is the first input variable p, that is, the operation of storing the first input variable p into the semi-floating gate 525 is completed, that is, Z=p. Similarly, if there is a second input variable q, the operation can also be used to store the second input variable q into the semi-floating gate 525, that is, Z=q.

[0127] In some implementations, the logical NOT operation on the first and second input variables, as shown in Table 6, is as follows:

[0128] First, perform the initialization.

[0129] Then, the first operation is performed: the first voltage signal is controlled to indicate the first input variable, the second voltage signal is controlled to indicate the corresponding input variable as 1, and the third voltage signal is controlled to indicate the control variable as 0, so that the voltage of the semi-floating gate 525 is used to indicate the first input variable through a logical "NOT" operation.

[0130] For example, as shown in Table 6, after the first initialization, the storage variable corresponding to the semi-floating gate 525 is 0. At this time, based on the storage variable being 0, the third voltage signal corresponding to the input control variable being 0 is used, and the target formula is applied. The first calculation is performed by inputting the first input variable p through the first voltage signal and the input variable that is 1 through the second voltage signal. In the target formula, the first input variable p is negated to obtain... Then, the 1 corresponding to the second voltage signal is compared with the first input variable p after being negated. Perform a logical AND operation to obtain Finally, a logical OR operation is performed with the stored variable Z', which is 0, to make the final result... This completes the process of storing the data obtained by performing a logical NOT operation on the first input variable p in the semi-floating gate 525. Right now Similarly, if there is a second input variable q, this operation can also be used to store the data after negating the second input variable q in the semi-floating gate 525. Right now

[0131] In some implementations, the logical OR operation performed on the first and second input variables as shown in Table 6 is as follows:

[0132] First, perform the initialization.

[0133] Then, the first calculation is performed: the first voltage signal is controlled to indicate that the corresponding input variable is 0, the second voltage signal is controlled to indicate that the first input variable is 0, and the third voltage signal is controlled to indicate that the control variable is 0.

[0134] For example, as shown in Table 6, after the first initialization, the current stored variable Z' is 0; at this time, the control variable is 0, and the target formula is used. In the first calculation, the input variable of the first voltage signal is negated to 1, and the calculation result Z is the first input variable p.

[0135] Then, the second operation is performed: the first voltage signal is controlled to indicate the first input variable, the second voltage signal is controlled to indicate the second input variable, and the third voltage signal is controlled to indicate that the control variable is 0, so that the voltage of the semi-floating gate 525 is used to indicate that the first input variable and the second input variable are subjected to a logical "or" operation.

[0136] For example, as shown in Table 6, the operation result Z obtained after the first operation is the first input variable p, which is used as the storage variable Z' of the second operation, and at this time, the control variable is 0, and the target formula The logical operation is performed. The first voltage signal corresponding to the input variable is negated to obtain data 1, and the data 1 and the second input variable q are subjected to a logical "and" operation to obtain the second input variable q, and then the second input variable q is subjected to a logical "or" operation with the storage variable Z' which is the first input variable p, that is, Z = p + q.

[0137] In some embodiments, the operation of performing a logical "XOR" operation on the first input variable and the second input variable as shown in Table 6 is as follows:

[0138] First, the first initialization is performed.

[0139] Then, the first operation is performed: the first voltage signal is controlled to indicate the first input variable, the second voltage signal is controlled to indicate the second input variable, and the third voltage signal is controlled to indicate that the control variable is 0.

[0140] For example, as shown in Table 6, after the first initialization, the current storage variable Z' is 0; at this time, the control variable is 0, and the target formula The first operation is performed, and the first input variable p is negated and subjected to a logical "and" operation with the second input variable q, and then the result is subjected to a logical "or" operation with the storage variable Z' which is 0, to obtain the operation result Z indicating that the first input variable p is negated and subjected to a logical "and" operation with the second input variable q.

[0141] Then, the second operation is performed: the first voltage signal is controlled to indicate the second input variable, the second voltage signal is controlled to indicate the first input variable, and the third voltage signal is controlled to indicate that the control variable is 0, so that the voltage of the semi-floating gate 525 is used to indicate that the first input variable and the second input variable are subjected to a logical "XOR" operation.

[0142] For example, as shown in Table 6, the operation result Z of the first operation is used as the storage variable Z' of the second operation, that is, the storage variable Z' is the operation result indicating that the first input variable p is negated and subjected to a logical "and" operation with the second input variable q; at this time, the control variable is 0, and the target formula The second input variable q is taken after the logical AND operation with the result of the logical AND operation of the first input variable p and the current storage variable Z', and the logical OR operation with the current storage variable Z' is performed to obtain the operation result of the logical XOR operation of the first input variable p and the second input variable q, that is

[0143] In some embodiments, the operation of the logical NOR operation of the first input variable and the second input variable is as shown in Table 6:

[0144] First, the first initialization is performed.

[0145] Then, the first operation is performed: the first voltage signal is controlled to indicate the first input variable, the second voltage signal is controlled to indicate the corresponding input variable as 1, and the third voltage signal is controlled to indicate the control variable as 0.

[0146] Exemplarily, as shown in Table 6, after the first initialization, the current storage variable Z' is 0; at this time, the control variable is 0, and the target formula The first operation is performed: the first input variable p after the logical NOT operation is taken after the logical AND operation with the input variable 1 corresponding to the second voltage signal to obtain the first input variable p after the logical NOT operation. The first input variable p after the logical NOT operation is taken after the logical OR operation with the storage variable Z' being 0 to obtain the operation result of the first input variable p after the logical NOT operation

[0147] Then, the second operation is performed: the first voltage signal is controlled to indicate the second input variable, the second voltage signal is controlled to indicate the corresponding input variable as 0, and the third voltage signal is controlled to indicate the control variable as 1, so that the voltage of the half-floating gate 525 is used to indicate the logical NOR operation of the first input variable and the second input variable.

[0148] Exemplarily, as shown in Table 6, the operation result Z of the first operation is taken as the storage variable Z' of the second operation, that is, the storage variable Z' is the operation result of the first input variable p after the logical NOT operation At this time, the control variable is 1, and the target formula The second operation is performed: the second input variable q after the logical NOT operation is taken after the logical OR operation with the input variable 0 corresponding to the second voltage signal to obtain the second input variable q after the logical NOT operation And the logical AND operation with the storage variable Z' is performed, that is The first input variable p after the logical NOT operation and the second input variable q after the logical NOT operation The logical AND operation is performed, that is, the logical NOR operation of the first input variable p and the second input variable q is performed, that is

[0149] In some embodiments, the operation of performing a logical AND operation on the first input variable and the second input variable as shown in Table 6 is:

[0150] First, a first initialization is performed.

[0151] Then, a first operation is performed: the first voltage signal is controlled to indicate that the corresponding input variable is 0, the second voltage signal is controlled to indicate the first input variable, and the third voltage signal is controlled to indicate that the control variable is 0.

[0152] Exemplarily, as shown in Table 6, after the first initialization, the current storage variable Z' is 0; at this time, the control variable is 0, and the target formula the first operation is performed; the input first input variable p is 1 after taking the NOT operation, and the first input variable p is obtained after performing a logical AND operation with the first input variable p, and the first input variable p is 0 after performing a logical OR operation with the storage variable Z' which is 0, and the operation result Z indicating the first input variable p is obtained.

[0153] Then, a second operation is performed: the first voltage signal is controlled to indicate that the corresponding input variable is 1, the second voltage signal is controlled to indicate the second input variable, and the third voltage signal is controlled to indicate that the control variable is 1, so that the voltage of the half-floating gate 525 is used to indicate that the first input variable and the second input variable have undergone a logical AND operation.

[0154] Exemplarily, as shown in Table 6, the operation result Z of the first operation is taken as the storage variable Z' of the second operation, that is, the storage variable Z' is the first input variable p; at this time, the control variable is 1, and the target formula the second operation is performed; the first voltage signal corresponding to the input variable 1 is 0 after taking the NOT operation, and the second input variable q is obtained after performing a logical OR operation with the second input variable q, and the second input variable q is obtained after performing a logical AND operation with the storage variable Z' indicating the first input variable p, that is, Z=pq.

[0155] In some embodiments, the operation of performing a logical NAND operation on the first input variable and the second input variable as shown in Table 6 is:

[0156] First, a first initialization is performed.

[0157] Then, a first operation is performed: the first voltage signal is controlled to indicate the first input variable, the second voltage signal is controlled to indicate that the corresponding input variable is 1, and the third voltage signal is controlled to indicate that the control variable is 0.

[0158] Exemplarily, as shown in Table 6, after the first initialization, the current storage variable Z' is 0; at this time, the control variable is 0, and the target formula The first operation is performed; the first input variable p is subjected to a logical "and" operation with the input variable 1 corresponding to the second voltage signal, and the first input variable p after being subjected to logical negation is obtained. The first input variable p after being subjected to logical negation is subjected to a logical "or" operation with the storage variable Z' being 0, and the operation result indicating the first input variable p after being subjected to logical negation is obtained.

[0159] Then, the second operation is performed: the first voltage signal is controlled to indicate the second input variable, the second voltage signal is controlled to indicate the corresponding input variable being 1, and the third voltage signal is controlled to indicate the control variable being 0, so that the voltage of the semi-floating gate 525 is used to indicate that the first input variable and the second input variable are subjected to logical "and non" operation.

[0160] Exemplarily, as shown in Table 6, the operation result Z of the first operation is taken as the storage variable Z' of the second operation, that is, the storage variable Z' is the first input variable p after being subjected to logical negation; at this time, the control variable is 0, and the target formula The second operation is performed. The first input variable p after being subjected to logical negation is subjected to a logical "and" operation with the input variable 1 corresponding to the second voltage signal, and the operation result indicating the first input variable p and the second input variable q subjected to logical "and non" operation is obtained. The operation result indicating the first input variable p and the second input variable q subjected to logical "and non" operation is obtained.

[0161] In some embodiments, the operation of performing logical "non-implication" (NIMP) operation or logical "reverse non-implication" (RNIMP) operation on the first input variable and the second input variable as shown in Table 6 is as follows:

[0162] First, the first initialization is performed.

[0163] Then, the first operation is performed: the first voltage signal is controlled to indicate the second input variable, the second voltage signal is controlled to indicate the first input variable, and the third voltage signal is controlled to indicate the control variable being 0, so that the voltage of the semi-floating gate 525 is used to indicate that the second input variable after being subjected to logical "non" operation is subjected to a logical "and" operation with the first input variable.

[0164] Exemplarily, as shown in Table 6, after the first initialization is performed, the current storage variable Z' is 0; when the first input variable is p and the second input variable is q, the logical "non-implication" (NIMP) operation is performed, that is, At this time, the control variable is 0, and the target formula ​​Perform the first operation; after inverting the second input variable p, perform a logical AND operation with the first input variable q to obtain the result Z of the implied NOT (NIMP) operation between the first input variable p and the second input variable q, i.e.

[0165] For example, as shown in Table 6, after the first initialization, the current stored variable Z' is 0; when the first input variable is q and the second input variable is p, the logical "inverse implied NOT (RNIMP)" operation is performed, that is... At this point, the control variable is 0, and the target formula is used. Perform the first operation; after inverting the second input variable p, perform a logical AND operation with the first input variable q to obtain the result Z of the inverse implied NOT (RNIMP) operation between the first input variable q and the second input variable p, i.e.

[0166] In some implementations, the operation of performing a logical "XNOR" operation on the first and second input variables as shown in Table 6 is as follows:

[0167] First, perform the second initialization.

[0168] Then, the first calculation is performed: the first voltage signal is controlled to indicate the first input variable, the second voltage signal is controlled to indicate the second input variable, and the third voltage signal is controlled to indicate that the control variable is 1.

[0169] For example, as shown in Table 6, after the second initialization, the current stored variable Z' is 1; at this time, the control variable is 1, and the target formula is used. Perform the first calculation; after inverting the first input variable p, we get... Perform a logical OR operation with the second input variable q to obtain the indication. The result of the calculation.

[0170] Then, a second operation is performed: the first voltage signal is controlled to indicate the second input variable, the second voltage signal is controlled to indicate the first input variable, and the third voltage signal is controlled to indicate the control variable as 1, so that the voltage of the semi-floating gate 525 is used to indicate the first input variable and the second input variable through a logical "XNOR" operation.

[0171] For example, as shown in Table 6, the result Z of the first operation is used as the storage variable Z' for the second operation, that is, the storage variable Z' is... At this point, the control variable is 1, and the target formula is used. Perform the second operation; after negating the second input variable q, we get... Then, the operation result of Then, the operation result of is performed, and the logical "XOR" operation is completed, i.e.

[0172] In some embodiments, the operation of the first input variable and the second input variable is performed by the logical "IMP" operation as shown in Table 6 or the logical "RIMP" operation as shown in Table 6.

[0173] First, the second initialization is performed.

[0174] Then, the first operation is performed: the first voltage signal indicates the first input variable, the second voltage signal indicates the second input variable, and the third voltage signal indicates the control variable is 1, so that the voltage of the semi-floating gate 525 is used to indicate the first input variable after the logical "NOT" operation and then the logical "OR" operation with the second input variable.

[0175] For example, as shown in Table 6, when the first input variable is p and the second input variable is q, the logical "IMP" operation is performed, i.e. After the second initialization operation, the storage variable Z' is 1; at this time, the control variable is 1, and the target formula is used to perform the first operation. The result of the logical "OR" operation of the first input variable p after the logical "NOT" operation and the second input variable q is logically "AND"ed with the storage variable Z' which is 1, to obtain the operation result of the logical "OR" operation of the first input variable p after the logical "NOT" operation and the second input variable q, i.e.

[0176] For example, as shown in Table 6, when the first input variable is q and the second input variable is p, the logical "RIMP" operation is performed, i.e. After the second initialization operation, the storage variable Z' is 1; at this time, the control variable is 1, and the target formula is used to perform the second operation. The result of the logical "OR" operation of the first input variable q after the logical "NOT" operation and the second input variable p is logically "AND"ed with the storage variable Z' which is 1, to obtain the operation result of the logical "OR" operation of the first input variable q after the logical "NOT" operation and the second input variable p, i.e.

[0177] ​​In summary, taking the variable p and the variable q as examples. Through the all-memory computing memory and the logic operation method provided in the embodiments of the present application, the storage data can be realized based on one half-floating gate transistor 520, the logic operation can be performed based on the data stored on the half-floating gate transistor 520, and the structure of the logic operation is stored on the half-floating gate transistor 520. Through the technical solutions described in the embodiments of the present application, the logic operation can be realized without reducing the storage capacity and the rate of processing data, and the processing and operation efficiency of the data is improved. At the same time, the present application does not need to rely on other devices, and can perform logic operation within three steps including initialization operation, and the logic operation that can be realized includes complete sixteen kinds of Boolean logic operations.

[0178] As shown in Figure 12 The embodiments of the present application also provide a chip system 600. The chip system 600 includes at least one processor 610 and at least one interface circuit 620. The at least one processor 610 and the at least one interface circuit 620 can be interconnected through a line. The processor 610 is configured to support the chip system to implement various functions or steps in the above method embodiments, and the at least one interface circuit 620 can be configured to receive signals from other devices (such as a memory) or send signals to other devices (such as a communication interface). The chip system can include a chip, and can also include other discrete devices.

[0179] The embodiments of the present application also provide a computer readable storage medium including instructions, when the instructions are executed on the above chip system or electronic device, the chip system or electronic device executes various functions or steps in the above method embodiments, for example, executes the method shown in Figure 11 .

[0180] The embodiments of the present application also provide a computer program product including instructions, when the instructions are executed on the above chip system or electronic device, the chip system or electronic device executes various functions or steps in the above method embodiments, for example, executes the method shown in Figure 11 .

[0181] The technical effects of the chip system, the computer readable storage medium, and the computer program product are referred to the technical effects of the above method embodiments.

[0182] The processor involved in the embodiments of the present application can be a chip. For example, it can be a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on chip (SoC), a central processing unit (CPU), a network processor (NP), a digital signal processor (DSP), a microcontroller unit (MCU), a programmable logic device (PLD) or other integrated chip.

[0183] It should be understood that the size of the sequence number of each process described above does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0184] Those of ordinary skill in the art can realize that the modules and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized in electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0185] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system, device and module described above can refer to the corresponding process in the foregoing method embodiments, which will not be repeated here.

[0186] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of the modules is only a logical function division, and actual implementation can have another division manner, for example, a plurality of modules or components can be combined or integrated into another device, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the shown or discussed each other can be through some interface, indirect coupling or communication connection between devices or modules, which can be electrical, mechanical or other forms.

[0187] The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, i.e., may be located in one device or distributed to multiple devices. Some or all of the modules can be selected according to actual needs to achieve the purpose of the embodiment.

[0188] In addition, the functional modules in each embodiment of the present application can be integrated in one device, or each module can be physically present alone, or two or more modules can be integrated in one device.

[0189] In the above embodiments, all or part can be implemented by software, hardware, firmware, or any combination thereof. When implemented by a software program, all or part can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions can be transferred from one website, computer, server, or data center to another website, computer, server, or data center through wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) manner. The computer-readable storage medium can be any available medium that a computer can access or include one or more data storage devices that can be integrated with the medium, such as servers, data centers, etc. The available medium can be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid state disk (SSD)), etc.

[0190] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. An in-memory computing memory, comprising: The memory array includes a controller and a storage array, each storage unit of the storage array being a semi-floating gate transistor; the semi-floating gate transistor includes a first input end, a second input end, a third input end and a semi-floating gate; the controller is configured to: output a first voltage signal to the first input end of the semi-floating gate transistor, output a second voltage signal to the second input end of the semi-floating gate transistor, and output a third voltage signal for indicating a control variable to the third input end of the semi-floating gate transistor; the third voltage signal is used to adjust a voltage induced state of the semi-floating gate; the control variable is used to indicate different voltage induced states of the semi-floating gate; the first voltage signal and the second voltage signal are used to adjust the voltage of the semi-floating gate in the different voltage induced states of the semi-floating gate; and the adjusted voltage of the semi-floating gate is used to indicate an operation result of logical operation between an input variable corresponding to the first voltage signal and an input variable corresponding to the second voltage signal.

2. The storage and computation integrated memory according to claim 1, wherein, The semi-floating gate transistor specifically includes a drain, a select gate, a control gate and a semi-floating gate located at the control gate; the select gate is the first input end, the control gate is the third input end, or the control gate is the first input end and the select gate is the third input end; and the drain is the second input end.

3. The storage-in-memory (SIM) device of claim 2, wherein, In two adjacent periods: the voltage of the semi-floating gate in the latter period is determined by the first voltage signal, the second voltage signal, the third voltage signal and the voltage of the semi-floating gate in the former period; the voltage of the semi-floating gate in the former period is used to indicate a storage variable; and the voltage of the semi-floating gate in the latter period is used to indicate an operation result obtained after inputting the first voltage signal corresponding input variable, the second voltage signal corresponding input variable and the storage variable into a target formula; and the target formula is determined by the voltage induced state of the semi-floating gate.

4. The memory according to claim 3, wherein when the control variable is 1, the target formula is: when the control variable is 0, the target formula is: Wherein, Z' is the storage variable; Z is the operation result; T1 is the input variable corresponding to the first voltage signal; T1 is the input variable corresponding to the first voltage signal; T2 is the input variable corresponding to the second voltage signal.

5. The storage-in-memory (SIM) device of claim 4, wherein, The controller is configured to: control the first voltage signal to indicate that the corresponding input variable is 1, control the second voltage signal to indicate that the corresponding input variable is 0, and control the third voltage signal to indicate that the control variable is 1, so that the voltage of the semi-floating gate indicates that the operation result is 0, to perform first initialization on the semi-floating gate.

6. The storage-in-memory (SIM) device of claim 5, wherein, The controller is configured to: in a first period, perform the first initialization on the semi-floating gate; in a second period, control the first voltage signal to indicate that the corresponding input variable is 0, control the second voltage signal to indicate a first input variable, and control the third voltage signal to indicate that the control variable is 0, so that the voltage of the semi-floating gate indicates that the operation result is the first input variable.

7. The storage-in-memory (SIM) device of claim 5, wherein, The controller is configured to: in a first period, perform the first initialization on the semi-floating gate; In the second period, the first voltage signal is controlled to indicate a first input variable, the second voltage signal is controlled to indicate a corresponding input variable as 1, and the third voltage signal is controlled to indicate the control variable as 0, so that the operation result of the voltage indication of the semi-floating gate is a logical "NOT" operation on the first input variable. 8.The all-memory computing device of claim 5, wherein, The controller is configured to: in the first period, perform the first initialization on the semi-floating gate; in the second period, control the first voltage signal to indicate a corresponding input variable as 0, control the second voltage signal to indicate a first input variable, and control the third voltage signal to indicate the control variable as 0; in the third period, control the first voltage signal to indicate the corresponding input variable as 0, control the second voltage signal to indicate a second input variable, and control the third voltage signal to indicate the control variable as 0, so that the operation result of the voltage indication of the semi-floating gate is a logical "OR" operation on the first input variable and the second input variable. 9.The all-memory computing device of claim 5, wherein, The controller is configured to: in the first period, perform the first initialization on the semi-floating gate; in the second period, control the first voltage signal to indicate a first input variable, control the second voltage signal to indicate a second input variable, and control the third voltage signal to indicate the control variable as 0; in the third period, control the first voltage signal to indicate the second input variable, control the second voltage signal to indicate the first input variable, and control the third voltage signal to indicate the control variable as 0, so that the operation result of the voltage indication of the semi-floating gate is a logical "XOR" operation on the first input variable and the second input variable.

10. The storage-in-memory (SIM) device of claim 5, wherein, The controller is configured to: in the first period, perform the first initialization on the semi-floating gate; in the second period, control the first voltage signal to indicate a first input variable, control the second voltage signal to indicate a corresponding input variable as 1, and control the third voltage signal to indicate the control variable as 0; in the third period, control the first voltage signal to indicate a second input variable, control the second voltage signal to indicate a corresponding input variable as 0, and control the third voltage signal to indicate the control variable as 1, so that the operation result of the voltage indication of the semi-floating gate is a logical "OR NOT" operation on the first input variable and the second input variable.

11. The storage-in-memory (SIM) device of claim 5, wherein, The controller is configured to: in the first period, perform the first initialization on the semi-floating gate; in the second period, control the first voltage signal to indicate a corresponding input variable as 0, control the second voltage signal to indicate a first input variable, and control the third voltage signal to indicate the control variable as 0; In the third period, the first voltage signal is controlled to indicate the corresponding input variable as 1, the second voltage signal is controlled to indicate the second input variable, and the third voltage signal is controlled to indicate the control variable as 1, so that the operation result of the voltage indication of the semi-floating gate is a logical AND operation of the first input variable and the second input variable.

12. The storage-in-memory (SIM) device of claim 5, wherein, The controller is configured to: in the first period, perform the first initialization on the semi-floating gate; in the second period, control the first voltage signal to indicate a first input variable, control the second voltage signal to indicate the corresponding input variable as 1, and control the third voltage signal to indicate the control variable as 0; in the third period, control the first voltage signal to indicate a second input variable, control the second voltage signal to indicate the corresponding input variable as 1, and control the third voltage signal to indicate the control variable as 0, so that the operation result of the voltage indication of the semi-floating gate is a logical AND NOT operation of the first input variable and the second input variable.

13. The storage-in-memory (SIM) device of claim 5, wherein, The controller is configured to: in the first period, perform the first initialization on the semi-floating gate; in the second period, control the first voltage signal to indicate a second input variable, control the second voltage signal to indicate a first input variable, and control the third voltage signal to indicate the control variable as 0, so that the operation result of the voltage indication of the semi-floating gate is a logical NOT operation on the second input variable and then a logical AND operation with the first input variable. 14.The all-memory computing device of claim 4, wherein, The controller is configured to: control the first voltage signal to indicate the corresponding input variable as 0, control the second voltage signal to indicate the corresponding input variable as 1, and control the third voltage signal to indicate the control variable as 0, so that the operation result of the voltage indication of the semi-floating gate is 1, to perform the second initialization on the semi-floating gate.

15. The storage-in-memory (SIM) device of claim 14, wherein, The controller is configured to: in the first period, perform the second initialization on the semi-floating gate; in the second period, control the first voltage signal to indicate a first input variable, control the second voltage signal to indicate a second input variable, and control the third voltage signal to indicate the control variable as 1; in the third period, control the first voltage signal to indicate the second input variable, control the second voltage signal to indicate the first input variable, and control the third voltage signal to indicate the control variable as 1, so that the operation result of the voltage indication of the semi-floating gate is a logical XOR operation of the first input variable and the second input variable.

16. The storage-in-memory (SIM) device of claim 14, wherein, The controller is configured to: in the first period, perform the second initialization on the semi-floating gate; in the second period, control the first voltage signal to indicate a first input variable, control the second voltage signal to indicate a second input variable, and control the third voltage signal to indicate the control variable as 1, so that the operation result of the voltage indication of the semi-floating gate is a logical NOT operation on the first input variable and then a logical OR operation with the second input variable.

17. The storage-in-memory (SIM) device of any one of claims 1-16, wherein, The semi-floating gate transistor further comprises a source; The source is configured to output a fourth power signal; and the fourth power signal is configured to indicate an operation result indicated by a voltage of the semi-floating gate.

18. A method of logical operation, characterized by, The application is applied to a memory-computing integrated memory; the memory-computing integrated memory comprises a controller and a memory array; each memory cell of the memory array is a semi-floating gate transistor; the semi-floating gate transistor comprises a first input end, a second input end, a third input end and a semi-floating gate. The method comprises: outputting a first voltage signal to the first input end of the semi-floating gate transistor, outputting a second voltage signal to the second input end of the semi-floating gate transistor, and outputting a third voltage signal for indicating a control variable to the third input end of the semi-floating gate transistor; The third voltage signal is configured to adjust a voltage sensing state of the semi-floating gate; the control variable is configured to indicate different voltage sensing states of the semi-floating gate; the first voltage signal and the second voltage signal are configured to adjust the voltage of the semi-floating gate in the different voltage sensing states of the semi-floating gate; and the adjusted voltage of the semi-floating gate is configured to indicate an operation result of logical operation between an input variable corresponding to the first voltage signal and an input variable corresponding to the second voltage signal.

19. The method of claim 18, wherein, The semi-floating gate transistor specifically comprises a drain, a select gate, a control gate and a semi-floating gate located at the control gate; the select gate is the first input end, the control gate is the third input end, or the control gate is the first input end and the select gate is the third input end; and the drain is the second input end.

20. The method of claim 19, wherein, The method specifically comprises: In two adjacent periods: In the latter period, the voltage of the semi-floating gate is determined by the first voltage signal, the second voltage signal, the third voltage signal and the voltage of the semi-floating gate in the former period; In the former period, the voltage of the semi-floating gate is configured to indicate a storage variable; and in the latter period, the voltage of the semi-floating gate is configured to indicate an operation result obtained after inputting an input variable corresponding to the first voltage signal, an input variable corresponding to the second voltage signal and the storage variable into a target formula; and the target formula is determined by the voltage sensing state of the semi-floating gate.

21. The method of claim 20, wherein when the control variable is 1, the target formula is: when the control variable is 0, the target formula is: Wherein, Z' is the storage variable; Z is the operation result; T1 is the input variable corresponding to the first voltage signal; T1 is the input variable corresponding to the first voltage signal; T2 is the input variable corresponding to the second voltage signal.

22. The method of claim 21, wherein, Further comprising: controlling the first voltage signal to indicate that the corresponding input variable is 1, controlling the second voltage signal to indicate that the corresponding input variable is 0, and controlling the third voltage signal to indicate that the control variable is 1, so that the operation result indicated by the voltage of the semi-floating gate in the latter period is 0, thereby performing first initialization on the semi-floating gate.

23. The method of claim 22, wherein, Further comprising: in a first period, performing the first initialization on the semi-floating gate; In the second period, the first voltage signal is controlled to indicate the corresponding input variable is 0, the second voltage signal is controlled to indicate the first input variable, and the third voltage signal is controlled to indicate the control variable is 0, so that the operation result of the voltage indication of the semi-floating gate is the first input variable.

24. The method of claim 22, wherein, Further comprising: In the first period, the first initialization is performed on the semi-floating gate; In the second period, the first voltage signal is controlled to indicate the first input variable, the second voltage signal is controlled to indicate the corresponding input variable is 1, and the third voltage signal is controlled to indicate the control variable is 0, so that the operation result of the voltage indication of the semi-floating gate is the logical "not" operation on the first input variable.

25. The method of claim 22, wherein, Further comprising: In the first period, the first initialization is performed on the semi-floating gate; In the second period, the first voltage signal is controlled to indicate the corresponding input variable is 0, the second voltage signal is controlled to indicate the first input variable, and the third voltage signal is controlled to indicate the control variable is 0; In the third period, the first voltage signal is controlled to indicate the corresponding input variable is 0, the second voltage signal is controlled to indicate the second input variable, and the third voltage signal is controlled to indicate the control variable is 0, so that the operation result of the voltage indication of the semi-floating gate is the logical "or" operation on the first input variable and the second input variable.

26. The method of claim 22, wherein, Further comprising: In the first period, the first initialization is performed on the semi-floating gate; In the second period, the first voltage signal is controlled to indicate the first input variable, the second voltage signal is controlled to indicate the second input variable, and the third voltage signal is controlled to indicate the control variable is 0; In the third period, the first voltage signal is controlled to indicate the second input variable, the second voltage signal is controlled to indicate the first input variable, and the third voltage signal is controlled to indicate the control variable is 0, so that the operation result of the voltage indication of the semi-floating gate is the logical "exclusive or" operation on the first input variable and the second input variable.

27. The method of claim 22, wherein, Further comprising: In the first period, the first initialization is performed on the semi-floating gate; In the second period, the first voltage signal is controlled to indicate the first input variable, the second voltage signal is controlled to indicate the corresponding input variable is 1, and the third voltage signal is controlled to indicate the control variable is 0; In the third period, the first voltage signal is controlled to indicate the second input variable, the second voltage signal is controlled to indicate the corresponding input variable is 0, and the third voltage signal is controlled to indicate the control variable is 1, so that the operation result of the voltage indication of the semi-floating gate is the logical "or not" operation on the first input variable and the second input variable.

28. The method of claim 22, wherein, Further comprising: In the first period, the first initialization is performed on the semi-floating gate; In the second period, the first voltage signal is controlled to indicate the corresponding input variable is 0, the second voltage signal is controlled to indicate the first input variable, and the third voltage signal is controlled to indicate the control variable is 0; In the third period, the first voltage signal is controlled to indicate the corresponding input variable as 1, the second voltage signal is controlled to indicate the second input variable, and the third voltage signal is controlled to indicate the control variable as 1, so that the operation result of the voltage indication of the semi-floating gate is a logical "and" operation of the first input variable and the second input variable.

29. The method of claim 22, wherein, Further comprising: In the first period, the first initialization is performed on the semi-floating gate; In the second period, the first voltage signal is controlled to indicate the first input variable, the second voltage signal is controlled to indicate the corresponding input variable as 1, and the third voltage signal is controlled to indicate the control variable as 0; In the third period, the first voltage signal is controlled to indicate the second input variable, the second voltage signal is controlled to indicate the corresponding input variable as 1, and the third voltage signal is controlled to indicate the control variable as 0, so that the operation result of the voltage indication of the semi-floating gate is a logical "and not" operation of the first input variable and the second input variable.

30. The method of claim 22, wherein, Further comprising: In the first period, the first initialization is performed on the semi-floating gate; In the second period, the first voltage signal is controlled to indicate the second input variable, the second voltage signal is controlled to indicate the first input variable, and the third voltage signal is controlled to indicate the control variable as 0, so that the operation result of the voltage indication of the semi-floating gate is a logical "not" operation on the second input variable and then a logical "and" operation with the first input variable.

31. The method of claim 20, wherein, Further comprising: The first voltage signal is controlled to indicate the corresponding input variable as 0, the second voltage signal is controlled to indicate the corresponding input variable as 1, and the third voltage signal is controlled to indicate the control variable as 0, so that the operation result of the voltage indication of the semi-floating gate is 1, to perform the second initialization on the semi-floating gate.

32. The method of claim 31, wherein, Further comprising: In the first period, the second initialization is performed on the semi-floating gate; In the second period, the first voltage signal is controlled to indicate the first input variable, the second voltage signal is controlled to indicate the second input variable, and the third voltage signal is controlled to indicate the control variable as 1; In the third period, the first voltage signal is controlled to indicate the second input variable, the second voltage signal is controlled to indicate the first input variable, and the third voltage signal is controlled to indicate the control variable as 1, so that the operation result of the voltage indication of the semi-floating gate is a logical "exclusive or" operation of the first input variable and the second input variable.

33. The method of claim 31, wherein, Further comprising: In the first period, the second initialization is performed on the semi-floating gate; In the second period, the first voltage signal is controlled to indicate the first input variable, the second voltage signal is controlled to indicate the second input variable, and the third voltage signal is controlled to indicate the control variable as 1, so that the operation result of the voltage indication of the semi-floating gate is a logical "not" operation on the first input variable and then a logical "or" operation with the second input variable.

34. The method of any one of claims 18-33, wherein, The semi-floating gate transistor further comprises a source; the semi-floating gate transistor outputs a fourth power signal through the source; the fourth power signal is used to indicate an operation result indicated by the voltage of the semi-floating gate.

35. An electronic device, comprising: The computer readable storage medium comprises instructions which, when executed on the electronic device as claimed in claim 35, cause the electronic device to perform the method as claimed in any one of claims 18-34.

36. A computer-readable storage medium, characterized in that, ​

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