A memory and a method for manufacturing a memory

Abstract

The embodiment of the present application provides a memory, characterized by comprising a substrate, a first storage array and a first redundancy array; the first storage array comprises a stacked structure composed of at least one transistor and at least one capacitor unit, and the first storage array is used for storing data; the first storage array comprises a stacked structure composed of at least one transistor and at least one capacitor unit, the height of the first redundancy array relative to the substrate is same as that of the first storage array, and the stacked structure of the first redundancy array is same as that of the first storage array. By arranging the redundancy array with the same stacked structure around the storage array, the edge part and the surrounding environment of the central part of the storage array can be similar, so that the deviation of the critical dimension caused by optical reflection and diffraction in the photoetching process is avoided, and the structural uniformity of the memory can be improved.

Description

Technical Field

[0001] This application relates to the field of memory, and mainly to a memory and a method for manufacturing the memory. Background Technology

[0002] To meet the requirements of Design for Manufacturing (DFM), the uniformity and flatness of each dielectric layer in the chip must be ensured after the chemical mechanical planarization (CMP) process. To reduce manufacturing defects, redundant structures unrelated to layout versus schematic (LVS) checks are typically added to areas without metal interconnects in the design layout. Traditional back-end metal-layer-by-layer redundancy methods cannot maintain a sufficiently consistent environment around the memory array. Therefore, during photolithography, due to light reflection and diffraction characteristics, the critical dimension (CD) deviation at the edges of the memory array is significant. Furthermore, because the added redundant structures are difficult to align with the memory array pattern, a uniform density distribution between the redundant structures and the memory array cannot be guaranteed. This can lead to metal layer dishing and dielectric layer erosion after CMP, resulting in uneven interlayer dielectric (ILD) thickness.

[0003] How to avoid deviations in the critical dimensions of the memory array caused by the photolithography process and improve the uniformity of the memory structure has become an urgent problem to be solved. Summary of the Invention

[0004] This application provides a memory and a method for fabricating the memory, which can reduce the deviation of critical dimensions of the memory array in the photolithography process and improve the structural uniformity of the memory.

[0005] In a first aspect, a memory is provided. The memory includes: a substrate, a first memory array, and a first redundant array. The first memory array includes a stacked structure composed of at least one transistor and at least one capacitor cell, and the first memory array is used to store data; the first redundant array has the same height as the first memory array relative to the substrate, and the first redundant array includes a stacked structure composed of at least one transistor and at least one capacitor cell, and the stacked structure of the first redundant array is the same as the stacked structure of the first memory array.

[0006] In this embodiment, a redundant array with the same stacking structure as the memory array can be set at the height of the memory array. This makes the surrounding environment of the edge part of the memory array similar to that of the center part, thereby avoiding the deviation of critical dimensions caused by optical reflection and diffraction during the photolithography process and improving the structural uniformity of the memory.

[0007] In conjunction with the first aspect, in some implementations of the first aspect, the stacked structure of the first storage array and the first redundant array includes an mTnC structure, wherein the mTnC structure includes stacked m transistors and n capacitor units, where m and n are positive integers greater than or equal to 1.

[0008] In this embodiment, by setting up a memory array with an mTnC structure and a redundant array, the deviation of the critical dimensions of the memory array caused by the photolithography process can be avoided, and the structure distribution of the memory can be made more uniform.

[0009] In conjunction with the first aspect, in some implementations of the first aspect, at least one transistor of the first memory array is disposed on the same layer as at least one transistor of the first redundant array, and at least one capacitor cell of the first memory array is disposed on the same layer as at least one capacitor cell of the first redundant array.

[0010] It should be understood that the same layer refers to the same wiring layer, or the same multi-layer wiring layer.

[0011] In this embodiment, by setting the transistors of the memory array and the redundant array on the same layer, and setting the capacitor units of the memory array and the redundant array on the same layer, the stacking structure of the redundant array and the memory array is the same, thereby avoiding deviations caused by photolithography and improving the uniformity of the memory structure distribution.

[0012] In conjunction with the first aspect, in some implementations of the first aspect, the stacked structure of the first memory array and the first redundant array further includes at least one of the following structures: word line, bit line, board line plane or pillar; any one of at least one transistor is connected to the word line, bit line or pillar; or, any one of at least one capacitor cell is disposed at the intersection of the board line plane and the pillar.

[0013] In this embodiment, a redundant array of at least one structure including word lines, bit lines, board lines, planes, or pillars, as well as transistor and capacitor units, can be provided, thereby making the surrounding environment of the edge portion of the memory array more consistent with that of the center portion, avoiding errors caused by photolithography process, and improving the structural uniformity of the memory.

[0014] In conjunction with the first aspect, in some implementations of the first aspect, the first storage array is electrically connected to an external circuit outside the memory, and the first redundant array is configured in a circuit-free state or is not electrically connected to the circuit in the memory.

[0015] In this embodiment, although the redundant array has the same stacking structure as the storage array, it cannot store data because the redundant array is set in a circuit break or is not electrically connected to the circuit in the memory, i.e., it does not have the substantial function of storing data.

[0016] In conjunction with the first aspect, in some implementations of the first aspect, the memory further includes: a first metal structure, a first redundant structure, and a first via; the first metal structure and the first redundant structure have the same height relative to the substrate, and the height of the first redundant structure relative to the substrate is lower than the height of the first redundant array relative to the substrate; the first via is used to connect the first redundant structure and the first redundant array.

[0017] In this embodiment, by adding a first redundant structure at the same height as the first metal structure, the structure of the layer at the height of the first metal structure becomes more uniform, thereby reducing the undulation of the layer after the CMP process. Furthermore, by adding a first through-hole connecting the first redundant structure and the first redundant array, plasma generated during the process can be released, preventing damage to the device.

[0018] In conjunction with the first aspect, in some implementations of the first aspect, the memory further includes: a second metal structure, a second redundant structure, and a second via; the second metal structure and the second redundant structure have the same height relative to the substrate, and the height of the second redundant structure relative to the substrate is higher than the height of the first redundant array relative to the substrate; the second via is used to connect the second redundant structure and the first redundant array.

[0019] In this embodiment, by adding a second redundant structure at the same height as the second metal structure, the uniformity of the structure at the height of the second metal structure can be increased, thereby increasing the smoothness of the layer after the CMP process. Furthermore, by adding a second via connecting the second redundant structure and the first redundant array, a discharge channel can be provided for plasma generated during the process, improving the reliability of the device.

[0020] Secondly, a method for fabricating a memory is provided. The method includes: forming a substrate for the memory; forming a first memory array and a first redundant array at the same height relative to the substrate, the first memory array comprising a stacked structure consisting of at least one transistor and at least one capacitor cell, the first memory array being used to store data, and the first redundant array comprising a stacked structure consisting of at least one transistor and at least one capacitor cell, the stacked structure of the first redundant array being identical to the stacked structure of the first memory array.

[0021] In this embodiment, a first redundant array with the same stacking structure as the first memory array can be added at the same height as the first memory array to avoid deviations in critical dimensions caused by photolithography, thereby protecting the edge portion of the memory array and improving the structural uniformity of the memory.

[0022] In conjunction with the second aspect, in some implementations of the second aspect, the stacked structure of the first memory array and the first redundant array includes an mTnC structure, wherein the mTnC structure includes stacked m transistors and n capacitor units, where m and n are positive integers greater than or equal to 1.

[0023] In this embodiment, by forming a memory array and a redundant array with an mTnC structure, the deviation of the critical dimensions of the memory array caused by the photolithography process can be avoided, and the structure distribution of the memory can be made more uniform.

[0024] In conjunction with the second aspect, in some implementations of the second aspect, at least one transistor of the first memory array and at least one transistor of the first redundant array are formed in the same layer as the first memory array and the first redundant array; at least one capacitor cell of the first memory array and at least one capacitor cell of the first redundant array are formed in the same layer as the first memory array and the first redundant array.

[0025] In this embodiment, by forming transistors and capacitors in the same layer of the first memory array and the first redundant array, the stacking structure of the first memory array and the first redundant array is the same, thereby avoiding errors caused by photolithography and improving the uniformity of the memory structure distribution.

[0026] In conjunction with the second aspect, in some implementations of the second aspect, the stacked structure of the first memory array and the first redundant array further includes at least one of the following structures: word line, bit line, board line plane or pillar; any one of at least one transistor is connected to the word line, bit line or pillar; or, any one of at least one capacitor cell is disposed at the intersection of the board line plane and the pillar.

[0027] In this embodiment, a redundant array of at least one structure including word lines, bit lines, board lines, planes, or pillars, as well as transistor and capacitor units, can be formed, thereby making the surrounding environment of the edge portion and the center portion of the memory array more consistent, avoiding errors caused by photolithography process, and improving the structural uniformity of the memory.

[0028] In conjunction with the second aspect, in some implementations of the second aspect, the first storage array is electrically connected to an external circuit outside the memory, and the first redundant array is configured to be in a circuit break or not electrically connected to the circuit in the memory.

[0029] In this embodiment, although the redundant array has the same stacking structure as the storage array, it cannot store data because the redundant array is set in a circuit break or is not electrically connected to the circuit in the memory, i.e., it does not have the substantial function of storing data.

[0030] In conjunction with the second aspect, in some implementations of the second aspect, a first metal structure and a first redundant structure are formed at the same height relative to the substrate, wherein the height of the first redundant structure relative to the substrate is lower than the height of the first redundant array relative to the substrate; a first through-hole is formed, wherein the first through-hole is used to connect the first redundant structure and the first redundant array.

[0031] In this embodiment, a first redundant structure at the same height as the first metal structure can be formed, thereby making the structure of the layer at the same height as the first metal structure more uniform and reducing the undulation of the layer after the CMP process. Furthermore, a first via can be formed connecting the first redundant structure and the first redundant array to release plasma generated during the process, thus preventing damage to the device.

[0032] In conjunction with the second aspect, in some implementations of the second aspect, a second through-hole is formed to connect the second redundant structure and the first redundant array; the second metal structure and the second redundant structure are formed at the same height relative to the substrate, and the height of the second redundant structure relative to the substrate is higher than the height of the first redundant array relative to the substrate.

[0033] In this embodiment, a second redundant structure at the same height as the second metal structure can be formed, thereby increasing the uniformity of the structure at the same height as the second metal structure, and thus increasing the smoothness of the layer after the CMP process. Furthermore, a second via can be formed connecting the second redundant structure and the first redundant array, thereby providing a discharge channel for plasma generated during the process and improving the reliability of the device.

[0034] Thirdly, a memory is provided, including a controller and a first memory array and a first redundant array as described in the first aspect, wherein the controller is electrically connected to the first memory array.

[0035] Fourthly, an electronic device is provided, including a circuit board and a memory as described in the first aspect.

[0036] Fifthly, an electronic device is provided, including a circuit board and a memory as described in the third aspect. Attached Figure Description

[0037] Figure 1 This is a schematic cross-sectional view of a post-processed integrated ferroelectric memory.

[0038] Figure 2 This is a schematic diagram of a 1TnC memory array.

[0039] Figure 3 This is a schematic circuit diagram of a 1TnC memory array.

[0040] Figure 4 This is a schematic diagram of the erosion of the metal layer in a disc shape and the dielectric layer.

[0041] Figure 5 This is a schematic structural diagram of a memory 300 according to an embodiment of this application.

[0042] Figure 6 This is a schematic structural diagram of a memory 400 according to another embodiment of this application.

[0043] Figure 7 This is a schematic structural diagram of a memory 500 according to another embodiment of this application.

[0044] Figure 8 This is a schematic cross-sectional view of a memory with an added redundant array according to an embodiment of this application.

[0045] Figure 9 This is a schematic cross-sectional view of a memory with added through-holes according to an embodiment of this application.

[0046] Figure 10 This is a schematic flowchart illustrating a method for fabricating a memory according to an embodiment of this application.

[0047] Figure 11 This is a schematic flowchart illustrating a method for fabricating a memory according to another embodiment of this application. Detailed Implementation

[0048] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0049] The technical solutions of the embodiments of this application can be applied to various back-end integrated memories, such as back-end integrated ferroelectric random access memory (FRAM), back-end integrated static random access memory (SRAM), back-end integrated dynamic random access memory (DRAM), back-end integrated electrically erasable programmable read-only memory (EEPROM), etc., and the embodiments of this application are not limited to these.

[0050] The following description uses back-end integrated FRAM as an example, but the embodiments of this application can also be applied to the various back-end integrated memories described above.

[0051] Figure 1 This is a schematic cross-sectional view of a back-end integrated FRAM. Figure 1 This includes the front end of line (FEOL), through-hole (CONT), metal structure M1, through-hole V1, metal structure M2, through-hole V2, metal structure M3, through-hole V3, metal structure M4, through-hole V4, through-hole CONT1, memory array MC, through-hole CONT2, metal structure M5, through-hole V5, metal structure M6, through-hole V6, metal structure M7, through-hole V7, metal structure M8, through-hole V8, and aluminum pad (AP). Furthermore, Figure 1 It also includes two redundant structures DM1, through-hole DV1, two redundant structures DM2, two through-hole DV2, two redundant structures DM3, through-hole DV3, redundant structure DM4, redundant structure DM0, redundant structure DM5, through-hole DV5, two redundant structures DM6, redundant structure DM7, and redundant structure DM8.

[0052] Among them, any one of the metal structures M1 to M8 is used for electrical conductivity and can be a metal wire. Any one of the through-holes V1-V8, CONT, CONT1, and CONT2 includes a conductive material and can be used for electrical conductivity. Redundant structures DM1-DM8 and DM0 can be metal blocks, and the material of the redundant structure is similar to or the same as the material of the metal structure at the same height. For example, both DM1s are located at the same height layer as M1, and the materials of both DM1s are similar to or the same as the material of M1. Any one of the through-holes DV1-DV3 and DV5 includes a conductive material and can be used for electrical conductivity.

[0053] It should be understood that "the metal structure and the redundant structure are located at the same height or at the same height layer" is similar to "the metal structure and the redundant structure are at the same height relative to the substrate." Similarly, "the height or height layer where the metal structure is located is higher than the height or height layer where the redundant structure is located" is similar to "the height of the metal structure relative to the substrate is higher than the height of the redundant structure relative to the substrate."

[0054] It should also be understood that the height relative to the substrate is a range, not a specific value.

[0055] The front-end FEOL structure can be based on various substrate types, such as silicon substrates, bulk semiconductor substrates, semiconductor-on-insulator substrates, compound semiconductor substrates, etc., and this application does not limit this. Figure 1The cross-section shown is located at the lowest height layer. In actual fabrication, the height layer containing FEOL is lower than... Figure 1 The height layers shown, excluding FEOL, contain the other structures.

[0056] The via CONT is positioned between FEOL and the metal structure M1, meaning CONT is located in the direction from FEOL toward the memory array MC. CONT connects FEOL and M1 and also serves as a conductor. In actual fabrication, the layer containing CONT is higher than the layer containing FEOL; that is, CONT is higher than FEOL. It should be understood that the height of CONT can be interpreted as its height relative to FEOL.

[0057] Metal structure M1 is located in the direction from CONT towards the storage array MC. In actual manufacturing, the height layer of metal structure M1 is higher than the height layer of CONT, meaning M1 is higher than CONT. It should be understood that the height of M1 can be interpreted as the height of M1 relative to FEOL.

[0058] Both redundant structures DM1 are located at the same height level as the metal structure M1. In the actual manufacturing process, the height level of both DM1 is higher than the height level of CONT.

[0059] A via V1 is positioned between metal structures M1 and M2, meaning V1 is located on M1 facing the memory array MC. V1 connects M1 and M2 and also serves as a conductor. In actual fabrication, the layer containing V1 is higher than the layer containing M1.

[0060] Via DV1 is positioned between DM1 and DM2, and DV1 and via V1 are located at the same height level. DV1 is positioned between the two DM1s facing the memory array MC. In actual manufacturing, the height level of DV1 is higher than the height level of the two DM1s.

[0061] Metal structure M2 is located in the direction from V1 toward the storage array MC. In the actual manufacturing process, the height layer of metal structure M2 is higher than the height layer of V1.

[0062] Both redundant structures DM2 are located at the same height level as the metal structure M2. In actual manufacturing, the height level of the two DM2 structures is higher than that of DV1.

[0063] Through-hole V2 is located between metal structures M2 and M3, meaning V2 is positioned in the direction from M2 towards the memory array MC. V2 connects M2 and M3 and also serves as a conductor. In actual fabrication, the layer containing V2 is higher than the layer containing M2.

[0064] Either of the two vias DV2 is positioned between a redundant structure DM2 and a redundant structure DM3, and both DV2s and the via V2 are located at the same height level. Both DV2s are positioned in the direction from the two DM2s toward the memory array MC. In actual manufacturing, the height level of the two DV2s is higher than the height level of the two DM2s.

[0065] Metal structure M3 is located in the direction from V2 toward the storage array MC. In the actual manufacturing process, the height layer of metal structure M3 is higher than the height layer of V2.

[0066] The two redundant structures DM3 and the metal structure M3 are all located at the same height level. In the actual manufacturing process, the height level of the two DM3s is higher than the height level of the two DV2s.

[0067] Via V3 is positioned between metal structures M3 and M4, meaning V3 is located on M3 facing the memory array MC. V3 connects M3 and M4 and also serves as a conductor. In actual fabrication, the layer containing V3 is higher than the layer containing M3.

[0068] Via DV3 is positioned between DM3 and DM4, and DV3 and via V3 are located at the same height level. DV3 is positioned between the two DM3s facing the memory array MC. In actual manufacturing, the height level of DV3 is higher than the height level of the two DM3s.

[0069] Metal structure M4 is located in the direction from V3 towards the storage array MC. In the actual manufacturing process, the height layer of metal structure M4 is higher than the height layer of V3.

[0070] The redundant structure DM4 and the metal structure M4 are located at the same height level. In the actual manufacturing process, the height level of DM4 is higher than that of DV3.

[0071] The through-hole CONT1 is located between the metal structure M4 and the memory array MC, meaning CONT1 is positioned on M4 facing the memory array MC. CONT1 connects M4 and the memory array MC and also serves as a conductor. In actual fabrication, the layer containing CONT1 is higher than the layer containing M4.

[0072] The memory array MC is positioned between vias CONT1 and CONT2. In actual fabrication, the layer containing the memory array MC is higher than the layer containing CONT1. The memory array MC has a stacked structure comprising at least one transistor and at least one capacitor unit, and can be used to store data. In ferroelectric memories, the memory array MC can have, for example... Figure 2The diagram shows a 1-transistor-n-capacitor unit (1TnC) structure or a m-transistor-n-capacitor unit (mTnC) structure, etc. n and m are positive integers greater than or equal to 1.

[0073] The via CONT2 is positioned between the memory array MC and the metal structure M5, meaning CONT2 is located on the memory array MC away from FEOL. CONT2 connects M5 to the memory array MC and also serves as a conductor. In actual fabrication, the layer containing CONT2 is higher than the layer containing the memory array MC.

[0074] Through-hole V4 is located between metal structures M4 and M5, excluding the memory arrays MC, CONT1, and CONT2. V4 connects M4 and M5 and also serves as a conductor. In actual fabrication, the layer containing V4 is higher than the layer containing M4.

[0075] The redundant structure DM0 and the storage array MC are located at the same height level, and DM0 is a metal block or sheet. In the actual manufacturing process, the height level of DM0 is higher than that of CONT1.

[0076] Metal structure M5 is located in the direction away from storage array MC from V4. In actual manufacturing, the height layer of metal structure M5 is higher than the height layer of V4.

[0077] The redundant structure DM5 and the metal structure M5 are located at the same height level. In the actual manufacturing process, the height level of DM5 is higher than that of DM0.

[0078] Via V5 is positioned between metal structures M5 and M6, meaning V5 is located on M5 away from the memory array MC. V5 connects M5 and M6 and also serves as a conductor. In actual fabrication, the layer containing V5 is higher than the layer containing M5.

[0079] Via DV5 is positioned between redundant structure DM5 and one of the two redundant structures DM6, and DV5 and via V5 are located at the same height level. DV5 is positioned away from the memory array DM0. In actual fabrication, the height level of DV5 is higher than that of DM5.

[0080] Metal structure M6 is located in the direction away from storage array MC in V5. In actual manufacturing, the height layer of metal structure M6 is higher than the height layer of V5.

[0081] The two redundant structures DM6 and the metal structure M6 are all located at the same height level. In the actual manufacturing process, the height level of the two DM6 structures is higher than the height level of the DV5 structure.

[0082] Via V6 is positioned between metal structures M6 and M7, meaning V6 is located on M6 away from the memory array MC. V6 connects M6 and M7 and also serves as a conductor. In actual fabrication, the layer containing V6 is higher than the layer containing M6.

[0083] Metal structure M7 is located in the direction away from storage array MC from V6. In actual manufacturing, the height layer of metal structure M7 is higher than the height layer of V6.

[0084] The redundant structure DM7 and the metal structure M7 are located at the same height level. In the actual manufacturing process, the height level of DM7 is higher than that of DM6.

[0085] Via V7 is positioned between metal structures M7 and M8, meaning V7 is located on M7 away from the memory array MC. V7 connects M7 and M8 and also serves as a conductor. In actual fabrication, the layer containing V7 is higher than the layer containing M7.

[0086] Metal structure M8 is located on V7 in the direction away from the memory array MC. In the actual manufacturing process, the height layer of metal structure M8 is higher than the height layer of V7.

[0087] The redundant structure DM8 and the metal structure M8 are located at the same height level. In the actual manufacturing process, the height level of DM8 is higher than that of DM7.

[0088] The via V8 is positioned between the aluminum contact AP and M8, meaning V8 is located on the side of M8 furthest from the memory array MC. V8 serves to connect AP and M8 and also provides electrical conductivity. In actual fabrication, the layer containing V8 is higher than the layer containing M8.

[0089] The aluminum contact AP is located on V8 away from the memory array MC. In actual manufacturing, the AP is on a higher layer than V8. The AP can be used for electrical conductivity.

[0090] because Figure 1 The environment differs significantly between the edge and center portions of the memory array (MC), making it susceptible to deviations in critical dimensions during photolithography due to optical reflection and diffraction. Furthermore, because... Figure 1 The memory structure is not uniformly distributed, so serious metal layer disk or dielectric layer erosion problems are likely to occur during the CMP process.

[0091] Figure 2 This is a schematic diagram of a 1TnC memory array. Figure 2 The memory array shown includes word lines 210, bit lines 220, back-end vertical transistors 230, pillars 240, ferroelectric capacitor cells 250, and board line planes 260.

[0092] Word line (WL) 210 and bit line (BL) 220 are two vertically intersecting metal lines on the bottom layer of the memory array. Back-end vertical transistor 230 can be connected to word line 210, bit line 220, and pillar 240. Back-end vertical transistor 230 includes a source (S), a gate (G), and a drain (D). The source (S) is connected to bit line 220, the gate (G) is connected to word line 210, and the drain (D) is connected to pillar 240.

[0093] The board line plane 260 is located on the upper layer of word line 210, bit line 220 and back-end vertical transistor 230. Figure 2 The storage array shown includes n plate-line planes 260 and multiple pillars 240, where n is a positive integer greater than or equal to 1. Each pillar 240 can penetrate n plate-line planes 260. The intersection point of each pillar 240 and each plate-line plane 260 is a ferroelectric capacitor unit 250. A ferroelectric capacitor unit 250 is composed of plate lines in each plate-line plane 260, pillars 240, and a ferroelectric crystal thin film. The plate lines in each plate-line plane 260 and the pillars 240 penetrating that plate-line plane 260 constitute the two stages of the ferroelectric capacitor unit 250, with the ferroelectric crystal thin film surrounding the intersection point. Since the ferroelectric crystal thin film can have different polarization states, the ferroelectric capacitor unit 250 can record different stored information through different polarization states of the ferroelectric crystal thin film. That is, one ferroelectric capacitor unit 250 is a storage cell of the storage array.

[0094] Figure 2 The 1TnC structure of the memory array shown includes n ferroelectric capacitor units 250 on a pillar 240 and a back-end vertical transistor connected to the lower end of the pillar 240.

[0095] Figure 3 This is a schematic circuit diagram of a 1TnC memory array. Figure 3 It includes two word lines, two bit lines, four board planes, four pillars, four back-end vertical transistors, and multiple ferroelectric capacitor units. Figure 3 In the direction of one of the pillars, there is one back-end vertical transistor and n ferroelectric capacitor units, where n is 4. Figure 3 The character lines 1 and 2 in the middle Figure 2 The character line 210 is similar. Figure 3 Bit line 1, bit line 2 and Figure 2 The bit line 220 is similar. Figure 3 Back-end vertical transistors and Figure 2 The back-end vertical transistor 230 is similar. Figure 3 Pillars 1, 2, 3, and 4 in the middle Figure 2 The pillar 240 is similar. Figure 3 Ferroelectric capacitor units in Figure 2 The ferroelectric capacitor unit 250 is similar. Figure 3 Plate line plane 1, plate line plane 2, plate line plane 3, and plate line plane 4 are in the same plane as the plate line plane 4. Figure 2 The plate line plane 260 in the middle is similar.

[0096] Because the metal and dielectric density distribution in each metal structure layer of the memory 100 is uneven, metal layer dishing or dielectric layer erosion occurs after the CMP process, resulting in uneven thickness of each layer and making it prone to defects during manufacturing. Simultaneously, due to the inconsistency between the surrounding environment of the central and edge portions of the first memory array 120, the critical dimensions of the first memory array 120 are prone to deviation during photolithography due to light reflection and diffraction characteristics. For example, the first memory array 120 should include 1024×1024 memory cells, but the actual manufactured first memory array 120 only includes 1000×990 memory cells.

[0097] Figure 4 This is a schematic diagram of the erosion of the metal layer in a disc shape and the dielectric layer. Figure 4 It comprises multiple metal structures and a dielectric layer. The multiple metal structures are located within the dielectric layer, and the remaining portion of the dielectric layer, excluding the multiple metal structures, is the dielectric material.

[0098] Before the CMP process, the upper edges of multiple metal structures were flush with the upper edge of the dielectric layer. After the CMP process, the height of the dielectric layer was lower than that before the CMP process, indicating dielectric layer erosion. Furthermore, after the CMP process, the upper edges of multiple metal structures were lower than the upper edge of the dielectric layer, indicating a metal layer dishing phenomenon occurred between the upper edges of the multiple metal structures and the upper edge of the dielectric layer. Simultaneously, due to... Figure 4 The density distribution of multiple metal structures and dielectrics in the medium is uneven, resulting in an uneven thickness of the dielectric layer after the CMP process, which has many defects.

[0099] In order to protect the edge portion of the memory array, avoid deviations in critical dimensions caused by optical reflection and diffraction during photolithography, and increase the smoothness of each layer in the memory after the CMP process, this application provides a memory.

[0100] Figure 5 This is a schematic structural diagram of a memory 300 provided in an embodiment of this application. The memory 300 includes a first storage array 310, a first redundant array 320, and a substrate 330.

[0101] The first memory array 310 includes a stacked structure consisting of at least one transistor and at least one capacitor unit, and the first memory array 310 can be used to store data. The first memory array 310 can be connected to... Figure 1 It is similar to the storage array MC in the example.

[0102] The first redundant array 320 includes a stacked structure consisting of at least one transistor and at least one capacitor unit. The first redundant array 320 and the first memory array 310 have the same height relative to the substrate 330, meaning they are located at the same height level, and the first redundant array 320 has the same layered or stacked structure as the first memory array 310. It should be understood that layered structure and stacked structure have similar meanings. It should also be understood that the height of the first redundant array 320 and the first memory array 310 relative to the substrate 330 is a range, not a specific numerical value.

[0103] For example, the first redundant array 320 and the first memory array 310 are at a first height relative to the substrate 330. That is, the first redundant array 320 and the first memory array 310 can be located at a first height layer, and the first redundant array 320 can have the same stacking structure as the first memory array 310, so that the edge portion of the first memory array 310 is similar to the surrounding environment of the center portion. The fact that the first redundant array 320 and the first memory array 310 have the same stacking structure can also make the structure of the first height layer more uniform, thereby improving the smoothness of the layer after the CMP process.

[0104] Optionally, the stacked structure may include an mTnC structure, wherein the mTnC structure includes m stacked transistors and n capacitor units, where m and n are positive integers greater than or equal to 1.

[0105] Optionally, at least one transistor of the first memory array 310 is disposed on the same layer as at least one transistor of the first redundant array 320. At least one capacitor cell of the first memory array 310 is disposed on the same layer as at least one capacitor cell 320 of the first redundant array. This same layer may be the same wiring layer or the same multi-layer wiring layer, which is not limited in this embodiment.

[0106] For example, assuming four transistors are disposed in the first wiring layer of the first memory array 310, then four transistors are also disposed in the first wiring layer of the first redundant array 320, and the arrangement of the four transistors in the first redundant array 320 is the same as that in the first memory array 310. Alternatively, assuming four capacitor cells are also disposed in the second wiring layer of the first memory array 310, then four capacitor cells are also disposed in the second wiring layer of the first redundant array 320. Furthermore, the arrangement of the four transistors and four capacitor cells in the first redundant array 320 is the same as that in the first memory array 310.

[0107] Optionally, the stacked structure of the first memory array and the first redundant array may further include at least one of the following structures: word line, bit line, board line plane or pillar; any one of at least one transistor is connected to the word line, bit line or pillar; or, any one of at least one capacitor cell is disposed at the intersection of the board line plane and the pillar.

[0108] It should be understood that, based on the fact that the first redundant array 320 has the same stacking structure as the first memory array 310, the first redundant array 320 may have exactly the same electronic components as the first memory array 310, or may have partially the same electronic components as the first memory array 310.

[0109] For example, assuming the memory is a ferroelectric memory, and the first memory array 310 includes, for example, a ferroelectric memory. Figure 2 All electronic components in the 1TnC structure shown, such as word lines, bit lines, board planes, pillars, transistors, and capacitor cells, can also be included in the first redundant array 320, such as... Figure 2 All electronic components in the 1TnC structure shown. Alternatively, the first redundant array may include, as Figure 2 Some of the electronic components in the 1TnC structure shown.

[0110] Optionally, the first storage array 310 can be electrically connected to an external circuit outside the memory. Alternatively, the first storage array 310 can be in a circuit path, i.e., the circuit containing the first storage array 310 is a closed circuit. Or, the first storage array 310 cannot be in a circuit open circuit, i.e., the circuit containing the first storage array 310 cannot be an open circuit. Since the first storage array 310 can be electrically connected to an external circuit outside the memory, the first storage array 310 can be used to store data, i.e., it has the substantial function of storing data.

[0111] Optionally, the first redundant array 320 cannot be electrically connected to external circuits outside the memory or to circuits within the memory. Alternatively, the first redundant array 320 cannot be in a circuit path, i.e., the circuit containing the first redundant array 320 is not a closed circuit. Or, the first redundant array 320 can be in a circuit open circuit, i.e., the circuit containing the first redundant array 320 is an open circuit. Although the first redundant array 320 has the same stacking structure as the first storage array 310, the first redundant array 320 cannot be electrically connected to external circuits outside the memory, therefore the first redundant array 320 cannot be used to store data, i.e., it does not have the substantial function of storing data.

[0112] The first redundant array 320 may have the same or similar dimensions as the first storage array 310 in the first dimension. The dimensions of the first redundant array 320 in the first dimension may include length, width, height, volume, and the number of storage cells it contains. For example, the dimensions of the first redundant array 320 in the first dimension may be the same as those of the first storage array 310 in the first dimension. Alternatively, the absolute value of the difference between the dimensions of the first redundant array 320 and the first storage array 310 in the first dimension may be less than a first threshold, where the first threshold is a non-negative number.

[0113] For example, the first redundant array 320 may have the same dimensions in the first dimension as the first storage array 310 in the first dimension. This could include: the length of the first redundant array 320 being the same as the length of the first storage array 310, or the volume of the first redundant array 320 being the same as the volume of the first storage array 310, or the number of arrays of storage cells contained in the first redundant array 320 being the same as the number of arrays of storage cells contained in the first storage array 310. This application embodiment does not limit this.

[0114] The absolute value of the difference between the size of the first redundant array 320 in the first dimension and the size of the first storage array 310 in the first dimension is less than a first threshold. This can include: the difference between the size of the first redundant array 320 in the first dimension and the size of the first storage array 310 in the first dimension is less than the first threshold, or the difference between the size of the first storage array 310 in the first dimension and the size of the first redundant array 320 in the first dimension is less than the first threshold. This application embodiment does not limit this.

[0115] The difference between the size of the first redundant array 320 in the first dimension and the size of the first storage array 310 in the first dimension is less than a first threshold. This can include: the difference between the length of the first redundant array 320 and the length of the first storage array 310 is less than the first threshold; or the difference between the width of the first redundant array 320 and the width of the first storage array 310 is less than the first threshold; or the difference between the height of the first redundant array 320 and the height of the first storage array 310 is less than the first threshold; or the difference between the number of arrays of storage cells included in the first redundant array 320 and the number of arrays of storage cells included in the first storage array 310 is less than the first threshold. This application embodiment is not limited in this respect.

[0116] The difference between the size of the first redundant array 320 in the first dimension and the size of the first storage array 310 in the first dimension is less than a first threshold, which is similar to the above description and will not be repeated here.

[0117] Depending on different practical needs or different CMP processes, the first threshold may be the same or different, and this application embodiment does not limit this. For example, if the difference between the length of the first redundant array 320 and the length of the first storage array 310 is less than the first threshold, then the first threshold may be 100 nanometers (nm). If the difference between the number of arrays contained in the first redundant array 320 and the number of arrays contained in the first storage array 310 is less than the first threshold, then the first threshold may be 50×50.

[0118] If the first threshold is large, the difference in size between the first redundant array 320 and the first memory array 310 in the first dimension will be large, resulting in a less uniform structure of the layer and inconsistencies between the edge and center portions of the first memory array 310. This less uniform structure leads to lower smoothness after the CMP process. Furthermore, the inconsistency between the edge and center portions of the first memory array 310 makes it prone to deviations in critical dimensions during photolithography. Conversely, if the first threshold is small, the difference in size between the first redundant array 320 and the first memory array 310 in the first dimension will be smaller, resulting in a more uniform structure and better consistency between the edge and center portions. However, minimizing this difference requires more precise fabrication techniques and may take longer.

[0119] If the difference between the size of the first redundant array 320 in the first dimension and the size of the first storage array 310 in the first dimension is less than a first threshold, the first redundant array 320 can be divided into a first part and a second part. The first part of the first redundant array 320 is the part with the same number of storage cells and stacking structure as the first storage array 310; that is, the first part of the first redundant array 320 includes the same number of storage cells and stacking structure as the first storage array 310. The second part of the first redundant array 320 can be any one of an mT structure, an nC structure, or an mTnC structure. The mT structure includes m... Figure 2 The back-end vertical transistor 230 shown has an nC structure including n such as Figure 2 The ferroelectric capacitor unit 250 is shown. The second part of the first redundant array 320 is connected to the first part.

[0120] Taking the first storage array 310 as an example of a 1TnC structure, the first part of the first redundant array 320 can be a 1TnC structure, and the second part of the first redundant array 320 can be one or more such structures located at the lower end of the first part and connected to the 1T structure in the first part. Figure 2 The back-end vertical transistor 230 is shown. Alternatively, the second portion of the first redundant array 320 can be one or more such structures connected to the upper end of the first portion and to the nC structure in the first portion. Figure 2 The ferroelectric capacitor unit 250 is shown. Alternatively, the second part of the first redundant array 320 may be one or more 1TnC structures connected to the left end of the first part and to the 1TnC structure at the left end of the first part. Alternatively, the second part of the first redundant array 320 may be one or more 1TnC structures connected to the right end of the first part and to the 1TnC structure at the right end of the first part.

[0121] The spacing between the first redundant array 320 and the first memory array 310 can be less than the sixth threshold. Depending on the CMP process, the sixth threshold can be the same or different, and this embodiment is not limited in this respect. For example, the value of the sixth threshold can range from 1 micrometer to 10 micrometers. If the sixth threshold is large, the spacing between the first redundant array 320 and the first memory array 310 will be large, which may easily lead to a less uniform structure in the layer, resulting in a less smooth layer after the CMP process. If the sixth threshold is small, the spacing between the first redundant array 320 and the first memory array 310 will be small, which may also lead to a less uniform structure in the layer, and leakage problems may occur during the memory fabrication process.

[0122] Optionally, the first redundant array 320 may have the same stacked structure as the first memory array 310, and the first redundant array 320 may include only metal wires. Alternatively, the first redundant array 320 may have the same stacked structure as the first memory array 310, and the first redundant array 320 may include electronic components similar to those included in the first memory array 310. For example, suppose the first memory array 310 is as follows: Figure 2 The 1TnC structure shown can include, in the first redundant array 320, elements related to... Figure 2 The 1TnC structure shown includes electronic components such as transistors (i.e., back-end vertical transistors 230) or capacitor units (i.e., ferroelectric capacitor units 250), but the transistors or capacitor units in the first redundant array 320 may not perform substantial functions such as storage.

[0123] Optionally, the memory 100 may further include a second redundant array. This second redundant array may be located at the same height level as the first memory array 310 and the first redundant array 320. For example, if the first memory array 310 and the first redundant array 320 are located at a first height level, the second redundant array is also located at the first height level.

[0124] The second redundant array can be located on the other side of the first storage array 310 away from the first redundant array 320, that is, the second redundant array can be located as follows: Figure 5 The left side of the first storage array 310 is shown. The second redundant array can have the same layered or stacked structure as the first storage array 310. The size of the second redundant array in the first dimension can be the same as or similar to the size of the first storage array 310 in the first dimension. The relationship between the second redundant array and the first storage array 310 in the first dimension is similar to the relationship between the first redundant array 320 and the first storage array 310 in the first dimension, and will not be repeated here. The spacing between the second redundant array and the first storage array can be less than the sixth threshold, that is, it can be similar to the spacing between the first redundant array and the first storage array, and will not be repeated here.

[0125] Optionally, the memory 100 may further include a third redundant array. This third redundant array may be located on the side of the first redundant array away from the first memory array, and at the same height level as the first redundant array. The spacing between the third redundant array and the first redundant array may be less than a sixth threshold, i.e., similar to the spacing between the first redundant array and the first memory array. The third redundant array may be similar to the first redundant array, and will not be elaborated further here.

[0126] Optionally, the memory 100 may further include a fourth redundant array. This fourth redundant array may be located on the side of the second redundant array away from the first memory array, and at the same height level as the second redundant array. The spacing between the fourth redundant array and the second redundant array may be less than a sixth threshold, i.e., similar to the spacing between the second redundant array and the first memory array. This fourth redundant array is similar to the second redundant array and will not be described further here.

[0127] Optionally, the memory 100 may further include a fifth redundant array. This fifth redundant array may be located above the first memory array and at the same height level. The fifth redundant array may together with the first memory array form an mTnC structure. For example, assuming the first memory array only includes an mT structure, the fifth redundant array can be an nC structure, and it may be located above the first memory array and connected to the mT structure of the first memory array, thereby forming an mTnC structure. In the case of an nC structure, the fifth redundant array may include n capacitor cells, where n is a positive integer greater than or equal to 1. Each of the n capacitor cells is connected to... Figure 2 Similar to the ferroelectric capacitor unit 250 in the middle, or each capacitor unit in n capacitor units is similar to Figure 3 It is similar to the ferroelectric capacitor unit in the example.

[0128] Optionally, the memory 100 may further include a sixth redundant array. This sixth redundant array may be located below the first memory array and at the same height level as the first memory array. The sixth redundant array may, together with the first memory array, form an mTnC structure. For example, assuming the first memory array only includes an nC structure, the sixth redundant array may be a 1T structure, and the sixth redundant array may be located below the first memory array and connected to the nC structure of the first memory array, thereby forming an mTnC structure. In the case of a 1T structure, the sixth redundant array may include one transistor, which is connected to... Figure 2 Similar to, or related to, the back-end vertical transistor 230 in the middle. Figure 3 It is similar to the back-end vertical transistor in the process.

[0129] Optionally, the memory 300 may also include a first metal structure and a first redundancy structure. The memory 300 may also include a first through-hole, which can connect the first redundancy array and the first redundancy structure. See details below. Figure 6 The description.

[0130] Optionally, the memory 300 may also include a second metal structure and a second redundancy structure. The memory 300 may also include a second through-hole, which can connect the first redundancy array and the second redundancy structure. See details below. Figure 7The description.

[0131] Figure 5 The memory 300 shown can have a first redundant array 320 with the same layered or stacked structure as the first memory array 310 in the same height layer as the first memory array 310, so that the structure of the layer can be more uniform, avoid excessive etching of the metal during CMP process, and increase the smoothness of the layer. Figure 5 The memory 300 shown can also make the edge portion of the first memory array 310 consistent with the surrounding environment of the memory cells in the center portion, thereby avoiding deviations in the critical dimensions of the first memory array during the photolithography process.

[0132] Figure 6 This is a schematic structural diagram of the memory 400 provided in an embodiment of this application. Figure 6 The memory 400 includes a first metal structure 410, a first redundant structure 420, a first through-hole 430, a first memory array 440, a first redundant array 450, a through-hole 460, and a substrate 470.

[0133] Wherein, substrate 470 is disposed in such a way as Figure 6 The lowest height layer shown is the layer other than substrate 470, meaning substrate 470 is below the first height. The first height can be the height of the first height layer from substrate 470. This height is a range, not a specific value.

[0134] The first metal structure 410 can be a metal wire for electrical conductivity. The height of the first metal structure 410 relative to the substrate 470 is a second height; that is, the first metal structure 410 is located in a second height layer, which is disposed in the direction from the first height layer toward the substrate 470. In other words, this second height layer is lower than the first height layer where the first memory array 440 and the first redundant array 450 are located, and is higher than the substrate 470. The height of the second height layer can be the distance between the second height layer and the substrate 470. This height is a range, not a specific numerical value.

[0135] The first metal structure 410 can be with Figure 1 The metal structures of M1-M4 are similar.

[0136] Optionally, the first metal structure 410 can be electrically connected to an external circuit outside the memory. Alternatively, the first metal structure 410 can be in a circuit path, that is, the circuit containing the first metal structure 410 is a closed circuit. Alternatively, the first metal structure 410 cannot be in a circuit open circuit, that is, the circuit containing the first metal structure 410 cannot be an open circuit.

[0137] The first redundant structure 420 and the first metal structure 410 are at the same height relative to the substrate 470, meaning that the first redundant structure 420 and the first metal structure 410 are located at the same height layer. In other words, the first redundant structure 420 is located at the second height layer.

[0138] Optionally, the first redundancy structure 420 can be a metal block or metal sheet, or it can be a metal wire. The first redundancy structure 420 cannot be electrically connected to external circuits outside the memory or to circuits within the memory. Alternatively, the first redundancy structure 420 cannot be in a circuit path, meaning the circuit containing the first redundancy structure 420 is not a closed circuit. Alternatively, the first redundancy structure 420 can be in a circuit open circuit, meaning the circuit containing the first redundancy structure 420 is an open circuit.

[0139] The first redundant structure 420 is made of the same or similar material as the first metal structure 410. For example, assuming the first metal structure 410 is a metal wire, the first redundant structure 420 can be a metal block or sheet with the same or similar density as the first metal structure. The first redundant structure 420 can be... Figure 1 The redundant structures in DM1-DM4 are similar.

[0140] The first redundant structure 420 and the first metal structure 410 have the same or similar dimensions in the second dimension. For example, the dimension of the first redundant structure 420 in the second dimension may be the same as the dimension of the first metal structure 410 in the second dimension. Alternatively, the absolute value of the difference between the dimension of the first redundant structure 420 and the dimension of the first metal structure 410 in the second dimension may be less than a second threshold, which is a non-negative number.

[0141] When the first metal structure is a metal wire, the dimension of the first metal structure in the second dimension can be the width of the metal wire, etc.

[0142] For example, the first redundant structure 420 may have the same dimensions in the second dimension as the first metal structure 410 in the second dimension, which may include the first redundant structure 420 having the same width as the first metal structure 410.

[0143] For example, the absolute value of the difference between the size of the first redundant structure 420 in the second dimension and the size of the first metal structure 410 in the second dimension is less than a second threshold. This can include: the difference between the size of the first redundant structure 420 in the second dimension and the size of the first metal structure 410 in the second dimension is less than a second threshold, or the difference between the size of the first metal structure 410 in the second dimension and the size of the first redundant structure 420 in the second dimension is less than a second threshold. This application embodiment does not limit this.

[0144] For example, the difference between the size of the first redundant structure 420 in the second dimension and the size of the first metal structure 410 in the second dimension is less than a second threshold. This may include the difference between the width of the first redundant structure 420 and the width of the first metal structure 410 being less than the second threshold. This application embodiment does not limit this.

[0145] The relationship between the difference between the second dimension of the first metal structure 410 and the second dimension of the first redundant structure 420 and the second threshold is similar to the above description and will not be repeated here.

[0146] Depending on different practical needs or different CMP processes, the second threshold may be the same or different, and this application embodiment does not limit this. For example, if the difference between the width of the first redundant structure 420 and the width of the first metal structure 410 is less than the second threshold, then the second threshold may be 90 nanometers (nm).

[0147] If the second threshold is large, the difference in size between the first redundant structure 420 and the first metal structure 410 in the second dimension will be large, resulting in a less uniform structure of the layer. Consequently, the smoothness of the layer will be lower after the CMP process. If the second threshold is small, the difference in size between the first redundant structure 420 and the first metal structure 410 in the second dimension will be small, resulting in a more uniform structure of the layer. However, this may require more time during the process.

[0148] The first via 430 is used to connect the first redundant structure 420 and the first redundant array 450. The first via 430 includes a conductive material and is used to conduct electricity between the first redundant structure 420 and the first redundant array 450, thereby allowing the transmission of plasma generated during the fabrication of the memory 400, preventing subsequent device failures and improving the reliability of subsequent devices.

[0149] Optionally, the first via 430 cannot be electrically connected to external circuitry outside the memory or to circuitry within the memory. Alternatively, the first via 430 cannot be in a circuit path, meaning the circuit containing the first via 430 is not a closed circuit. Or, the first via 430 can be in a circuit break, meaning the circuit containing the first via 430 is an open circuit. Although the first redundant array 450 has the same stacking structure as the first memory array 440, the first redundant structure 420, the first via 430, and the first redundant array 450 cannot be electrically connected to external circuitry outside the memory. Therefore, the first redundant array 450 cannot be used to store data, i.e., it does not have the substantial function of storing data.

[0150] First storage array 440 and Figure 5 The first storage array 310 is similar, and will not be described in detail here.

[0151] First redundant array 450 and Figure 5 The first redundant array 320 in the model is similar and will not be described in detail here.

[0152] The via 460 is located between the first height layer and the second height layer and can be used to connect the first metal structure 410 and the first memory array 440. The via 460 can also be used for electrical conductivity. The via 460 and... Figure 1 The through-hole CONT1 is similar.

[0153] The via 460 can be electrically connected to an external circuit outside the memory. Alternatively, the via 460 can be in a circuit path, meaning the circuit containing the via 460 is a closed circuit. Or, the via 460 cannot be in a circuit break, meaning the circuit containing the via 460 cannot be an open circuit. Since the first metal structure 410, the first memory array 440, and the via 460 can be electrically connected to an external circuit outside the memory, the first memory array 440 can be used to store data, i.e., it has the substantial function of storing data.

[0154] Substrate 470 is disposed in a direction away from the first metal structure 410 and away from the first memory array 440. Substrate 470 can be coupled with... Figure 1 The front-end structure is similar to FEOL.

[0155] Figure 6 The memory 400 shown can make the edge portion of the first memory array more consistent with the surrounding environment of the central portion, thereby avoiding deviations caused by light reflection or diffraction. Figure 6 The memory 400 shown can also increase the smoothness of the layer where the storage array or metal structure is located by adding a first redundant array and a first redundant structure, thereby making the structure more uniform, avoiding the phenomenon of metal layer dishing or dielectric layer erosion. Figure 6 The storage 400 shown can also provide a discharge channel for plasma generated during the process through the first through-hole, thereby avoiding damage to downstream devices.

[0156] Figure 7 This is a schematic structural diagram of the memory 500 according to an embodiment of this application. Figure 7 The memory 500 includes a third metal structure 501, a third redundant structure 502, a first metal structure 503, a first redundant structure 504, a first memory array 506, a first redundant array 507, a second metal structure 509, a second redundant structure 510, a fourth metal structure 511, a fourth redundant structure 512, a through hole 513, a through hole 514, and a substrate 515.

[0157] The first redundant array 507 is connected to the first redundant structure 504 through a first through-hole 505, and the first redundant array 507 is connected to the second redundant structure 510 through a second through-hole 508. The substrate 515 is disposed on... Figure 7 The lowest height layer shown is the layer other than substrate 515, meaning substrate 515 is lower than the first height. Substrate 515 can be connected to... Figure 1 The frontal structure FEOL is similar to, or related to Figure 6 The substrate 470 is similar and will not be described again here. The first height can be the height of the first height layer relative to the substrate 515.

[0158] The first storage array 506 and the first redundant array 507 are located at the first height layer. Figure 5 The first storage array 310 is similar to that in the previous model, and will not be described further here. The first redundant array 507 is similar to... Figure 5 The first redundant array 320 in the model is similar and will not be described in detail here.

[0159] The third metal structure 501 and the third redundant structure 502 are at the same height relative to the substrate 515. The height of the third metal structure 501 and the third redundant structure 502 relative to the substrate 515 is a fourth height, meaning that the third metal structure 501 and the third redundant structure 502 are located in a fourth height layer, which is disposed in the direction from the first height layer towards the substrate. In other words, this fourth height layer is lower than the first height layer where the first memory array 506 and the first redundant array 507 are located, and this fourth height layer is higher than the substrate 515. The height of the fourth height layer can be the distance between the fourth height layer and the substrate 515. This height is a range, not a specific numerical value.

[0160] Optionally, the third metal structure 501 can be electrically connected to an external circuit outside the memory. Alternatively, the third metal structure 501 can be in a circuit path, i.e., the circuit containing the third metal structure 501 is a closed circuit. Alternatively, the third metal structure 501 cannot be in a circuit open circuit, i.e., the circuit containing the third metal structure 501 cannot be an open circuit.

[0161] Optionally, the third redundancy structure 502 cannot be electrically connected to external circuits outside the memory or to circuits within the memory. Alternatively, the third redundancy structure 502 cannot be in a circuit path, i.e., the circuit containing the third redundancy structure 502 is not a closed circuit. Alternatively, the third redundancy structure 502 can be in a circuit open circuit, i.e., the circuit containing the third redundancy structure 502 is an open circuit.

[0162] The difference between the dimension of the third metal structure 501 in the fourth dimension and the dimension of the third redundant structure 502 in the fourth dimension is less than the fourth threshold. The third metal structure 501 and... Figure 6The first metal structure 410 is similar to that in the previous section, and will not be described in detail here. The third redundant structure 502 is similar to... Figure 6 The first redundant structure 420 is similar to that in the first metal structure 410, and will not be described in detail here. The dimensions of the third metal structure 501 in the fourth dimension are similar to those of the first metal structure 410 in the second dimension, and will not be described in detail here.

[0163] The first metal structure 503 and the first redundant structure 504 are located in the second height layer. This second height layer is positioned between the first height layer and the fourth height layer; that is, the second height layer is lower than the first height layer where the first memory array 506 and the first redundant array 507 are located, and higher than the fourth height layer where the third metal structure 501 and the third redundant structure 502 are located. The height of the second height layer can be the distance between the second height layer and the substrate 515.

[0164] First metal structure 503 and Figure 6 The first metal structure 410 is similar to that in the previous section, and will not be described in detail here. The first redundant structure 504 is similar to... Figure 6 The first redundant structure 420 is similar, and will not be described in detail here.

[0165] The via 513 is located between the first height layer and the second height layer, and the via 513 can be used for electrical conduction. The via 513 and... Figure 1 Similar to the through-hole CONT1 in the example, or it can be related to... Figure 6 The through-hole 460 is similar.

[0166] The first through-hole 505 is used to connect the first redundant array 507 and the first redundant structure 504. Figure 6 The first through hole 430 is similar, and will not be described in detail here.

[0167] The second metal structure 509 and the second redundant structure 510 are at the same height relative to the substrate 515. The height of the second metal structure 509 and the second redundant structure 510 relative to the substrate 515 is a third height, meaning the second metal structure 509 and the second redundant structure 510 are located in a third height layer, which is positioned away from the substrate from the first height layer. In other words, this third height layer is higher than the first height layer where the first memory array 506 and the first redundant array 507 are located. The height of the third height layer can be the distance between the third height layer and the substrate 515. This height is a range, not a specific numerical value.

[0168] The second metal structure 509 can be a metal wire, which can be used for electrical conductivity. The second metal structure 509 can be connected to... Figure 1 The metal structures in them are similar to those in M5-M8.

[0169] Optionally, the second metal structure 509 can be electrically connected to an external circuit outside the memory. Alternatively, the second metal structure 509 can be in a circuit path, i.e., the circuit containing the second metal structure 509 is a closed circuit. Alternatively, the second metal structure 509 cannot be in a circuit open circuit, i.e., the circuit containing the second metal structure 509 cannot be an open circuit.

[0170] Optionally, the second redundancy structure 510 can be a metal block or sheet, or a metal wire. The second redundancy structure 510 cannot be electrically connected to external circuits outside the memory or to circuits within the memory. Alternatively, the second redundancy structure 510 cannot be in a circuit path, i.e., the circuit containing the second redundancy structure 510 is not a closed circuit. Alternatively, the second redundancy structure 510 can be in a circuit open circuit, i.e., the circuit containing the second redundancy structure 510 is an open circuit.

[0171] The second redundancy structure 510 is made of the same or similar material as the second metal structure 509. For example, assuming the second metal structure 509 is a metal wire, then the second redundancy structure 510 is a metal block or sheet with the same or similar density as the second metal structure. The second redundancy structure 510 can be... Figure 1 The redundant structures in DM5-DM8 are similar.

[0172] The second redundant structure 510 and the second metal structure 509 have the same or similar dimensions in the third dimension. For example, the dimension of the second redundant structure 510 in the third dimension may be the same as the dimension of the second metal structure 509 in the third dimension. Alternatively, the absolute value of the difference between the dimension of the second redundant structure 510 and the dimension of the second metal structure 509 in the third dimension may be less than a third threshold, which is a non-negative number.

[0173] When the second metal structure 509 is a metal wire, the dimension of the second metal structure 509 in the third dimension can be the width of the metal wire, etc.

[0174] For example, the second redundant structure 510 may have the same dimensions in the third dimension as the second metal structure 509, which may include the second redundant structure 510 having the same width as the second metal structure 509.

[0175] For example, the absolute value of the difference between the size of the second redundant structure 510 in the third dimension and the size of the second metal structure 509 in the third dimension is less than a third threshold. This can include: the difference between the size of the second redundant structure 510 in the third dimension and the size of the second metal structure 509 in the third dimension is less than a third threshold, or the difference between the size of the second metal structure 509 in the third dimension and the size of the second redundant structure 510 in the third dimension is less than a third threshold. This application embodiment does not limit this.

[0176] For example, the difference between the size of the second redundant structure 510 in the third dimension and the size of the second metal structure 509 in the third dimension is less than a third threshold. This may include the difference between the width of the second redundant structure 510 and the width of the second metal structure 509 being less than a third threshold. This application embodiment does not limit this.

[0177] The relationship between the difference between the size of the second metal structure 509 in the third dimension and the size of the second redundant structure 510 in the third dimension and the third threshold is similar to the description above, and will not be repeated here.

[0178] Depending on different practical needs or different CMP processes, the third threshold may be the same or different, and the embodiments of this application do not limit this. For example, if the difference between the width of the second redundant structure 510 and the width of the second metal structure 509 is less than the third threshold, then the third threshold may be 100 nanometers (nm).

[0179] If the third threshold is large, the difference in size between the second redundant structure 510 and the second metal structure 509 in the third dimension will be large, resulting in a less uniform structure of the layer. Consequently, the smoothness of the layer will be lower after the CMP process. If the third threshold is small, the difference in size between the second redundant structure 510 and the second metal structure 509 in the third dimension will be small, resulting in a more uniform structure of the layer. However, this may require more time during the process.

[0180] The via 514 is located between the first height layer and the third height layer, and the via 514 can be used for electrical conduction. The via 514 and... Figure 1 The through-hole CONT2 is similar.

[0181] Optionally, the via 514 can be electrically connected to an external circuit outside the memory. Alternatively, the via 514 can be in a circuit path, i.e., the circuit containing the via 514 is a closed circuit. Alternatively, the via 514 cannot be in a circuit break, i.e., the circuit containing the via 514 cannot be an open circuit. Since the first metal structure 503, the via 513, the first memory array 506, the via 514, and the second metal structure 509 can be electrically connected to an external circuit outside the memory, the first memory array 506 can store data, i.e., it has the substantial function of storing data.

[0182] The second via 508 is used to connect the first redundant array 507 and the second redundant structure 510. The second via includes a conductive material and is used to conduct electricity between the first redundant array 507 and the second redundant structure 510, thereby allowing the transfer of plasma generated during the fabrication of the memory 500 and preventing subsequent device failures.

[0183] Optionally, the second via 508 cannot be electrically connected to external circuitry outside the memory or to circuitry within the memory. Alternatively, the second via 508 cannot be in a circuit path, i.e., the circuit containing the second via 508 is not a closed circuit. Or, the second via 508 can be in a circuit break, i.e., the circuit containing the second via 508 is an open circuit. Although the first redundant array 507 has the same stacking structure as the first memory array 506, because the first redundant structure 504, the first via 505, the first redundant array 507, the second via 508, and the second redundant structure 510 cannot be electrically connected to external circuitry outside the memory, the first redundant array 507 cannot be used to store data, i.e., it cannot have the substantial function of storing data.

[0184] The fourth metal structure 511 and the fourth redundant structure 512 are at the same height relative to the substrate 515. The height of the fourth metal structure 511 and the fourth redundant structure 512 relative to the substrate 515 is the fifth height, meaning that the fourth metal structure 511 and the fourth redundant structure 512 are located in a fifth height layer, which is positioned away from the substrate from the third height layer. In other words, this fifth height layer is higher than the third height layer where the second metal structure 509 and the second redundant structure 510 are located. The height of the fifth height layer can be the distance between the fifth height layer and the substrate 515. This height is a range, not a specific numerical value.

[0185] The difference between the size of the fourth metal structure in the fifth dimension and the size of the fourth redundant structure in the fifth dimension is less than the fifth threshold. The fourth metal structure 511 is similar to the second metal structure 509, and will not be described further here. The fourth redundant structure 512 is similar to the second redundant structure 510, and will not be described further here. The size of the fourth metal structure in the fifth dimension is similar to the size of the second metal structure 509 in the third dimension, and will not be described further here.

[0186] Optionally, the fourth metal structure 511 can be a metal wire. The fourth metal structure 511 can be electrically connected to an external circuit outside the memory. Alternatively, the fourth metal structure 511 can be in a circuit path, that is, the circuit in which the fourth metal structure 511 is located is a closed circuit. Alternatively, the fourth metal structure 511 cannot be in a circuit open circuit, that is, the circuit in which the fourth metal structure 511 is located cannot be an open circuit.

[0187] Optionally, the fourth redundancy structure 512 can be a metal block or sheet, or a metal wire. The fourth redundancy structure 512 cannot be electrically connected to external circuits outside the memory or to circuits within the memory. Alternatively, the fourth redundancy structure 512 cannot be in a circuit path, i.e., the circuit containing the fourth redundancy structure 512 is not a closed circuit. Alternatively, the fourth redundancy structure 512 can be in a circuit open circuit, i.e., the circuit containing the fourth redundancy structure 512 is an open circuit.

[0188] Optionally, the memory 500 may include one or more first metal structures and one or more first redundant structures, with each of the one or more first metal structures corresponding to one or more first redundant structures. Each of the one or more first redundant structures is located on the same layer as the first metal structure corresponding to it. Each of the one or more first redundant structures is disposed in the direction of the first height layer toward the substrate 515, that is, each first redundant structure is lower than the first height layer where the first redundant array is located.

[0189] Alternatively, the memory 500 may include one or more third metal structures and one or more third redundant structures, with each of the one or more third metal structures corresponding to one or more third redundant structures. Each of the one or more third redundant structures is located on the same layer as the third metal structure corresponding to it. Each of the one or more third redundant structures is disposed in the direction of the first height layer toward the substrate 515, that is, each third redundant structure is lower than the first height layer where the first redundant array is located.

[0190] Optionally, the memory 500 may include one or more second metal structures and one or more second redundant structures, with each of the one or more second metal structures corresponding to one or more second redundant structures. Each of the one or more second redundant structures is located on the same layer as the second metal structure corresponding to it. Each of the one or more second redundant structures is disposed in the first height layer away from the substrate 515, that is, each second redundant structure is higher than the first height layer where the first redundant array is located.

[0191] Alternatively, the memory 500 may include one or more fourth metal structures and one or more fourth redundant structures, with each of the one or more fourth metal structures corresponding to one or more fourth redundant structures. Each of the one or more fourth redundant structures is located on the same layer as the fourth metal structure corresponding to it. Each of the one or more fourth redundant structures is disposed in the first height layer away from the substrate 515, that is, each fourth redundant structure is higher than the first height layer where the first redundant array is located.

[0192] Optionally, the memory 500 may further include at least one third through-hole or at least one fourth through-hole. Each of the at least one third through-hole and each of the at least one fourth through-hole can be used to transfer plasma generated during the fabrication of the memory 500, avoiding damage to subsequent devices and improving the reliability of subsequent devices.

[0193] Optionally, the third via can be used to connect adjacent first redundant structures and third redundant structures, wherein the first redundant structure and the third redundant structure partially or completely overlap in the vertical direction, and the spacing between the first redundant structure and the third redundant structure is less than the seventh threshold.

[0194] For example, the memory 500 may also include a third through-hole connecting an adjacent first redundant structure 504 and a third redundant structure 502, wherein the first redundant structure 504 and the third redundant structure 502 partially or completely overlap in the vertical direction, and the spacing between the first redundant structure 504 and the third redundant structure 502 is less than a seventh threshold.

[0195] Optionally, the fourth via can be used to connect adjacent second and fourth redundant structures, and the second and fourth redundant structures partially or completely overlap in the vertical direction, and the spacing between the second and fourth redundant structures is less than the eighth threshold.

[0196] For example, the memory 500 may also include a fourth through-hole connecting an adjacent second redundant structure 510 and a fourth redundant structure 512, wherein the second redundant structure 510 and the fourth redundant structure 512 partially or completely overlap in the vertical direction, and the spacing between the second redundant structure 510 and the fourth redundant structure 512 is less than an eighth threshold.

[0197] When the memory 500 includes at least two first redundant structures, the memory 500 also includes a third through-hole for connecting two adjacent first redundant structures. The two adjacent first redundant structures partially or completely overlap in the vertical direction, and the distance between the two adjacent first redundant structures is less than a seventh threshold.

[0198] Alternatively, when the memory 500 includes at least two third redundant structures, the memory 500 also includes a third via for connecting two adjacent third redundant structures. The two adjacent third redundant structures partially or completely overlap in the vertical direction, and the distance between the two adjacent third redundant structures is less than a seventh threshold.

[0199] Depending on different practical needs or different CMP processes, the seventh threshold may be the same or different, and the embodiments of this application are not limited in this regard. For example, the value range of the seventh threshold is approximately 90 nanometers to 120 nanometers.

[0200] If the seventh threshold is large, the spacing between the two redundant structures connected by the third via is large, which increases the manufacturing difficulty and makes it easy for the two redundant structures to break. If the seventh threshold is small, the spacing between the two redundant structures connected by the third via is small, which is easier to manufacture, but it is prone to leakage problems, thus making the device unstable.

[0201] When the memory 500 includes at least two second redundant structures, the memory 500 also includes a fourth through-hole for connecting two adjacent second redundant structures. The two adjacent second redundant structures partially or completely overlap in the vertical direction, and the distance between the two adjacent second redundant structures is less than an eighth threshold.

[0202] When the memory 500 includes at least two fourth redundancy structures, the memory 500 also includes a fourth through-hole for connecting two adjacent fourth redundancy structures. The two adjacent fourth redundancy structures partially or completely overlap in the vertical direction, and the distance between the two adjacent fourth redundancy structures is less than an eighth threshold.

[0203] Depending on different practical needs or different CMP processes, the eighth threshold can be the same or different, and the embodiments of this application are not limited in this regard. For example, the value range of the eighth threshold can be from 200 nanometers to 400 nanometers.

[0204] If the eighth threshold is large, the spacing between the two redundant structures connected by the fourth via is large, which increases the manufacturing difficulty and makes it easy for the two redundant structures to break. If the eighth threshold is small, the spacing between the two second redundant structures connected by the fourth via is small, which is easier to manufacture, but it is prone to leakage problems, thus making the device unstable.

[0205] Optionally, the memory 500 may also include a fifth through-hole. This fifth through-hole can be used to transfer plasma generated during the fabrication of the memory 500, preventing subsequent device failures and improving the reliability of subsequent devices.

[0206] Optionally, the fifth via can be used to connect adjacent first redundant structures and second redundant structures. These adjacent first and second redundant structures partially or completely overlap in the vertical direction, and the spacing between them is less than a ninth threshold.

[0207] For example, if the memory 500 does not include a first storage array 506 or a first redundant array 507 located between the first redundant structure 504 and the second redundant structure 510, the memory 500 may also include a fifth via connecting adjacent first redundant structures 504 and second redundant structures 510. The adjacent first redundant structure 504 and second redundant structure 510 may partially or completely overlap, and the spacing between the first redundant structure 504 and the second redundant structure 510 is less than a ninth threshold.

[0208] Depending on different practical needs or different CMP processes, the ninth threshold can be the same or different, and the embodiments of this application are not limited in this regard. For example, the value range of the ninth threshold can be from 100 nanometers to 300 nanometers.

[0209] If the ninth threshold is large, the spacing between adjacent first and second redundant structures will be large, increasing the manufacturing difficulty and making it easier for the two redundant structures to disconnect. If the ninth threshold is small, the spacing between adjacent first and second redundant structures will be small, making the manufacturing process easier, but leakage current problems are more likely to occur, thus making the device unstable.

[0210] Figure 7 The memory 500 shown can make the edge portion of the first memory array more consistent with the surrounding environment of the center portion, thereby avoiding deviations caused during the photolithography process. Figure 7 The memory 500 shown can also improve the uniformity of the structure in each height layer and increase the smoothness of the layer after the CMP process by adding a first redundant array, a first redundant structure, and a second redundant structure. Figure 7 The memory 500 shown can also release plasma generated during the process through the first and second through holes, thereby improving the reliability of downstream devices.

[0211] In actual industrial manufacturing, the cross-sectional schematic diagram of the memory in the embodiments of this application is as follows: Figure 8 , 9 As shown.

[0212] Figure 8 A cross-sectional schematic diagram of the memory after adding a redundant array. Figure 8 Including, for example Figure 1 All structures shown are excluding the redundant structure DM0. Figure 8 It also includes a redundant array DMC.

[0213] The redundant array DMC and the memory array MC are at the same height relative to the front-end structure FEOL, meaning the DMC and MC are located at the same height level. Figure 5-7Similar to the first redundant array in the memory, the DMC has the same stacking structure as the memory array MC. In actual manufacturing, the height layer of the DMC is higher than the height layer of the redundant structure DM4.

[0214] because Figure 8 The redundant array DMC in the memory array has the same stacking structure as the memory array MC. Therefore, the environmental difference between the edge and center parts of the memory array MC is small, resulting in smaller deviations in the critical dimensions of the memory array MC during the photolithography process. Furthermore, because... Figure 8 The redundant array DMC in the structure has a relatively uniform structural distribution in the height layer. Therefore, during the CMP process, this layer is less prone to severe metal layer dishing or dielectric layer erosion problems.

[0215] Figure 9 A cross-sectional view of the memory after adding through-holes. Figure 9 Including, for example Figure 8 All the structures shown, and Figure 9 It also includes through holes DCONT1 and DCONT2.

[0216] Through-hole DCONT1 is positioned between the redundant structure DM4 and the redundant array DMC, and DCONT1 and CONT1 have the same height relative to FEOL, meaning DCONT1 and CONT1 are located at the same height level. DCONT1 is positioned from DM4 towards the redundant array DMC. In actual fabrication, the height level of DCONT1 is higher than that of DM4. Figure 6 Similar to, or related to, the first through hole 430 in the middle. Figure 7 The first through hole 505 is similar.

[0217] Through-hole DCONT2 is positioned between the redundant structure DM5 and the redundant array DMC, and DCONT2 and CONT2 have the same height relative to FEOL, meaning DCONT2 and CONT2 are located at the same height level. DCONT2 is positioned from DM5 towards the redundant array DMC. In actual fabrication, the height level of DCONT2 is higher than the height level of the redundant array DMC. DCONT2 and Figure 7 The second through hole 508 is similar.

[0218] Figure 9 The memory in the process releases plasma generated during the process by adding vias DCONT1 connecting the redundant structure DM4 to the redundant array DMC, and vias DCONT2 connecting the redundant structure DM5 to the DMC, thereby avoiding damage to the device.

[0219] Figure 10 It refers to the method of fabricating memory. Figure 10The method shown includes the following steps.

[0220] S610 forms the substrate for the memory.

[0221] Optionally, the substrate of the memory can be disposed at the lowest height layer, that is, the substrate can be lower than the first height. The first height is the height of the first memory array and the first redundant array relative to the substrate.

[0222] Optionally, the substrate can be of various forms, such as a silicon substrate, a bulk semiconductor material substrate, a semiconductor-on-insulator substrate, a compound semiconductor substrate, etc., and the embodiments of this application are not limited thereto. The substrate can be with Figure 1 The front-end structure FEOL, Figure 5 Substrate 330 in Figure 6 Substrate 470, or Figure 7 The substrate 515 is similar.

[0223] S620, a first memory array and a first redundant array are formed at the same height relative to the substrate.

[0224] A first memory array and a first redundant array are formed at the same height relative to the substrate. The height of the first memory array and the first redundant array relative to the substrate can be a first height. This first height is a range, not a specific numerical value. That is, the first redundant array and the first memory array can be placed in the same height layer, such as a first height layer, like... Figure 5 The memory 300 in the memory is shown.

[0225] The first memory array has a stacked structure consisting of at least one transistor and at least one capacitor unit, and the first memory array can be used to store data.

[0226] The first redundant array includes a stacked structure consisting of at least one transistor and at least one capacitor unit, and the stacked structure of the first redundant array is identical to that of the first memory array. The dimensions of the first redundant array and the first memory array in a first dimension are similar or identical. The first redundant array can be... Figure 5 Similar to the first redundant array 320 shown, this first storage array can be... Figure 5 The first storage array 310 shown is similar.

[0227] Optionally, the stacked structure of the first memory array and the first redundant array may include an mTnC structure, wherein the mTnC structure includes stacked m transistors and n capacitor units, where m and n are positive integers greater than or equal to 1.

[0228] Optionally, forming a first memory array and a first redundant array at the same height relative to the substrate includes: forming at least one transistor of the first memory array and at least one transistor of the first redundant array in the same layer as the first memory array and the first redundant array; and forming at least one capacitor cell of the first memory array and at least one capacitor cell of the first redundant array in the same layer as the first memory array and the first redundant array. This same layer may be the same wiring layer or the same multilayer wiring layer; this embodiment of the application is not limited in this respect.

[0229] Optionally, the stacked structure of the first memory array and the first redundant array may further include at least one of the following structures: word line, bit line, board line plane or pillar; any one of at least one transistor is connected to the word line, bit line or pillar; or, any one of at least one capacitor cell is disposed at the intersection of the board line plane and the pillar.

[0230] It should be understood that, based on the fact that the first redundant array has the same stacking structure as the first memory array, the first redundant array may have exactly the same electronic components as the first memory array, or may have partially the same electronic components as the first memory array.

[0231] Optionally, the first storage array is electrically connected to an external circuit outside the memory, and the first redundant array is configured in a circuit break or is not electrically connected to the circuit inside the memory. Alternatively, the first storage array can be configured in a circuit path, and the first redundant array cannot be electrically connected to either an external circuit outside the memory or the circuit inside the memory.

[0232] Optionally, the embodiments of this application do not limit the order in which the first memory array and the first redundant array are formed in the first height layer of the memory. For example, the first memory array may be formed first in the first height layer of the memory, and then the first redundant array may be formed in the first height layer of the memory. Alternatively, the first redundant array may be formed first in the first height layer of the memory, and then the first memory array may be formed in the first height layer of the memory. Alternatively, the first memory array and the first redundant array may be formed simultaneously in the first height layer of the memory.

[0233] Optionally, simultaneously forming a first memory array and a first redundant array in a first height layer includes: simultaneously forming at least one electronic component of the first memory array and at least one electronic component corresponding to the first redundant array in the first height layer. For example, simultaneously forming at least one word line of the first memory array and at least one word line corresponding to the first redundant array in the first height layer. Alternatively, simultaneously forming at least one bit line of the first memory array and at least one bit line corresponding to the first redundant array in the first height layer, etc.

[0234] Figure 10The memory fabrication method described above can add a first redundant array with the same stacked structure to the same height layer of the first memory array, thereby making the surrounding environment of the edge portion and the center portion of the first memory array more consistent and avoiding deviations caused by photolithography. Furthermore, adding a first redundant array with the same stacked structure can also make the structure in that height layer more uniform, thereby increasing the smoothness of that layer after the CMP process.

[0235] Figure 11 It refers to the method of fabricating memory. Figure 11 The method shown includes the following steps.

[0236] S710, forming the substrate of the memory. Step S710 is similar to step S610, and will not be described again here.

[0237] S720, a first metal structure and a first redundant structure are formed at the same height relative to the substrate.

[0238] The height of the first metal structure and the first redundant structure relative to the substrate can be a second height, which is a range rather than a specific value. In other words, the first metal structure and the first redundant structure can be disposed in a second height layer.

[0239] The second height layer is disposed in the direction of the first height layer toward the substrate of the memory, that is, the second height layer is lower than the first height layer of the memory. The first redundant structure of the second height layer in the memory has the same or similar dimensions in the second dimension as the first metal structure, and the first redundant structure has the same or similar material as the first metal structure. The first metal structure can be... Figure 7 The first metal structure 503 is similar to that in the previous section, and will not be described in detail here. This first redundant structure can be related to... Figure 7 The first redundant structure 504 is similar, and will not be described in detail here.

[0240] Optionally, the first metal structure and the first redundant structure can be formed simultaneously in the second height layer.

[0241] Optionally, the first metal structure can be a metal wire. The first metal structure can be electrically connected to an external circuit outside the memory. Alternatively, the first metal structure can be in a circuit path, i.e., the circuit containing the first metal structure is a closed circuit. Alternatively, the first metal structure cannot be in a circuit break, i.e., the circuit containing the first metal structure cannot be an open circuit.

[0242] Optionally, the first redundancy structure can be a metal block or sheet, or a metal wire. The first redundancy structure cannot be electrically connected to external circuits outside the memory or to circuits within the memory. Alternatively, the first redundancy structure cannot be in a circuit path, i.e., the circuit containing the first redundancy structure is not a closed circuit. Or, the first redundancy structure can be in a circuit open circuit, i.e., the circuit containing the first redundancy structure is an open circuit.

[0243] Optionally, before forming the first metal structure and the first redundant structure in the second height layer, a third metal structure and a third redundant structure may be formed in a fourth height layer. This fourth height layer is disposed in the direction from the second height layer toward the substrate, i.e., the fourth height layer is lower than the second height layer of the memory and higher than the substrate. The third redundant structure and the third metal structure have the same or similar dimensions in the fourth dimension, and the third redundant structure and the third metal structure are made of the same or similar material. The third metal structure can be... Figure 7 The third metal structure 501 is similar to that in the previous example, and will not be described further here. This third redundant structure can be connected with... Figure 7 The third redundancy structure 502 is similar and will not be described in detail here.

[0244] Optionally, a third through-hole may be formed before the first metal structure and the first redundant structure are formed in the second height layer. This third through-hole is used to connect adjacent first and third redundant structures. These adjacent first and third redundant structures partially or completely overlap, and the spacing between them is less than a seventh threshold.

[0245] The sequence for forming the third via is as follows: first, a third metal structure and a third redundant structure are formed in the fourth height layer; second, a third via is formed, with one side of the third via connected to the third redundant structure; then, a first metal structure and a first redundant structure are formed in the second height layer, with the first redundant structure connected to the other side of the third via.

[0246] Optionally, multiple first redundant structures can be formed, and a third via can be formed between two adjacent first redundant structures. These two adjacent first redundant structures have partial or complete overlap, and the spacing between the two first redundant structures is less than a seventh threshold. The implementation of forming a third via between two adjacent first redundant structures is similar to the above description and will not be repeated here.

[0247] Alternatively, multiple third redundant structures can be formed, and a third via can be formed between two adjacent third redundant structures. These adjacent third redundant structures may have partial or complete overlap, and the spacing between the two third redundant structures is less than the seventh threshold. The implementation of forming a third via between two adjacent third redundant structures is similar to the above description and will not be repeated here.

[0248] S730 forms the first through hole.

[0249] After forming the first metal structure and the first redundant structure at the same height relative to the substrate, a first via can be formed. This first via is used to connect the first redundant structure and the first redundant array; that is, the first via can be disposed between the first height layer and the second height layer. The first via and... Figure 6 Similar to, or related to, the first through hole 430 in the middle. Figure 7 The first through hole 505 is similar.

[0250] Optionally, the first via cannot be electrically connected to an external circuit outside the memory or a circuit within the memory. Alternatively, the first via cannot be in a circuit path, i.e., the circuit containing the first via is not a closed circuit. Alternatively, the first via can be in a circuit break, i.e., the circuit containing the first via is an open circuit.

[0251] S740, a first memory array and a first redundant array are formed at the same height relative to the substrate.

[0252] After forming the first via, a first memory array and a first redundant array can be formed at the same height relative to the substrate. The height of the first memory array and the first redundant array relative to the substrate is a first height, meaning the first memory array and the first redundant array are located at a first height layer. This first height layer is disposed in a direction away from the substrate from the second height layer, meaning the first height layer is higher than the second height layer. The first redundant array is connected to the first via.

[0253] The specific implementation of forming the first memory array and the first redundant array at the same height relative to the substrate is similar to step S610, and will not be repeated here.

[0254] S750 forms the second through hole.

[0255] After forming the first memory array and the first redundant array at the same height relative to the substrate, a second via can be formed. This second via connects the first redundant array and the second redundant structure; that is, the second via is located between the first height layer and the third height layer. This second via and... Figure 7 The second through hole 508 is similar.

[0256] Optionally, the second via cannot be electrically connected to external circuits outside the memory or to circuits within the memory. Alternatively, the second via cannot be in a circuit path, meaning the circuit containing the second via is not a closed circuit. Alternatively, the second via can be in a circuit break, meaning the circuit containing the second via is an open circuit.

[0257] S760, a second metal structure and a second redundant structure are formed at the same height relative to the substrate.

[0258] The height of the second metal structure and the second redundant structure relative to the substrate can be a third height, meaning the second metal structure and the second redundant structure can be located in a third height layer. The third height layer is disposed in the direction away from the substrate from the first height layer, meaning the third height layer is higher than the first height layer. The second redundant structure and the second metal structure in the third height layer have the same or similar dimensions in the third dimension, and the second redundant structure and the second metal structure are made of the same or similar materials. The second metal structure can be... Figure 7 The second metal structure 509 is similar to that in the previous example, and will not be described further here. This second redundant structure can be connected with... Figure 7 The second redundant structure 510 is similar and will not be described in detail here.

[0259] Optionally, a second metal structure and a second redundant structure can be formed simultaneously in the third height layer.

[0260] Optionally, the second metal structure can be a metal wire. The second metal structure can be electrically connected to an external circuit outside the memory. Alternatively, the second metal structure can be in a circuit path, i.e., the circuit containing the second metal structure is a closed circuit. Alternatively, the second metal structure cannot be in an open circuit, i.e., the circuit containing the second metal structure cannot be an open circuit. Since the first metal structure, the first memory array, and the second metal structure can be electrically connected to an external circuit outside the memory, the first memory array 506 can store data, i.e., it has the substantial function of storing data.

[0261] Optionally, the second redundancy structure can be a metal block or sheet, or a metal wire. The second redundancy structure cannot be electrically connected to external circuits outside the memory or to circuits within the memory. Alternatively, the second redundancy structure cannot be in a circuit path, meaning the circuit containing the second redundancy structure is not a closed circuit. Or, the second redundancy structure can be in a circuit open circuit, meaning the circuit containing the second redundancy structure is an open circuit. Although the first redundancy array has the same stacking structure as the first memory array, because the first redundancy structure, the first via, the first redundancy array, the second via, and the second redundancy structure cannot be electrically connected to external circuits outside the memory, the first redundancy array cannot be used to store data, i.e., it cannot have the substantial function of storing data.

[0262] Optionally, after forming the second metal structure and the second redundant structure in the third height layer, a fourth metal structure and a fourth redundant structure can also be formed in the fifth height layer. The fifth height layer is disposed in the direction away from the substrate from the third height layer, i.e., the fifth height layer is higher than the third height layer. The fourth redundant structure and the fourth metal structure in the fifth height layer have the same or similar dimensions in the fifth dimension, and the fourth redundant structure and the fourth metal structure are made of the same or similar material. This fourth metal structure can be... Figure 7 The fourth metal structure 511 is similar to that in [the previous section], and will not be described further here. This fourth redundant structure can be [compared to / into / other structures]. Figure 7 The fourth redundancy structure 512 is similar and will not be described in detail here.

[0263] Optionally, a fourth via may be formed before the fourth metal structure and the fourth redundant structure are formed in the fifth height layer. This fourth via is used to connect adjacent second and fourth redundant structures. These adjacent second and fourth redundant structures partially or completely overlap, and the spacing between them is less than an eighth threshold.

[0264] The sequence for forming the fourth via is as follows: first, a second metal structure and a second redundant structure are formed in the third height layer; second, a fourth via is formed, with one side of the fourth via connected to the second redundant structure; then, a fourth metal structure and a fourth redundant structure are formed in the fifth height layer, with the fourth redundant structure connected to the other side of the fourth via.

[0265] Optionally, multiple second redundant structures can be formed, and a fourth via can be formed between two adjacent second redundant structures. The two adjacent second redundant structures may have partial or complete overlap, and the spacing between them is less than an eighth threshold. The implementation of forming the fourth via between two adjacent second redundant structures is similar to the above description and will not be repeated here.

[0266] Alternatively, multiple fourth redundancy structures can be formed, and a fourth via can be formed between two adjacent fourth redundancy structures. These two adjacent fourth redundancy structures may have partial or complete overlap, and the distance between them is less than the eighth threshold. The implementation of forming a fourth via between two adjacent fourth redundancy structures is similar to the above description and will not be repeated here.

[0267] Figure 11The method for fabricating the memory in this process utilizes a first redundant array with identical stacked structures, ensuring that the edges of the first memory array are more uniform with the surrounding environment of the center, thus avoiding deviations caused by photolithography. Furthermore, this method also results in a more uniform structure within each height layer, increasing the smoothness of that layer after the CMP process. Simultaneously, this method can release plasma generated during the process through first and second vias, thereby preventing damage to subsequent devices.

[0268] This application also provides a memory, which includes a controller and a first memory array and a first redundant array as described in the above-described embodiments. The controller is electrically connected to the first memory array.

[0269] This application also provides an electronic device, which includes a circuit board and the memory described in the above-described embodiments.

[0270] This application also provides an electronic device, which includes a circuit board, a controller, and a first storage array and a first redundancy array as described in the above-described embodiments.

[0271] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0272] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0273] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0274] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0275] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0276] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0277] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A memory, characterized in that, include: Substrate, first memory array and first redundant array; The first memory array includes a stacked structure consisting of at least one transistor and at least one capacitor unit, and the first memory array is used to store data; The first redundant array and the first memory array have the same height relative to the substrate. The first redundant array includes a stacked structure consisting of at least one transistor and at least one capacitor unit. The stacked structure of the first redundant array is the same as that of the first memory array.

2. The memory according to claim 1, characterized in that, The stacked structure of the first memory array and the first redundant array includes an mTnC structure, wherein the mTnC structure includes stacked m transistors and n capacitor units, where m and n are positive integers greater than or equal to 1.

3. The memory according to claim 1 or 2, characterized in that, At least one transistor of the first memory array is disposed on the same layer as at least one transistor of the first redundant array, and at least one capacitor cell of the first memory array is disposed on the same layer as at least one capacitor cell of the first redundant array.

4. The memory according to any one of claims 1 to 3, characterized in that, The stacked structure of the first storage array and the first redundant array further includes at least one of the following structures: word line, bit line, board line plane or pillar; Any one of the at least one transistors is connected to the word line, the bit line, or the pillar; or... Any one of the at least one capacitor unit is disposed at the intersection of the plate line plane and the support column.

5. The memory according to any one of claims 1 to 4, characterized in that, The first storage array is electrically connected to an external circuit outside the memory, and the first redundant array is either in a circuit break or not electrically connected to the circuit in the memory.

6. The memory according to any one of claims 1 to 5, characterized in that, The memory further includes: a first metal structure, a first redundant structure, and a first through-hole; The first metal structure and the first redundant structure are at the same height relative to the substrate, and the height of the first redundant structure relative to the substrate is lower than the height of the first redundant array relative to the substrate. The first through hole is used to connect the first redundant structure and the first redundant array.

7. The memory according to any one of claims 1 to 6, characterized in that, The memory further includes: a second metal structure, a second redundant structure, and a second through-hole; The second metal structure and the second redundant structure are at the same height relative to the substrate, and the second redundant structure is at a higher height relative to the substrate than the first redundant array is at a higher height relative to the substrate. The second through hole is used to connect the second redundant structure to the first redundant array.

8. A method for fabricating a memory, characterized in that, include: The substrate for forming the memory; A first memory array and a first redundant array are formed at the same height relative to the substrate. The first memory array includes a stacked structure consisting of at least one transistor and at least one capacitor cell. The first memory array is used to store data. The first redundant array includes a stacked structure consisting of at least one transistor and at least one capacitor cell. The stacked structure of the first redundant array is the same as that of the first memory array.

9. The method according to claim 8, characterized in that, The first memory array and the first redundant array stacked structure includes an mTnC structure, wherein the mTnC structure includes stacked m transistors and n capacitor units, where m and n are positive integers greater than or equal to 1.

10. The method according to claim 8 or 9, characterized in that, The step of forming a first memory array and a first redundancy array at the same height relative to the substrate includes: At least one transistor of the first memory array and at least one transistor of the first redundant array are formed in the same layer as the first memory array and the first redundant array. At least one capacitor cell of the first storage array and at least one capacitor cell of the first redundant array are formed in the same layer as the first storage array and the first redundant array.

11. The method according to any one of claims 8 to 10, characterized in that, The stacked structure of the first storage array and the first redundant array further includes at least one of the following structures: word line, bit line, board line plane or pillar; Any one of the at least one transistors is connected to the word line, the bit line, or the pillar; or... Any one of the at least one capacitor unit is disposed at the intersection of the plate line plane and the support column.

12. The method according to any one of claims 8 to 11, characterized in that, The first storage array is electrically connected to an external circuit outside the memory, and the first redundant array is either in a circuit break or not electrically connected to the circuit in the memory.

13. The method according to any one of claims 8 to 12, characterized in that, Before forming the first memory array and the first redundant array at the same height relative to the substrate, the method further includes: A first metal structure and a first redundant structure are formed at the same height relative to the substrate, wherein the height of the first redundant structure relative to the substrate is lower than the height of the first redundant array relative to the substrate. A first through-hole is formed, which is used to connect the first redundant structure and the first redundant array.

14. The method according to any one of claims 8 to 13, characterized in that, The method further includes: A second through-hole is formed, which is used to connect the second redundant structure to the first redundant array; A second metal structure and a second redundant structure are formed at the same height relative to the substrate, wherein the height of the second redundant structure relative to the substrate is higher than the height of the first redundant array relative to the substrate.

15. A memory, characterized in that, It includes a controller and a first storage array and a first redundant array as described in any one of claims 1 to 7, wherein the controller and the first storage array are electrically connected.

16. An electronic device, characterized in that, Includes a circuit board and a memory as described in any one of claims 1 to 7.

17. An electronic device, characterized in that, Includes a circuit board and the memory as described in claim 15.

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