Capacitance detection circuit and method

Abstract

The application relates to the technical field of capacitance detection, and discloses a capacitance detection circuit and method, which comprises an input circuit, a capacitance power supply circuit, an output circuit, a detection circuit and a control circuit; the input circuit, the capacitance power supply circuit, the output circuit and a load are sequentially connected, the capacitance power supply circuit is connected with the detection circuit, and the control circuit is connected with the capacitance power supply circuit and the detection circuit respectively; a plurality of capacitors are arranged in the capacitance power supply circuit; wherein the control circuit is used for determining a time-sharing detection instruction based on a preset detection period, and the detection circuit is used for sequentially detecting each capacitor based on the time-sharing detection instruction. The application realizes capacitance detection under the premise that the capacitance circuit is normally powered.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of capacitance detection, and particularly relates to a capacitance detection circuit and method. BACKGROUND

[0002] With the rapid development of electrical products, more and more circuits using capacitors to supply power to electrical products. However, the storage capacity of the capacitor decreases with the increase of the use time, which affects the normal power supply of the electrical product. Therefore, higher requirements are put forward for the detection of the capacitor.

[0003] The traditional capacitance detection method is to control the discharge of a single capacitor to be detected, and determine the capacitance of the capacitor at this time according to the current and voltage during the discharge of the capacitor, and then realize the capacitance detection. This capacitance detection method has great defects, which can only be used for the detection of a single capacitor, and cannot guarantee the normal power supply of the capacitor when detecting multiple capacitors. Therefore, a new capacitance detection circuit is needed to realize capacitance detection under the premise of ensuring the normal power supply of the capacitor circuit. SUMMARY

[0004] The main purpose of the present application is to provide a capacitance detection circuit and method, which aims to realize capacitance detection under the premise of normal power supply of the capacitor circuit.

[0005] To achieve the above purpose, the present application provides a capacitance detection circuit, which comprises an input circuit, a capacitor power supply circuit, an output circuit, a detection circuit and a control circuit.

[0006] The input circuit, the capacitor power supply circuit, the output circuit and the load are connected in sequence, the capacitor power supply circuit is connected with the detection circuit, and the control circuit is connected with the capacitor power supply circuit and the detection circuit respectively; the capacitor power supply circuit comprises a plurality of capacitors.

[0007] The control circuit is used for determining a time-sharing detection instruction based on a preset detection period, and the detection circuit is used for detecting each capacitor in sequence based on the time-sharing detection instruction.

[0008] Optionally, the capacitor power supply circuit comprises N capacitor power supply circuits; wherein N is not less than 2, and N-1 capacitor power supply circuits are the number of capacitor power supply circuits required by the load.

[0009] The input circuit, the first end of the capacitor power supply circuit and the output circuit are connected in sequence, the second end of the capacitor power supply circuit is connected with the system power supply ground, the third end of the capacitor power supply circuit is connected with the detection circuit, and the fourth end of the capacitor power supply circuit is connected with the control circuit.

[0010] Optionally, the output circuit comprises at least a boost circuit, an input end of the boost circuit being connected with the first end of the capacitor supply circuit, and an output end of the boost circuit being connected with the load.

[0011] Optionally, the capacitor supply circuit comprises a first switch tube, a power supply capacitor and a first grounding resistor, a first end of the first switch tube being the first end of the capacitor supply circuit, a control end of the first switch tube being connected with a first end of the first grounding resistor and then being the fourth end of the capacitor supply circuit, a second end of the first grounding resistor being connected with the system power ground, a second end of the first switch tube being connected with a first end of the power supply capacitor and then being the third end of the capacitor supply circuit, and a second end of the power supply capacitor being the second end of the capacitor supply circuit.

[0012] Optionally, the detection circuit comprises N capacitor detection sub-circuits connected with the capacitor supply circuit respectively and a detection control circuit.

[0013] A first end of the capacitor detection sub-circuit is connected with the third end of the capacitor supply circuit, a second end of the capacitor detection sub-circuit is connected with the control circuit, and the third end of the capacitor supply circuit is connected with the detection control circuit.

[0014] Optionally, the capacitor detection sub-circuit comprises a second switch tube and a second grounding resistor, a first end of the second switch tube being the first end of the capacitor detection sub-circuit, a control end of the second switch tube being connected with a first end of the second grounding resistor and then being the second end of the capacitor detection sub-circuit, a second end of the second grounding resistor being connected with the system power ground, and a second end of the second switch tube being connected with the detection control circuit.

[0015] Optionally, the detection control circuit comprises a first voltage dividing resistor, a second voltage dividing resistor, a comparator, a voltage stabilizing circuit and a resistor discharging circuit, wherein the resistor discharging circuit comprises a plurality of discharging resistors connected in parallel and having the same resistance value.

[0016] A first input end of the comparator is connected with the third end of the capacitor supply circuit, a first end of the first voltage dividing resistor is connected with a comparison voltage, a second end of the first voltage dividing resistor is connected with a second input end of the comparator and a first end of the second voltage dividing resistor respectively, a second end of the second voltage dividing resistor is connected with the system power ground, an output end of the comparator is connected with an enable end of the voltage stabilizing circuit, an input end of the voltage stabilizing circuit is connected with a third end of the capacitor detection sub-circuit, an output end of the voltage stabilizing circuit is connected with a first end of the resistor discharging circuit, and a second end of the resistor discharging circuit is connected with the system power ground.

[0017] Optionally, the control circuit comprises a central processor and a control chip, the central processor is in communication connection with the control chip, and the control chip is provided with N first control ports, N second control ports and an enable control port;

[0018] The enable control port is connected with an enable end of the voltage stabilizing circuit, N first control ports are respectively connected with fourth ends of N capacitor charging sub-circuits, and N second control ports are respectively connected with second ends of N capacitor detection sub-circuits.

[0019] In addition, to achieve the above-mentioned purpose, the application further provides a capacitor detection method, which is applied to the capacitor detection circuit, and the steps of the converter method, comprising:

[0020] If the current detection interval length meets the preset detection period, a time-sharing detection instruction is generated;

[0021] Capacitor detection is performed according to the time-sharing detection instruction.

[0022] Optionally, the step of performing capacitor detection according to the time-sharing detection instruction comprises:

[0023] A switch tube control instruction of a target capacitor is generated based on the time-sharing detection instruction; wherein the switch tube control instruction is an instruction for controlling the target capacitor to be disconnected from an output circuit and connected with the detection circuit;

[0024] A duration of a real-time enable signal when the switch tube control instruction is executed is obtained; wherein the real-time enable signal comprises an enable end signal of a voltage stabilizing circuit in the detection circuit, and the duration refers to a duration of the real-time enable signal in the same state;

[0025] A detection result of the target capacitor is determined based on the duration and preset circuit parameters;

[0026] After the step of determining the detection result of the target capacitor based on the duration and preset circuit parameters, comprising:

[0027] The target capacitor is updated based on a preset detection sequence, and the step of obtaining the duration of the real-time enable signal when the switch tube control instruction is executed is executed based on the target capacitor after the update.

[0028] The application provides a capacitor detection circuit, which comprises an input circuit, a capacitor power supply circuit, an output circuit, a detection circuit and a control circuit; the input circuit, the capacitor power supply circuit, the output circuit and a load are sequentially connected, the capacitor power supply circuit is connected with the detection circuit, and the control circuit is connected with the capacitor power supply circuit and the detection circuit respectively; the capacitor power supply circuit comprises a plurality of capacitors; wherein the control circuit is used for determining a time-sharing detection instruction based on a preset detection period, and the detection circuit is used for sequentially detecting each capacitor based on the time-sharing detection instruction.

[0029] By determining a time-sharing detection instruction based on a preset detection period, and sequentially detecting each capacitor based on the time-sharing detection instruction in the detection circuit, the phenomenon that the capacitor detection mode in the prior art can only be used for detecting a single capacitor and cannot guarantee normal power supply of the capacitor when detecting multiple capacitors is avoided, and capacitor detection can be realized under the premise of normal power supply of the capacitor circuit. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of the drawings shown.

[0031] Figure 1 It is a structural schematic diagram of the capacitor detection circuit of the present application.

[0032] Figure 2 It is a connection schematic diagram of the capacitor detection circuit of the present application.

[0033] Figure 3 It is another connection schematic diagram of the capacitor detection circuit of the present application.

[0034] Figure 4 It is a schematic diagram of the control circuit of the capacitor detection circuit of the present application.

[0035] Figure 5 It is a flow schematic diagram of an embodiment of the capacitor detection method of the present application.

[0036] Figure 6 It is a flow schematic diagram of the capacitor detection method of the present application.

[0037] Explanation of reference numerals:

[0038]

[0039]

[0040] The purposes, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0041] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the protection scope of the present application.

[0042] It should be noted that if the embodiments of the present application involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative position relationship, movement condition, etc. between components in a certain posture (as shown in the drawings). If the certain posture changes, the directional indications also change accordingly.

[0043] In addition, if the embodiments of the present application involve descriptions of “first”, “second”, etc., the descriptions of “first”, “second”, etc. are only for description purposes, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features limited by “first”, “second” can explicitly or implicitly include at least one of the features. In addition, the technical solutions of the various embodiments can be combined with each other, but it must be based on the fact that a person of ordinary skill in the art can realize the combination. When the combination of technical solutions contradicts each other or cannot be realized, it should be considered that the combination of technical solutions does not exist and is not within the protection scope of the present application.

[0044] The present application provides a capacitance detection circuit.

[0045] In an embodiment of the present application, as shown in Figure 1 FIG. 1 is a structural schematic diagram of a capacitance detection circuit, which comprises an input circuit 10, a capacitance power supply circuit 20, an output circuit 30, a detection circuit 40 and a control circuit 50. Figure 1

[0046] The input circuit 10, the capacitance power supply circuit 20, the output circuit 30 and a load 100 are connected in sequence, the capacitance power supply circuit 20 is connected with the detection circuit 40, and the control circuit 50 is connected with the capacitance power supply circuit 20 and the detection circuit 40 respectively; the capacitance power supply circuit 20 comprises a plurality of capacitors.

[0047] ​The control circuit 50 is configured to determine a time-sharing detection instruction based on a preset detection period, and the detection circuit 40 is configured to detect each capacitor in sequence based on the time-sharing detection instruction.

[0048] In some industrial control occasions, due to cost constraints, it is impossible to equip each device with a power supply, which may cause data loss due to abnormal power failure. In order to ensure that the key data is saved, a low-cost power failure saving circuit is usually built into the whole machine. The general power failure saving circuit generally uses a super capacitor for power supply. However, with the increase of service life and the influence of field working conditions, the capacity of the super capacitor will gradually decrease. When the capacity decreases to a certain value, the power supply time of the power failure saving cannot be met, and the key data will still be lost in abnormal power failure. Therefore, based on the above use of super capacitors or ordinary capacitors for power supply, there is an urgent need for a capacitor detection circuit to detect the capacitor power supply scene.

[0049] In this embodiment, the commonly used detection method is to control the capacitor to discharge at a fixed detection time to realize capacitor detection. At this time, the entire circuit needs to be separately removed for detection, or a special and separate control program is used for control detection, or the capacity of the super capacitor is directly detected. When the super capacitor needs to be discharged, if the system is powered off at this time, the power failure saving circuit will be invalid due to insufficient super capacitor power, and the entire circuit function will be invalid. Based on the above problems, this embodiment provides a low-cost super capacitor life detection method suitable for power failure saving circuits (which can also be other circuits using capacitors or super capacitors for power supply, and hereinafter the power failure circuit is taken as an example). By determining a time-sharing detection instruction based on a preset detection period, and detecting each capacitor in the detection circuit based on the time-sharing detection instruction, capacitor detection can be realized under the premise that the capacitor circuit is normally powered. The preset detection period refers to the period defined by the user for using capacitors or super capacitors, and the time-sharing detection instruction refers to the instruction for detecting the capacitors or super capacitors in the power failure circuit at different times. It is worth noting that the entire capacitor detection circuit also includes a first diode D1 and a second diode D2. The first diode D1 is connected between the input circuit 10 and the capacitor power supply circuit 20, and the second diode D2 is connected between the output circuit 30 and the load 100, so as to prevent current backflow during charging and power supply. The super capacitor capacity can be checked regularly by the time-sharing detection and the design of the capacitor in the circuit, and the overall capacity of the super capacitor is not affected, that is, when the super capacitor capacity is detected, the data can still be saved in abnormal power failure.

[0050] The embodiment provides a capacitor detection circuit, which comprises an input circuit, a capacitor power supply circuit, an output circuit, a detection circuit and a control circuit; the input circuit, the capacitor power supply circuit, the output circuit and a load are sequentially connected, the capacitor power supply circuit is connected with the detection circuit, and the control circuit is connected with the capacitor power supply circuit and the detection circuit respectively; the capacitor power supply circuit comprises a plurality of capacitors; wherein the control circuit is used for determining a time-sharing detection instruction based on a preset detection period, and the detection circuit is used for sequentially detecting each capacitor based on the time-sharing detection instruction. The time-sharing detection instruction is determined based on the preset detection period, and each capacitor is sequentially detected based on the time-sharing detection instruction in the detection circuit. Thus, the phenomenon that the capacitor detection mode in the prior art can only be used for detecting a single capacitor and cannot guarantee normal power supply of the capacitors when multiple capacitors are detected is avoided. Each capacitor is sequentially detected based on the time-sharing detection instruction in the detection circuit, and thus capacitor detection can be realized under the premise of normal power supply of the capacitor circuit.

[0051] Further, in another embodiment of the capacitor detection circuit, referring to Figure 2 , Figure 2 is a connection diagram of the capacitor detection circuit, the capacitor power supply circuit 20 comprises N capacitor power supply circuits 21-2N; wherein N is not less than 2, and N-1 capacitor power supply circuits 21-2N are the number of capacitor power supply circuits required by the load 100;

[0052] The input circuit 10, the first end of the capacitor power supply circuit 21-2N and the output circuit 30 are sequentially connected, the second end of the capacitor power supply circuit 21-2N is connected with a system power supply ground, the third end S1-SN of the capacitor power supply circuit 21-2N is connected with the detection circuit 40, and the fourth end K1-KN of the capacitor power supply circuit 21-2N is connected with the control circuit 50.

[0053] Specifically, the output circuit 30 at least comprises a boost circuit 31, the input end of the boost circuit 31 is connected with the first end of the capacitor power supply circuit 21-2N, and the output end of the boost circuit 31 is connected with the load 100.

[0054] Specifically, the capacitor power supply circuit 21-2N (taking the capacitor power supply circuit 21 as an example) comprises a first switch tube M1, a power supply capacitor C1 and a first ground resistor RX, the first end of the first switch tube M1 is the first end of the capacitor power supply circuit 21, the control end of the first switch tube M1 is connected with the first end of the first ground resistor RX and then becomes the fourth end of the capacitor power supply circuit 21, the second end of the first ground resistor RX is connected with the system power supply ground, the second end of the first switch tube M1 is connected with the first end of the power supply capacitor C1 and then becomes the third end of the capacitor power supply circuit 21, and the second end of the power supply capacitor C1 is the second end of the capacitor power supply circuit 21.

[0055] In the embodiment, the capacitor power supply circuit 20 comprises N capacitor power supply circuits 21-2N; wherein N is not less than 2, and N-1 capacitor power supply circuits 21-2N are the number of capacitor power supply circuits required by the load 100, that is, N is the number of capacitors that meet the power failure saving time, and one super capacitor is additionally arranged to meet the basic power failure saving time requirement in the time-sharing detection (N-1 capacitor power supply circuits ensure normal data saving of the load, and one capacitor power supply circuit performs capacitor detection each time power failure protection is performed). The circuit comprises a charging circuit 11, a current limiting circuit 12, a super capacitor parallel circuit and a boost circuit 31 in an output circuit 30, and needs to be noted that the charging circuit 11 and the current limiting circuit 12 can be common charging circuits and current limiting circuits, and the boost circuit 31 can be a boost circuit or other boost circuits. Each capacitor power supply circuit comprises a first switch tube M1, a power supply capacitor C1 and a first ground resistor RX, such as the capacitor power supply circuit 2(N-1) comprising a first switch tube M1, a power supply capacitor C(N-1) and a first ground resistor RX, and then the third end S1-SN of the capacitor power supply circuit 21-2N is connected with a detection circuit 40 respectively, thereby realizing detection of each circuit of the capacitor power supply circuit 21-2N, and the fourth end K1-KN of the capacitor power supply circuit 21-2N is connected with a control circuit 50, thereby realizing power supply of the capacitor power supply circuit 21-2N to the load. Since there is actually one more capacitor power supply circuit 21-2N, N-1 capacitor power supply circuits can ensure normal data saving of the load each time power failure protection is performed, and one capacitor power supply circuit can perform capacitor detection, and capacitor detection can be realized on the premise that the capacitor circuit is normally powered.

[0056] In still another embodiment, referring to Figure 3 , Figure 3As another connection diagram of the capacitor detection circuit, the detection circuit 40 comprises N capacitor detection sub-circuits 41-4N (taking the capacitor detection sub-circuit 41 as an example) and a detection control circuit connected with the capacitor supply circuit 21-2N respectively, wherein N is an integer greater than or equal to 1.

[0057] The first end of the capacitor detection sub-circuit 41 is connected with the third end of the capacitor supply circuit 21, the second end Z1 of the capacitor detection sub-circuit 41 is connected with the control circuit 50, and the third end of the capacitor supply circuit 41 is connected with the detection control circuit.

[0058] Specifically, the capacitor detection sub-circuit 41 comprises a second switch tube M2 and a second ground resistance RN, the first end of the second switch tube M2 is taken as the first end of the capacitor detection sub-circuit 41, the control end of the second switch tube M2 is connected with the first end of the second ground resistance RN and then taken as the second end Z1 of the capacitor detection sub-circuit 41, the second end of the second ground resistance RN is connected with the system power supply ground, and the second end of the second switch tube M2 is connected with the detection control circuit.

[0059] Specifically, the detection control circuit comprises a first voltage dividing resistance R1, a second voltage dividing resistance R2, a comparator U, a voltage stabilizing circuit 4B and a resistance discharging circuit 4C; wherein the resistance discharging circuit 4C comprises a plurality of discharging resistances RM connected in parallel and having the same resistance value.

[0060] The first input end of the comparator U is connected with the third end of the capacitor supply circuit 21, the first end of the first voltage dividing resistance R1 is connected with a comparison voltage VCC, the second end of the first voltage dividing resistance R1 is connected with the second input end of the comparator U and the first end of the second voltage dividing resistance R2 respectively, the second end of the second voltage dividing resistance R2 is connected with the system power supply ground, the output end of the comparator U is connected with the enable end EN of the voltage stabilizing circuit, the input end of the voltage stabilizing circuit 4B is connected with the third end of the capacitor detection sub-circuit 21, the output end of the voltage stabilizing circuit 4B is connected with the first end of the resistance discharging circuit 4C, and the second end of the resistance discharging circuit 4C is connected with the system power supply ground.

[0061] In the embodiment, the time-sharing detection voltage stabilizing circuit 3B is a boost voltage stabilizing circuit, and the detection circuit 40 comprises N capacitor detection sub-circuits, such as the capacitor detection sub-circuit 41 connected to the capacitor supply circuit 21, the capacitor detection sub-circuit 42 connected to the capacitor supply circuit 22, the capacitor detection sub-circuit 43 connected to the capacitor supply circuit 23, and the capacitor detection sub-circuit 4N connected to the capacitor supply circuit 2N. The capacitor detection sub-circuit 41 comprises a second switch tube M2 and a second ground resistor RN, and the detection of the capacitor is realized by controlling the second switch tube M2 (the second switch tube M2 is connected to the capacitor and the detection control circuit, and the first switch tube M1 is disconnected from the capacitor and the load). The boost voltage stabilizing circuit and the resistor discharge circuit 4C are current stabilizing circuits, which are used to confirm that the discharge of the capacitor is constant in voltage and current, so as to calculate the capacity of the super capacitor. The time-sharing detection circuit can ensure that the power-off saving circuit is not affected when the capacity detection is performed. Since the discharge of the super capacitor is an unstable signal, the current and voltage can be stabilized by the voltage stabilizing circuit 4B, and the capacity of the capacitor can be determined by determining the discharge time, and then it can be determined whether the capacitor needs to be replaced according to the determined capacity of the capacitor. The comparator U is used to output a specific level when the voltage value of the capacitor discharge is lower than a preset value (for example, when the voltage of the capacitor discharge is higher than the preset value, the comparator U outputs a high level, and when the voltage of the capacitor discharge is lower than the preset value, the comparator U outputs a low level, and then the time of the high level output by the comparator U can be used as the discharge time of the capacitor). Since the capacity of the capacitor is related to the voltage change rate (the inverse of the voltage and time) and the current, and the voltage and current are constant due to the voltage stabilizing circuit 4B, the detection result of the capacitor can be determined based on the discharge time of the capacitor. Then, the capacitor detection can be realized under the premise that the capacitor circuit normally supplies power.

[0062] In an embodiment of the application, as shown in Figure 4 Figure 4 The control circuit of the capacitor detection circuit of the application is a schematic diagram, which comprises a central processing unit and a control chip, the central processing unit CPU is in communication connection with the control chip MCU, the control chip MCU is provided with N first control ports, N second control ports and an enable control port;

[0063] The enable control port is connected with the enable end of the voltage stabilizing circuit, the N first control ports are respectively connected with the fourth ends of the N capacitor supply circuits 21-2N, and the N second control ports are respectively connected with the second ends of the N capacitor detection sub-circuits 41-4N.

[0064] ​In the embodiment, the whole circuit control logic is implemented by relying on a CPLD (omplex Programmable Logic Device, complex logic programmer) (FPGA (Field Programmable Gate Array, logic programmer) / MCU (Microcontroller Unit, microcontroller) active control device can be used), and a communication interface is needed between the CPLD and the CPU (Central Processing Unit, central processor) to transmit the super capacitor capacity alarm information to the CPU; the CPLD opens the super capacitor capacity detection circuit through N first control ports and N second control ports, calculates the super capacitor capacity through U / I / T and other key parameters, and feeds back the result to the CPU, and the CPU prompts the customer super capacitor capacity information according to the feedback data. Since the super capacitor capacity attenuation period is long, the capacity detection period can be extended to a month, so as to prevent the super capacitor life from being affected by too many detection frequencies. The boost circuit in the output circuit 30 also communicates with the CPLD, and when the CPU knows that power failure protection is needed, the CPU informs the CPLD that work is needed, and then the CPLD controls the conduction between the capacitor and the load 100 to supply power. If the first super capacitor is to be detected, the N first control ports will output an on-off transistor instruction, such as high level for on-off transistor, and low level for off-off transistor. Then the first control ports of the second to the Nth output high level, and the first control port outputs low level. At this time, the super capacitor 2-N supplies power to the load, the second to the Nth second control port outputs low level, and the first second control port outputs high level. At this time, the super capacitor 1 is connected to the detection circuit for detection, and the discharge time of the super capacitor 1 can be determined by connecting the enable control port to receive the enable signal output by the comparator U or directly connecting the PW end of the voltage stabilizing circuit 3B. Then, based on the time, the capacitor capacity of the super capacitor 1 is detected, and then the capacitor capacity of the super capacitor 2 is detected (the super capacitors 1-N are fully charged and are used for power failure protection next time). Then, based on a simple circuit, the capacitor detection can be quickly realized, the accuracy of the capacitor detection is ensured, and the detection efficiency is greatly improved.

[0065] Further, based on the above-mentioned embodiment of the capacitor detection circuit, the first embodiment of the capacitor detection method of the application is proposed, as shown in Figure 5 , Figure 5 is a flowchart of the first embodiment of the capacitor detection method of the application. As shown in Figure 5 , the steps of the capacitor detection method of the application include:

[0066] Step S10, if the current detection interval length meets the preset detection period, a time-sharing detection instruction is generated;

[0067] Step S20, performing the capacitance detection according to the time-sharing detection instruction.

[0068] In the embodiment, the capacitance detection does not need to be performed in real time, and the timing needs to be selected (for example, the two capacitors cannot be detected in sequence continuously, and if the second capacitor is detected, power-off protection needs to be performed, and at this time, the first capacitor has not been fully charged, and thus the whole capacitance power supply circuit cannot work normally), and thus the time of use of the whole capacitance power supply circuit is timed, and if the current detection interval length collected at a certain moment meets the preset detection period, a time-sharing detection instruction is generated, and finally the capacitance detection is performed based on the time-sharing detection instruction. The current detection interval length is the length from the current time to the last time of capacitance detection, the preset detection period refers to the period defined by the user for using the capacitance or super capacitor, and the time-sharing detection instruction refers to the instruction for detecting the capacitance or super capacitor in the power-off circuit in a time-sharing manner. Thus, when the length of the timing reaches the preset detection period, for example, after one year, the time-sharing detection instruction is generated to perform the capacitance detection. The time-sharing detection instruction is an instruction for controlling all capacitors to be detected in a time-sharing manner, and the core is to detect the next capacitor after the charging of the current capacitor is completed, or to detect the capacitors in sequence when the load is at rest, so that when power-off protection is needed, the capacitance power supply circuit can provide sufficient power to realize the data storage of the load. The super capacitor capacity can be checked regularly, and the overall capacity of the super capacitor is not affected, that is, when the super capacitor capacity is detected, the data storage during abnormal power-off can still be ensured.

[0069] Further, based on the above-mentioned embodiment of the capacitance detection method, a second embodiment of the capacitance detection method of the application is provided. The step of performing the capacitance detection according to the time-sharing detection instruction comprises:

[0070] Step A10, generating a switch control instruction of a target capacitor based on the time-sharing detection instruction; wherein the switch control instruction is an instruction for controlling the target capacitor to be disconnected from the output circuit and connected to the detection circuit;

[0071] Step A20, acquiring the duration of a real-time enable signal when the switch control instruction is executed; wherein the real-time enable signal comprises an enable end signal of a voltage stabilizing circuit in the detection circuit, and the duration refers to the duration of the real-time enable signal in the same state;

[0072] Step A30, determining the detection result of the target capacitor based on the duration and preset circuit parameters.

[0073] In the embodiment, the switch control instruction of the target capacitor is generated when the time-sharing detection instruction is determined, wherein the switch control instruction refers to the instruction of controlling the target capacitor to be disconnected from the output circuit and connected to the detection circuit, that is, the instruction of controlling the first switch of the target capacitor to be disconnected and the second switch to be connected, so as to realize the connection of the target capacitor and the detection of the detection circuit. The target capacitor refers to the first capacitor to be detected. The duration of the real-time enable signal when the switch control instruction is executed is obtained, wherein the real-time enable signal includes the enable signal of the voltage stabilizing circuit in the detection circuit, and can also be other signals, such as the PW signal in Figure 3 . The duration of the real-time enable signal refers to the duration of the real-time enable signal in the same state. Finally, the detection result of the target capacitor can be determined based on the duration and the preset circuit parameters, wherein the preset circuit parameters refer to the stable current and voltage of the voltage stabilizing circuit. Since the capacitance value of the capacitor is related to the voltage change rate (the inverse of voltage and time) and the current, and the voltage and current are constant due to the voltage stabilizing circuit, the detection result of the capacitor can be determined based on the capacitor discharge time. The detection result refers to the capacitance value of the capacitor. When the capacitance value is less than the preset value, the capacitor needs to be replaced to ensure the function of the capacitor power supply circuit. After the step of determining the detection result of the target capacitor based on the duration and the preset circuit parameters, the following steps are included:

[0074] Step A40, updating the target capacitor based on the preset detection sequence, and performing the step of obtaining the duration of the real-time enable signal when the switch control instruction is executed based on the updated target capacitor.

[0075] In the embodiment, the result can be directly output after the detection of the target capacitor is completed, or the detection results of all capacitors can be output together. Then, the target capacitor is updated based on the preset detection sequence, and the step of obtaining the duration of the real-time enable signal when the switch control instruction is executed is performed based on the updated target capacitor. That is, the preset detection sequence is the detection sequence of each capacitor in the capacitor power supply circuit, such as from left to right. Then, all capacitors are detected, and the detection results of all capacitors are output when the updated target capacitor is determined to be the last detected capacitor, and the duration of the detection cycle is counted again. Then, the capacitor detection can be realized under the premise of ensuring the normal operation of the power failure protection circuit. Further, refer to Figure 6 , Figure 6This is a flowchart illustrating the capacitance detection method of the present invention. It involves time counting to determine if the counted time has reached the detection cycle. If the detection cycle has not been reached, time counting continues; if the detection cycle is reached, capacitance detection is performed. The entire capacitance detection process is as follows: First, the nth capacitor is initially detected, where 1 ≤ n ≤ N. Then, the charging channel of the nth supercapacitor is closed, and the capacitance detection channel of the nth supercapacitor is opened, i.e., the nth capacitor is detected. While the nth capacitor is being detected, the other N-1 capacitors are either powered down or preparing to be powered down. At this point, the boost voltage regulator circuit (a type of voltage regulator circuit) is enabled, i.e., the boost voltage regulator circuit is controlled to start working. At this time, boost_pwrgd (…) will be detected. Figure 3 The timing begins when `boost_pwrgd` goes high and stops when `boost_pwrgd` goes low. If no `boost_pwrgd` goes high, the process proceeds directly, indicating a problem with the capacitor or the detection circuit. The timing determines the discharge time of the nth capacitor. The capacitor capacity is calculated based on the discharge time and voltage drop, as it is related to the rate of change of current and voltage (voltage is the reciprocal of the discharge time; current and voltage are fixed values ​​due to the boost regulator circuit). Therefore, knowing the discharge time is sufficient to determine the capacitor capacity, completing the capacitance detection for the nth capacitor. At this point, the charging channel for the nth supercapacitor needs to be opened, and the capacitance detection channel needs to be closed, or both channels can be closed (in cases where power-off protection is not required). Then, a time interval `T` is waited for the nth supercapacitor to fully charge. Therefore, at least `T` time is required for the just-discharged capacitor to fully charge before the next capacitance detection. Then, `n` is updated to `n+1`. If `n>N`, the detection steps are repeated. For example, if `n=1` initially and `n=2` after the update, the capacitance of the second capacitor is detected. After all capacitors have been tested, the supercapacitor's capacity is determined to be abnormal, specifically by its discharge time. An abnormality is defined as a discharge time less than a certain value. This abnormal capacity is then fed back to the CPU, which issues an alarm to the user. This allows for periodic checks of the supercapacitor's capacity without affecting its overall capacity; that is, data preservation is ensured even during abnormal power outages.

[0076] The present invention also provides a capacitance detection device.

[0077] The device of the present invention includes: a memory, a processor, a capacitance detection circuit in the capacitance detection method, and a capacitance detection program stored in the memory and executable on the processor. When the capacitance detection program is executed by the processor, it implements the steps of the capacitance detection method as described above.

[0078] The present invention also provides a storage medium.

[0079] The storage medium of the present application stores a capacitance detection program, which, when executed by a processor, implements the steps of the capacitance detection method as described above.

[0080] The method implemented when the capacitance detection program running on the processor is executed can refer to each embodiment of the capacitance detection method of the present application, which will not be described here again.

[0081] It should be noted that in this document, the terms "comprising", "including", or any other variant thereof are intended to cover non-exclusive inclusions, so that a process, method, article or system that includes a series of elements not only includes those elements, but also includes other elements not explicitly listed, or inherent to such a process, method, article or system. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of other identical elements in the process, method, article or system that includes the element.

[0082] The above-mentioned embodiment numbers of the present application are only for description, not representing the advantages and disadvantages of the embodiments.

[0083] The above-mentioned embodiments of the present application are only optional embodiments, and do not limit the patent scope of the present application. Any equivalent structural transformation made by using the content of the present application specification and drawings, or direct / indirect application in other related technical fields under the concept of the present application is included in the patent protection scope of the present application.

Claims

1. A capacitance detection circuit, characterized by, The capacitor detection circuit comprises an input circuit, a capacitor power supply circuit, an output circuit, a detection circuit and a control circuit; The input circuit, the capacitor power supply circuit, the output circuit and a load are sequentially connected, the capacitor power supply circuit is connected with the detection circuit, and the control circuit is connected with the capacitor power supply circuit and the detection circuit respectively; the capacitor power supply circuit comprises a plurality of capacitors, wherein the capacitor power supply circuit comprises N capacitor power supply sub-circuits; N is not less than 2, and N-1 capacitor power supply sub-circuits are the number of capacitor power supply sub-circuits required by the load; the input circuit, the first end of the capacitor power supply sub-circuit and the output circuit are sequentially connected, the second end of the capacitor power supply sub-circuit is connected with a system power supply ground, the third end of the capacitor power supply sub-circuit is connected with the detection circuit, and the fourth end of the capacitor power supply sub-circuit is connected with the control circuit; The capacitor power supply sub-circuit comprises a first switch tube, a power supply capacitor and a first ground resistor, the first end of the first switch tube serves as the first end of the capacitor power supply sub-circuit, the control end of the first switch tube is connected with the first end of the first ground resistor and then serves as the fourth end of the capacitor power supply sub-circuit, the second end of the first ground resistor is connected with the system power supply ground, the second end of the first switch tube is connected with the first end of the power supply capacitor and then serves as the third end of the capacitor power supply sub-circuit, and the second end of the power supply capacitor serves as the second end of the capacitor power supply sub-circuit; The detection circuit comprises N capacitor detection sub-circuits connected with the capacitor power supply sub-circuit respectively and a detection control circuit; the first end of the capacitor detection sub-circuit is connected with the third end of the capacitor power supply sub-circuit, the second end of the capacitor detection sub-circuit is connected with the control circuit, and the third end of the capacitor power supply sub-circuit is connected with the detection control circuit; The capacitor detection sub-circuit comprises a second switch tube and a second ground resistor, the first end of the second switch tube serves as the first end of the capacitor detection sub-circuit, the control end of the second switch tube is connected with the first end of the second ground resistor and then serves as the second end of the capacitor detection sub-circuit, the second end of the second ground resistor is connected with the system power supply ground, and the second end of the second switch tube is connected with the detection control circuit; The control circuit is used for determining a time-sharing detection instruction based on a preset detection period, the detection circuit is used for detecting each capacitor based on the time-sharing detection instruction, a switch tube control instruction of a target capacitor is generated based on the time-sharing detection instruction, the switch tube control instruction is an instruction for controlling the target capacitor to be disconnected from the output circuit and connected with the detection circuit, that is, the first switch tube of the target capacitor is controlled to be disconnected and the second switch tube of the target capacitor is controlled to be connected, so that the target capacitor is connected with the detection circuit for detection.

2. The capacitance detection circuit of claim 1, wherein, The output circuit comprises at least a boost circuit, the input end of the boost circuit is connected with the first end of the capacitor power supply sub-circuit, and the output end of the boost circuit is connected with the load.

3. The capacitance detection circuit of claim 1, wherein, The detection control circuit comprises a first voltage dividing resistor, a second voltage dividing resistor, a comparator, a voltage stabilizing circuit and a resistor discharging circuit; wherein the resistor discharging circuit comprises a plurality of discharging resistors connected in parallel and having the same resistance value; The first input end of the comparator is connected with the third end of the capacitor charging circuit, the first end of the first voltage dividing resistor is connected with a comparison voltage, the second end of the first voltage dividing resistor is connected with the second input end of the comparator and the first end of the second voltage dividing resistor respectively, the second end of the second voltage dividing resistor is connected with the system power supply ground, the output end of the comparator is connected with the enable end of the voltage stabilizing circuit, the input end of the voltage stabilizing circuit is connected with the third end of the capacitor detection sub-circuit, the output end of the voltage stabilizing circuit is connected with the first end of the resistor discharging circuit, and the second end of the resistor discharging circuit is connected with the system power supply ground.

4. The capacitance detection circuit of claim 3, wherein, The control circuit comprises a central processing unit and a control chip, the central processing unit is communicatively connected with the control chip, and N first control ports, N second control ports and an enable control port are arranged on the control chip; The enable control port is connected with the enable end of the voltage stabilizing circuit, the N first control ports are respectively connected with the fourth ends of the N capacitor charging circuits, and the N second control ports are respectively connected with the second ends of the N capacitor detection sub-circuits.

5. A capacitance detection method characterized by, The capacitor detection method is applied to the capacitor detection circuit of any one of claims 1 to 4, and the steps of the capacitor detection method comprise: If the current detection interval length collected satisfies the preset detection period, a time-sharing detection instruction is generated; Capacitor detection is performed according to the time-sharing detection instruction.

6. The capacitance detection method as described in claim 5, characterized in that, The step of performing capacitor detection according to the time-sharing detection instruction comprises: A switch tube control instruction of a target capacitor is generated based on the time-sharing detection instruction; wherein the switch tube control instruction is an instruction for controlling the target capacitor to be disconnected from an output circuit and connected with the detection circuit; A duration of a real-time enable signal when the switch tube control instruction is executed is acquired; wherein the real-time enable signal comprises an enable end signal of a voltage stabilizing circuit in the detection circuit, and the duration refers to a duration of the real-time enable signal in the same state; A detection result of the target capacitor is determined based on the duration and preset circuit parameters; After the step of determining the detection result of the target capacitor based on the duration and preset circuit parameters, the steps comprise: The target capacitor is updated based on a preset detection sequence, and the step of acquiring the duration of the real-time enable signal when the switch tube control instruction is executed is executed based on the target capacitor after the update.

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