A gain-switching readout device and an image sensor

Abstract

This application belongs to the technical field of circuit gain control, and relates to a gain switching readout device and an image sensor, including a signal intensity detection circuit and a gain switching readout circuit; the signal intensity detection circuit is used to receive a pixel voltage signal and output a corresponding number of valid levels according to the voltage value of the pixel voltage signal; the gain switching readout circuit includes a gain selection module, and the gain selection module is used to receive the pixel voltage signal and convert the pixel voltage signal into a pixel current signal of a corresponding gear according to the number of valid levels. The gain switching readout device and the image sensor provided by this application can achieve the effect of improving accuracy by detecting the intensity of the input pixel voltage signal and converting the pixel voltage signal into a pixel current signal of a corresponding gear according to the intensity of the pixel voltage signal.

Description

Technical Field

[0001] This application relates to the technical field of circuit gain switching, and particularly to a gain switching readout device and an image sensor. Background Art

[0002] With the development of technology, computing devices have been gradually applied to all levels of modern society and made great contributions to the development of modern society, including but not limited to digital cameras, video cameras, smart phones, navigation systems, etc. In particular, in recent years, devices with image acquisition functions such as digital cameras have become increasingly popular, and the requirements for their imaging quality are getting higher and higher.

[0003] In existing image sensors, one or more pixels correspond to a pixel readout circuit, and the pixel readout circuit is used to read the sensing signals of each pixel and perform quantization, amplification, etc. on the sensing signals (such as pixel voltage signals) to obtain image data.

[0004] The pixel readout circuits of existing image sensors generally use a single gain and have low precision.

[0005] In view of the above problems, those skilled in the art have been seeking solutions.

[0006] The foregoing description is for the purpose of providing general background information and does not necessarily constitute prior art. Summary of the Invention

[0007] The technical problem to be solved by this application is to provide a gain switching readout device and an image sensor in view of the defects of the above-mentioned prior art, which can convert a pixel voltage signal into a pixel current signal of a corresponding gear according to the intensity of the pixel voltage signal, thereby achieving the effect of improving precision.

[0008] This application is implemented as follows:

[0009] This application provides a gain switching readout device, including a signal intensity detection circuit (10) and a gain switching readout circuit (20);

[0010] Among them, the signal intensity detection circuit (10) is used to receive a pixel voltage signal and output a corresponding number of valid levels according to the voltage value of the pixel voltage signal;

[0011] The gain switching readout circuit (20) includes a gain selection module (21), and the gain selection module (21) is used to receive the pixel voltage signal and convert the pixel voltage signal into a pixel current signal of a corresponding gear according to the number of the valid levels.

[0012] Optionally, the signal strength detection circuit (10) includes a detection module (11 / 12 / 13), and the detection module (11 / 12 / 13) includes a comparator (A1 / A2 / A3). A first input terminal of the comparator (A1 / A2 / A3) is coupled to a comparison signal input terminal (P1 / P2 / P3), a second input terminal of the comparator (A1 / A2 / A3) is coupled to a pixel voltage signal input terminal (P(vbtl)), and an output terminal of the comparator (A1 / A2 / A3) is configured to output a valid level to the gain selection module (21) according to a comparison result between the comparison signal (corresponding to P1 / P2 / P3) and the voltage value of the pixel voltage signal.

[0013] Optionally, the detection module (11 / 12 / 13) includes: a first detection module (11), a second detection module (12), and a third detection module (13);

[0014] Among them, the first detection module (11) includes a first comparator (A1). A first input terminal of the first comparator (A1) is coupled to a first comparison signal input terminal (P1), a second input terminal of the first comparator (A1) is coupled to a pixel voltage signal input terminal (P(vbtl)), and an output terminal of the first comparator (A1) is configured to output a first valid level to the gain selection module (21) according to a comparison result between the first comparison signal (corresponding to P1) and the voltage value of the pixel voltage signal;

[0015] The second detection module (12) includes a second comparator (A2). A first input terminal of the second comparator (A2) is coupled to a second comparison signal input terminal (P2), a second input terminal of the second comparator (A2) is coupled to the pixel voltage signal input terminal (P(vbtl)), and an output terminal of the second comparator (A2) is configured to output a second valid level to the gain selection module (21) according to a comparison result between the second comparison signal (corresponding to P2) and the voltage value of the pixel voltage signal;

[0016] The third detection module (13) includes a third comparator (A3). A first input terminal of the third comparator (A3) is coupled to a third comparison signal input terminal (P3), a second input terminal of the third comparator (A3) is coupled to the pixel voltage signal input terminal, and an output terminal of the third comparator (A3) is configured to output a third valid level to the gain selection module (21) according to a comparison result between the third comparison signal (corresponding to P3) and the voltage value of the pixel voltage signal.

[0017] Optionally, the gain selection module (21) includes a gain selection component, an initial resistance element (R), and a voltage conversion element (M1). The gain selection component includes switch elements (K1 / K2 / K3) and resistance elements (R1 / R2 / R3) connected in series. The first control ends of the switch elements (K1 / K2 / K3) are connected to the output ends of the comparators (A1 / A2 / A3). The first path ends of the switch elements (K1 / K2 / K3) are connected to the first input end of the voltage conversion element (M1) through the resistance elements (R1 / R2 / R3). The second path ends of the switch elements (K1 / K2 / K3) are connected to the common low voltage end. The switch elements (K1 / K2 / K3) are used to conduct when receiving the valid level, so that the resistance elements (R1 / R2 / R3) are connected into the loop including the voltage conversion element (M1).

[0018] The first end of the initial resistance element (R) is connected to the first input end of the voltage conversion element (M1), and the second end of the initial resistance element (R) is connected to the common low voltage end. The initial resistance element (R) is used to control the level of the initial pixel current signal according to the initial resistance value of the gain selection module (21).

[0019] The second input end of the voltage conversion element (M1) receives the pixel voltage signal. The voltage conversion element (M1) is used to convert the pixel voltage signal into a pixel current signal and output the corresponding pixel current signal according to the resistance value of the loop.

[0020] Optionally, the gain selection component includes: a first gain selection component, a second gain selection component, and a third gain selection component. The first input end of the voltage conversion element is connected to the first gain selection component, the second gain selection component, and the third gain selection component.

[0021] Wherein, the first gain selection component includes a first switch element (K1) and a first resistance element (R1) connected in series. The first control end of the first switch element (K1) is connected to the output end of the first comparator (A1). The first path end of the first switch element (K1) is connected to the first input end of the voltage conversion element (M1) through the first resistance element (R1). The second path end of the first switch element (K1) is connected to the common low voltage end. The first switch element (K1) is used to conduct when receiving the first valid level, so that the first resistance element (R1) is connected into the loop including the voltage conversion element (M1).

[0022] The second gain selection component includes a second switching element (K2) and a second resistance element (R2) connected in series. A first control end of the second switching element (K2) is connected to an output end of the second comparator (A2). A first path end of the second switching element (K2) is connected to a first input end of the voltage conversion element (M1) through the second resistance element (R2). A second path end of the second switching element (K2) is connected to a common low voltage end. The second switching element (K2) is used to conduct when receiving the second valid level, so that the second resistance element (R2) is connected into a loop including the voltage conversion element (M1).

[0023] The third gain selection component includes a third switching element (K3) and a third resistance element (R3) connected in series. A first control end of the third switching element (K3) is connected to an output end of the third comparator (A3). A first path end of the third switching element (K3) is connected to a first input end of the voltage conversion element (M1) through the third resistance element (R3). A second path end of the third switching element (K3) is connected to a common low voltage end. The third switching element (K3) is used to conduct when receiving the third valid level, so that the third resistance element (R3) is connected into a loop including the voltage conversion element (M1).

[0024] Optionally, the first gain selection component, the second gain selection component, the third gain selection component, and the initial resistance element (R) are all connected to a receiving ground signal terminal.

[0025] Optionally, the detection module (11 / 12 / 13) further includes a first capacitor element (C1 / C3 / C5) and a second capacitor element (C2 / C4 / C6);

[0026] The first capacitor element (C1 / C3 / C5) is located between a first input end of the comparator (A1 / A2 / A3) and an input end of the comparison signal (corresponding to P1 / P2 / P3). The first capacitor element (C1 / C3 / C5) is used to filter the comparison signal (corresponding to P1 / P2 / P3);

[0027] The second capacitor element (C2 / C4 / C6) is coupled between a second input end of the comparator (A1 / A2 / A3) and an input end of the pixel voltage signal. The second capacitor element (C2 / C4 / C6) is used to filter the pixel voltage signal.

[0028] Optionally, the voltage value of the comparison signal (corresponding to P1 / P2 / P3) is 100mv, 200mv or 400mv.

[0029] Optionally, the comparator (A1 / A2 / A3) is further connected to a voltage reset signal input terminal (az) for resetting the voltage of the comparator (A1 / A2 / A3) according to a voltage reset signal (corresponding to az).

[0030] Optionally, the voltage values of the first comparison signal received by the first comparator (A1), the second comparison signal received by the second comparator (A2), and the third comparison signal received by the third comparator (A3) increase in sequence.

[0031] Optionally, the voltage value of the first comparison signal is 100 mv, the voltage value of the second comparison signal is 200 mv, and the voltage value of the third comparison signal is 400 mv.

[0032] Optionally, the gain switching readout circuit (20) further includes a current mirror module (22). The first input terminal of the current mirror module (22) is connected to the output terminal of the voltage conversion element (M1), the second input terminal of the current mirror module (22) is connected to a bias voltage source (VDD), and the output terminal of the current mirror module (22) is used for outputting the pixel current signal corresponding to the corresponding gear.

[0033] Optionally, the current mirror module (22) includes a first common-gate transistor (M2) and a second common-gate transistor (M3). The gates of the first common-gate transistor (M2) and the second common-gate transistor (M3) are both connected to the output terminal of the voltage conversion element (M1).

[0034] Optionally, the gain switching readout circuit (20) further includes an analog-to-digital conversion module (23). The analog-to-digital conversion module (23) is connected to the output terminal of the current mirror module (22) for receiving the pixel current signal output by the current mirror module (22) and converting it into a digital signal.

[0035] This application further provides an image sensor, including the above-mentioned gain switching readout device.

[0036] This application provides a gain switching readout device and an image sensor. By detecting the intensity of the input pixel voltage signal and converting the pixel voltage signal into a pixel current signal corresponding to the corresponding gear according to the intensity of the pixel voltage signal, the effect of improving the accuracy can be achieved.

[0037] To make the above and other purposes, features, and advantages of this application more obvious and understandable, the following specifically enumerates preferred embodiments and, in conjunction with the accompanying drawings, makes the following detailed description. Description of the Drawings

[0038] Figure 1 is a circuit schematic diagram of a gain switching readout device provided by the first embodiment of this application;

[0039] Figure 2 It is a circuit schematic diagram of a gain switching readout device provided by the second embodiment of the present application;

[0040] Figure 3 It is a timing schematic diagram of a gain switching readout device provided by the second embodiment of the present application;

[0041] Figure 4 It is a circuit schematic diagram of a gain switching readout device provided by the third embodiment of the present application;

[0042] Figure 5 It is a circuit schematic diagram of a gain switching readout device provided by the fourth embodiment of the present application. Specific embodiments

[0043] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0044] The present application provides a gain switching readout device, including a signal strength detection circuit and a gain switching readout circuit.

[0045] Among them, the signal strength detection circuit is used to receive the pixel voltage signal and output the corresponding number of valid levels according to the voltage value of the pixel voltage signal.

[0046] The gain switching readout circuit includes a gain selection module, and the gain selection module is used to receive the pixel voltage signal and convert the pixel voltage signal into a pixel current signal of the corresponding gear according to the number of valid levels.

[0047] Optionally, the signal strength detection circuit includes a detection module, the detection module includes a comparator, the first input end of the comparator is coupled to the comparison signal input end, the second input end of the comparator is coupled to the pixel voltage signal input end, and the output end of the comparator is used to output a valid level to the gain selection module according to the comparison result of the comparison signal and the voltage value of the pixel voltage signal.

[0048] Optionally, the detection module includes: a first detection module, a second detection module, and a third detection module.

[0049] Among them, the first detection module includes a first comparator. The first input terminal of the first comparator is coupled to the first comparison signal input terminal, the second input terminal of the first comparator is coupled to the pixel voltage signal input terminal, and the output terminal of the first comparator is used to output a first valid level to the gain selection module according to the comparison result of the voltage values of the first comparison signal and the pixel voltage signal; the second detection module includes a second comparator. The first input terminal of the second comparator is coupled to the second comparison signal input terminal, the second input terminal of the second comparator is coupled to the pixel voltage signal input terminal, and the output terminal of the second comparator is used to output a second valid level to the gain selection module according to the comparison result of the voltage values of the second comparison signal and the pixel voltage signal; the third detection module includes a third comparator. The first input terminal of the third comparator is coupled to the third comparison signal input terminal, the second input terminal of the third comparator is coupled to the pixel voltage signal input terminal, and the output terminal of the third comparator is used to output a third valid level to the gain selection module according to the comparison result of the voltage values of the third comparison signal and the pixel voltage signal.

[0050] Optionally, the gain selection module includes a gain selection component, an initial resistance element, and a voltage conversion element. The gain selection component includes a switch element and a resistance element connected in series. The first control terminal of the switch element is connected to the output terminal of the comparator. The first path terminal of the switch element is connected to the first input terminal of the voltage conversion element through the resistance element. The second path terminal of the switch element is connected to the common low voltage terminal. The switch element is used to conduct when receiving a valid level, so that the resistance element is connected to the loop including the voltage conversion element; the first end of the initial resistance element is connected to the first input terminal of the voltage conversion element, and the second end of the initial resistance element is connected to the common low voltage terminal. The initial resistance element is used to control the gear of the initial pixel current signal according to the initial resistance value of the gain selection module; the second input terminal of the voltage conversion element receives the pixel voltage signal. The voltage conversion element is used to convert the pixel voltage signal into a pixel current signal and output a corresponding pixel current signal according to the resistance value of the loop.

[0051] Optionally, the gain selection component includes: a first gain selection component, a second gain selection component, and a third gain selection component; the first input terminal of the voltage conversion element is connected to the first gain selection component, the second gain selection component, and the third gain selection component.

[0052] Among them, the first gain selection component includes a first switching element and a first resistance element connected in series. The first control end of the first switching element is connected to the output end of the first comparator. The first path end of the first switching element is connected to the first input end of the voltage conversion element through the first resistance element. The second path end of the first switching element is connected to the common low voltage end. The first switching element is used to conduct when receiving the first valid level, so that the first resistance element is connected into the loop including the voltage conversion element; the second gain selection component includes a second switching element and a second resistance element connected in series. The first control end of the second switching element is connected to the output end of the second comparator. The first path end of the second switching element is connected to the first input end of the voltage conversion element through the second resistance element. The second path end of the second switching element is connected to the common low voltage end. The second switching element is used to conduct when receiving the second valid level, so that the second resistance element is connected into the loop including the voltage conversion element; the third gain selection component includes a third switching element and a third resistance element connected in series. The first control end of the third switching element is connected to the output end of the third comparator. The first path end of the third switching element is connected to the first input end of the voltage conversion element through the third resistance element. The second path end of the third switching element is connected to the common low voltage end. The third switching element is used to conduct when receiving the third valid level, so that the third resistance element is connected into the loop including the voltage conversion element.

[0053] Optionally, the first gain selection component, the second gain selection component, the third gain selection component, and the initial resistance element are all connected to the receiving ground signal terminal.

[0054] Optionally, the detection module further includes a first capacitance element and a second capacitance element.

[0055] The first capacitance element is located between the first input end of the comparator and the input end of the comparison signal. The first capacitance element is used to filter the comparison signal; the second capacitance element is coupled between the second input end of the comparator and the pixel voltage signal input end. The second capacitance element is used to filter the pixel voltage signal.

[0056] Optionally, the voltage value of the comparison signal is 100mv, 200mv or 400mv.

[0057] Optionally, the comparator is further connected to the voltage reset signal input end, and is used to reset the voltage of the comparator according to the voltage reset signal.

[0058] Optionally, the voltage values of the first comparison signal received by the first comparator, the second comparison signal received by the second comparator, and the third comparison signal received by the third comparator increase in sequence.

[0059] Optionally, the voltage value of the first comparison signal is 100 mv, the voltage value of the second comparison signal is 200 mv, and the voltage value of the third comparison signal is 400 mv.

[0060] Optionally, the gain switching readout circuit further includes a current mirror module. The first input end of the current mirror module is connected to the output end of the voltage conversion element, the second input end of the current mirror module is connected to the bias voltage source, and the output end of the current mirror module is used to output the pixel current signal corresponding to the gear.

[0061] Optionally, the current mirror module includes a first common-gate transistor and a second common-gate transistor. The gates of the first common-gate transistor and the second common-gate transistor are both connected to the output end of the voltage conversion element.

[0062] Optionally, the gain switching readout circuit further includes an analog-to-digital conversion module. The analog-to-digital conversion module is connected to the output end of the current mirror module, and is used to receive the pixel current signal output by the current mirror module and convert it into a digital signal.

[0063] The following combines several specific embodiments to detail the solution of the present application.

[0064] Embodiment 1

[0065] Figure 1 is a schematic structural diagram of the pixel circuit provided by the first embodiment of the present application. Please refer to Figure 1 , the gain switching readout device provided by the first embodiment of the present application includes a signal strength detection circuit 10 and a gain switching readout circuit 20.

[0066] In the first embodiment, the signal strength detection circuit 10 includes: a first detection module 11, a second detection module 12, and a third detection module 13. The first detection module 11 includes a first comparator A1, the second detection module 12 includes a second comparator A2, and the third detection module 13 includes a third comparator A3. The first input end of the first comparator A1 is coupled to the first comparison signal input end P1, and the second input end of the first comparator A1 is coupled to the pixel voltage signal input end P(vbtl); the first input end of the second comparator A2 is coupled to the second comparison signal input end P2, and the second input end of the second comparator A2 is coupled to the pixel voltage signal input end P(vbtl); the first input end of the third comparator A3 is coupled to the third comparison signal input end P3, and the second input end of the third comparator A3 is coupled to the pixel voltage signal input end (vbtl).

[0067] In the first embodiment, the gain switching readout circuit 20 includes a gain selection module 21.

[0068] Among them, the first comparator A1 is configured to output a first valid level sw-1 or a first invalid level sw-1' to the gain selection module 21 according to the comparison result between the first comparison signal and the voltage value of the pixel voltage signal. The second comparator A2 is configured to output a second valid level sw-2 or a second invalid level sw-2' to the gain selection module 21 according to the comparison result between the second comparison signal and the voltage value of the pixel voltage signal. The third comparator A3 is configured to output a third valid level sw-3 or a third invalid level sw-3' to the gain selection module 21 according to the comparison result between the third comparison signal and the voltage value of the pixel voltage signal.

[0069] In the first embodiment, the gain selection module 21 includes a gain selection component, an initial resistance element R, and a voltage conversion element M1.

[0070] Specifically, the gain selection component includes: a first gain selection component, a second gain selection component, and a third gain selection component. The first gain selection component includes a first switch element K1 and a first resistance element R1 connected in series. The second gain selection component includes a second switch element K2 and a second resistance element R2 connected in series. The third gain selection component includes a third switch element K3 and a third resistance element R3 connected in series. The first control end of the first switch element K1 is connected to the output end of the first comparator A1. The first path end of the first switch element K1 is connected to the first input end of the voltage conversion element M1 through the first resistance element R1, and the second path end of the first switch element K1 is connected to the common low voltage end. The first control end of the second switch element K2 is connected to the output end of the second comparator A2. The first path end of the second switch element K2 is connected to the first input end of the voltage conversion element M1 through the second resistance element R2, and the second path end of the second switch element K2 is connected to the common low voltage end. The first control end of the third switch element K3 is connected to the output end of the third comparator A3. The first path end of the third switch element K3 is connected to the first input end of the voltage conversion element M1 through the third resistance element R3, and the second path end of the third switch element K3 is connected to the common low voltage end.

[0071] The first switch element K1 is configured to conduct when receiving the first valid level sw-1, so that the first resistance element R1 is connected into the loop including the voltage conversion element M1. The second switch element K2 is configured to conduct when receiving the second valid level sw-2, so that the second resistance element R2 is connected into the loop including the voltage conversion element M1. The third switch element K3 is configured to conduct when receiving the third valid level sw-3, so that the third resistance element R3 is connected into the loop including the voltage conversion element M1.

[0072] The first end of the initial resistance element R is connected to the first input terminal of the voltage conversion element M1, the second end of the initial resistance element R is connected to the common low voltage terminal, and the second input terminal of the voltage conversion element M1 receives the pixel voltage signal.

[0073] In the first embodiment, the first gain selection component, the second gain selection component, the third gain selection component, and the initial resistance element R are all connected to the terminal receiving the ground signal.

[0074] In the first embodiment, the first detection module 11 further includes a first capacitor element C1, a second capacitor element C2, a third capacitor element C3, a fourth capacitor element C4, a fifth capacitor element C5, and a sixth capacitor element C6. The first capacitor element C1 is located between the first input terminal of the first comparator A1 and the input terminal P1 of the first comparison signal. The second capacitor element C2 is coupled between the second input terminal of the first comparator A1 and the pixel voltage signal input terminal P(vbtl). The third capacitor element C3 is located between the first input terminal of the second comparator A2 and the input terminal P2 of the second comparison signal. The fourth capacitor element C4 is coupled between the second input terminal of the second comparator A2 and the pixel voltage signal input terminal P(vbtl). The fifth capacitor element C5 is located between the first input terminal of the third comparator A3 and the input terminal P3 of the third comparison signal. The sixth capacitor element C6 is coupled between the second input terminal of the third comparator A3 and the pixel voltage signal input terminal P(vbtl).

[0075] In the first embodiment, the first comparator A1, the second comparator A2, and the third comparator A3 are also respectively connected to the voltage reset signal input terminal az, and are used to reset the voltages of the first comparator A1, the second comparator A2, and the third comparator A3 according to the voltage reset signal.

[0076] In this embodiment, the voltage value of the first comparison signal is 100mv, the voltage value of the second comparison signal is 200mv, and the voltage value of the third comparison signal is 400mv.

[0077] In the first embodiment, the gain switching readout circuit 20 may further include a current mirror module 22. The first input terminal of the current mirror module 22 is connected to the output terminal of the voltage conversion element M1, and the second input terminal of the current mirror module 22 is connected to the bias voltage source VDD.

[0078] Specifically, the current mirror module 22 includes a first common-gate transistor M2 and a second common-gate transistor M3. The gates of the first common-gate transistor M2 and the second common-gate transistor M3 are both connected to the output terminal of the voltage conversion element M1.

[0079] In the first embodiment, the gain switching readout circuit 20 further includes an analog-to-digital conversion module 23. The analog-to-digital conversion module 23 is connected to the output end of the current mirror module 22 and is configured to receive the pixel current signal output by the current mirror module 22 and convert it into a digital signal.

[0080] The implementation principle of the first embodiment of this application is as follows: The comparator logically compares the comparison signal with the voltage value of the pixel voltage signal, and outputs a valid level or an invalid level according to the comparison result to control the corresponding switching element to conduct or cut off, thereby controlling whether the resistance element is connected to the loop including the voltage conversion element to control the current value input to the analog-to-digital conversion module. That is, according to the comparison result of the comparison signal and the voltage value of the pixel voltage signal, the total resistance value of the gain switching readout circuit is controlled to control the current value input to the analog-to-digital conversion module.

[0081] In the first embodiment, the voltage value of the third comparison signal is greater than the voltage value of the second comparison signal, and the voltage value of the second comparison signal is greater than the voltage value of the first comparison signal.

[0082] Exemplarily, please refer to Figure 1, when the first resistor element R1, the second resistor element R2, and the third resistor element R3 in the gain selection module 21 are not connected to the circuit of the voltage conversion element M1, the total resistance of the gain switching readout circuit 20 can be quantified as R(total) = R + r (where R is the resistance value of the initial resistor element and r is the fixed resistance value of the gain switching readout circuit 20); the voltage conversion element M1 converts the pixel voltage signal into a pixel current signal, and the total current, that is, the current output to the analog-to-digital conversion module, can be quantified as I(total) = VDD / (R + r). If the first comparison signal output terminal P1 outputs a first comparison signal with a voltage value of 100 mv to the first comparator A1, and the pixel voltage signal input terminal P(vbtl) outputs a pixel voltage signal to the first comparator A1, the first comparator A1 logically compares the 100 mv first comparison signal with the voltage value of the pixel voltage signal. If the voltage value of the pixel voltage signal is greater than 100 mv, the first comparator A1 outputs a first valid level sw-1 to the first switching element K1 to make the first switching element K1 conduct, then the first resistor element R1 is connected to the circuit. At this time, the first resistor element R1 is in parallel with the initial resistor element R, and the total resistance of the gain switching readout circuit 20 can be quantified as R(total) = (R × R1) / (R + R1) + r, and the total current can be quantified as I(total) = VDD / ((R × R1) / (R + R1) + r); if the voltage value of the pixel voltage signal is less than 100 mv, the first comparator A1 outputs a first invalid level sw-1' to the first switching element K1 to make the first switching element K1 non-conducting, then only the initial resistor element R is connected to the circuit, the total resistance of the gain switching readout circuit 20 remains unchanged, and the total current remains unchanged, that is, when the voltage value of the pixel voltage signal is less than 100 mv, the gain switching readout circuit 20 is at the initial gain.

[0083] The working principles of the second comparator A2 and the third comparator A3 are the same as those of the first comparator A1, and will not be elaborated here.

[0084] Specifically, if the voltage value of the pixel voltage signal input at the pixel voltage signal input terminal is greater than the voltage value of the second comparison signal (e.g., 200 mv) and less than the voltage value of the third comparison signal (e.g., 400 mv), that is, when 200 mv < vbtl < 400 mv, where vbtl is the voltage value of the pixel voltage signal, according to the comparator principle, the first comparator A1 outputs the first valid level sw-1 to the first switching element K1, the second comparator A2 outputs the second valid level sw-2 to the second switching element K2, and the third comparator A3 outputs the third invalid level sw-3' to the third switching element K3. Then, both the first switching element K1 and the second switching element K2 can be turned on, and the third switching element K3 is not turned on. Then, both the first resistance element R1 and the second resistance element R2 are connected to the circuit. At this time, the three resistance elements of the first resistance element R1, the second resistance element R2, and the initial resistance element R are in parallel. Then, the total resistance of the gain switching readout circuit 20 can be quantified as R(total) = (R × R1 × R2) / (R1 × R2 + R × R2 + R × R1) + r, and the total current can be quantified as I(total) = VDD / ((R × R1 × R2) / (R1 × R2 + R × R2 + R × R1) + r).

[0085] Similarly, if the voltage value of the pixel voltage signal input at the pixel voltage signal input terminal is greater than the voltage value of the third comparison signal (400 mv) and less than the preset maximum voltage threshold, that is, 400 mv < vbtl < 800 mv, the first resistance element R1, the second resistance element R2, and the third resistance element R3 are all connected to the circuit. At this time, the four resistance elements of the first resistance element R1, the second resistance element R2, the third resistance element R3, and the initial resistance element R are in parallel. Then, the total resistance of the gain switching readout circuit 20 can be quantified as R(total) = (R × R1 × R2 × R3) / (R1 × R2 × R3 + R × R2 × R3 + R × R1 × R3 + R × R1 × R2) + r, and the total current can be quantified as I(total) = VDD / ((R × R1 × R2 × R3) / (R1 × R2 × R3 + R × R2 × R3 + R × R1 × R3 + R × R1 × R2) + r).

[0086] In summary, when the voltage values of the pixel voltage signal are respectively in the change intervals of 0 < vbtl < 100mv, 100mv < vbtl < 200mv, 200mv < vbtl < 400mv, and 400mv < vbtl < 800mv, the gear currents input to the corresponding analog-to-digital conversion module 23 can be respectively quantified as the first gear current VDD / (R + r), the second gear current VDD / ((R×R1) / (R + R1)+r), the third gear current VDD / ((R×R1×R2) / (R1×R2 + R×R2 + R×R1)+r), and the fourth gear current VDD / ((R×R1×R2×R3) / (R1×R2×R3 + R×R2×R3 + R×R1×R3 + R×R1×R2)+r).

[0087] In one embodiment, the comparison signal is a signal with different amplitude falling edges, and the maximum amplitude falling edge can be 400mv, so the preset maximum voltage threshold is 800mv. In other embodiments, it can be set to other maximum voltage thresholds such as 780mv and 820mv according to user requirements.

[0088] Embodiment 2

[0089] Figure 2 It is a circuit schematic diagram of a gain switching readout device provided by the second embodiment of the present application. Please refer to Figure 2 The gain switching readout device provided by the second embodiment of the present application includes a signal intensity detection circuit 30 and a gain switching readout circuit 40.

[0090] The signal intensity detection circuit 30 includes a fourth detection module 31 and a latch module 32. The fourth detection module 31 includes a fourth comparator A4. The first input terminal of the fourth comparator A4 is coupled to the fourth comparison signal input terminal P4, and the second input terminal of the fourth comparator A4 is coupled to the pixel voltage signal input terminal P(vbtl); the latch module 32 includes a first latch D1, a second latch D2, and a third latch D3. The input terminals of the first latch D1, the second latch D2, and the third latch D3 are all connected to the output terminal of the fourth comparator A4.

[0091] In the second embodiment, the gain switching readout circuit 40 includes a gain selection module 41.

[0092] Among them, the first latch D1 is used to store the comparison result of the voltage values of the fourth comparison signal and the pixel voltage signal, and output the fourth active level sw-4 or the fourth inactive level sw-4' to the gain selection module 41. The second latch D2 is used to store the comparison result of the voltage values of the fourth comparison signal and the pixel voltage signal, and output the fifth active level sw-5 or the fifth inactive level sw-5' to the gain selection module 41. The third latch D3 is used to store the comparison result of the voltage values of the fourth comparison signal and the pixel voltage signal, and output the sixth active level sw-6 or the sixth inactive level sw-6' to the gain selection module 41.

[0093] In the second embodiment, the gain selection module 41 includes a gain selection component, an initial resistance element R, and a voltage conversion element M1.

[0094] Specifically, the gain selection component includes: a fourth gain selection component, a fifth gain selection component, and a sixth gain selection component. The fourth gain selection component includes a fourth switch element K4 and a fourth resistance element R4 connected in series. The first control end of the fourth switch element K4 is connected to the output end of the first latch D1. The first path end of the fourth switch element K4 is connected to the first input end of the voltage conversion element M1 through the fourth resistance element R4. The second path end of the fourth switch element K4 is connected to the common low voltage end. The fifth gain selection component includes a fifth switch element K5 and a fifth resistance element R5 connected in series. The first control end of the fifth switch element K5 is connected to the output end of the second latch D2. The first path end of the fifth switch element K5 is connected to the first input end of the voltage conversion element M1 through the fifth resistance element R5. The second path end of the fifth switch element K5 is connected to the common low voltage end. The sixth gain selection component includes a sixth switch element K6 and a sixth resistance element R6 connected in series. The first control end of the sixth switch element K6 is connected to the output end of the third latch D3. The first path end of the sixth switch element K6 is connected to the first input end of the voltage conversion element M1 through the sixth resistance element R6. The second path end of the sixth switch element K6 is connected to the common low voltage end.

[0095] The first end of the initial resistance element R is connected to the first input end of the voltage conversion element M1. The second end of the initial resistance element R is connected to the common low voltage end. The second input end of the voltage conversion element M1 receives the pixel voltage signal.

[0096] Optionally, the detection module further includes a seventh capacitor element C7 and an eighth capacitor element C8. The seventh capacitor element C7 is located between the first input terminal of the fourth comparator A4 and the input terminal P4 of the fourth comparison signal. The eighth capacitor element C8 is located between the second input terminal of the fourth comparator A4 and the pixel voltage signal input terminal P(vbtl). The seventh capacitor element C7 and the eighth capacitor element C8 are used for filtering the pixel voltage signal vbtl and the comparison signal.

[0097] In the second embodiment, the voltage value of the fourth comparison signal is 100mv or 200mv or 400mv.

[0098] Optionally, the fourth comparator A4 is further connected to the voltage reset signal input terminal az, and is used to reset the voltage of the fourth comparator A4 according to the voltage reset signal.

[0099] Optionally, the gain switching readout circuit 40 further includes a current mirror module 42. The first input terminal of the current mirror module 42 is connected to the output terminal of the voltage conversion element M1, and the second input terminal of the current mirror module 42 is connected to the bias voltage source VDD.

[0100] Specifically, the current mirror module 42 includes a first common-gate transistor M2 and a second common-gate transistor M3. The gates of the first common-gate transistor M2 and the second common-gate transistor M3 are both connected to the output terminal of the voltage conversion element M1.

[0101] Optionally, the gain switching readout circuit 40 further includes an analog-to-digital conversion module 43. The analog-to-digital conversion module 43 is connected to the output terminal of the current mirror module 42, and is used to receive the pixel current signal output by the current mirror module 42 and convert it into a digital signal.

[0102] Figure 3 is a timing schematic diagram of a gain switching readout device provided by the second embodiment of the present application. Please refer to Figure 2 and Figure 3 simultaneously. Before the fourth comparator A4 performs the logical comparison between the fourth comparison signal vref and the pixel voltage signal vbtl, the fourth comparator A4 receives the voltage reset signal az so that the voltages of the input terminal and the output terminal of the fourth comparator A4 rise to a certain preset voltage threshold simultaneously. After a period of time, the voltages of the input terminal and the output terminal of the fourth comparator A4 drop to the same voltage value simultaneously. After the voltage reset of the voltages of the input terminal and the output terminal of the fourth comparator A4 is completed, the fourth comparator A4 performs the logical comparison between the fourth comparison signal vref and the pixel voltage signal vbtl.

[0103] As Figure 3As shown, the fourth comparison signal vref includes fourth comparison signals with different amplitude falling edges. vbtl is the pixel voltage signal. According to the change trend of the fourth comparison signal vref, the first locking signal SET1 corresponds to the comparison signal with a first falling edge of 100 mv at time t1, that is, the interval of the fourth comparison signal at this time can be expressed as 100 mv < vbtl < 200 mv; the second locking signal SET2 corresponds to the comparison signal with a second falling edge of 100 mv at time t2, that is, the total falling edge is 200 mv, that is, the interval of the fourth comparison signal at this time can be expressed as 200 mv < vbtl < 400 mv; the third locking signal SET3 corresponds to the comparison signal with a third falling edge of 200 mv at time t3, that is, the total falling edge is 400 mv, that is, the interval of the fourth comparison signal at this time can be expressed as vbtl > 400 mv.

[0104] In the second embodiment, the latch is a D latch. According to the working principle of the D latch: when a high level (i.e., an active level) is input, the output level changes with the input level; when a low level (i.e., an inactive level) is input, the output level remains unchanged. The first latch D1, the second latch D2, and the third latch D3 output corresponding active levels or inactive levels according to the input high / low levels to control the conduction or cutoff of the fourth switching element K4, the fifth switching element K5, and the sixth switching element K6, and further control whether the corresponding fourth resistance element R4, the fifth resistance element R5, and the sixth resistance element R6 are connected to the circuit including the voltage conversion element M1.

[0105] Specifically, at time t1, the fourth comparison signal vref is a comparison signal with a falling edge of 100 mv, and the voltage value of the pixel voltage signal vbtl drops to x mv (x is greater than zero). The fourth comparator A4 logically compares the fourth comparison signal vref with the voltage value of the pixel voltage signal vbtl. The first latch D1 is loaded with the first locking signal SET1 and the first storage signal EN1. According to the comparator principle, the fourth comparator A4 outputs the fourth active level sw-4 to the first latch D1, and the first latch D1 stores the fourth active level sw-4 during the time period from t1 to t2 according to the first storage signal EN1. That is, when the interval of the fourth comparison signal is 100 mv < vbtl < 200 mv, the first latch D1 outputs the fourth active level sw-4 to the fourth switching element K4 to make the fourth switching element K4 conduct, and the fourth resistance element R4 is connected to the circuit including the voltage conversion element M1. At this time, the fourth resistance element R4 is connected in parallel with the initial resistance element R.

[0106] At time t2, the fourth comparison signal vref is a comparison signal with a falling edge of 200 mV, the pixel voltage signal vbtl is x mV, the fourth comparator A4 compares the fourth comparison signal vref with the voltage value of the pixel voltage signal vbtl, the second latch D2 is loaded with the second lock signal SET2 and the second storage signal EN2. According to the comparator principle, the fourth comparator A4 outputs the fifth valid level sw-5 to the first latch D1 and the second latch D2. Then the second latch D2 stores the fifth valid level sw-5 during the time period from t2 to t3 according to the second storage signal EN2. That is, when the range of the fifth comparison signal is 200 mV < vbtl < 400 mV, the first latch D1 outputs the fifth valid level sw-5 to the fourth switching element K4 to turn on the fourth switching element K4, and the second latch D2 outputs the fifth valid level sw-5 to the fifth switching element K5 to turn on the fifth switching element K5. Then the fourth resistor element R4 and the fifth resistor element R5 are both connected to the circuit including the voltage conversion element M1. At this time, the fourth resistor element R4, the fifth resistor element R5 and the initial resistor element R are in parallel. ;

[0107] At time t3, the fourth comparison signal vref is a comparison signal with a falling edge of 400 mV, the pixel voltage signal vbtl is x mV, the fourth comparator A4 compares the fourth comparison signal vref with the voltage value of the pixel voltage signal vbtl, the third latch D3 is loaded with the third lock signal SET3 and the third storage signal EN3. According to the comparator principle, the fourth comparator A4 outputs the sixth valid level sw-6 to the first latch D1, the second latch D2 and the third latch D3. Then the third latch D3 stores the sixth valid level sw-6 during the time period from t3 to t4 according to the third storage signal EN3. That is, when the range of the sixth comparison signal is vbtl > 400 mV, the first latch D1 outputs the sixth valid level sw-6 to the fourth switching element K4 to turn on the fourth switching element K4, the second latch D2 outputs the sixth valid level sw-6 to the fifth switching element K5 to turn on the fifth switching element K5, and the third latch D3 outputs the sixth valid level sw-6 to the sixth switching element K6 to turn on the sixth switching element K6. Then the fourth resistor element R4, the fifth resistor element R5 and the sixth resistor element R6 are all connected to the circuit including the voltage conversion element M1. At this time, the fourth resistor element R4, the fifth resistor element R5, the sixth resistor element R6 and the initial resistor element R are in parallel.

[0108] In the second embodiment, the gain switching control method of the gain switching readout circuit 40 is the same as that in the first embodiment, and will not be elaborated here.

[0109] Embodiment 3

[0110] Figure 4 This is a circuit schematic diagram of the gain switching readout device provided in the third embodiment of the present application. Please refer to Figure 4 The gain switching readout device provided in the third embodiment of the present application includes a signal intensity detection circuit 50 and a gain switching readout circuit 60.

[0111] In the third embodiment, the signal intensity detection circuit 50 includes: a fifth detection module 51, a sixth detection module 52, and a seventh detection module 53. The fifth detection module 51 includes a fifth comparator A5. The first input terminal of the fifth comparator A5 is coupled to the fifth comparison signal input terminal P5, and the second input terminal of the fifth comparator A5 is coupled to the pixel voltage signal input terminal P(vbtl). The sixth detection module 52 includes a sixth comparator A6. The first input terminal of the sixth comparator A6 is coupled to the sixth comparison signal input terminal P6, and the second input terminal of the sixth comparator A6 is coupled to the pixel voltage signal input terminal P(vbtl). The seventh detection module 53 includes a seventh comparator A7. The first input terminal of the seventh comparator A7 is coupled to the seventh comparison signal input terminal P7, and the second input terminal of the seventh comparator A7 is coupled to the pixel voltage signal input terminal P(vbtl).

[0112] In the third embodiment, the gain switching readout circuit 60 includes a gain selection module 61.

[0113] Among them, the fifth comparator A5 is configured to output a seventh valid level sw-7 or a fifth invalid level sw-7' to the gain selection module 61 according to the comparison result of the fifth comparison signal and the voltage value of the pixel voltage signal. The sixth comparator A6 is configured to output an eighth valid level sw-8 or an eighth invalid level sw-8' to the gain selection module 61 according to the comparison result of the sixth comparison signal and the voltage value of the pixel voltage signal. The seventh comparator A7 is configured to output a ninth valid level sw-9 or a ninth invalid level sw-9' to the gain selection module 61 according to the comparison result of the seventh comparison signal and the voltage value of the pixel voltage signal.

[0114] In the third embodiment, the gain selection module 61 includes a gain selection component, an initial resistance element R, and a voltage conversion element M1.

[0115] Specifically, the gain selection components include: a seventh gain selection component, an eighth gain selection component, and a ninth gain selection component. The seventh gain selection component includes a seventh switching element K7 and a seventh resistor element R7 connected in parallel. The eighth gain selection component includes an eighth switching element K8 and an eighth resistor element R8 connected in parallel. The ninth gain selection component includes a ninth switching element K9 and a ninth resistor element R9 connected in parallel. The first control terminal of the seventh switching element K7 is connected to the output terminal of the fifth comparator A5. The first path terminal of the seventh switching element K7 is connected to the first input terminal of the voltage conversion element M1 through the eighth resistor element R8, the ninth resistor element R9, and the initial resistor element R connected in series. The second path terminal of the seventh switching element K7 is connected to the common low voltage terminal. The first control terminal of the eighth switching element K8 is connected to the output terminal of the sixth comparator A6. The first path terminal of the eighth switching element K8 is connected to the first input terminal of the voltage conversion element M1 through the ninth resistor element R9 and the initial resistor element R connected in series. The second path terminal of the eighth switching element K8 is connected to the common low voltage terminal. The first control terminal of the ninth switching element K9 is connected to the output terminal of the seventh comparator A7. The first path terminal of the ninth switching element K9 is connected to the first input terminal of the voltage conversion element M1 through the initial resistor element R. The second path terminal of the ninth switching element K9 is connected to the common low voltage terminal.

[0116] The seventh switching element K7 is used to conduct when receiving the seventh valid level sw-7, so that the seventh resistor element R7 is not connected to the loop including the voltage conversion element M1. The eighth switching element K8 is used to conduct when receiving the eighth valid level sw-8, so that the seventh resistor element R7 and the eighth resistor element R8 are not connected to the loop including the voltage conversion element M1. The ninth switching element K9 is used to conduct when receiving the ninth valid level sw-9, so that the seventh resistor element R7, the eighth resistor element R8, and the ninth resistor element R9 are not connected to the loop including the voltage conversion element M1.

[0117] The first end of the initial resistor element R is connected to the first input terminal of the voltage conversion element M1. The second end of the initial resistor element R is connected to the common low voltage terminal. The second input terminal of the voltage conversion element M1 receives the pixel voltage signal.

[0118] In the third embodiment, the seventh gain selection component, the eighth gain selection component, and the ninth gain selection component are all connected to the receiving ground signal terminal.

[0119] In the third embodiment, the fifth detection module 51 further includes a ninth capacitor element C9 and a tenth capacitor element C10. The sixth detection module 52 further includes an eleventh capacitor element C11 and a twelfth capacitor element C12. The seventh detection module 53 further includes a thirteenth capacitor element C13 and a fourteenth capacitor element C14. The ninth capacitor element C9 is located between the first input terminal of the fifth comparator A5 and the input terminal P5 of the fifth comparison signal. The tenth capacitor element C10 is coupled between the second input terminal of the fifth comparator A5 and the pixel voltage signal input terminal P(vbtl). The eleventh capacitor element C11 is located between the first input terminal of the sixth comparator A6 and the input terminal P6 of the sixth comparison signal. The twelfth capacitor element C12 is coupled between the second input terminal of the sixth comparator A6 and the pixel voltage signal input terminal P(vbtl). The thirteenth capacitor element C13 is located between the first input terminal of the seventh comparator A7 and the input terminal P7 of the seventh comparison signal. The fourteenth capacitor element C14 is coupled between the second input terminal of the seventh comparator A7 and the pixel voltage signal input terminal P(vbtl).

[0120] In the third embodiment, the fifth comparator A5, the sixth comparator A6, and the seventh comparator A7 are also respectively connected to the voltage reset signal input terminal az, and are used to reset the voltages of the fifth comparator A5, the sixth comparator A6, and the seventh comparator A7 according to the voltage reset signal respectively.

[0121] In the third embodiment, the voltage value of the fifth comparison signal is 100 mv, the voltage value of the sixth comparison signal is 200 mv, and the voltage value of the seventh comparison signal is 400 mv.

[0122] In the third embodiment, the gain switching readout circuit 60 may further include a current mirror module 62. The first input terminal of the current mirror module 62 is connected to the output terminal of the voltage conversion element M1, and the second input terminal of the current mirror module 62 is connected to the bias voltage source VDD.

[0123] Specifically, the current mirror module 62 includes a first common-gate transistor M2 and a second common-gate transistor M3. The gates of the first common-gate transistor M2 and the second common-gate transistor M3 are both connected to the output terminal of the voltage conversion element M1.

[0124] In the third embodiment, the gain switching readout circuit 60 further includes an analog-to-digital conversion module 63. The analog-to-digital conversion module 23 is connected to the output terminal of the current mirror module 62, and is used to receive the pixel current signal output by the current mirror module 62 and convert it into a digital signal.

[0125] Exemplarily, please refer to Figure 4When the seventh resistor element R7, the eighth resistor element R8, and the ninth resistor element R9 in the gain selection module 61 are not connected to the loop including the voltage conversion element M1, the total resistance of the gain switching readout circuit 60 can be quantified as R(total) = R7 + R8 + R9 + R + r (where R is the resistance value of the initial resistor element and r is the fixed resistance value of the gain switching readout circuit 60); the voltage conversion element M1 converts the pixel voltage signal into a pixel current signal, and the total current, that is, the current output to the analog-to-digital conversion module, can be quantified as I(total) = VDD / (R7 + R8 + R9 + R + r). The fifth comparison signal output terminal P5 outputs a fifth comparison signal with a voltage value of 100 mV to the fifth comparator A5, and the pixel voltage signal input terminal P(vbtl) outputs a pixel voltage signal to the fifth comparator A5. The fifth comparator A5 logically compares the fifth comparison signal of 100 mV with the voltage value of the pixel voltage signal. If the voltage value of the pixel voltage signal is greater than 100 mV and less than 200 mV, that is, 100 mV < vbtl < 200 mV, the fifth comparator A5 outputs a seventh valid level sw-7 to the seventh switching element K7 to turn on the seventh switching element K7, then the seventh resistor element R7 is not connected to the circuit. At this time, the eighth resistor element R8, the ninth resistor element R9 are in series with the initial resistor element R, and the total resistance of the gain switching readout circuit 60 can be quantified as R(total) = R8 + R9 + R + r, and the total current can be quantified as I(total) = VDD / (R8 + R9 + R + r); if the voltage value of the pixel voltage signal is less than 100 mV, that is, 0 < vbtl < 100 mV, the fifth comparator A5 outputs a seventh invalid level sw-7' to the seventh switching element K7 to turn off the seventh switching element K7, then the seventh resistor element R7, the eighth resistor element R8, the ninth resistor element R9 and the initial resistor element R are connected in series to the circuit, and the total resistance of the gain switching readout circuit 60 remains unchanged, and the total current remains unchanged, that is, when the voltage value of the pixel voltage signal is less than 100 mV, the gain switching readout circuit 60 is at the initial gain.

[0126] The working principles of the sixth comparator A6 and the seventh comparator A7 are the same as those of the fifth comparator A5, and will not be elaborated here.

[0127] Similarly, as described above, when the voltage value of the pixel voltage signal is in the change intervals of 0 < vbtl < 100 mV, 100 mV < vbtl < 200 mV, 200 mV < vbtl < 400 mV, and 400 mV < vbtl < 800 mV respectively, the corresponding currents of the gears input to the analog-to-digital conversion module 63 can be quantified as the first gear current VDD / (R7 + R8 + R9 + R + r), the second gear current VDD / (R8 + R9 + R + r), the third gear current VDD / (R9 + R + r), and the fourth gear current VDD / (R + r).

[0128] Embodiment 4

[0129] Figure 5 The circuit schematic diagram of a gain switching readout device provided by the fourth embodiment of the present application is shown in Figure 5 . The gain switching readout device provided by the fourth embodiment of the present application includes: a signal strength detection circuit 70 and a gain switching readout circuit 80.

[0130] The signal strength detection circuit 70 includes: an eighth detection module 71, a ninth detection module 72, a tenth detection module 73, an eleventh detection module 74, a twelfth detection module 75, and a thirteenth detection module 76. The eighth detection module 71 includes an eighth comparator A8, the ninth detection module 72 includes a ninth comparator A9, the tenth detection module 73 includes a tenth comparator A10, the eleventh detection module 74 includes an eleventh comparator A11, the twelfth detection module 75 includes a twelfth comparator A12, and the thirteenth detection module 76 includes a thirteenth comparator A13. The first input terminal of the eighth comparator A8 is coupled to the eighth comparison signal input terminal P8, and the second input terminal of the eighth comparator A8 is coupled to the pixel voltage signal input terminal P(vbtl); the first input terminal of the ninth comparator A9 is coupled to the ninth comparison signal input terminal P9, and the second input terminal of the ninth comparator A9 is coupled to the pixel voltage signal input terminal P(vbtl); the first input terminal of the tenth comparator A10 is coupled to the tenth comparison signal input terminal P10, and the second input terminal of the tenth comparator A10 is coupled to the pixel voltage signal input terminal (vbtl); the first input terminal of the eleventh comparator A11 is coupled to the eleventh comparison signal input terminal P11, and the second input terminal of the eleventh comparator A11 is coupled to the pixel voltage signal input terminal (vbtl); the first input terminal of the twelfth comparator A12 is coupled to the twelfth comparison signal input terminal P12, and the second input terminal of the twelfth comparator A12 is coupled to the pixel voltage signal input terminal (vbtl); the first input terminal of the thirteenth comparator A13 is coupled to the thirteenth comparison signal input terminal P13, and the second input terminal of the thirteenth comparator A13 is coupled to the pixel voltage signal input terminal (vbtl).

[0131] The output terminal of the eighth comparator A8 is connected to the first control terminal of the tenth switching element K10 through a NOT gate circuit N and a NAND-OR-NOT gate circuit F, and is used to output an invalid level opposite to the valid level or output a valid level opposite to the invalid level according to the comparison result of the voltage values of the eighth comparison signal and the pixel voltage signal; the output terminals of the ninth comparator A9 and the tenth comparator A10 are both connected to the first control terminal of the tenth switching element K10 through an AND gate circuit AND1 and a NAND-OR-NOT gate circuit F, and are used to output a valid level when the ninth comparator A9 and the tenth comparator A10 respectively output the same valid level according to the comparison results, or output an invalid level when the ninth comparator A9 and the tenth comparator A10 respectively output the same invalid level according to the comparison results, or output an invalid level when the ninth comparator A9 and the tenth comparator A10 respectively output different levels according to the comparison results; the output terminals of the eleventh comparator A11 and the twelfth comparator A12 are both connected to the first control terminal of the tenth switching element K10 through an AND gate circuit AND2 and a NAND-OR-NOT gate circuit F, and are used to output a valid level when the eleventh comparator A11 and the twelfth comparator A12 respectively output the same valid level according to the comparison results, or output an invalid level when the eleventh comparator A11 and the twelfth comparator A12 respectively output the same invalid level according to the comparison results, or output an invalid level when the eleventh comparator A11 and the twelfth comparator A12 respectively output different levels according to the comparison results; the output terminal of the thirteenth comparator A13 is connected to the first control terminal of the tenth switching element K10 through a NAND-OR-NOT gate circuit F. The first path terminal of the tenth switching element K10 is coupled to the bias voltage source VDD, and the second path terminal of the tenth switching element K10 is connected to the first input terminal of the voltage conversion element M1, and is used to control the conduction and cutoff of the tenth switching element K10 according to the high level or low level output by the NAND-OR-NOT gate circuit F, and further control the magnitude of the bias voltage between the first input terminal and the second input terminal of the input voltage conversion element M1.

[0132] In the fourth embodiment, the gain switching readout circuit 80 includes a gain selection module 81, and the gain selection module 81 includes a gain selection component, a fixed resistance element R10, and a voltage conversion element M1.

[0133] Specifically, the gain selection component includes: a tenth gain selection component and an eleventh gain selection component. The tenth gain selection component includes an eleventh switching element K11 and an eleventh resistance element R11 connected in series, and the eleventh gain selection component includes a twelfth switching element K12 and a twelfth resistance element R12 connected in series.

[0134] The first control terminal of the eleventh switching element K11 is connected to an AND gate circuit formed by the output terminals of the eleventh comparator A11 and the twelfth comparator A12. The first path terminal of the eleventh switching element K11 is connected to the first input terminal of the voltage conversion element M1 through the eleventh resistor element R11, and the second path terminal of the eleventh switching element K11 is connected to the common low voltage terminal. The first control terminal of the twelfth switching element K12 is connected to the output terminal of the thirteenth comparator A13. The first path terminal of the twelfth switching element K12 is connected to the first input terminal of the voltage conversion element M1 through the twelfth resistor element R12, and the second path terminal of the twelfth switching element K12 is connected to the common low voltage terminal.

[0135] In the fourth embodiment, the working principle of the switching element is the same as that in the first embodiment, and will not be elaborated here.

[0136] The first end of the fixed resistor element R10 is connected to the first input terminal of the voltage conversion element M1, the second end of the fixed resistor element R10 is connected to the common low voltage terminal, and the second input terminal of the voltage conversion element M1 receives the pixel voltage signal.

[0137] In the fourth embodiment, the tenth gain selection component, the eleventh gain selection component, and the fixed resistor element R10 are all connected to the receiving ground signal terminal.

[0138] In the fourth embodiment, the eighth detection module 71 further includes a fifteenth capacitor element C15 and a sixteenth capacitor element C16. The ninth detection module 72 further includes a seventeenth capacitor element C17 and an eighteenth capacitor element C18. The tenth detection module 73 further includes a nineteenth capacitor element C19 and a twentieth capacitor element C20. The eleventh detection module 74 further includes a twenty-first capacitor element C21 and a twenty-second capacitor element C22. The twelfth detection module 75 further includes a twenty-third capacitor element C23 and a twenty-fourth capacitor element C24. The thirteenth detection module 76 further includes a twenty-fifth capacitor element C25 and a twenty-sixth capacitor element C26. The connection manner of the capacitor elements in this embodiment is the same as that of the capacitor elements in the first embodiment, and will not be elaborated here.

[0139] In the fourth embodiment, the eighth comparator A8, the ninth comparator A9, the tenth comparator A10, the eleventh comparator A11, the twelfth comparator A12, and the thirteenth comparator A13 are also respectively connected to the voltage reset signal input terminal az for resetting the voltages of the comparators according to the voltage reset signal.

[0140] In the fourth embodiment, the voltage value of the eighth comparison signal is 110 mv, the voltage value of the ninth comparison signal is 90 mv, the voltage value of the tenth comparison signal is 210 mv, the voltage value of the eleventh comparison signal is 190 mv, the voltage value of the twelfth comparison signal is 410 mv, and the voltage value of the thirteenth comparison signal is 390 mv.

[0141] In the fourth embodiment, the gain switching readout circuit 80 may further include a current mirror module 82. The first input end of the current mirror module 82 is connected to the output end of the voltage conversion element M1, and the second input end of the current mirror module 82 is connected to the bias voltage source VDD.

[0142] Specifically, the current mirror module 82 includes a first common-gate transistor M2 and a second common-gate transistor M3. The gates of the first common-gate transistor M2 and the second common-gate transistor M3 are both connected to the output end of the voltage conversion element M1.

[0143] In the fourth embodiment, the gain switching readout circuit 80 further includes an analog-to-digital conversion module 83. The analog-to-digital conversion module 83 is connected to the output end of the current mirror module 82 and is used to receive the pixel current signal output by the current mirror module 82 and convert it into a digital signal.

[0144] In the fourth embodiment, the gain switching control method of the gain switching readout circuit 80 is the same as that in the first embodiment, and will not be described in detail here.

[0145] Obviously, those skilled in the art can make various changes and modifications to the invention without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these changes and modifications. The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered that the scope described in this specification is covered.

[0146] It should be noted that in this document, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising one..." does not exclude the presence of additional identical elements in the process, method, article or device comprising that element. In addition, components, features, and elements with the same name in different embodiments of this application may have the same meaning or different meanings, and their specific meanings need to be determined based on their explanations in the specific embodiments or further in combination with the context of the specific embodiments.

[0147] It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this document, the first element may also be referred to as the second element, and similarly, the second element may also be referred to as the first element. Depending on the context, as used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context indicates otherwise. It should be further understood that the terms "comprise" and "include" indicate the presence of the stated features, steps, operations, elements, components, items, kinds, and / or groups, but do not exclude the presence, occurrence or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or meaning any one or any combination. Thus, "A, B or C" or "A, B and / or C" means "any one of the following: A; B; C; A and B; A and C; B and C; A, B and C". An exception to this definition only occurs when the combination of elements, functions, steps or operations is inherently mutually exclusive in some way.

[0148] The above are only the preferred embodiments of this application and are not intended to limit this application. Any modifications, equivalent replacements or improvements made within the spirit and principles of this application shall be included within the protection scope of this application.

Claims

1. A gain switching readout device, characterized in that, It includes a signal strength detection circuit and a gain switching readout circuit; Among them, the signal strength detection circuit is used to receive a pixel voltage signal and output a corresponding number of valid levels according to the voltage value of the pixel voltage signal; The gain switching readout circuit includes a gain selection module, and the gain selection module is used to receive the pixel voltage signal and convert the pixel voltage signal into a pixel current signal of a corresponding gear according to the number of valid levels; The signal strength detection circuit includes a detection module, and the detection module includes a comparator. The first input end of the comparator is coupled to a comparison signal input end, the second input end of the comparator is coupled to a pixel voltage signal input end, and the output end of the comparator is used to output a valid level to the gain selection module according to the comparison result of the comparison signal and the voltage value of the pixel voltage signal; The gain selection module includes a gain selection component, an initial resistance element, and a voltage conversion element. The gain selection component includes a switch element and a resistance element connected in series. The first control end of the switch element is connected to the output end of the comparator. The first path end of the switch element is connected to the first input end of the voltage conversion element through the resistance element. The second path end of the switch element is connected to a common low voltage end. The switch element is used to conduct when receiving the valid level, so that the resistance element is connected into a loop including the voltage conversion element; The first end of the initial resistance element is connected to the first input end of the voltage conversion element, and the second end of the initial resistance element is connected to a common low voltage end. The initial resistance element is used to control the gear of the initial pixel current signal according to the initial resistance value of the gain selection module; The second input end of the voltage conversion element receives the pixel voltage signal. The voltage conversion element is used to convert the pixel voltage signal into a pixel current signal and output the corresponding pixel current signal according to the resistance value of the loop; The comparator is also connected to a voltage reset signal input end and is used to reset the voltage of the comparator according to the voltage reset signal.

2. The gain switching readout device according to claim 1, characterized in that The detection module includes: a first detection module, a second detection module, and a third detection module; Among them, the first detection module includes a first comparator. The first input end of the first comparator is coupled to a first comparison signal input end, the second input end of the first comparator is coupled to a pixel voltage signal input end, and the output end of the first comparator is used to output a first valid level to the gain selection module according to the comparison result of the first comparison signal and the voltage value of the pixel voltage signal; The second detection module includes a second comparator. The first input end of the second comparator is coupled to a second comparison signal input end, the second input end of the second comparator is coupled to the pixel voltage signal input end, and the output end of the second comparator is used to output a second valid level to the gain selection module according to the comparison result of the second comparison signal and the voltage value of the pixel voltage signal; The third detection module includes a third comparator. The first input terminal of the third comparator is coupled to a third comparison signal input terminal. The second input terminal of the third comparator is coupled to the pixel voltage signal input terminal. The output terminal of the third comparator is configured to output a third valid level to the gain selection module according to the comparison result of the third comparison signal and the voltage value of the pixel voltage signal.

3. The gain switching readout device according to claim 2, wherein: The gain selection component includes: a first gain selection component, a second gain selection component, and a third gain selection component; the first input terminal of the voltage conversion element is connected to the first gain selection component, the second gain selection component, and the third gain selection component; Wherein, the first gain selection component includes a first switch element and a first resistor element connected in series. The first control terminal of the first switch element is connected to the output terminal of the first comparator. The first path terminal of the first switch element is connected to the first input terminal of the voltage conversion element through the first resistor element. The second path terminal of the first switch element is connected to a common low voltage terminal. The first switch element is configured to conduct when receiving the first valid level, so that the first resistor element is connected into the loop including the voltage conversion element; The second gain selection component includes a second switch element and a second resistor element connected in series. The first control terminal of the second switch element is connected to the output terminal of the second comparator. The first path terminal of the second switch element is connected to the first input terminal of the voltage conversion element through the second resistor element. The second path terminal of the second switch element is connected to a common low voltage terminal. The second switch element is configured to conduct when receiving the second valid level, so that the second resistor element is connected into the loop including the voltage conversion element; The third gain selection component includes a third switch element and a third resistor element connected in series. The first control terminal of the third switch element is connected to the output terminal of the third comparator. The first path terminal of the third switch element is connected to the first input terminal of the voltage conversion element through the third resistor element. The second path terminal of the third switch element is connected to a common low voltage terminal. The third switch element is configured to conduct when receiving the third valid level, so that the third resistor element is connected into the loop including the voltage conversion element.

4. The gain-switching readout device according to claim 3, wherein The first gain selection component, the second gain selection component, the third gain selection component, and the initial resistor element are all connected to the receiving ground signal terminal.

5. The gain-switching readout device according to claim 1, characterized in that, The detection module further includes a first capacitor element and a second capacitor element; The first capacitor element is located between the first input terminal of the comparator and the input terminal of the comparison signal. The first capacitor element is configured to filter the comparison signal; The second capacitor element is coupled between the second input terminal of the comparator and the pixel voltage signal input terminal. The second capacitor element is configured to filter the pixel voltage signal.

6. The gain-switching readout device according to claim 1, characterized in that, The voltage value of the comparison signal is 100mv, 200mv or 400mv.

7. The gain-switching readout device according to claim 2, wherein The voltage values of the first comparison signal received by the first comparator, the second comparison signal received by the second comparator, and the third comparison signal received by the third comparator increase in sequence.

8. The gain switching readout device according to claim 7, wherein The voltage value of the first comparison signal is 100mv, the voltage value of the second comparison signal is 200mv, and the voltage value of the third comparison signal is 400mv.

9. The gain switching readout device according to claim 1, wherein The gain switching readout circuit further includes a current mirror module. The first input end of the current mirror module is connected to the output end of the voltage conversion element, the second input end of the current mirror module is connected to a bias voltage source, and the output end of the current mirror module is used to output the pixel current signal corresponding to the corresponding gear.

10. The gain-switching readout device according to claim 9, characterized in that, The current mirror module includes a first common-gate transistor and a second common-gate transistor. The gates of the first common-gate transistor and the second common-gate transistor are both connected to the output end of the voltage conversion element.

11. The gain-switching readout device according to claim 9, wherein The gain switching readout circuit further includes an analog-to-digital conversion module. The analog-to-digital conversion module is connected to the output end of the current mirror module and is used to receive the pixel current signal output by the current mirror module and convert it into a digital signal.

12. An image sensor, characterized in that, It includes the gain switching readout device according to any one of claims 1-11.

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