Display substrate, display device, and test apparatus

Abstract

The application relates to a display substrate, comprising a display area and a frame area located around the display area, the display area comprising a plurality of data lines and a plurality of gate lines, and a pixel area defined by the intersection of the plurality of data lines and the plurality of gate lines, along a first direction, the frame area comprising a test area located on one side of the display area, the test area comprising at least one row of a plurality of first test electrodes and a plurality of second test electrodes arranged side by side; the test area further comprising a plurality of test transistors, one of the test transistors being connected with three of the first test electrodes; and a plurality of the second test electrodes being connected with the data lines through signal lines. The application further relates to a display device and a test equipment.

Description

Technical Field

[0001] This invention relates to the field of testing technology for display products, and more particularly to a display substrate, a display device, and testing equipment. Background Technology

[0002] As flat panel displays (FPS) have an increasingly significant impact on people's production and daily lives, TFTs, as their core components, also require continuous improvement to meet the ever-increasing market demands. In TFT research and experimentation, characterizing the electrical properties of the device is of paramount importance. On one hand, it directly verifies material evaluation and process development; on the other hand, it guides the design of subsequent circuit functions. Currently, testing a single TFT takes a relatively long time, resulting in only random sampling during the mass production of flat panel displays. This prevents comprehensive monitoring of all electrical parameters of the product. Therefore, shortening the electrical parameter testing time, improving testing efficiency, and expanding the coverage of TFT electrical testing in actual production have become urgent problems to be solved. Summary of the Invention

[0003] To address the aforementioned technical problems, this invention provides a display substrate, a display device, and a testing equipment, thereby resolving the issue of low testing efficiency.

[0004] To achieve the above objectives, the technical solution adopted in this embodiment of the invention is as follows: a display substrate, including a display area and a border area located around the display area, the display area including multiple data lines and multiple gate lines, and a pixel area defined by the intersection of the multiple data lines and multiple gate lines, along a first direction, the border area including a test area located on one side of the display area, the test area including at least one row of multiple first test electrodes and multiple second test electrodes arranged side by side;

[0005] The test area also includes a plurality of test transistors, and one of the test transistors is connected to a plurality of the first test electrodes respectively;

[0006] Multiple second test electrodes are connected to the data line via signal lines.

[0007] Optionally, a plurality of the first test electrodes and a plurality of the second test electrodes are arranged side by side along a second direction, the second direction intersecting the first direction.

[0008] Optionally, the three first test electrodes corresponding to the same test transistor are arranged adjacent to each other.

[0009] Optionally, along the second direction, a plurality of the first test electrodes are located on the same side of a plurality of the second test electrodes, and the second direction is the arrangement direction of the plurality of the second test electrodes.

[0010] Optionally, along the second direction, a plurality of the second test electrodes are respectively disposed on opposite sides of the plurality of the second test electrodes.

[0011] Optionally, in the first direction, the test transistor is located on one side of the first test electrode, and the test transistor includes a virtual gate, a virtual source, and a virtual drain. Along the first direction, the first test electrode connected to the virtual gate is located between the first test electrode connected to the virtual source and the second test electrode connected to the virtual drain.

[0012] Optionally, one of the second test electrodes is connected to the plurality of data lines via a switching element.

[0013] Optionally, each pixel region includes a pixel transistor, the test transistor and the pixel transistor have the same structure, and the test transistor and the pixel transistor are formed using a synchronous patterning process.

[0014] This invention also provides a display device, including the display substrate described above.

[0015] This invention also provides a testing device, including the above-described display substrate and testing apparatus. The testing apparatus includes a probe, and the probe includes at least one row of probes. Each row of probes is configured to correspond one-to-one with the first test electrode and the second test electrode arranged in the same row.

[0016] The beneficial effects of this invention are: by integrating the first test electrode, which is used in conjunction with an electrical parameter monitoring machine, and the second test electrode, which is used in conjunction with an array tester, and by arranging the first and second test electrodes side by side, it is possible to simultaneously test the pixel transistors in the display area and the test transistors in the test area, thereby improving testing efficiency. Attached Figure Description

[0017] Figure 1 A schematic diagram illustrating a display substrate in related technologies;

[0018] Figure 2 A schematic diagram showing the distribution of the first test electrode in the related technology;

[0019] Figure 3 This diagram illustrates the arrangement of the first and second test electrodes in an embodiment of the present invention. Figure 1 ;

[0020] Figure 4 This diagram illustrates the arrangement of the first and second test electrodes in an embodiment of the present invention. Figure 2 ;

[0021] Figure 5 This diagram illustrates the arrangement of the first and second test electrodes in an embodiment of the present invention. Figure 3 ;

[0022] Figure 6 A schematic diagram of the display substrate in an embodiment of the present invention.

[0023] 1 First test electrode; 2 Second test electrode; 3 Test transistor; 4 Signal line; 10 Gate line; 20 Data line; 30 Pixel area; 31 Pixel transistor; 32 Pixel electrode. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0025] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0026] refer to Figures 3-6This embodiment provides a display substrate, including a display area A and a border area located around the display area A. The display area A includes multiple data lines 20 and multiple gate lines 10, and a pixel area 30 defined by the intersection of the multiple data lines 20 and the multiple gate lines 10. A pixel transistor 31 and a pixel electrode 32 are disposed in the pixel area 30. The gate of the pixel transistor 31 is connected to the gate line 1 corresponding to the pixel area 30, and the source of the pixel transistor 31 is connected to the data line 2 corresponding to the pixel area 30, along a first direction (i.e. Figure 6 The direction parallel to the extension direction of data line 20, refer to Figure 6 (in the X direction), the border area includes a test area B located on one side of the display area A, and the test area B includes at least one row of multiple first test electrodes 1 and multiple second test electrodes 2 arranged side by side;

[0027] The test area B also includes a plurality of test transistors 3, and one of the test transistors 3 is connected to a plurality of the first test electrodes 1 respectively;

[0028] Multiple second test electrodes 2 are connected to the data line 2 via signal line 4.

[0029] The first test electrode 1 and the second test electrode 2 used for different functional tests are integrated into one configuration. This represents a significant improvement over the separate AT and EPM tests used in related technologies. In this embodiment, the test area includes at least one row of multiple first test electrodes 1 and multiple second test electrodes 2 arranged side-by-side, enabling simultaneous testing of the AA area array line pixel detection and the TEG area transistor electrical properties. This integration method overcomes the limitations of single-point testing, as seen in previous related technologies where AT and EPM tests were performed separately. The EPM device's single-HEAD mode is improved to a BAR test mode, enabling rapid testing of all glass points, significantly reducing test time and improving test accuracy.

[0030] The Array Test Electrical Measurement Unit (EPM) is integrated into a single, bar-style structure. The distribution of the first test electrode 1 and the second test electrode 2, corresponding to the EPM, is also integrated. This allows for simultaneous connection of probes to both the first and second test electrodes 1 and 2 during testing of the same row of electrodes. This enables simultaneous pixel testing of the AA area array circuit and electrical testing of the TEG area transistors. This integration breaks the limitations of traditional separate AT and EPM testing, consolidating the two testing methods into a single testing process, significantly improving testing efficiency.

[0031] In related technologies, the first test electrode 1 and the second test electrode 2 are disposed separately, as shown in the reference. Figure 1 In this embodiment, the first test electrode 1 and the second test electrode 2 are integrated. The advantage of this design strategy is that it significantly saves the physical space required for testing, compared to... Figure 1 The traditional design shown achieves efficient use of space.

[0032] In an exemplary embodiment, a plurality of first test electrodes 1 and a plurality of second test electrodes 2 are aligned along a second direction (reference). Figure 6 The first direction and the second direction are arranged side by side in the Y direction, and the second direction intersects with the first direction.

[0033] In an exemplary embodiment, a plurality of first test electrodes 1 and a plurality of second test electrodes 2 are aligned along a second direction (reference). Figure 6 The first direction and the second direction are arranged side by side in the Y direction, and the second direction is perpendicular to the first direction.

[0034] refer to Figure 6 The second test electrode 2 is connected to the data line 20 through the signal line 4. The extension direction of the data line 20 is parallel to the first direction. Relative to the extension of the data line 20 along a direction perpendicular to the first direction, the length of the signal line 4 can be shortened, which facilitates the arrangement of the signal line 4 and reduces the space occupied by the signal line 4, thereby facilitating the realization of a narrow bezel.

[0035] In the first direction, the test area B is located on one side of the display area A. The length of the test area B in the first direction is finite, while the length of the test area B in the second direction is much greater than the length of the test area B in the first direction. Therefore, a plurality of first test electrodes 1 and a plurality of second test electrodes 2 are arranged side by side along the second direction. Figure 6 This reduces the length of the display substrate in the first direction, facilitating the setting of a narrow bezel. Furthermore, the plurality of first test electrodes 1 and the plurality of second test electrodes 2 are arranged side-by-side along the second direction, without affecting the length of the display substrate in the second direction.

[0036] For example, the number of first test electrodes 1 corresponding to the same test transistor 3 is three, wherein one first test electrode 1 is used to connect to the virtual gate of the test transistor 3, one first test electrode 1 is used to connect to the virtual source of the test transistor 3, and one first test electrode 1 is used to connect to the virtual drain of the test transistor 3. In an exemplary embodiment, the three first test electrodes 1 corresponding to the same test transistor 3 are arranged adjacent to each other.

[0037] The test transistor 3 includes a virtual gate G, a virtual source S, and a virtual drain D, as referenced. Figure 5 The three first test electrodes 1, corresponding to the same test transistor 3, are arranged adjacently. This design optimizes the circuit layout, making the circuit simpler and more compact, thereby facilitating the efficient and stable operation of the test transistor 3. This arrangement significantly reduces signal transmission delay and improves the overall circuit efficiency.

[0038] In an exemplary embodiment, along a second direction, a plurality of first test electrodes 1 are located on the same side of a plurality of second test electrodes 2, and the second direction is the arrangement direction of the plurality of second test electrodes 2.

[0039] In an exemplary embodiment, along a second direction, a plurality of first test electrodes 1 are located on one side of a plurality of second test electrodes 2, and the second direction is the arrangement direction of the plurality of second test electrodes 2.

[0040] In an exemplary embodiment, along a second direction, a plurality of second test electrodes 2 are respectively disposed on opposite sides of the plurality of second test electrodes 2, wherein the second direction is the arrangement direction of the plurality of second test electrodes 2, with reference to... Figure 6 in the Y direction.

[0041] In one exemplary embodiment, when the first test electrode 1 is provided on both sides of the second test electrode 2 along the second direction, the number of the first test electrode 1 on both sides of the plurality of second test electrodes 2 may be the same, that is, the corresponding second test electrodes 2 form a symmetrical layout on both sides of the plurality of second test electrodes 2; when the first test electrode 1 is provided on both sides of the second test electrode 2, the number of the first test electrode 1 on both sides of the plurality of second test electrodes 2 may also be different.

[0042] Furthermore, the second direction actually refers to the arrangement direction of the plurality of second test electrodes 2. In other words, if we view this layout from a specific angle, the plurality of first test electrodes 1 will form a straight line on the same side of the plurality of second test electrodes 2. This arrangement is more conducive to connecting the first test electrodes 1 and the second test electrodes 2 to probes simultaneously for testing.

[0043] It should be emphasized that the embodiments described herein are merely exemplary and do not constitute a limitation on all possible embodiments. In practical applications, the position and number of the first test electrode 1 and the second test electrode 2 in the second direction can be adjusted according to actual needs to obtain the best application effect.

[0044] It should be noted that, among the first test electrode 1 and the second test electrode 2 arranged in the same row, the position and number of the first test electrode 1 can be set according to actual needs. Figure 3 In the distribution of the first test electrode 1 and the second test electrode 2 shown, in the second direction, all of the plurality of first test electrodes 1 are located on one side of the plurality of second test electrodes 2. Figure 4 In the distribution of the first test electrode 1 and the second test electrode 2 shown, in the second direction, a plurality of first test electrodes 1 are respectively disposed on opposite sides of a plurality of second test electrodes 2. Figure 5 In the distribution of the first test electrode 1 and the second test electrode 2 shown, in the second direction, a plurality of first test electrodes 1 are respectively disposed on opposite sides of a plurality of second test electrodes 2. Figure 3 In the distribution of the first test electrode 1 and the second test electrode 2 shown, in the second direction, 12 first test electrodes 1 are provided on one side of the plurality of second test electrodes 2. Figure 4 In the distribution of the first test electrode 1 and the second test electrode 2 shown, in the second direction, three first test electrodes 1 are respectively arranged on opposite sides of the plurality of second test electrodes 2. Figure 5 In the distribution of the first test electrode 1 and the second test electrode 2 shown, in the second direction, six first test electrodes 1 are respectively arranged on opposite sides of the plurality of second test electrodes 2.

[0045] Figure 4 In the distribution of the first test electrode 1 and the second test electrode 2 shown, the arrangement of the test electrodes in the same row includes 6 first test electrodes 1, and 3 first test electrodes 1 are respectively arranged on both sides of the plurality of second test electrodes 2. The three first test electrodes corresponding to a test transistor 3 are located on the same side of the plurality of second test electrodes 2. Figure 3 and Figure 5In this configuration, the arrangement of test electrodes in the same row includes 12 first test electrodes 1, each connected to one of the four test transistors. This is equivalent to merging the first test electrode in a single pin card of the head structure in EPM testing with the second test electrode 2 in a single pin card of the bar-type structure in AT testing, but it is not limited to this. This merging and integration not only improves testing efficiency but also makes the entire testing process more convenient and accurate. Of course, the above description is not the only possible configuration, but only some possible examples, and is not a limitation.

[0046] refer to Figures 3-6 In an exemplary embodiment, in the first direction, the test transistor 3 is located on one side of the first test electrode 1. The test transistor 3 includes a virtual gate G, a virtual source S, and a virtual drain D. Along the first direction, the first test electrode 1 connected to the virtual gate G is located between the first test electrode 1 connected to the virtual source S and the first test electrode 1 connected to the virtual drain D.

[0047] The purpose of adopting the above technical solution is to optimize the circuit distribution, making the circuit simpler and more compact, thereby facilitating the efficient and stable operation of the test transistor 3, and reducing the space occupied by the first test electrode 1, the test transistor 3, and the connecting leads connecting the first test electrode 1 and the test transistor 3.

[0048] In an exemplary embodiment, one of the second test electrodes 2 is connected to multiple data lines via a switching element. This method reduces the number of second test electrodes 2, saving space and cost.

[0049] In some embodiments, the plurality of second test electrodes 2 and the plurality of data lines 20 may be configured in a one-to-one correspondence, as shown in the reference. Figure 6 Therefore, the number of second test electrodes 2 needs to be the same as the number of data lines. This connection method increases the space occupied by multiple second test electrodes 2, and also increases the difficulty of distributing the signal lines 4 connecting the second test electrodes 2 and the corresponding data lines 20.

[0050] In one exemplary embodiment, to make full and efficient use of space and reduce costs, one of the second test electrodes 2 is connected to multiple data lines via a switching element. By adopting this embodiment, signal connections to all data lines can still be established for testing while reducing the number of second test electrodes 2.

[0051] It should be noted that the number of data lines 20 connected to one of the second test electrodes 2 can be set according to actual needs.

[0052] In an exemplary embodiment, the spacing between the plurality of first test electrodes 1 is the same as the spacing between the plurality of second test electrodes 2, and the spacing between one first test electrode 1 and the second test electrode 2 disposed adjacent to it is the same as the spacing between the plurality of first test electrodes 1, which facilitates the connection between the probe and the corresponding test electrode.

[0053] In an exemplary embodiment, each pixel region 30 includes a pixel transistor 31, the test transistor 3 and the pixel transistor 31 have the same structure, and the test transistor 3 and the pixel transistor 31 are formed using a synchronous patterning process.

[0054] The structure of the test transistor 3 is exactly the same as that of the pixel transistor 31. Since the test transistor 3 and the pixel transistor 31 have the same structure and materials, their impedance characteristics are identical. The impedance characteristics of the test transistor 3 can reflect the true impedance characteristics of the pixel transistor 31. This structural similarity allows the test transistor 3 to effectively simulate the behavior of the pixel transistor 31, thereby providing more accurate results during the testing phase.

[0055] When testing the test transistor 3 through the first test electrode 1, a certain voltage is applied between the virtual source and virtual drain of the test transistor 3 through the first test electrode 1, forming a conductive electrical circuit between the virtual source and virtual drain of the test transistor 3. Then, a scanning voltage is applied to the virtual gate of the test transistor 3 through the first test electrode 1, causing the voltage to change slowly, gradually connecting the virtual source and virtual drain. The drain current-gate voltage curve during this process is detected, thereby determining the characteristic value of the test transistor 3. Furthermore, the average value of multiple simultaneously measured characteristic values ​​of the test transistor 3 can be calculated, allowing for a more accurate determination of the properties of the test transistor 3.

[0056] A simultaneous patterning process was employed in the formation of the test transistor 3 and the pixel transistor 31. This process involves a series of complex steps, including thin film deposition, photolithography, doping, and electroplating, all of which require precise control and optimization to ensure the performance and quality of the final product. This process allows the test transistor 3 and the pixel transistor 31 to be precisely fabricated on the display substrate, ensuring they possess consistent performance characteristics.

[0057] The fabrication processes of the pixel transistor 31 and the test transistor 3 are as follows.

[0058] 1): First, a flexible layer and a buffer layer are fabricated on the glass substrate.

[0059] 2): On the buffer layer, A-Si (ACT layer, i.e., active layer) is deposited using physical vapor deposition (PVD) or chemical vapor deposition (CVD) technology. The material of the buffer layer can be insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, and the material of the Act layer can be metal oxide materials, such as IGZO.

[0060] 3): Perform E1A (excimer laser annealing) and doping processes on the ACT layer to adjust its electrical properties. This step is a key step in transistor manufacturing and requires precise control of the annealing temperature and the type and dosage of dopants.

[0061] 4): The ACT Pattern is obtained through coating, developing, etching and cleaning. That is, the ACT layer is formed into the desired pattern through steps such as coating, developing, etching and cleaning. This step requires precise control of time and temperature to ensure the accuracy and consistency of the pattern.

[0062] 5): Deposit an insulating layer GI1 layer on the formed ACT layer pattern to completely cover the ACT layer; wherein the material of the GI1 layer can be insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0063] 6): A Gate1 layer (first gate metal layer) is deposited on the GI1 layer. After coating, developing, etching and cleaning, the required pattern of the Gate1 layer is obtained. The material of the Gate1 layer can be common metals such as Mo, Al, Ti, Au, Cu, Hf, Ta, or Cu process, such as MoNd / Cu / MoNd.

[0064] 7): Deposit an insulating layer GI2 layer on the formed Gate1 layer pattern to completely cover the Gate1 layer. The material of the GI2 layer can be insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.

[0065] 8): A Gate2 layer (second gate metal layer) is deposited on the GI2 layer. After coating, developing, etching and cleaning, the required pattern of the Gate2 layer is obtained. The material of the Gate2 layer can be common metals such as Mo, Al, Ti, Au, Cu, Hf, Ta, or Cu process, such as MoNd / Cu / MoNd.

[0066] 9): An insulating ILD layer is deposited on the formed Gate1 layer pattern, and the Hole (via) is obtained by coating, developing, etching and cleaning.

[0067] 10): After DEP of SD1 (source / drain metal layer), the required pattern of SD 1 layer is obtained by coating, developing, etching and cleaning.

[0068] Every step of the manufacturing process requires precise control of process parameters to ensure transistor performance and quality. Among these, annealing temperature, dopant type and dosage, thin film deposition temperature and time, and pattern shape and size are all critical factors that need to be strictly controlled.

[0069] The above steps complete the fabrication process for the pixel transistor and the test transistor 3.

[0070] This invention also provides a display device, including the display substrate described above.

[0071] Along the first direction, the frame area includes a test area B located on one side of the display area A. The test area B includes at least one row of multiple first test electrodes 1 and multiple second test electrodes 2 arranged side by side. The three first test electrodes 1 are connected to a test transistor 3.

[0072] The test transistor 3 includes a virtual gate G, a virtual source S, and a virtual drain D. The testing process using the test transistor 3 and the second test electrode 2 is as follows: a signal is provided to the first test electrode 1 corresponding to the virtual gate G, virtual source S, and virtual drain D. At this time, a level of -5.1V is applied to the virtual gate, and the virtual drain is scanned within a scanning range of 15 to -15V with a scanning gradient of 0.2V. The required data is obtained from the virtual source. Finally, the device's SUM module detects and records the electrical parameters of the device, plots the IDVG curve, and obtains electrical parameter values ​​such as VTH, MOB, SS2, and IOFF.

[0073] The testing process using the second test electrode 2 is as follows: A driving signal, such as VDD, VINIT, VGL, VGH, etc., is applied to the second test electrode 2 to drive the AA area through the GOA area on the display substrate. The voltage fed back by the pixel is converted into a grayscale image by digital signal analogization to determine the TFT working state of the entire AA area pixel.

[0074] The display device can be any product or component with display function, such as an LCD TV, LCD monitor, digital photo frame, mobile phone, or tablet computer. The display device also includes a flexible circuit board, a printed circuit board, and a backplate.

[0075] This invention also provides a testing device, including the above-mentioned display substrate and testing apparatus. The testing apparatus includes a probe, and the probe includes at least one row of probes. Each row of probes is configured in one-to-one correspondence with the first test electrode 1 and the second test electrode 2 arranged in the same row.

[0076] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A display substrate, comprising a display area and a border area surrounding the display area, the display area comprising a plurality of data lines and a plurality of gate lines, and a pixel area defined by the intersection of the plurality of data lines and the plurality of gate lines, characterized in that, Along the first direction, the frame area includes a test area located on one side of the display area, the test area including at least one row of multiple first test electrodes and multiple second test electrodes arranged side by side; The test area also includes a plurality of test transistors, one of which is connected to a plurality of first test electrodes, and the three first test electrodes connected to the same test transistor are arranged adjacent to each other. Multiple second test electrodes are connected to the data line via signal lines.

2. The display substrate according to claim 1, characterized in that, A plurality of first test electrodes and a plurality of second test electrodes are arranged side by side along a second direction, the second direction intersecting the first direction.

3. The display substrate according to claim 1, characterized in that, Along the second direction, a plurality of first test electrodes are located on the same side of a plurality of second test electrodes, and the second direction is the arrangement direction of the plurality of second test electrodes.

4. The display substrate according to claim 1, characterized in that, Along the second direction, a plurality of second test electrodes are respectively disposed on opposite sides of the plurality of second test electrodes.

5. The display substrate according to claim 1, characterized in that, In the first direction, the test transistor is located on one side of the first test electrode. The test transistor includes a virtual gate, a virtual source, and a virtual drain. Along the first direction, the first test electrode connected to the virtual gate is located between the first test electrode connected to the virtual source and the second test electrode connected to the virtual drain.

6. The display substrate according to claim 1, characterized in that, One of the second test electrodes is connected to the plurality of data lines via a switching element.

7. The display substrate according to claim 1, characterized in that, Each pixel region includes a pixel transistor, the test transistor and the pixel transistor have the same structure, and the test transistor and the pixel transistor are formed using a synchronous patterning process.

8. A display device, characterized in that, Includes the display substrate as described in any one of claims 1-7.

9. A testing device, characterized in that, The invention includes a display substrate and a testing apparatus as described in any one of claims 1-7, wherein the testing apparatus includes a probe, the probe including at least one row of probes, and each row of probes is configured in one-to-one correspondence with the first test electrode and the second test electrode arranged in the same row.

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