Convolution circuit and control method thereof, neural network accelerator, and electronic device

Abstract

The present application relates to the field of artificial intelligence chips, and provides a convolution circuit and a control method thereof, a neural network accelerator and electronic equipment, the convolution circuit comprising a convolution calculation unit, the convolution calculation unit comprising a selector group, a feature register group, a weight register group, a multiplier group, an adder group and a result register group; the selector group is used for caching input feature data to the feature register group through an input selector, and is also used for shifting the cached feature data through a shift selector; the feature register group is used for caching the input feature data and providing P feature data to the multiplier group; the weight register group is used for caching P input weight data; the multiplier group is used for calculating the product of corresponding weight data and corresponding feature data; and the adder group is used for accumulating the calculation results of the multiplier group and storing them into the result register group. The structure of the convolution circuit can be reused in different convolution operation neural networks, thereby avoiding resource waste.

Description

Technical Field

[0001] This invention relates to the field of artificial intelligence chip technology, and in particular to a convolution circuit and its control method, a neural network accelerator, and an electronic device. Background Technology

[0002] With the development of artificial intelligence technology, neural networks are playing an increasingly important role. The most frequent operation in neural network operations is convolution. Different neural networks perform different convolution operations. In order to implement convolution operations, it is necessary to set up corresponding circuit structures for different neural networks. The application of a certain circuit structure is limited. Summary of the Invention

[0003] This invention provides a convolution circuit and its control method, a neural network accelerator, and an electronic device to solve the problem of limited application of circuit structures for implementing convolution operations in the prior art, and to enable convolution operations to support multiple convolution kernels through the same convolution circuit.

[0004] This invention provides a convolution circuit, including a convolution calculation unit; the convolution calculation unit includes a selector group, a feature register group, a weight register group, a multiplier group, an adder group, and a result register group; the selector group includes an input selector and a shift selector;

[0005] The selector group is used to cache the input feature data into the feature register group through the input selector, and is also used to shift the cached feature data through the shift selector;

[0006] The feature register group is used to buffer the input feature data and provide P feature data to the multiplier group, where P is a positive integer;

[0007] The weight register group is used to cache P input weight data and provide the P weight data to the multiplier group, and the P weight data correspond one-to-one with the P feature data;

[0008] The multiplier group is used to calculate the product of the corresponding weight data and the corresponding feature data;

[0009] The adder group is used to accumulate the calculation results of the multiplier group and store them in the result register group.

[0010] According to a convolution circuit provided by the present invention, the input feature data is one-dimensional data; the input feature data is input data of one-dimensional convolution, or the input feature data is input data obtained after multi-dimensional convolution is converted into one-dimensional convolution.

[0011] According to a convolution circuit provided by the present invention, the multiplier group includes P multipliers, each of the P multipliers corresponding to one of the P weight data, and each multiplier is used to calculate the product of the corresponding weight data and the corresponding feature data;

[0012] The adder group is used to accumulate the product of each multiplier in parallel and store the accumulation result in the result register group.

[0013] According to a convolution circuit provided by the present invention, the feature register group includes P+X-1 feature registers, where X is the maximum convolution kernel size parameter supported by the convolution calculation unit, and X is a positive integer; the selector group includes P+X-2 selectors and a shift controller;

[0014] The first to the second feature registers in the P+X-1 feature registers correspond one-to-one with the P+X-2 selectors; the feature registers are used to cache the directly input feature data or to cache the feature data provided by the corresponding selector;

[0015] P+X-2 selectors serve as input selectors, and each input selector is used to cache the input feature data into the corresponding feature register.

[0016] The P+X-2 selectors also serve as shift selectors, and the i-th shift selector is used to shift the feature data cached in the (i+1)-th feature register to the i-th feature register under the control of the shift controller, where i is a positive integer;

[0017] The first to the Pth feature registers in the P+X-1 feature registers correspond one-to-one with the P multipliers, and are used to provide the cached feature data to the corresponding multiplier.

[0018] According to a convolution circuit provided by the present invention, the adder group includes P adders, a clear controller, and P clear selectors; the result register group includes P result registers;

[0019] There is a one-to-one correspondence between the P adders and the P multipliers;

[0020] Each of the P adders corresponds one-to-one with one of the P result registers;

[0021] Each of the P adders also corresponds one-to-one with a P clear selector;

[0022] Each of the P result registers also corresponds one-to-one with one of the P clear selectors;

[0023] The clear controller is used to control each clear selector to select zero for output when it is necessary to restart the accumulation; and to control each clear selector to select the accumulation result stored in the corresponding result register for output when it is not necessary to restart the accumulation.

[0024] The adder is used to accumulate the product of the output of the corresponding clear selector and the corresponding multiplier, and store the accumulation result in the corresponding result register.

[0025] According to a convolution circuit provided by the present invention, the number of convolution calculation units is m, where m is a positive integer greater than 1; the m convolution calculation units are cascaded.

[0026] The convolution circuit further includes m-1 first cascade selectors, wherein the j-th convolution calculation unit and the (j-1)-th convolution calculation unit in the m convolution calculation units are cascaded through the (j-1)-th first cascade selector, where j is a positive integer greater than 1;

[0027] The convolution calculation unit further includes a second cascade selector, which corresponds to the Pth shift selector;

[0028] The (j-1)th first cascade selector is used to select the feature data cached in the first feature register of the j-th convolutional computation unit and output it to the second cascade selector of the (j-1)th convolutional computation unit;

[0029] The second cascade selector of the (j-1)th convolutional computation unit is used to select the feature data cached in the (P+1)th feature register of the (j-1)th convolutional computation unit or the feature data cached in the first feature register of the j-th convolutional computation unit, and output it to the Pth shift selector of the (j-1)th convolutional computation unit.

[0030] The Pth shift selector in the (j-1)th convolutional computation unit is further configured to shift the feature data cached in the first feature register of the j-th convolutional computation unit to the Pth feature register of the (j-1)th convolutional computation unit under the control of the shift controller.

[0031] The present invention also provides a control method based on any of the convolution circuits described above, comprising:

[0032] The selector group buffers the input feature data into the feature register group through the input selector, or shifts the buffered feature data through the shift selector;

[0033] The feature register group provides P cached feature data to the multiplier group, where P is a positive integer;

[0034] The weight register group buffers the input P weight data and provides the P weight data to the multiplier group, and the P weight data correspond one-to-one with the P feature data;

[0035] The multiplier group calculates the product of each of the P weight data and the corresponding feature data;

[0036] The adder group accumulates the calculation results of the multiplier group and stores them in the result register group.

[0037] A control method for a convolutional circuit according to the present invention includes: the input feature data is one-dimensional data; the input feature data is input data for one-dimensional convolution, or the input feature data is input data obtained after multi-dimensional convolution is converted into one-dimensional convolution.

[0038] The present invention also provides a neural network accelerator, including the convolution circuit as described in any of the above.

[0039] The present invention also provides an electronic device including a neural network accelerator as described in any of the above embodiments.

[0040] The convolution circuit provided by this invention can realize the product calculation and accumulation of different feature data and weight data by shifting. In this way, it can handle multiple convolution kernels. Thus, the same convolution circuit can realize the convolution operation of multiple convolution kernels, so that the structure of the convolution circuit can be reused in neural networks with different convolution operations, avoiding resource waste. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0042] Figure 1 This is one of the structural schematic diagrams of the convolution circuit provided by the present invention;

[0043] Figure 2 This is the second schematic diagram of the convolution circuit provided by the present invention;

[0044] Figure 3 This is the third schematic diagram of the convolution circuit provided by the present invention;

[0045] Figure 4This is a flowchart illustrating the control method for the convolution circuit provided by the present invention. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0047] The following is combined with Figures 1 to 3 The convolution circuit of the present invention is described.

[0048] This embodiment provides a convolution circuit, including: a convolution calculation unit 200;

[0049] The convolution calculation unit includes a selector group 220, a feature register group 250, a weight register group 230, a multiplier group 210, an adder group 240, and a result register group 260; the selector group 220 includes an input selector and a shift selector;

[0050] The selector group 220 is used to cache the input feature data into the feature register group 250 through the input selector, and is also used to shift the cached feature data through the shift selector;

[0051] The feature register group 250 is used to buffer the input feature data and provide P feature data to the multiplier group 210, where P is a positive integer;

[0052] The weight register group 230 is used to cache P input weight data and provide the P weight data to the multiplier group, wherein the P weight data correspond one-to-one with the P feature data;

[0053] The multiplier group 210 is used to calculate the product of the corresponding weight data and the corresponding feature data;

[0054] The adder group 240 is used to accumulate the calculation results of the multiplier group 210 and store them in the result register group.

[0055] The convolution calculation unit is used to perform convolution operations. The maximum convolution kernel size parameter that the convolution calculation unit can support is X, where X is a positive integer.

[0056] In practice, the convolution circuit can select each weight data in the target convolution kernel as the current weight data according to a set order and send it to the weight register group 230 for buffering and then to the multiplier group 210.

[0057] The input feature data may include L feature data. For example, the value of L is less than or equal to P+X-1. The selector group 220 includes an input selector and a shift selector. For example, in a first state, the input selector selects the feature data to be received from the external input and buffers it in the feature register group 250. In a second state, the shift selector shifts the feature data buffered in the feature register group 250 under the control of the shift signal of the shift controller. Here, the state of the selector is used to determine which input is selected as the output, including a first state and a second state, which are used to select different inputs as outputs.

[0058] The target convolution kernel is the convolution kernel used in the current convolution operation. For example, the size of the target convolution kernel is less than or equal to X*X. For instance, if X = 5, then the target convolution kernel can be 1*1, 2*2, 3*3, 4*4, or 5*5. That is, the same convolution circuit in this embodiment can support convolution operations with multiple convolution kernels. The stride of the corresponding convolution operation can also be set according to actual needs, such as a stride of 1, a stride of 2, etc.

[0059] The data required for convolution operations include feature data and weight data of the target convolution kernel. During convolution, the product of the feature data and the weight data needs to be calculated and the result of the multiplication is obtained. A weight register group 230 is set up in the convolution circuit to store the weight data, and the weight data in the weight register group 230 can be provided to the multiplier group 210. A feature register group 250 is set up to store the feature data.

[0060] In implementation, each weight data in the target convolution kernel can be selected as the current weight data according to a set order and sent to the weight register group 230 for buffering and then provided to the multiplier group 210. Furthermore, the selector group 220 can be controlled to enter the first state, acquire L feature data and send them to the convolution calculation unit for buffering in the feature register group 250, and provide P of the feature data to the multiplier group 210. The multiplier group 210 calculates the product of the current weight data provided by the weight register group 230 and the P feature data provided by the feature register group 250, and outputs the product to the adder group 240 for addition. Of course, if some of the L feature data needs further computation, the selector group 220 can be controlled in the second state to use a shift selector to select the feature data in the feature register group 250 for shifting and then providing the shifted data to the multiplier group 210.

[0061] In practice, one weight data point from the target convolutional kernel can be sent out every clock cycle.

[0062] In this embodiment, the product calculation and accumulation of different feature data and weight data can be achieved by shifting. In this way, multiple convolution kernels can be handled. Thus, the same convolution circuit can be used to perform convolution operations of multiple convolution kernels, so that the structure of the convolution circuit can be reused in neural networks with different convolution operations, avoiding resource waste.

[0063] The convolution circuit in this embodiment can be applied to artificial intelligence chips used for image processing to accelerate the inference of image processing neural networks.

[0064] In an exemplary embodiment, such as Figure 2 As shown, the multiplier group 210 includes P multipliers 211, and each of the P multipliers 211 corresponds one-to-one with the P weight data. Each multiplier 211 is used to calculate the product of the corresponding weight data and the corresponding feature data.

[0065] The adder group 240 is used to accumulate the products of each of the multipliers 211 in parallel and store the accumulation result in the result register group 260.

[0066] In this embodiment, the results of each multiplier 211 in the multiplier group 210 can be accumulated in parallel, thereby improving computational efficiency.

[0067] In an exemplary embodiment, such as Figure 2 As shown, the adder group 240 includes P adders 241, a clear controller, and P clear selectors 242; the result register group 260 includes P result registers 261.

[0068] There is a one-to-one correspondence between the P adders 241 and the P multipliers 211;

[0069] There is a one-to-one correspondence between the P adders 241 and the P result registers 261;

[0070] Each of the P adders 241 also corresponds one-to-one with each of the P clear selectors 242;

[0071] Each of the P result registers 261 also corresponds one-to-one with each of the P clear selectors 242;

[0072] The clear controller is used to control each of the clear selectors 242 to select zero for output when it is necessary to restart the accumulation; and to control each of the clear selectors 242 to select the accumulation result stored in the corresponding result register 261 for output when it is not necessary to restart the accumulation.

[0073] The adder 241 is used to accumulate the product of the output of the corresponding clear selector 242 and the corresponding multiplier 211 and store the accumulation result in the corresponding result register 261.

[0074] The diagram shows eight different result registers, R0 to R7.

[0075] Thus, under the target convolution kernel, each adder 241 can accumulate the product of its corresponding multiplier 211, ultimately outputting P results in parallel. When the adder needs to re-accumulate after completing a convolution calculation, a clear signal can be sent by the clear controller to control the clear selector 242 to output zero, thereby clearing the previous accumulation result of the adder 241 and restarting the accumulation of the multiplier's product.

[0076] In an exemplary embodiment, such as Figure 2 As shown, the feature register group 250 includes P+X-1 feature registers 251, where X is the maximum convolution kernel size parameter supported by the convolution calculation unit 200; the selector group 220 includes P+X-2 selectors 221 and a shift controller.

[0077] The first to the second feature register 251 of the P+X-1 feature registers 251 correspond one-to-one with the P+X-2 selectors 221; the feature register 251 is used to cache the directly input feature data or to cache the feature data provided by the corresponding selector 221;

[0078] P+X-2 selectors 221 serve as input selectors, and each input selector is used to cache the input feature data into the corresponding feature register 251.

[0079] P+X-2 selectors 221 also serve as shift selectors. The i-th shift selector is used to shift the feature data cached in the (i+1)-th feature register 251 to the i-th feature register 251 under the control of the shift controller. i is a positive integer; the value of i is 1, 2, ..., P+X-2.

[0080] The first to the Pth feature registers 251 of the P+X-1 feature registers 251 correspond one-to-one with the P multipliers 211, and are used to provide the cached feature data to the corresponding multiplier 211.

[0081] In an exemplary embodiment, such as Figure 2 As shown, the weight register group 230 includes P weight registers 231;

[0082] The P weight registers 231 correspond one-to-one with the P multipliers 211, and are used to cache the input weight data and provide it to the corresponding multiplier 211.

[0083] Figure 2 The example shown uses P=8 and X=5. The feature register group 250 can store a maximum of 12 feature data. Figure 2 In the state shown, the feature register on the left is the first feature register.

[0084] The convolution circuit in this embodiment can be implemented using a simple register, multiplier 211, and selector, resulting in a simpler structure. The selector allows externally input feature data to be cached in feature register 251, and also allows the feature data in feature register 251 to be shifted for further multiplication and accumulation operations, significantly improving computational efficiency.

[0085] The weight register 231 can be used to easily cache weight data, thereby providing the weight data corresponding to the feature data.

[0086] In an exemplary embodiment, the input feature data is one-dimensional data; the input feature data is input data for one-dimensional convolution, or the input feature data is input data obtained by converting multi-dimensional convolution into one-dimensional convolution. The multi-dimensional convolution can be two-dimensional or three-dimensional. For multi-dimensional convolution, it can be first converted into one-dimensional convolution before the feature data is input to the convolution calculation unit for calculation. Thus, the convolution circuit of this embodiment has a wider range of applications.

[0087] The following is based on Figure 2 Taking an example, the convolution circuit of the present invention will be illustrated.

[0088] In this embodiment, different feature data are input into the feature register and enabled by shift signal and clear signal to control the implementation of 3*3 and 5*5 convolution kernels and one-dimensional, two-dimensional and three-dimensional convolution with stride of 2. Among them, stride of 2 can support 3*3 two-dimensional convolution.

[0089] One-dimensional convolution:

[0090] When the target convolution kernel is a 1*3 convolution kernel and the stride is 1, the convolution operation process of the convolution circuit is explained in Table 1.

[0091] Table 1. 1*3 convolution kernel with stride of 1.

[0092]

[0093]

[0094] In this embodiment, the 10 feature data are feature data from the feature map in the same channel. F0 to F9 represent 10 different feature data, where W0 to W7 represent 8 weight registers, and w0 to w2 represent 3 weight data in the 1*3 convolution kernel. Shifting refers to shifting the feature data in the feature registers using a shift selector. "Shift + Multiplication" means performing the shift and then multiplying the shifted feature data with the corresponding weight data. In Table 1, the input F0 to F7 are multiplied with weight data w0, the shifted F1 to F8 are multiplied with weight data w1, and the shifted F2 to F9 are multiplied with weight data w2. The convolution operation process in Table 1 achieves a 1*3 convolution kernel with a stride of 1.

[0095] For a 1*5 convolution kernel, the same principle applies as for a 1*3 convolution kernel; simply increase the input feature data to 12 F0 to F11 values. This will not be elaborated upon here.

[0096] Two-dimensional convolution:

[0097] When the target convolution kernel is a 3*3 convolution kernel and the stride is 1, the convolution operation process of the convolution circuit is explained in Table 2.

[0098] Table 2 shows 3x3 convolution kernels with a stride of 1.

[0099]

[0100]

[0101] In this embodiment, the 10 feature data are feature data from the same channel feature map. F0 to F9 represent 10 different feature data, where W0 to W7 represent 8 weight registers, and w0 to w8 represent 9 weight data in the 3*3 convolution kernel. The convolution operation with a 3*3 convolution kernel and a stride of 1 can be achieved through the convolution operation process shown in Table 2.

[0102] For a 5x5 convolution kernel, similar to the 3x3 convolution kernel, simply increase the input feature data to 12 F0 to F11 values; this will not be elaborated upon here.

[0103] When the target convolution kernel is a 3*3 convolution kernel and the stride is 2, the convolution operation process of the convolution circuit is explained in Table 3.

[0104] Table 3 shows 3x3 convolution kernels with a stride of 2.

[0105]

[0106]

[0107] In this embodiment, the feature data to be convolutionally processed includes 20 feature data points, represented by the index x_. The index indicates the position of the feature data, and for example, includes x_0, x_1, x_2, x_3, x_4, x_5, x_6, x_7, x_8, x_9, x_10, x_11, x_12, x_13, x_14, x_15, x_16, x_17, x_18, and x_19. The 10 even-indexed feature data points can be input first, followed by the 10 odd-indexed feature data points. Specifically, a row of registers can be set up to store the feature data to be input. Every two registers are connected to a 2-to-1 selector to select either the odd-indexed feature data or the even-indexed feature data as the input. F0 to F9 represent 10 different input feature data, where W0 to W7 represent 8 weight registers, and w0 to w8 represent 9 weight data in the 3*3 convolution kernel. The convolution operation with a 3*3 kernel and a stride of 2 can be achieved through the convolution operation process shown in Table 3.

[0108] For a 5x5 convolution kernel, the same principle applies as for a 3x3 convolution kernel; simply increase the number of input feature data to 12. This will not be elaborated upon here.

[0109] 3D convolution:

[0110] When the target convolution kernel is a 3*3*3 convolution kernel and the stride is 1, the convolution operation process of the convolution circuit is explained in Table 4.

[0111] Table 4. 3*3*3 convolution kernel with stride of 1.

[0112]

[0113]

[0114]

[0115] In this embodiment, the 10 feature data are feature data of the feature map in the same channel. F0 to F9 represent 10 different feature data, where W0 to W7 represent 8 weight registers, and w0 to w26 represent 27 weight data in the 3*3*3 convolution kernel. The convolution operation with a 3*3*3 convolution kernel and a stride of 1 can be achieved through the convolution operation process in Table 4.

[0116] For a 5*5*5 convolution kernel, similarly to a 3*3*3 convolution kernel, simply increase the input feature data to 12 F0~F11 values ​​and the weight data to w124. This will not be elaborated further here.

[0117] Therefore, the convolution circuit provided in this embodiment can achieve high computational efficiency in various scenarios through its simple structure. During convolution operations, the input data bandwidth remains constant, and all multipliers operate, achieving 100% acceleration efficiency. Due to the input data bandwidth limitation, increasing the input data bandwidth can also achieve even higher acceleration efficiency. Thus, by keeping the multipliers active, high efficiency is achieved within the limits of available data bandwidth and with proper data organization.

[0118] In an exemplary embodiment, such as Figure 3 As shown, the number of convolutional computation units 200 is m, where m is a positive integer greater than 1; the m convolutional computation units 200 are cascaded.

[0119] The convolution circuit further includes m-1 first cascade selectors 300. The j-th convolution calculation unit 200 and the (j-1)-th convolution calculation unit 200 are cascaded through the (j-1)-th first cascade selector 300, where j is a positive integer greater than 1; the value of j can be 2, 3, ..., m.

[0120] The convolution calculation unit 200 further includes a second cascade selector 270, which corresponds to the Pth shift selector.

[0121] The (j-1)th first cascade selector 300 is used to select the feature data cached in the first feature register of the j-th convolutional calculation unit and output it to the second cascade selector 270 of the (j-1)th convolutional calculation unit 200;

[0122] The second cascade selector 270 of the (j-1)th convolutional computation unit 200 is used to select the feature data cached in the (P+1)th feature register of the (j-1)th convolutional computation unit or the feature data cached in the first feature register of the j-th convolutional computation unit 200, and output it to the Pth shift selector of the (j-1)th convolutional computation unit 200;

[0123] The Pth shift selector in the (j-1)th convolutional computation unit is further configured to shift the feature data cached in the first feature register of the j-th convolutional computation unit to the Pth feature register of the (j-1)th convolutional computation unit under the control of the shift controller.

[0124] Figure 3Taking the current convolutional computation unit as the j-th convolutional computation unit pe_j as an example, and illustrating it with 12 feature registers, the structures of two adjacent convolutional computation units pe_j+1 and pe_j-1 are the same as the current convolutional computation unit pe_j. The specific structure of the convolutional computation unit can be referred to the above embodiment, and will not be repeated here. Two adjacent convolutional computation units 200 are cascaded through a first cascade selector 300. Specifically, the (j-1)-th first cascade selector 300 implements the cascading between the first feature register of the j-th convolutional computation unit 200 and the second cascade selector 270 of the (j-1)-th convolutional computation unit 200, used to select feature data cached in the first feature register of the j-th convolutional computation unit 200 or select preset data, and output it to the second cascade selector 270 of the (j-1)-th convolutional computation unit.

[0125] When convolution is performed through cascaded convolution calculation units 200, when the (j-1)th first cascade selector 300 selects the feature data cached in the first feature register of the j-th convolution calculation unit 200, the P-th shift selector in the (j-1)th convolution calculation unit, under the control of the shift controller, shifts the feature data cached in the first feature register of the j-th convolution calculation unit to the P-th feature register of the (j-1)th convolution calculation unit.

[0126] Without performing convolution operations through cascaded convolution calculation units 200, the Pth shift selector in the (j-1)th convolution calculation unit, under the control of the shift controller, shifts the feature data cached in the (P+1)th feature register 251 to the Pth feature register 251.

[0127] Additionally, when the input feature data requires padding, the (j-1)th first cascade selector 300 can select preset data (e.g., 0) and output it to the (j-1)th second cascade selector 270 of the convolution calculation unit 200. The (j-1)th second cascade selector 270 of the convolution calculation unit 200 selects the preset data and outputs it to the Pth shift selector to be cached in the feature register 251 as padding feature data.

[0128] In this embodiment, multiple convolutional computation units are cascaded together, which allows for the simultaneous input of more feature data and the shifting of feature data between convolutional computation units, thereby greatly increasing the input data bandwidth and improving the efficiency of convolutional operations.

[0129] The control method of the convolution circuit provided by the present invention is described below. The control method of the convolution circuit described below can be referred to in correspondence with the convolution circuit described above.

[0130] This embodiment provides a control method based on the convolution circuit provided in any of the above embodiments, such as... Figure 4 As shown, it includes:

[0131] Step 410: The selector group buffers the input feature data into the feature register group through the input selector, or shifts the buffered feature data through the shift selector.

[0132] Step 420: The feature register group provides the P cached feature data to the multiplier group, where P is a positive integer.

[0133] Step 430: The weight register group buffers the input P weight data and provides the P weight data to the multiplier group, and the P weight data correspond one-to-one with the P feature data.

[0134] Step 440: The multiplier group calculates the product of each of the P weight data and the corresponding feature data.

[0135] Step 450: The adder group accumulates the calculation results of the multiplier group and stores them in the result register group.

[0136] The present invention also provides a neural network accelerator, including the convolution circuit as provided in any of the above embodiments.

[0137] The present invention also provides an electronic device including a neural network accelerator as provided in any of the above embodiments.

[0138] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0139] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0140] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A convolution circuit, characterized in that, include: A convolution computation unit; the convolution computation unit includes a selector group, a feature register group, a weight register group, a multiplier group, an adder group, and a result register group; the selector group includes an input selector and a shift selector; The selector group is used to cache the input feature data into the feature register group through the input selector, and is also used to shift the cached feature data through the shift selector; The feature register group is used to buffer the input feature data and provide P feature data to the multiplier group, where P is a positive integer; The weight register group is used to cache P input weight data and provide the P weight data to the multiplier group, and the P weight data correspond one-to-one with the P feature data; The multiplier group is used to calculate the product of the corresponding weight data and the corresponding feature data; The adder group is used to accumulate the calculation results of the multiplier group and store them in the result register group; The multiplier group includes P multipliers, and each of the P multipliers corresponds one-to-one with the P weight data. Each multiplier is used to calculate the product of the corresponding weight data and the corresponding feature data. The adder group is used to accumulate the product of each multiplier in parallel and store the accumulation result in the result register group; The feature register group includes P+X-1 feature registers, where X is the maximum convolution kernel size parameter supported by the convolution calculation unit, and X is a positive integer; the selector group includes P+X-2 selectors and a shift controller; The first to the second feature registers in the P+X-1 feature registers correspond one-to-one with the P+X-2 selectors; the feature registers are used to cache the directly input feature data or to cache the feature data provided by the corresponding selector; P+X-2 selectors serve as input selectors, and each input selector is used to cache the input feature data into the corresponding feature register. The P+X-2 selectors also serve as shift selectors, and the i-th shift selector is used to shift the feature data cached in the (i+1)-th feature register to the i-th feature register under the control of the shift controller, where i is a positive integer; The first to the Pth feature registers in the P+X-1 feature registers correspond one-to-one with the P multipliers, and are used to provide the cached feature data to the corresponding multiplier.

2. The convolution circuit according to claim 1, characterized in that, The input feature data is one-dimensional data; the one-dimensional data is the input data of a one-dimensional convolution, or the one-dimensional data is the input data obtained after converting a multi-dimensional convolution into a one-dimensional convolution.

3. The convolution circuit according to claim 1, characterized in that, The weight register group includes P weight registers; Each of the P weight registers corresponds one-to-one with a P multiplier, and is used to cache the input weight data and provide it to the corresponding multiplier.

4. The convolution circuit according to claim 1, characterized in that, The adder group includes P adders, a clear controller, and P clear selectors; the result register group includes P result registers; There is a one-to-one correspondence between the P adders and the P multipliers; Each of the P adders corresponds one-to-one with one of the P result registers; Each of the P adders also corresponds one-to-one with a P clear selector; Each of the P result registers also corresponds one-to-one with one of the P clear selectors; The clear controller is used to control each of the clear selectors to select zero for output when it is necessary to restart the accumulation. When it is not necessary to restart the accumulation, control each of the clear selectors to select the accumulation result stored in the corresponding result register for output; The adder is used to accumulate the product of the output of the corresponding clear selector and the corresponding multiplier, and store the accumulation result in the corresponding result register.

5. The convolution circuit according to claim 1, characterized in that, The number of convolutional computation units is m, where m is a positive integer greater than 1; the m convolutional computation units are cascaded. The convolution circuit further includes m-1 first cascade selectors, wherein the j-th convolution calculation unit and the (j-1)-th convolution calculation unit in the m convolution calculation units are cascaded through the (j-1)-th first cascade selector, where j is a positive integer greater than 1; The convolution calculation unit further includes a second cascade selector, which corresponds to the Pth shift selector; The (j-1)th first cascade selector is used to select the feature data cached in the first feature register of the j-th convolutional computation unit and output it to the second cascade selector of the (j-1)th convolutional computation unit; The second cascade selector of the (j-1)th convolutional computation unit is used to select the feature data cached in the (P+1)th feature register of the (j-1)th convolutional computation unit or the feature data cached in the first feature register of the j-th convolutional computation unit, and output it to the Pth shift selector of the (j-1)th convolutional computation unit. The Pth shift selector in the (j-1)th convolutional computation unit is further configured to shift the feature data cached in the first feature register of the j-th convolutional computation unit to the Pth feature register of the (j-1)th convolutional computation unit under the control of the shift controller.

6. A control method based on the convolution circuit as described in any one of claims 1 to 5, characterized in that, include: The selector group buffers the input feature data into the feature register group through the input selector, or shifts the buffered feature data through the shift selector; The feature register group provides P cached feature data to the multiplier group, where P is a positive integer; The weight register group buffers the input P weight data and provides the P weight data to the multiplier group, and the P weight data correspond one-to-one with the P feature data; The multiplier group calculates the product of each of the P weight data and the corresponding feature data; The adder group accumulates the calculation results of the multiplier group and stores them in the result register group.

7. A neural network accelerator, characterized in that, Includes the convolution circuit as described in any one of claims 1 to 5.

8. An electronic device, characterized in that, Including the neural network accelerator as described in claim 7.

Images